TWI379355B - Methods of etching trenches into silicon of a semiconductor substrate, methods of forming trench isolation in silicon of a semiconductor substrate, and methods of forming a plurality of diodes - Google Patents

Methods of etching trenches into silicon of a semiconductor substrate, methods of forming trench isolation in silicon of a semiconductor substrate, and methods of forming a plurality of diodes Download PDF

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TWI379355B
TWI379355B TW097145260A TW97145260A TWI379355B TW I379355 B TWI379355 B TW I379355B TW 097145260 A TW097145260 A TW 097145260A TW 97145260 A TW97145260 A TW 97145260A TW I379355 B TWI379355 B TW I379355B
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mask
trench
semiconductor substrate
forming
plasma
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TW097145260A
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TW200937519A (en
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Krupakar M Subramanian
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Micron Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Description

1379355 f I 九、發明說明： 【發明所屬之技術領域】 本文中所揭示之實施例係關於蝕刻溝渠至半導體基板之 石夕中的方法，關於在半導體基板之矽中形成溝渠隔離 (trench isolation)之方法，且關於形成複數個二極體之方法。 【先前技術】 在積體電路之製造中’將很多器件封裝至半導體基板之 小區域中以產生積體電路。該等個別器件中之許多器件彼 此電隔離。因此，電隔離係半導體器件設計之一整體部分 以防止產生在相鄰組件及器件之間的不必要的電耦合。 隨著積體電路之尺寸減小而將構成電路之器件更緊密地 置放在一起。隔離電路組件之習知方法包括溝渠隔離。此 溝渠隔離係藉由蝕刻溝渠至半導體基板中且用絕緣材料填 充該等溝渠而進行。隨著半導體基板上之組件的密度增 加，溝渠之寬度減小《此外，溝渠之深度趨於增加。其中 形成有隔離溝渠之一種類型之半導體基板材料為結晶矽， 且該半導體基板材料可包括其他材料，諸如鍺及/或傳導性 調節摻雜劑（conductivity modifying dopant)。舉例而言，在 溝渠隔離之製造中，仍需開發出使得能夠蝕刻溝渠至矽中 之改良的触刻化學物質。 【發明内容】 本發明之實施例包括蝕刻溝渠至半導體基板之矽中的方 法，且亦包括在半導體基板之矽中形成溝渠隔離之方法。 此外，本發明之實施例亦包括形成複數個二極體之方法。 136134.doc 1379355 1 mTorr(毫托）至約50 mT〇rr，且基板所在之晶座的實例溫 度範圍為約0°C至約50°C。實例電源功率範圍為約1〇〇 w至 約i，ooo w，且實例偏壓為約-20 v至約_1〇〇〇 Ve舉例而 言，在SF0、Or N2及HBr為前驅氣體之情況下，實例流動 速率包括：對於SF6，約1 sccm(標準立方公分每分鐘）至約 lOOsccm;對於〇2,約 i〇sccm至約 5〇〇sccm;對於咖，〇sccm 至約50〇sccm ;及對於n2，約丨sccm至約5〇〇sccm。在lam Kiyo電漿蝕刻腔室中的一特定付諸實踐之實例包括：5mT〇rr、 7°C、-500 V偏壓、400 W電源功率、35〇 3_之 ^ ; 45 之〇2，60 sccm之N2 ;及20 sccm之HBr。所使用之特定電漿 蝕刻器可能夠操作以使得偏壓或偏功率可為設定點，而允 許另一者浮動。在一實施例中，設定偏壓，且允許偏功率 浮動。在另一實施例中，設定偏功率，且允許偏壓浮動。 已確定，使用SF0及〇2而不使用任何含氮化合物之蝕刻可 導致顯著之溝渠側壁侵蝕、不規則溝渠側壁及/或v形溝渠 底邛。然而，已發現，藉由將含氮化合物添加至電漿餘刻 化學物質，較平滑且/或較平直之溝渠側壁產生且具有較平 坦之溝渠底部，但除非字面上如此主張，否則本發明不必 要求達成該等結果中之任一者。此外，不必受本發明之任 何理論的限制，氮在電漿中之存在可產生NFx物質，此物質 可有助於或可並不有助於形成較平直之側壁及較平坦之底 部。 無論如何，本發明之一實施例包括使用一遮罩來電漿蝕 刻溝渠至半導體基板之矽中，該遮罩具有經形成為穿過該 136I34.doc 1379355 圖8為圖5之基板之處於圖5所示之處理後之處理下的視 圖。 圖9為圖8之基板之穿過圖8中之線9_9獲取的剖視圖。 圖1〇為圖5之基板之穿過圖8中之線1〇_1〇獲取的剖視圖。 圖11為圖8之基板之處於圖8所示之處理後之處理下的視 圖。 圖12為圖U之基板之穿過圖u中之線12_12獲取的剖視 圖。 圖13為圖U之基板之穿過圖n中之線1313獲取的剖視 圖。 圖14為圖11之基板之處於圖u所示之處理後之處理下的 視圖。 圖15為圖14之基板之穿過圖14中之線15-15獲取的剖視 圖。 圖16為圖14之基板之穿過圖14中之線ι6_16獲取的剖視 圖。 圖17為圖14之基板之處於圖14所示之處理後之處理下的 視圖。 圖18為圖17之基板之穿過圖π中之線ι8_18獲取的剖視 圖。 圖19為圖17之基板之穿過圖17中之線19-19獲取的剖視 圖。 圖20為圖19之基板之處於圖19所示之處理後之處理下的 視圖。 136134.doc 14

Claims (1)

1379355 • · 日修(更)王本、申請專利範"Ϊ'Τ 第097145260號專利申請案 中文申請專利範圍替換本(101年9月） 1. 一種蝕刻溝渠至一半導體基板之矽中之方法，其包含： 在一半導體基板之矽上形成一第一遮罩，該第一遮罩 包含經形成為穿過該遮罩之溝渠； 使用該第HI電漿敍㈣渠至該半導體基板之該 二，該電浆姓刻包含使用包含SF6、—含氧化合物及一 含氮化合物之前驅氣體來形成一蝕刻電漿；及 在該等第一溝渠上形成一第二遮罩，該第二遮罩具有 多個不通過該等第一溝渠之第二溝渠。 2. 如請求们之方法，其中該含氧化合物及該含氮化合物包 含不同化合物。 月東項1之方法，其中該含氧化合物及該含氮化合物包 含相同化合物。 4·如請求項3之方法’其中該相同化合物包含ΝΟχ。 5·如:求項1之方法，其中該等前驅氣體包含HBr。 6·如=求項1之方法，其中該遮罩在該電歌餘刻至該石夕中之 =較後部分期間包含—最外硬式遮罩層 遮罩層不含碳。 巧 7.如請求項〗 之方法，其中該含氮化合物包含 8 . 如請求項7夕士 方法’其中該等前驅氣體包含HBr。 9. 如請求項1 > +、 方法，其中該等前驅氣體包含兩種含氧化合 中之Γί含氧化合物中之—者不含氣，該等含氧化合物 —者包含該含氮化合物。 10. 如請求項9之 万法，其中該等前驅氣體之該一者包含〇2且 I36134-101092E.doc 1379355 該另一者包含N0X。 11. 一種钱刻溝渠至一半導體基板之矽中之方法，其包含： 在半導體基板之衫上形成一第一遮罩，該第一遮罩 包含經形成為穿過該遮罩之溝渠；及 使用該第一遮罩來電漿蝕刻第一溝渠至該半導體基板 之該石夕中，該電漿蝕刻包含一包含一含硫組分其包含 SF6、一含氧組分及一包含NFx之氮絚分之钱刻電漿； 在該等第一溝渠上形成一第二遮罩，該第二遮罩包含 多個不通過該等第一溝渠之第二溝渠。 12. 如請求項11之方法，其中該含硫組分之硫由一包含5匕之 前驅氣體形成。 13. 如請求項Η之方法，其中該含氧組分之氧由一包含〇2之 前驅氣體形成’且該NFx之氮由一不含氧之前驅氣體化合 物形成。 14. 如請求項11之方法，豆中該合氫 /、T °豕3軋組分之氧及該NFX之氮由 一包含N0X之前驅氣體形成。 15· -種在-半導體基板之矽中形成溝渠隔離之方法，其包 含： 遮罩，該第一遮罩 » 半導體基板之該石夕 2及N2之前驅氣體來 在一半導體基板之矽上形成一第— 包含經形成為穿過該遮罩之第—溝渠 使用該遮罩來電漿蝕刻溝渠至該 中，該電装钮刻包含使用包含SF6、〇 形成一钱刻電聚； ;及 將絕緣的溝渠隔離材料沈積至該等溝渠内 136134-1010928.doc • 2 - 1379355 在該等第-溝渠上形成一第二 多個不通過該等第—溝渠之第二耸；早，邊第·二遮罩具有 16.如請求項15之方法，直 渠0 17·如請求項15之方法 孔體包含HBr。 之每一者多之N2。 、 〇 引**氣體包含比sf6及02中 18. 如請求項15之方法，其中該飯刻 基本上由SF6、〇2及N 之6亥形成係由使用 19. -種在一丰則驅氣體而進行。 半導體基板之矽中形成 含： 心戍4渠隔離之方法，其包 在一半導體基板之石夕上形成 句冬铋拟士、达办 遮罩’該第一遮罩 δ、，、Φ成為穿過該第一遮 -主要方向上延伸之第一溝準广體基板上在-第 遮罩層；_之第该第-遮罩包含-硬式 使用該第一遮罩來電㈣刻第-溝渠至該半導體基板 之該石夕中，該電漿蝕刻該等第一溝土板 /再杀至该矽中包含使用 、6 3氧化口物及-含氮化合物之前驅氣體來形 成一餘刻電漿； 在該等第-溝渠上形成-第二遮罩，該第二遮罩包含 經形成為穿過該第二遮罩在該半導體基板上在一與該第 一主要方向正交之第二主要方向上延伸之第二溝渠，該 第二遮罩包含該第—遮罩之該硬式遮罩層且不通過該等 第一溝渠； 使用該第二遮罩來電漿餘溝渠至料導體基板 之該矽中，該電毁姓刻該等第二溝渠至該矽中包含使用 136134-I010928.doc iyjJD B 6 s氧化合物及一含氮化合物之前驅氣體來形 成一蝕刻電漿；及 在電聚ϋ刻該等第二溝渠之後，將絕緣的溝渠隔離材 料沈積至該矽中之該等第一及第二溝渠内。 "月求項19之方法，其中該第二遮罩由收容於該第一遮 罩之該硬式遮罩層上之多層抗蝕劑形成。 如。月求項19之方法’其中該第_遮罩之該硬式遮罩層為 絕緣性。 «•月求項19之方法，其中該第一遮罩之該硬式遮罩層為 導電性。 23.如清求項22之方法，其中該第一遮革之該導電性硬式遮 罩層包含一耐火金屬氮化物、一耐火金屬矽化物或一基 本形式之金屬中之至少一者。 24· —種形成複數個二極體之方法，其包含： 在一半導體基板之石夕上形成一第一遮罩，該第一遮罩 包含經形成為穿過該第一遮罩在該半導體基板上在一第 一主要方向上延伸之第一溝渠，該第一遮罩包含一硬式 遮罩層； 使用該第一遮罩來電漿蝕刻第一溝渠至該半導體基板 之該矽令，該電襞蝕刻該等第一溝渠至該矽中包含=用 包含SF6、-含氧化合物及-含氫化合物之前驅氣體來形 成一蝕刻電漿； 在該等第-溝渠上形成-第二遞罩，該第二遮罩包含 經形成為穿過該第二遮罩在該半導體基板上在一與該第 136134-1010928.doc -4- -主要方向正交之第二主要方向 第二遮罩包含竽篦.g 之第一溝¥，該 第一溝渠，=1罩之該硬式遮罩層且不通過該等 遮罩層;、 溝渠延伸穿過該第一遮罩之該硬式 使用。亥第一遮罩來電漿钱刻第二溝渠至該半導體基板 之：石夕中，該電漿钱刻該等第二溝渠至該石夕中包含使用 ^ s SFe含氧化合物及一含氮化合物之前驅氣體來形 成-#刻電漿’該電㈣刻該等第二溝渠至該碎中形成-間隔之含石夕凸台；及 在該4凸台中之個別凸台上提供個別二極體，且沈積 絕緣材料以使其收容於該等間隔之含矽凸台周圍。 25.如請求項24之方法，其中該等個別二極體包含_ p型含矽 區域及一 η型含石夕區域。 I36l34-I010928.doc
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