CN101878521A - 向半导体衬底的硅中蚀刻沟道的方法、在半导体衬底的硅中形成沟道隔离的方法及形成多个二极管的方法 - Google Patents

向半导体衬底的硅中蚀刻沟道的方法、在半导体衬底的硅中形成沟道隔离的方法及形成多个二极管的方法 Download PDF

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CN101878521A
CN101878521A CN2008801182349A CN200880118234A CN101878521A CN 101878521 A CN101878521 A CN 101878521A CN 2008801182349 A CN2008801182349 A CN 2008801182349A CN 200880118234 A CN200880118234 A CN 200880118234A CN 101878521 A CN101878521 A CN 101878521A
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克鲁帕卡尔·M·苏布拉马尼安
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Abstract

本发明提供一种向半导体衬底的硅中蚀刻沟道的方法，其包括在半导体衬底的硅上方形成掩模，其中所述掩模包含穿过所述掩模而形成的沟道。使用所述掩模进行等离子体蚀刻以向所述半导体衬底的所述硅中形成沟道。在一个实施例中，所述等离子体蚀刻包括使用包括SF6、含氧化合物及含氮化合物的前驱气体来形成蚀刻等离子体。在一个实施例中，所述等离子体蚀刻包括包含含硫组分、含氧组分及NFx的蚀刻等离子体。

Description

向半导体衬底的硅中蚀刻沟道的方法、在半导体衬底的硅中形成沟道隔离的方法及形成多个二极管的方法
技术领域
本文中所揭示的实施例关于向半导体衬底的硅中蚀刻沟道的方法，关于在半导体衬底的硅中形成沟道隔离的方法，且关于形成多个二极管的方法。
背景技术
在集成电路的制造中，将众多装置封装到半导体衬底的小区域中以产生集成电路。所述个别装置中的许多装置彼此电隔离。因此，电隔离是半导体装置设计的整体部分以用于防止在邻近组件及装置之间产生不需要的电耦合。
随着集成电路的尺寸减小，组成电路的装置被更紧密地放置在一起。隔离电路组件的常规方法包括沟道隔离。此沟道隔离是通过向半导体衬底中蚀刻沟道且用绝缘材料填充所述沟道而发生的。随着半导体衬底上的组件的密度已增加，沟道的宽度也已减小。此外，沟道的深度已趋于增加。其内形成有隔离沟道的一种类型的半导体衬底材料为晶体硅，且所述半导体衬底材料可包括其它材料，例如锗及/或导电性修改掺杂剂。仍需要开发出使得能够例如在沟道隔离的制造中向硅中蚀刻沟道的经改进的蚀刻化学物质。
附图说明
图1为在根据本发明的实施例的工艺中的半导体衬底的一部分的图解等距视图。
图2为图1的衬底的穿过图1中的线2-2获取的剖视图。
图3为图2的衬底的处于图2所示的处理后的处理下的视图。
图4为图3的衬底的处于图3所示的处理后的处理下的视图。
图5为图1的衬底的处于图4所示的处理后的处理下的视图。
图6为图5的衬底的穿过图5中的线5-5获取的剖视图。
图7为图5的衬底的穿过图5中的线7-7获取的剖视图。
图8为图5的衬底的处于图5所示的处理后的处理下的视图。
图9为图8的衬底的穿过图8中的线9-9获取的剖视图。
图10为图5的衬底的穿过图8中的线10-10获取的剖视图。
图11为图8的衬底的处于图8所示的处理后的处理下的视图。
图12为图11的衬底的穿过图11中的线12-12获取的剖视图。
图13为图11的衬底的穿过图11中的线13-13获取的剖视图。
图14为图11的衬底的处于图11所示的处理后的处理下的视图。
图15为图14的衬底的穿过图14中的线15-15获取的剖视图。
图16为图14的衬底的穿过图14中的线16-16获取的剖视图。
图17为图14的衬底的处于图14所示的处理后的处理下的视图。
图18为图17的衬底的穿过图17中的线18-18获取的剖视图。
图19为图17的衬底的穿过图17中的线19-19获取的剖视图。
图20为图19的衬底的处于图19所示的处理后的处理下的视图。
图21为图17的衬底的处于图20所示的处理后的处理下的视图。
图22为图21的衬底的穿过图21中的线22-22获取的剖视图。
图23为图21的衬底的穿过图21中的线23-23获取的剖视图。
图24为图21的衬底的处于图21所示的处理后的处理下的视图。
图25为图25的衬底的穿过图24中的线25-25获取的剖视图。
图26为图25的衬底的穿过图24中的线26-26获取的剖视图。
具体实施方式
本发明的实施例包括向半导体衬底的硅中蚀刻沟道的方法，且还包括在半导体衬底的硅中形成沟道隔离的方法。此外，本发明的实施例还包括形成多个二极管的方法。
最初参看图1及图2，半导体衬底大体上用参考标号10指示。在本文献的上下文中，术语“半导体衬底”或“半导电衬底”经定义为意指包含半导电材料的任何构造，其包括(但不限于)例如半导电晶片等块状半导电材料(其是单独的或在其上包含其它材料的组合中)及半导电材料层(其是单独的或在包含其它材料的组合中)。术语“衬底”指代任何支撑结构，其包括(但不限于)上文所述的半导电衬底。衬底10经描绘为包含块状半导体衬底，例如包含单晶硅12，但可使用其它含硅衬底(例如绝缘体上半导体)及其它衬底。材料12可包括其它材料，例如锗及/或导电性修改掺杂剂。在一个实施例中，块状硅材料12包含经掺杂到任何适合的p级掺杂的p型块状区14。其上方依序描绘经n型掺杂的n+区16、n型n-掺杂区18及p型p+掺杂区20。当然还预期替代的含硅衬底。
一系列掩蔽层接纳于硅材料20上方。这些层包括衬垫氧化物层22、氮化硅或多晶硅层24、硬掩蔽层26、抗反射涂层28及经图案化的光致抗蚀剂层30。这些层中的任何层是任选的，且可包含多种互不相同的材料及/或层。所述材料可为或可不为最终牺牲的。在某些实施例中，硬掩模层26可为以下性质中的任一者：绝缘的、半导电的或导电的。用于硬掩模层26的实例绝缘材料包括经掺杂或未经掺杂的二氧化硅，以及氮化硅。用于硬掩模层26的实例导电材料包括难熔金属氮化物(即TiN、WN等)、难熔金属硅化物(WSix、TiSx等)或呈元素形式的任何金属(Ti、W等)中的任一者或其组合。光致抗蚀剂30经描绘为已被图案化以形成到达抗反射涂层28的沟道32。
参看图3，光致抗蚀剂30(未图示)及抗反射涂层28(未图示)已用作用以蚀刻穿过硬掩模层26的掩模，其中光致抗蚀剂层30及抗反射涂层28由所述蚀刻及/或随后被至少部分地移除。用于进行所述蚀刻的实例各向异性干式蚀刻化学物质针对光致抗蚀剂包括SO2+O2或O2+HBr或O2+N2，且针对抗反射涂层通常包括一种或一种以上碳氟化合物(例如，CF4)+HBr+He。
参看图4，经图案化的硬掩模层26已用作用于蚀刻穿过层24及22的掩模，进而使沟道32最终延伸到硅12。用于蚀刻穿过氮化硅层24的实例蚀刻化学物质包括一种或一种以上碳氟化合物+SF6+NF3，而用于在所述蚀刻后清除衬垫氧化物22的实例蚀刻化学物质包括一种或一种以上碳氟化合物(例如，CF4、CHF3、CH2F2等)。图4进而描绘(仅在一个实例实施例中)在半导体衬底的硅上方形成掩模35，其中掩模35包含穿过所述掩模35而形成的沟道32。所述掩模可包括或可不包括硬掩模层，且仅在一个实例中可被视为第一掩模，所述第一掩模包含穿过所述第一掩模而形成的第一沟道32，所述第一沟道32在衬底10上方在第一主要方向上延伸。在图4的描绘中的所述实例第一主要方向将垂直进入及离开图4所在页面的平面。当然，第一沟道32在此方向上可并不完全笔直且可(仅借助于实例)相对于彼此蜿蜒，尽管如此，在一个实施例中，第一沟道32如刚才所描述在衬底上方在第一主要方向上延伸。
参看图5、图6及图7，已通过使用掩模35来向衬底10的硅12中等离子体蚀刻而使沟道32相对于衬底10延伸。在一个实施例中，所述等离子体蚀刻包含使用包含SF6、含氧化合物及含氮化合物的前驱气体来形成蚀刻等离子体。含氧化合物及含氮化合物可包含不同化合物且/或可包含相同化合物。举例来说，在一个实施例中，含氧化合物包含O2且含氮化合物包含N2。相同化合物所包含的实例含氧化合物及含氮化合物包括NOx，其中“x”在例如约1到3的范围内。
此外，当然，前驱气体可包含两种含氧化合物，例如，其中含氧化合物中的一者不含氮且含氧化合物中的另一者包含氮。举例来说，仅在一个实施例中，前驱气体可包含SF6、N2、O2及NOx。或者，在所述实例中，使得发生等离子体蚀刻的前驱气体可不包括N2。此外，在一个实施例中，前驱气体可包含SF6、O2及N2，基本上由SF6、O2及N2组成，或由SF6、O2及N2组成。当然，还可使用额外的前驱气体，例如HBr。在一个实施例中，在使用SF6、O2及N2这三种气体的情况下，使得进行等离子体蚀刻的前驱气体可包含比SF6及O2中的每一者多的N2。在一个实施例中，在蚀刻期间使用的掩模在向硅中等离子体蚀刻的至少较后部分期间包含最外硬掩模层，且在一个实施例中，所述外部掩模层不含碳，因为所陈述的等离子体蚀刻化学物质可能会蚀刻包含碳的最外硬掩模层。
已使用LAM喜世(LAM Kiyo)等离子体蚀刻腔室将本发明付诸实践。无论如何且仅借助于实例，在蚀刻期间的实例压力可为约1毫托到约50毫托，且上面搁置衬底的基座的实例温度范围为约0℃到约50℃。实例电源功率范围为约100W到约1,000W，且实例偏压为约-20V到约-1,000V。在例如SF6、O2、N2及HBr为前驱气体的情况下，实例流动速率包括：对于SF6，约1sccm到约100sccm；对于O2，约10sccm到约500sccm；对于HBr，0sccm到约500sccm及对于N2，约1sccm到约500sccm。在LAM喜世(LAM Kiyo)等离子体蚀刻腔室中的特定付诸实践的实例包括：5毫托、7℃、-500V偏压、400W电源功率、350sccm的SF6、45sccm的O2、60sccm的N2及20sccm的HBr。所使用的特定等离子体蚀刻器可能能够操作以使得偏压或偏置功率可为设定点，同时允许另一者浮动。在一个实施例中，设定偏压，且允许偏置功率浮动。在另一实施例中，设定偏置功率，且允许偏压浮动。
已确定，使用SF6及O2而不使用任何含氮化合物的蚀刻可导致显著的沟道侧壁侵蚀、不规则沟道侧壁及/或V形沟道底部。然而，已发现，通过将含氮化合物添加到等离子体蚀刻化学物质，产生较平滑且/或较笔直的沟道侧壁且具有较平坦的沟道底部，但除非字面上如此主张，否则本发明不必要求实现所述结果中的任一者。此外且在不必受本发明的任何理论限制的情况下，在等离子体中存在氮可产生NFx物质，此物质可有助于或可并不有助于形成较笔直的侧壁及较平坦的底部。
无论如何，本发明的一个实施例包括使用掩模来向半导体衬底的硅中等离子体蚀刻沟道，所述掩模具有穿过所述掩模而形成的沟道，其中所述等离子体蚀刻包含包括含硫组分、含氧组分及NFx的蚀刻等离子体。在一个实施例中，含硫组分由包含SF6的前驱气体形成。在一个实施例中，含氧组分的氧可由包含O2的前驱气体形成，且NFx的氮可由不含氧的前驱气体化合物形成。此外，在一个实施例中，含氧组分的氧及NFx的氮可由包含NOx的前驱气体形成。此外，实例前驱气体包括上文所述的前驱气体中的任一者，包括其任何组合。
沟道32在硅12内的实例蚀刻深度为约7，500埃到约20,000埃，其中9,000埃仅为一个特定实例。
参看图8、图9及图10，掩蔽层40已形成于衬底10上方且因此形成于衬底的硅内的第一沟道32上方。在一个实施例中，掩蔽层40包含多层抗蚀剂，其中三个此类实例层被依序展示为包含第一层42、在第一层42上方的层44及另一层45。在一个实例中，层42呈液态树脂的形式，所述液态树脂沉积以完全填充第一沟道32并被接纳于第一掩模35的硬掩模层26上方且其后经固化。实例层44为任何含硅硬掩模，其上方为包含感光材料(例如光致抗蚀剂)的实例层45。
参看图11、图12及图13，感光层45已经图案化以形成第二沟道50，所述第二沟道50在衬底10上方在与第一主要方向正交的第二主要方向上延伸。图13中的实例第二主要方向将垂直进入及离开图13所在页面的平面，且在图11中的箭头13所指的方向上。此外，如上文所述的所述第一主要方向将在图11中的箭头12所指的方向上。当然，第二沟道50在此第二主要方向上可并不完全笔直且可(仅借助于实例)相对于彼此而蜿蜒，尽管如此，在一个实施例中，第二沟道50如刚才所描述在衬底上方在第二主要方向上延伸。
参看图14、图15及图16，经图案化的感光材料45(未图示)已用作用以蚀刻含硅硬掩模层44、树脂42及第一掩模35的硬掩模层26的掩模，以使第二沟道50穿过硬掩模层26而延伸到氮化硅层24，其中感光材料45在所述蚀刻期间及/或随后被移除。
参看图17、图18及图19，已进行蚀刻以使沟道50穿过氮化硅层24及衬垫氧化物层22而延伸到硅材料12。因此，且仅在一个实施例中，第二沟道50延伸穿过第一掩模35的硬掩模层26，且第二掩模55形成于第一沟道上方且包含第一掩模的硬掩模层26。
参看图20，已通过使用第二掩模55对硅12进行等离子体蚀刻而使第二沟道50延伸到硅12中。材料42的一些材料(图20中未展示或不可见)可保留而免受图14、图15及图16所描绘的处理(未图示)，或将另一材料提供于第一沟道32的底部(图20中未展示或不可见)，以防止在蚀刻第二沟道50的同时将所述第一沟道的若干部分蚀刻得较深。在一个实施例中，向硅中等离子体蚀刻第二沟道包含使用包含SF6、含氧化合物及含氮化合物的前驱气体来形成蚀刻等离子体。可使用上文所描述的处理中的任一者。此外，用以在硅内形成第二沟道的等离子体蚀刻可与用以在硅材料内形成第一沟道的等离子体蚀刻相同或不同。此外且无论如何，用以形成第二沟道的等离子体蚀刻可包含包括含硫组分、含氧组分及NFx的蚀刻等离子体，例如也如上所述。无论如何且仅借助于实例，沟道50在硅材料12内的实例深度为约2,500埃到约3,500埃，其中约3,000埃为特定实例。
所述材料22、24、26、42及44中的一些或全部材料最终可被或可不被从衬底移除。仅借助于实例，图21、图22及图23描绘所有所述材料已被移除，且无论如何，对第二沟道的等离子体蚀刻导致形成间隔的含硅台面65。
本发明的实施例包括在半导体衬底的硅内形成沟道隔离的方法，且可包含或可不包含间隔的含硅台面的形成。举例来说且仅借助于实例，上文所述的在图5到图7之后的处理或其它处理可包括将绝缘的沟道隔离材料沉积到所述沟道内而不必形成上述实例第二沟道。此外且不管形成台面，可将绝缘的沟道隔离材料沉积到形成于硅内的第一及第二沟道内。
无论如何，本发明的实施例还包含结合形成间隔的含硅台面而形成多个二极管的方法。举例来说且仅借助于实例，图24、图25及图26描绘后续处理，借此已沉积绝缘材料66以使其接纳于间隔的含硅台面65周围且将导电硅化物层68形成于台面65上方。实例绝缘材料66包括氮化硅及二氧化硅中的一者或其组合，且特定实例导电硅化物材料68包括硅化钴。当然，可使用替代及/或额外的材料。仅借助于实例，可通过以下方式来制造图24到26的构造：沉积材料66以过量填充沟道，将其平面化且图案化以暴露含硅台面，继而将台面的暴露的硅材料予以后续硅化金属沉积。
无论如何，图24到26描绘在间隔的含硅台面65中的个别台面上形成个别实例二极管75。在一个实施例中，个别二极管包含p型含硅区(即，区20)及n型含硅区(即，区16、18)。在一个实施例中，个别二极管包含含硅区(即，区20)及金属区(即，区68)。仅借助于实例，二极管可用于可编程导电随机存取存储器(PCRAM)应用中。

Claims (25)

1.一种向半导体衬底的硅中蚀刻沟道的方法，其包含：
在半导体衬底的硅上方形成掩模，所述掩模包含穿过所述掩模而形成的沟道；及使用所述掩模来向所述半导体衬底的所述硅中等离子体蚀刻沟道，所述等离子体蚀刻包含使用包含SF6、含氧化合物及含氮化合物的前驱气体来形成蚀刻等离子体。
2.根据权利要求1所述的方法，其中所述含氧化合物及所述含氮化合物包含不同化合物。
3.根据权利要求1所述的方法，其中所述含氧化合物及所述含氮化合物包含相同化合物。
4.根据权利要求3所述的方法，其中所述相同化合物包含NOx。
5.根据权利要求1所述的方法，其中所述前驱气体包含HBr。
6.根据权利要求1所述的方法，其中所述掩模在所述向所述硅中等离子体蚀刻的至少较后部分期间包含最外硬掩模层，所述最外硬掩模层不含碳。
7.根据权利要求1所述的方法，其中所述含氮化合物包含N2。
8.根据权利要求7所述的方法，其中所述前驱气体包含HBr。
9.根据权利要求1所述的方法，其中所述前驱气体包含两种含氧化合物，所述含氧化合物中的一者不含氮，所述含氧化合物中的另一者包含所述含氮化合物。
10.根据权利要求9所述的方法，其中所述一者包含O2且所述另一者包含NOx。
11.一种向半导体衬底的硅中蚀刻沟道的方法，其包含：
在半导体衬底的硅上方形成掩模，所述掩模包含穿过所述掩模而形成的沟道；及使用所述掩模来向所述半导体衬底的所述硅中等离子体蚀刻沟道，所述等离子体蚀刻包含包括含硫组分、含氧组分及NFx的蚀刻等离子体。
12.根据权利要求11所述的方法，所述含硫组分的硫是由包含SF6的前驱气体形成的。
13.根据权利要求11所述的方法，其中所述含氧组分的氧是由包含O2的前驱气体形成的，且所述NFx的氮是由不含氧的前驱气体化合物形成的。
14.根据权利要求11所述的方法，其中所述含氧组分的所述氧及所述NFx的所述氮是由包含NOx的前驱气体形成的。
15.一种在半导体衬底的硅中形成沟道隔离的方法，其包含：
在半导体衬底的硅上方形成掩模，所述掩模包含穿过所述掩模而形成的沟道；
使用所述掩模来向所述半导体衬底的所述硅中等离子体蚀刻沟道，所述等离子体蚀刻包含使用包含SF6、O2及N2的前驱气体来形成蚀刻等离子体；及将绝缘的沟道隔离材料沉积到所述沟道内。
16.根据权利要求15所述的方法，其中所述前驱气体包含HBr。
17.根据权利要求15所述的方法，其中所述前驱气体包含比SF6及O2中的每一者多的N2。
18.根据权利要求15所述的方法，其中通过使用基本上由SF6、O2及N2组成的前驱气体进行所述蚀刻等离子体的所述形成。
19.一种在半导体衬底的硅中形成沟道隔离的方法，其包含：
在半导体衬底的硅上方形成第一掩模，所述第一掩模包含穿过所述第一掩模而形成的在所述衬底上方在第一主要方向上延伸的第一沟道，所述第一掩模包含硬掩模层；
使用所述第一掩模来向所述半导体衬底的所述硅中等离子体蚀刻第一沟道，所述向所述硅中等离子体蚀刻所述第一沟道包含使用包含SF6、含氧化合物及含氮化合物的前驱气体来形成蚀刻等离子体；
在所述第一沟道上方形成第二掩模，所述第二掩模包含穿过所述第二掩模而形成的在所述衬底上方在与所述第一主要方向正交的第二主要方向上延伸的第二沟道，所述第二掩模包含所述第一掩模的所述硬掩模层；
使用所述第二掩模来向所述半导体衬底的所述硅中等离子体蚀刻第二沟道，所述向所述硅中等离子体蚀刻所述第二沟道包含使用包含SF6、含氧化合物及含氮化合物的前驱气体来形成蚀刻等离子体；及
在等离子体蚀刻所述第二沟道之后，将绝缘的沟道隔离材料沉积到所述硅中的所述第一及第二沟道内。
20.根据权利要求19所述的方法，其中所述第二掩模是由接纳于所述第一掩模的所述硬掩模层上方的多层抗蚀剂形成的。
21.根据权利要求19所述的方法，其中所述第一掩模的所述硬掩模层为绝缘的。
22.根据权利要求19所述的方法，其中所述第一掩模的所述硬掩模层为导电的。
23.根据权利要求22所述的方法，其中所述第一掩模的所述导电硬掩模层包含难熔金属氮化物、难熔金属硅化物或呈元素形式的金属中的至少一者。
24.一种形成多个二极管的方法，其包含：
在半导体衬底的硅上方形成第一掩模，所述第一掩模包含穿过所述第一掩模而形成的在所述衬底上方在第一主要方向上延伸的第一沟道，所述第一掩模包含硬掩模层；
使用所述第一掩模来向所述半导体衬底的所述硅中等离子体蚀刻第一沟道，所述向所述硅中等离子体蚀刻所述第一沟道包含使用包含SF6、含氧化合物及含氮化合物的前驱气体来形成蚀刻等离子体；
在所述第一沟道上方形成第二掩模，所述第二掩模包含穿过所述第二掩模而形成的在所述衬底上方在与所述第一主要方向正交的第二主要方向上延伸的第二沟道，所述第二掩模包含所述第一掩模的所述硬掩模层，所述第二沟道延伸穿过所述第一掩模的所述硬掩模层；
使用所述第二掩模来向所述半导体衬底的所述硅中等离子体蚀刻第二沟道，所述向所述硅中等离子体蚀刻所述第二沟道包含使用包含SF6、含氧化合物及含氮化合物的前驱气体来形成蚀刻等离子体，所述向所述硅中等离子体蚀刻所述第二沟道形成间隔的含硅台面；及
在所述台面中的个别台面上提供个别二极管，且沉积绝缘材料以使其被接纳于所述间隔的含硅台面周围。
25.根据权利要求24所述的方法，其中所述个别二极管包含p型含硅区及n型含硅区。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104040407A (zh) * 2011-12-22 2014-09-10 高通Mems科技公司 用于显示装置的倾斜小面
CN104425222A (zh) * 2013-08-28 2015-03-18 中芯国际集成电路制造(上海)有限公司 图形化方法
CN104685643A (zh) * 2012-09-27 2015-06-03 欧司朗光电半导体有限公司 用于对半导体层的区域进行分割的方法
CN109326596A (zh) * 2017-08-01 2019-02-12 联华电子股份有限公司 具有电容连接垫的半导体结构与电容连接垫的制作方法

Families Citing this family (131)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7704849B2 (en) 2007-12-03 2010-04-27 Micron Technology, Inc. Methods of forming trench isolation in silicon of a semiconductor substrate by plasma
US8030215B1 (en) * 2008-02-19 2011-10-04 Marvell International Ltd. Method for creating ultra-high-density holes and metallization
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
KR20130102399A (ko) * 2012-03-07 2013-09-17 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9267739B2 (en) 2012-07-18 2016-02-23 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US20140271097A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9627216B2 (en) * 2013-10-04 2017-04-18 Applied Materials, Inc. Method for forming features in a silicon containing layer
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9484376B2 (en) * 2014-05-30 2016-11-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor isolation structure and manufacturing method thereof
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) * 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
JP6529357B2 (ja) * 2015-06-23 2019-06-12 東京エレクトロン株式会社 エッチング方法
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
KR102403619B1 (ko) * 2017-09-18 2022-05-30 삼성전자주식회사 반도체 장치 및 그 제조 방법
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
TWI766433B (zh) 2018-02-28 2022-06-01 美商應用材料股份有限公司 形成氣隙的系統及方法
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes
US11257683B2 (en) * 2019-06-21 2022-02-22 Fei Company Perimeter trench formation and delineation etch delayering

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04188869A (ja) * 1990-11-22 1992-07-07 Mitsubishi Electric Corp 接合型電界効果トランジスタとキャパシタとを含む半導体記憶装置およびその製造方法
JPH0555178A (ja) 1991-08-27 1993-03-05 Fujitsu Ltd 多層レジストを用いるパターニング方法
JP3322936B2 (ja) * 1992-03-19 2002-09-09 株式会社東芝 半導体記憶装置
US5314576A (en) * 1992-06-09 1994-05-24 Sony Corporation Dry etching method using (SN)x protective layer
US6199874B1 (en) * 1993-05-26 2001-03-13 Cornell Research Foundation Inc. Microelectromechanical accelerometer for automotive applications
JPH09186138A (ja) 1996-01-08 1997-07-15 Hitachi Ltd イオンビーム加工装置
JPH09186139A (ja) 1996-01-08 1997-07-15 Canon Inc ドライエッチング方法
US5750441A (en) * 1996-05-20 1998-05-12 Micron Technology, Inc. Mask having a tapered profile used during the formation of a semiconductor device
KR19990071626A (ko) * 1996-09-24 1999-09-27 매튜스 죤 씨. 사파이어플라즈마애셔에서기판으로부터잔류물을제거하는방법및그장치
DE19706682C2 (de) * 1997-02-20 1999-01-14 Bosch Gmbh Robert Anisotropes fluorbasiertes Plasmaätzverfahren für Silizium
US6020091A (en) * 1997-09-30 2000-02-01 Siemens Aktiengesellschaft Hard etch mask
US5872061A (en) * 1997-10-27 1999-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Plasma etch method for forming residue free fluorine containing plasma etched layers
US5958793A (en) * 1997-12-24 1999-09-28 Sarnoff Corporation Patterning silicon carbide films
US5935874A (en) * 1998-03-31 1999-08-10 Lam Research Corporation Techniques for forming trenches in a silicon layer of a substrate in a high density plasma processing system
US6797189B2 (en) * 1999-03-25 2004-09-28 Hoiman (Raymond) Hung Enhancement of silicon oxide etch rate and nitride selectivity using hexafluorobutadiene or other heavy perfluorocarbon
US6303513B1 (en) * 1999-06-07 2001-10-16 Applied Materials, Inc. Method for controlling a profile of a structure formed on a substrate
US6372151B1 (en) * 1999-07-27 2002-04-16 Applied Materials, Inc. Storage poly process without carbon contamination
US6583065B1 (en) * 1999-08-03 2003-06-24 Applied Materials Inc. Sidewall polymer forming gas additives for etching processes
JP3485504B2 (ja) * 1999-09-09 2004-01-13 沖電気工業株式会社 半導体装置のドライエッチング方法
US6284623B1 (en) * 1999-10-25 2001-09-04 Peng-Fei Zhang Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect
US6491835B1 (en) * 1999-12-20 2002-12-10 Applied Materials, Inc. Metal mask etching of silicon
US6437383B1 (en) * 2000-12-21 2002-08-20 Intel Corporation Dual trench isolation for a phase-change memory cell and method of making same
US7345342B2 (en) * 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6500725B1 (en) * 2001-09-06 2002-12-31 Taiwan Semiconductor Manufacturing Company, Ltd Microelectronic fabrication method providing alignment mark and isolation trench of identical depth
US6518670B1 (en) 2002-03-06 2003-02-11 International Business Machines Corporation Electrically porous on-chip decoupling/shielding layer
US6579760B1 (en) * 2002-03-28 2003-06-17 Macronix International Co., Ltd. Self-aligned, programmable phase change memory
US7078334B1 (en) * 2002-06-06 2006-07-18 Cypress Semiconductor Corporation In situ hard mask approach for self-aligned contact etch
US7074723B2 (en) * 2002-08-02 2006-07-11 Applied Materials, Inc. Method of plasma etching a deeply recessed feature in a substrate using a plasma source gas modulated etchant system
US6576558B1 (en) * 2002-10-02 2003-06-10 Taiwan Semiconductor Manufacturing Company High aspect ratio shallow trench using silicon implanted oxide
TW583764B (en) * 2002-11-11 2004-04-11 Macronix Int Co Ltd Mask ROM having diodes and manufacturing method thereof
US6875651B2 (en) * 2003-01-23 2005-04-05 Sharp Laboratories Of America, Inc. Dual-trench isolated crosspoint memory array and method for fabricating same
US7078351B2 (en) * 2003-02-10 2006-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Photoresist intensive patterning and processing
US6942816B2 (en) * 2003-02-12 2005-09-13 Lam Research Corporation Methods of reducing photoresist distortion while etching in a plasma processing system
EP1599894A4 (en) * 2003-03-03 2010-04-28 Lam Res Corp PROCESS FOR IMPROVING PROFILE CONTROL AND N / P LOADING IN DOUBLE-DOTED GATE APPLICATIONS
US6960517B2 (en) * 2003-06-30 2005-11-01 Intel Corporation N-gate transistor
US7285433B2 (en) * 2003-11-06 2007-10-23 General Electric Company Integrated devices with optical and electrical isolation and method for making
US7407837B2 (en) * 2004-01-27 2008-08-05 Fuji Electric Holdings Co., Ltd. Method of manufacturing silicon carbide semiconductor device
US7326950B2 (en) * 2004-07-19 2008-02-05 Micron Technology, Inc. Memory device with switching glass layer
US7180160B2 (en) * 2004-07-30 2007-02-20 Infineon Technologies Ag MRAM storage device
US7084024B2 (en) * 2004-09-29 2006-08-01 International Business Machines Corporation Gate electrode forming methods using conductive hard mask
DE102004054558A1 (de) * 2004-11-11 2006-05-24 Infineon Technologies Ag Verfahren zur Herstellung einer resistiv schaltenden Speicherzelle, hergestellte Speicherzelle sowie daraus aufgebautes Speicherbauelement
KR100639467B1 (ko) * 2004-12-31 2006-10-26 동부일렉트로닉스 주식회사 플래시 메모리 소자의 소자 분리 영역 형성 방법
US7468307B2 (en) * 2005-06-29 2008-12-23 Infineon Technologies Ag Semiconductor structure and method
US7223650B2 (en) * 2005-10-12 2007-05-29 Intel Corporation Self-aligned gate isolation
US20070102399A1 (en) * 2005-11-07 2007-05-10 Tokyo Electron Limited Method and apparatus for manufacturing a semiconductor device, control program and computer-readable storage medium
US7732340B2 (en) * 2006-08-08 2010-06-08 Tokyo Electron Limited Method for adjusting a critical dimension in a high aspect ratio feature
US7829465B2 (en) * 2006-08-09 2010-11-09 Shouliang Lai Method for plasma etching of positively sloped structures
US20080050871A1 (en) * 2006-08-25 2008-02-28 Stocks Richard L Methods for removing material from one layer of a semiconductor device structure while protecting another material layer and corresponding semiconductor device structures
KR100818654B1 (ko) * 2006-12-01 2008-04-01 주식회사 하이닉스반도체 벌브형 리세스 게이트를 갖는 반도체 소자 및 그 제조 방법
US20090050867A1 (en) * 2007-08-20 2009-02-26 David Wells Feature formed beneath an existing material during fabrication of a semiconductor device and electronic systems comprising the semiconductor device
US7704849B2 (en) 2007-12-03 2010-04-27 Micron Technology, Inc. Methods of forming trench isolation in silicon of a semiconductor substrate by plasma
US20100298324A1 (en) 2007-12-19 2010-11-25 Smith Kline Beecham Corporation Prolyl Hydroxylase Inhibitors

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104040407A (zh) * 2011-12-22 2014-09-10 高通Mems科技公司 用于显示装置的倾斜小面
CN104040407B (zh) * 2011-12-22 2016-12-07 追踪有限公司 用于显示装置的倾斜小面
US9678329B2 (en) 2011-12-22 2017-06-13 Qualcomm Inc. Angled facets for display devices
CN104685643A (zh) * 2012-09-27 2015-06-03 欧司朗光电半导体有限公司 用于对半导体层的区域进行分割的方法
US9589943B2 (en) 2012-09-27 2017-03-07 Osram Opto Semiconductors Gmbh Method for separating regions of a semiconductor layer
CN104685643B (zh) * 2012-09-27 2017-10-17 欧司朗光电半导体有限公司 用于对半导体层的区域进行分割的方法
US9865776B2 (en) 2012-09-27 2018-01-09 Osram Opto Semiconductors Gmbh Method for separating regions of a semiconductor layer
CN104425222A (zh) * 2013-08-28 2015-03-18 中芯国际集成电路制造(上海)有限公司 图形化方法
CN109326596A (zh) * 2017-08-01 2019-02-12 联华电子股份有限公司 具有电容连接垫的半导体结构与电容连接垫的制作方法
CN109326596B (zh) * 2017-08-01 2022-05-03 联华电子股份有限公司 具有电容连接垫的半导体结构与电容连接垫的制作方法

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