CN101707194B - 一种镀钯键合铜丝的制造方法 - Google Patents

一种镀钯键合铜丝的制造方法 Download PDF

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CN101707194B
CN101707194B CN200910221819XA CN200910221819A CN101707194B CN 101707194 B CN101707194 B CN 101707194B CN 200910221819X A CN200910221819X A CN 200910221819XA CN 200910221819 A CN200910221819 A CN 200910221819A CN 101707194 B CN101707194 B CN 101707194B
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copper wire
copper
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purity
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CN101707194A (zh
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郑康定
冯小龙
李彩莲
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NINGBO KANGQIANG ELECTRONICS CO Ltd
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Abstract

本发明公开了一种以高纯铜丝为基体、表面覆有纯钯保护层的键合铜丝制造方法，它包括：提取高纯铜、制备单晶铜棒、粗拔、热处理、表面镀钯、精拔、热处理、表面清洗和分卷步骤。本发明专利摒弃了传统工艺先拉拔、后电镀即直接应用的落后工艺，而是先制成线径小于1mm的铜丝，再电镀纯钯层，最后精密拉拔成镀钯键合铜丝成品。应用本专利技术可以有效提升键合铜丝的抗氧化性能，确保成品外观保持银白色金属光泽，大大延长键合铜丝产品拆封后的保质期；又由于成品机械强度的提高、抗氧化性能提升，有利于进一步缩小键合铜丝的线径，缩短焊接间距，更加适用于高密度、多引脚集成电路封装。

Description

一种镀钯键合铜丝的制造方法
技术领域
本发明涉及微电子后道封装工序用金属键合丝产品技术领域，尤其指键合铜丝的表面镀钯结构及其制造方法。
背景技术
微电子器件芯片的键合工序，是指在一定温度下采用超声加压的方式将键合丝两端分别焊接在芯片焊盘和引线框架引脚上，实现芯片内部电路与外部电路的连接。早期的键合丝多由纯金制成，但随着黄金资源的日益稀缺、价格持续攀升，微电子封装成本大幅上升，为此业内人士研发成功了以铜丝产品来替代昂贵的金丝产品，此类比较典型的产品如国家知识产权局于2008年9月24日授权公告的ZL200610154487.4名称为“键合铜丝及其制备方法”和2008年10月22日授权公告的ZL200610154485.5名称为“一种键合铜丝及其制备方法”的发明专利产品。这些键合铜丝价格低廉，且在拉伸、剪切强度和延展等方面的性能优于金丝，已经成功应用于如DIP、SOP和功率器件等产品的封装生产。但是，随着微电子器件芯片行业日益、快速向小型化、多引脚高密度方向发展，对于键合铜丝的性能要求也越来越苛刻，特别是在键合工艺中，要求键合铜丝具备良好的耐高温氧化和耐热稳定性，以及与表面镀钯类引线框架产品(例如2007年5月23日授权公告的专利号为ZL02813731.0名称为“引线框架及其制造方法”发明专利产品)具有较好的接合性及焊接性；另外由于封装密度加大、打线数量增多，除了进一步缩减键合铜丝的线径外，还有必要在铜丝表面覆盖绝缘层，以减少短路现象发生。现在，行业中已经有人在探索用电镀钯层替代电镀金层的键合铜丝制造工艺，因为钯的成本要比金便宜得多，钯在高温、高湿或硫化物含量高的空气中性能稳定，能耐酸的侵蚀；钯有良好的延展性和可塑性，但又比金硬，能承受弯曲和摩擦，可长期保持良好的外观和光泽。但由于一直无法解决镀钯层与纯铜丝基体表面结合强度问题，直至本发明专利申请日仍未见有此类可大规模、产业化应用的镀钯键合铜丝专利文献在国家知识产权局网站公开。
发明内容
本发明要解决的技术问题是克服现有合金类键合铜丝表面易氧化、高温稳定性差以及镀金类键合铜丝生产成本高、电镀层硬度低不耐摩擦的缺陷和不足，向社会提供一种以纯铜丝为基体、以镀钯层替代镀金层的低成本、高性能键合铜丝产品制造方法，满足微电子器件芯片向小型化、多引脚高密度方向发展的需求。
本发明解决其技术问题所采用的技术方案是：镀钯键合铜丝以高纯铜丝为基体，所述基体表面覆有纯钯保护层；按照重量百分比，钯为1.35％-8.19％，其余为铜，两者之和等于100％。
所述镀钯键合铜丝直径为18μm-50μm；铜的纯度大于99.9995％，钯的纯度大于99.999％。
本发明专利镀钯键合铜丝的制造方法，包括以下步骤：
①提取高纯铜：以国家标准1号纯铜为原料，提取纯度大于99.9995％的高纯铜，清洗、烘干备用；
②制备单晶铜棒：将高纯铜置于金属单晶连铸室，连铸得到
Figure GSB00000516458100021
纵向和横向晶粒数均为1个的高纯铜棒；
③粗拔：将
Figure GSB00000516458100022
单晶铜棒拉拔成直径小于1mm的铜丝；
④热处理：将直径小于1mm的铜丝退火；
⑤表面镀钯：对退火后的铜丝电镀纯钯保护层，电镀用钯的纯度要求大于99.999％，按照纯铜密度为8.92g/cm3、纯钯密度为12.0g/cm3，镀钯层的重量百分比控制在1.35％-8.19％，其余为铜；
⑥精拔：将前述电镀有纯钯保护层的铜丝，精密拉拔成的镀钯键合铜丝；
⑦热处理：将镀钯键合铜丝连续退火；
⑧表面清洗：先用酸液酸洗，再由高纯水清洗、烘干；
⑨分卷：单卷定尺。
在所述③粗拔步骤，是将
Figure GSB00000516458100024
单晶铜棒拉拔成
Figure GSB00000516458100025
的铜丝。
在所述⑤表面镀金步骤，镀层厚度控制在0.5μm-3μm，按照纯铜密度为8.92g/cm3、纯钯密度为12.0g/cm3换算，可得知镀钯层重量百分比为1.35％-8.19％。
在所述⑥精拔步骤，将电镀有纯钯保护层的铜丝精密拉拔成
Figure GSB00000516458100026
的键合铜丝。
本发明镀钯键合铜丝的制造方法，摒弃了传统工艺通常采用的——先拉拔、后电镀即直接应用的落后工艺；而是先制成直径小于1mm的铜丝后，电镀一定厚度的纯钯保护层，镀钯层厚度主要根据键合铜丝成品线径确定，成品线径越小，拉拔率越大，则所需镀层越厚；反之所需镀层越薄；一般情况下，镀层厚度控制在0.5μm-3μm，按照纯铜密度为8.92g/cm3、纯钯密度为12.0g/cm3换算，可以得知镀的重量百分比为1.35％-8.19％，其余为铜；电镀后的半成品再经多道次工序精密拉拔成
Figure GSB00000516458100031
等不同规格的镀钯键合铜丝成品。在将电镀有纯钯保护层的
Figure GSB00000516458100032
纯铜丝精密拉拔成镀钯键合铜丝成品过程中，镀钯保护层的材质更加致密、均匀，表面光滑、线型一致，基体表面与镀钯层之间钯、铜分子互相交融、渗透，镀钯层结合强度大幅提高，可以有效提升键合铜丝的抗氧化性能，确保成品外观保持银白色金属光泽，大大延长键合铜丝产品拆封后的保质期；又由于成品机械强度的提高、抗氧化性能提升，有利于进一步缩小键合铜丝的线径，缩短焊接间距，更加适用于高密度、多引脚集成电路封装。本发明专利制造方法具有构思新颖、工序简单、受益显著的优点，可以广泛应用于各类复合型结构的金属键合丝产品制造领域。
附图说明
图1是本发明产品制造方法流程示意图。
具体实施方式
下面结合附图通过对两个实施例的描述，详细叙述本发明镀钯键合铜丝的制造方法技术方案。
实施例一
①提取高纯铜：将硝酸铜溶液按1∶4比例加高纯水进行稀释，配制成电解液；以国家标准1号纯铜作为阳极浸入电解液，并确保有95％体积比的纯铜浸入电解液中；以高纯铜箔作为阴极浸入电解液中，同样确保有95％体积比的高纯铜箔浸入电解液中；在阳极、阴极之间输入7-9V、2.5-3.5A的直流电，以补充新鲜电解液方式维持电解液温度不超过60℃；待阴极积聚纯度大于99.9995％的高纯铜，及时更换高纯铜箔，再以清洗、烘干备用。
②制备单晶铜棒：在一个有氮气保护的水平连铸金属单晶的连铸室，加入提纯所得的纯度大于99.9995％的高纯铜；应用中频感应加热至1090-1110℃，待完全熔化、精炼和除气后，将熔液注入连铸室中间的储液池保温，在维持2-5L/min净化氮气流量的连铸室中，完成对纯铜熔液的水平单晶连铸，得到
Figure GSB00000516458100033
纵向和横向晶粒数均为1个的高纯铜棒；单晶铜棒可有效降低铜丝的电阻率、提高导电率，增强其搞氧化性能。本工序更为详细的方法及其所应用设备，可参阅国家知识产权局于2008年4月30日授权公告的ZL200510023514.X名称为“金属单晶连铸工艺的控制方法及装备”发明专利技术，应属于公知技术范畴。
③粗拔：应用常规拉拔设备和工艺，将
Figure GSB00000516458100041
单晶铜棒经多道次工序，拉拔成
Figure GSB00000516458100042
的铜丝。
④热处理：将
Figure GSB00000516458100043
的铜丝置于退火炉中，在300℃温度下保温25min；保温期间通以氮气保护，然后随炉冷却。
⑤表面镀钯：应用常规电镀设备和工艺，对退火后的
Figure GSB00000516458100044
铜丝电镀纯钯防氧化保护层，电镀用钯的纯度要求大于99.999％；电流密度1-1.2A/dm2，铜丝速度为4-5m/min，镀层厚度控制在0.5μm；镀钯后的铜丝产品，按照纯铜密度为8.92g/cm3、纯钯密度为12.0g/cm3换算，可得知钯的重量百分比为1.35％，其余为铜。
⑥精拔：应用常规精密拉拔设备和工艺，将前述电镀有纯钯防氧化保护层的
Figure GSB00000516458100045
铜丝经多道次工序，精密拉拔成
Figure GSB00000516458100046
的镀钯键合铜丝；对于此
Figure GSB00000516458100047
的镀钯键合铜丝，按照金属压延加工中体积不变定律，即在任一截面上，钯面积与铜面积之比始终是相同的，所以可换算出纯钯防氧化保护层的厚度为0.057μm，此厚度镀钯层可以有效隔离铜丝表面与空气的接触，大大增强成品抗氧化性能，确保外观保持银白色金属光泽，有效延长键合铜丝产品拆封后的保质期。
⑦热处理：将镀钯键合铜丝由退火炉在350℃温度下连续退火，键合铜丝线速度为65m/min。
⑧表面清洗：先用浓度为1-2％的酸液进行酸洗，再由高纯水清洗两次后烘干。
⑨分卷：以500m为单卷定尺，控制绕丝张力为8g，绕丝速度为60-65m/min，线间距4mm。
实施例二
步骤①至步骤④同实施例一。
⑤表面镀钯：应用常规电镀设备和工艺，对退火后的铜丝电镀纯钯防氧化保护层，电镀用钯的纯度要求大于99.999％；电流密度4-4.5A/dm2，铜丝速度为4-5m/min，镀层厚度控制在3μm；镀钯后的铜丝产品，按照纯铜密度为8.92g/cm3、纯钯密度为12.0g/cm3换算，可得知钯的重量百分比为8.19％，其余为铜。
⑥精拔：应用常规精密拉拔设备和工艺，将前述电镀有纯钯防氧化保护层的铜丝经多道次工序，精密拉拔成
Figure GSB000005164581000411
的镀钯键合铜丝；对于此
Figure GSB000005164581000412
的镀钯键合铜丝，按照金属压延加工中体积不变定律，即在任一截面上，钯面积与铜面积之比始终是相同的，所以可换算出纯钯防氧化保护层的厚度为0.34μm，此厚度镀钯层完全足以有效隔离铜丝表面与空气的接触，大大增强成品抗氧化性能，确保外观保持银白色金属光泽，有效延长键合铜丝产品拆封后的保质期。
其余步骤⑦至步骤⑨同实施例一。
本发明镀钯键合铜丝的制造方法，如实施例一和实施例二所述，摒弃了传统工艺采用的——先拉拔、后电镀即直接应用的落后工艺；而是先制成
Figure GSB00000516458100051
的铜丝后，电镀一定厚度的纯钯保护层，镀钯层的厚度主要根据键合铜丝成品线径确定，即成品线径越小，拉拔率越大，则所需镀层越厚；反之成品线径越大，拉拔率越小，所需镀层越薄；一般情况下镀层厚度控制在0.5μm-3μm，按照纯铜密度为8.92g/cm3、纯钯密度为12.0g/cm3换算，可以得知镀的重量百分比为1.35％-8.19％，其余为铜；电镀后的半成品再精密拉拔成
Figure GSB00000516458100052
等不同规格的镀钯键合铜丝成品。在精密拉拔过程中，镀钯层材质更加致密、均匀，表面光滑、线型一致，基体表面与镀钯层之间钯、铜分子互相交融、渗透，镀钯层结合强度大幅提高，可以有效提升键合铜丝的抗氧化性能，确保外观保持良好的金属光泽，大大延长键合铜丝产品拆封后的保质期。
将按照实施例一和实施例二方法制造的两种
Figure GSB00000516458100053
镀钯键合铜丝成品应用于封装工序时，其测试结果与纯铜键合丝的对比结果如下：
从上述对比结果表格可以得知，本发明专利方法制造的镀钯键合铜丝产品，其封装后的拉断力和推球剪切力(铲除焊点力)均明显高于相同规格的纯铜键合丝产品，与芯片焊盘、引线框架引脚的焊接牢固度更高，具备更加稳定的剪切断裂载荷。
将按照实施例一和实施例二方法制造的两种
Figure GSB00000516458100055
镀钯键合铜丝成品理化指标与等径的纯铜键合丝对比结果如下表：
  技术参数   实施例一成品   实施例二成品   φ23μm纯铜键合丝
  抗拉强度   230N/mm2(MPa)   250N/mm2(MPa)   ＞220N/mm2(MPa)
  屈服强度   135N/mm2(MPa)   150N/mm2(MPa)   ＞110N/mm2(MPa)
  线材硬度   95HV0.01   100HV0.01   90±10HV0.01
  铜球硬度   60-70HV0.01   70-80HV0.01   70-90HV0.01
  电阻率   1.5×10-8-1.63×10-8Ωm   1.5×10-8-1.67×10-8Ωm   1.6666-1.689×10-8Ωm
  熔断电流   最小0.4A，最大8.5A   最小0.4A，最大8.9A   最小0.37A，最大8.73A
  弧高范围   110-225μm   110-230μm   115-225μm
  弧长范围   最大290mil   最大300mil   最大280mil
从上述对比结果表格可以得知，本发明专利方法制造的镀钯键合铜丝产品，其机械强度要高于纯铜键合丝产品；成品键合丝硬度适中、焊接成球性好；由于机械强度的提高，可以进一步缩小键合丝的线径，缩短焊接间距，更加适用于高密度、多引脚集成电路封装；本产品可以有效提升键合铜丝的抗氧化性能，确保外观保持良好的金属光泽，大大延长键合铜丝产品拆封后的保质期。

Claims (6)

1.一种镀钯键合铜丝的制造方法，以高纯铜丝为基体，所述基体表面覆有纯钯保护层；按照重量百分比，钯为1.35％-8.19％，其余为铜，两者之和等于100％；所述镀钯键合铜丝直径为18μm-50μm，铜的纯度大于99.9995％，钯的纯度大于99.999％；它包括以下步骤：
①提取高纯铜：以国家标准1号纯铜为原料，提取纯度大于99.9995％的高纯铜，清洗、烘干备用；
②制备单晶铜棒：将高纯铜置于金属单晶连铸室，连铸得到
Figure FSB00000516458000011
纵向和横向晶粒数均为1个的高纯铜棒；
③粗拔：将
Figure FSB00000516458000012
单晶铜棒拉拔成直径小于1mm的铜丝；
④热处理：将直径小于1mm的铜丝退火；
⑤表面镀钯：对退火后的铜丝电镀纯钯保护层，电镀用钯的纯度要求大于99.999％，按照纯铜密度为8.92g/cm3、纯钯密度为12.0g/cm3，镀钯层的重量百分比控制在1.35％-8.19％，其余为铜；
⑥精拔：将前述电镀有纯钯保护层的铜丝，精密拉拔成
Figure FSB00000516458000013
的镀钯键合铜丝；
⑦热处理：将镀钯键合铜丝连续退火；
⑧表面清洗：先用酸液酸洗，再由高纯水清洗、烘干；
⑨分卷：单卷定尺。
2.如权利要求1所述镀钯键合铜丝的制造方法，其特征在于：在所述③粗拔步骤，是将
Figure FSB00000516458000014
单晶铜棒拉拔成
Figure FSB00000516458000015
的铜丝。
3.如权利要求2所述镀钯键合铜丝的制造方法，其特征在于：在所述⑤表面镀钯步骤，镀钯层厚度控制在0.5μm，按照纯铜密度为8.92g/cm3、纯钯密度为12.0g/cm3换算，可得知镀钯层重量百分比为1.35％。
4.如权利要求2所述镀钯键合铜丝的制造方法，其特征在于：在所述⑤表面镀钯步骤，镀钯层厚度控制在3μm，按照纯铜密度为8.92g/cm3、纯钯密度为12.0g/cm3换算，可得知镀钯层重量百分比为8.19％。
5.如权利要求3所述镀钯键合铜丝的制造方法，其特征在于：在所述⑥精拔步骤，将电镀有纯钯保护层的铜丝，精密拉拔成
Figure FSB00000516458000021
的键合铜丝。
6.如权利要求4所述镀钯键合铜丝的制造方法，其特征在于：在所述⑥精拔步骤，将电镀有纯钯保护层的铜丝，精密拉拔成
Figure FSB00000516458000022
的键合铜丝。
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