CN109686713A - 一种镀金钯铜线及其制备方法 - Google Patents
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Abstract
本发明提供了一种镀金钯铜线及其制备方法,以高纯铜线为基体,将铜线设置在放线机上,所述基体表面覆有纯钯,包括以下步骤:步骤(1)超声波脱脂;步骤(2)酸洗;步骤(3)表面镀钯;步骤(4)表面镀金;步骤(5)精拔;步骤(6)烫洗;步骤(7)烘干;步骤(8)收线。本发明提供了一种以纯铜线为基体、以镀金层、镀钯层替代原纯镀金层的低成本、抗氧化性强、高性能键合铜线产品制造方法,满足微电子器件芯片向小型化、多引脚高密度方向发展的需求。
Description
技术领域
本发明涉及微电子后道封装工序用金属键合丝产品技术领域,具体涉及一种镀钯键合铜线的制造方法。
背景技术
微电子器件芯片的键合工序,是指在一定温度下采用超声加压的方式将键合丝两端分别焊接在芯片焊盘和引线框架引脚上,实现芯片内部电路与外部电路的连接。早期的键合丝多由纯金制成,但随着黄金资源的日益稀缺、价格持续攀升,微电子封装成本大幅上升,为此业内人士研发成功了以铜线产品来替代昂贵的金丝产品,此类比较典型的产品如国家知识产权局于2008年9月24日授权公告的ZL200610154487.4名称为“键合铜线及其制备方法”和2008年10月22日授权公告的ZL200610154485.5名称为“一种键合铜线及其制备方法”的发明专利产品。这些键合铜线价格低廉,且在拉伸、剪切强度和延展等方面的性能优于金丝,已经成功应用于如:DIP、SOP和功率器件等产品的封装生产。但是,随着微电子器件芯片行业日益、快速向小型化、多引脚高密度方向发展,对于键合铜线的性能要求也越来越苛刻,特别是在键合工艺中,要求键合铜线具备良好的耐高温氧化和耐热稳定性,以及与表面镀金、镀钯类引线框架产品具有较好的接合性及焊接性;另外由于封装密度加大、打线数量增多,除了进一步缩减键合铜线的线径外,还有必要在铜线表面覆盖绝缘层,以减少短路现象发生。因此,如何将镀金层、镀钯层与纯铜线基体表面结合成为目前迫在眉睫的问题。
发明内容
本发明克服现有技术中合金类键合铜线表面易氧化、高温稳定性差以及镀金类键合铜线生产成本高、电镀层硬度低不耐摩擦的缺陷和不足,提供了一种以纯铜线为基体、以镀金层、镀钯层替代原纯镀金层的低成本、抗氧化性强、高性能键合铜线产品制造方法,满足微电子器件芯片向小型化、多引脚高密度方向发展的需求。
本发明是通过以下技术方案实现的:
一种镀金钯铜线及其制备方法,以57.75微米的高纯铜线为基体,将铜线设置在放线机上,所述基体表面覆有纯钯、纯金保护层;按照重量百分比,钯为1.2%-8.8%,金为0.8-7.2%,其余为铜,三者之和等于100%;其中,铜的纯度大于99.9995%、钯的纯度大于99.999%、金的纯度大于99.999%;包括以下步骤:
步骤(1)超声波脱脂:先利于超声波脱脂技术对粘附在57.75微米的高纯铜线表面的油脂、污垢进行迅速清除,然后再利用高纯水对57.75微米的高纯铜线表面进行清洗;
步骤(2)酸洗:在步骤(1)的基础上,利用酸液对57.75微米的高纯铜线表面进行酸洗,酸洗后再由高纯水清洗、烘干,备用;
步骤(3)表面镀钯:对酸洗后的57.75微米的高纯铜线通过镀钯漕进行电镀纯钯保护层,电镀纯钯的纯度要求大于99.999%,镀钯层的重量百分比控制在1.2%-8.8%,其余为铜;
步骤(4)表面镀金:在步骤(3)的基础上,对57.75微米的高纯铜线通过金漕进行电镀纯金保护层,电镀纯金的纯度要求大于99.999%,镀金层的重量百分比控制在0.8% -7.2%,其余为铜;
步骤(5)精拔:将前述电镀有纯钯、纯金保护层的57.75微米的高纯铜线,精密拉拔成的镀金钯键合铜线;
步骤(6)烫洗:对步骤(5)精拔后的收线进行高纯属水清洗,然后再置入温度为60度的盐水中汤洗;
步骤(7)烘干:在步骤(6)的基础上,将镀金钯键合铜线穿过真空烘干机进行烘干,烘干温度为80度;
步骤(8)收线:对成型的镀金钯键合铜线进行收线。
作为上述技术方案的改进,所述57.75微米的高纯铜线是以国家标准1号纯铜为原料,提取纯度大于99.9995%的高纯铜线,其直径为57.75微米。
作为上述技术方案的改进,步骤(3)中镀钯层厚度控制在0.45μm,步骤(4)中镀金层厚度控制在0.35μm。
作为上述技术方案的改进,步骤(5)所述精拔,是将步骤(3)、步骤(4)电镀有纯钯、纯金保护层的铜线精密拉拔成的键合铜线。
本发明的有益效果:
本发明将电镀有纯钯、纯金保护层的纯铜线精密拉拔成镀金钯键合铜线成品过程中,镀金钯保护层的材质更加致密、均匀,表面光滑、线型一致,基体表面与镀金钯层之间钯、铜分子互相交融、渗透,镀金钯层结合强度大幅提高,可以有效提升键合铜线的抗氧化性能,确保成品外观保持银白色金属光泽,大大延长键合铜线产品拆封后的保质期;又由于成品机械强度的提高、抗氧化性能提升,有利于进一步缩小键合铜线的线径,缩短焊接间距,更加适用于高密度、多引脚集成电路封装。
本发明专利制造方法具有构思新颖、工序简单、受益显著,可以广泛应用于各类复合型结构的金属键合丝产品制造领域。
具体实施方式
一、本发明所述57.75微米的高纯铜线的制备如下:将硝酸铜溶液按1:4比例加高纯水进行稀释,配制成电解液;以国家标准1号纯铜作为阳极浸入电解液,并确保有95%体积比的纯铜浸入电解液中;以高纯铜箔作为阴极浸入电解液中,同样确保有95%体积比的高纯铜箔浸入电解液中;在阳极、阴极之间输入7-9V、2.5-3.5A的直流电,以补充新鲜电解液方式维持电解液温度不超过60℃;待阴极积聚纯度大于99.9995%的高纯铜,及时更换高纯铜箔,再以清洗、烘干备用;
二、将上述备用的高纯铜箔再经制备单晶铜棒:将高纯铜置于金属单晶连铸室,连铸得到纵向和横向晶粒数均为1个的高纯铜棒;粗拔:将单晶铜棒拉拔成直径57.75微米的铜线;热处理:最后将直径57.75微米的铜线退火,制得上述所述待用的57.75微米的高纯铜线。
实施例1:
一种镀金钯铜线及其制备方法,以57.75微米的高纯铜线为基体,将铜线设置在放线机上,所述基体表面覆有纯钯、纯金保护层;按照重量百分比,钯为1.2%-8.8%,金为0.8-7.2%,其余为铜,三者之和等于100%;其中,铜的纯度大于99.9995%、钯的纯度大于99.999%、金的纯度大于99.999%;包括以下步骤:
步骤(1)超声波脱脂:先利于超声波脱脂技术对粘附在57.75微米的高纯铜线表面的油脂、污垢进行迅速清除,然后再利用高纯水对57.75微米的高纯铜线表面进行清洗;
步骤(2)酸洗:在步骤(1)的基础上,利用3-5%的酸液对57.75微米的高纯铜线表面进行酸洗,酸洗后再由高纯水清洗、烘干,备用;
步骤(3)表面镀钯:对酸洗后的57.75微米的高纯铜线通过镀钯漕进行电镀纯钯保护层,电流密度1-1.2A/dm2,铜线速度为4-5m/min,电镀纯钯的纯度要求大于99.999%,镀钯层的重量百分比控制在1.2%-8.8%,其余为铜;
步骤(4)表面镀金:在步骤(3)的基础上,对57.75微米的高纯铜线通过金漕进行电镀纯金保护层,电流密度1.2-1.6A/dm2,铜线速度为7-8m/min,电镀纯金的纯度要求大于99.999%,镀金层的重量百分比控制在0.8%-7.2%,其余为铜;
步骤(5)精拔:将前述电镀有纯钯、纯金保护层的57.75微米的高纯铜线,精密拉拔成的镀金钯键合铜线;具体地,应用常规精密拉拔设备和工艺,将前述电镀有纯金、纯钯防氧化保护层的铜线经多道次工序,精密拉拔成的镀金钯键合铜线;对于此镀金钯键合铜线,按照金属压延加工中体积不变定律,即在任一截面上,金、钯面积与铜面积之比始终是相同的,所以得出纯金钯防氧化保护层的厚度为0.080μm,此厚度镀金钯层可以有效隔离铜线表面与空气的接触,大大增强成品抗氧化性能,确保外观保持银白色金属光泽,有效延长键合铜线产品拆封后的保质期
步骤(6)烫洗:对步骤(5)精拔后的收线进行高纯属水清洗,然后再置入温度为60度的盐水中汤洗;
步骤(7)烘干:在步骤(6)的基础上,将镀金钯键合铜线穿过真空烘干机进行烘干,烘干温度为80度,其真空烘干,避免了镀金钯键合铜线与空气接触;
步骤(8)收线:对成型的镀金钯键合铜线进行收线;具体地,以500m为单卷定尺,控制绕线张力为8g,收线速度控制在55-65m/min。
具体地,所述57.75微米的高纯铜线是以国家标准1号纯铜为原料,提取纯度大于99.9995%的高纯铜线,其直径为57.75微米;步骤(3)中镀钯层厚度控制在0.045μm,步骤(4)中镀金层厚度控制在0.035μm;步骤(5)所述精拔,是将步骤(3)、步骤(4)电镀有纯钯、纯金保护层的铜线精密拉拔成的键合铜线。本发明将电镀有纯钯、纯金保护层的纯铜线精密拉拔成镀金钯键合铜线成品过程中,镀金钯保护层的材质更加致密、均匀,表面光滑、线型一致,基体表面与镀金钯层之间钯、铜分子互相交融、渗透,镀金钯层结合强度大幅提高,可以有效提升键合铜线的抗氧化性能,确保成品外观保持银白色金属光泽,大大延长键合铜线产品拆封后的保质期;又由于成品机械强度的提高、抗氧化性能提升,有利于进一步缩小键合铜线的线径,缩短焊接间距,更加适用于高密度、多引脚集成电路封装。
实施例2:
删去步骤(4)表面镀金的工艺,其余步骤(1)、(2)、(3)、(5)、(6)、(7)、(8)均与实施例1相同。
即为:一种镀金钯铜线及其制备方法,以57.75微米的高纯铜线为基体,将铜线设置在放线机上,所述基体表面覆有纯钯保护层;其中,铜的纯度大于99.9995%、钯的纯度大于 99.999%;包括以下步骤:
步骤(1)超声波脱脂:先利于超声波脱脂技术对粘附在57.75微米的高纯铜线表面的油脂、污垢进行迅速清除,然后再利用高纯水对57.75微米的高纯铜线表面进行清洗;
步骤(2)酸洗:在步骤(1)的基础上,利用3-5%的酸液对57.75微米的高纯铜线表面进行酸洗,酸洗后再由高纯水清洗、烘干,备用;
步骤(3)表面镀钯:对酸洗后的57.75微米的高纯铜线通过镀钯漕进行电镀纯钯保护层,电流密度1-1.2A/dm2,铜线速度为4-5m/min,电镀纯钯的纯度要求大于99.999%,镀钯层的重量百分比控制在1.2%-8.8%,其余为铜;
步骤(5)精拔:将前述电镀有纯钯保护层的57.75微米的高纯铜线,精密拉拔成的镀钯键合铜线;具体地,应用常规精密拉拔设备和工艺,将前述电镀有纯钯防氧化保护层的铜线经多道次工序,精密拉拔成的镀钯键合铜线;对于此镀钯键合铜线,按照金属压延加工中体积不变定律,即在任一截面上,钯面积与铜面积之比始终是相同的,所以得出纯钯防氧化保护层的厚度为0.080μm,此厚度镀钯层可以有效隔离铜线表面与空气的接触,大大增强成品抗氧化性能,确保外观保持银白色金属光泽,有效延长键合铜线产品拆封后的保质期
步骤(6)烫洗:对步骤(5)精拔后的收线进行高纯属水清洗,然后再置入温度为60度的盐水中汤洗;
步骤(7)烘干:在步骤(6)的基础上,将镀钯键合铜线穿过真空烘干机进行烘干,烘干温度为80度,其真空烘干,避免了镀钯键合铜线与空气接触;
步骤(8)收线:对成型的镀钯键合铜线进行收线;具体地,以500m为单卷定尺,控制绕线张力为8g,收线速度控制在55-65m/min。
将按照实施例1和实施例2相同的方法制造两种不同的键合铜线(一种含有镀金、钯保护层;另外,是只含有镀钯保护层)成品应用于封装工序时,其测试结果对比结果如下:
从上述对比结果表格可以得知,本发明所述配料及方法制造的镀金钯键合铜线产品,其封装后的拉断力和推球剪切力(铲除焊点力)均明显高于相同规格的镀钯键合铜线产品,与芯片焊盘、引线框架引脚的焊接牢固度更高,具备更加稳定的剪切断裂载荷。
此外,从上述对比及内容可以得知,本发明方法制造的镀钯键合铜线产品,其机械强度要高于纯镀钯保护层的铜键合丝产品;成品键合丝硬度适中、焊接成球性好;由于机械强度的提高,可以进一步缩小键合丝的线径,缩短焊接间距,更加适用于高密度、多引脚集成电路封装;本产品可以有效提升键合铜线的抗氧化性能,确保外观保持良好的金属光泽,大大延长键合铜线产品拆封后的保质期。
Claims (4)
1.一种镀金钯铜线及其制备方法,其特征在于:以57.75微米的高纯铜线为基体,将铜线设置在放线机上,所述基体表面覆有纯钯、纯金保护层;按照重量百分比,钯为1.2%-8.8%,金为0.8-7.2%,其余为铜,三者之和等于100%;其中,铜的纯度大于99.9995%、钯的纯度大于99.999%、金的纯度大于99.999%;包括以下步骤:
步骤(1)超声波脱脂:先利于超声波脱脂技术对粘附在57.75微米的高纯铜线表面的油脂、污垢进行迅速清除,然后再利用高纯水对57.75微米的高纯铜线表面进行清洗;
步骤(2)酸洗:在步骤(1)的基础上,利用酸液对57.75微米的高纯铜线表面进行酸洗,酸洗后再由高纯水清洗、烘干,备用;
步骤(3)表面镀钯:对酸洗后的57.75微米的高纯铜线通过镀钯漕进行电镀纯钯保护层,电镀纯钯的纯度要求大于99.999%,镀钯层的重量百分比控制在1.2%-8.8%,其余为铜;
步骤(4)表面镀金:在步骤(3)的基础上,对57.75微米的高纯铜线通过金漕进行电镀纯金保护层,电镀纯金的纯度要求大于99.999%,镀金层的重量百分比控制在0.8%-7.2%,其余为铜;
步骤(5)精拔:将前述电镀有纯钯、纯金保护层的57.75微米的高纯铜线,精密拉拔成的镀金钯键合铜线;
步骤(6)烫洗:对步骤(5)精拔后的收线进行高纯属水清洗,然后再置入温度为60度的盐水中汤洗;
步骤(7)烘干:在步骤(6)的基础上,将镀金钯键合铜线穿过真空烘干机进行烘干,烘干温度为80度;
步骤(8)收线:对成型的镀金钯键合铜线进行收线。
2.根据权利要求1所述一种镀金钯铜线及其制备方法,其特征在于:所述57.75微米的高纯铜线是以国家标准1号纯铜为原料,提取纯度大于99.9995%的高纯铜线,其直径为57.75微米。
3.根据权利要求1所述一种镀金钯铜线及其制备方法,其特征在于:步骤(3)中镀钯层厚度控制在0.45μm,步骤(4)中镀金层厚度控制在0.35μm。
4.根据权利要求1所述一种镀金钯铜线及其制备方法,其特征在于:步骤(5)所述精拔,是将步骤(3)、步骤(4)电镀有纯钯、纯金保护层的铜线精密拉拔成的键合铜线。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116657207A (zh) * | 2023-06-25 | 2023-08-29 | 上海万生合金材料有限公司 | 一种铜镀钯金键合线及其电镀工艺 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101707194A (zh) * | 2009-11-11 | 2010-05-12 | 宁波康强电子股份有限公司 | 一种镀钯键合铜丝及其制造方法 |
CN102263038A (zh) * | 2011-08-19 | 2011-11-30 | 张若京 | 键合铜丝在生产过程中的表面处理技术 |
CN102586830A (zh) * | 2011-01-10 | 2012-07-18 | 深圳市奥美特科技有限公司 | 金属丝表面镀金或镀钯的设备及方法 |
CN103219312A (zh) * | 2013-03-01 | 2013-07-24 | 溧阳市虹翔机械制造有限公司 | 一种镀钯镀金的双镀层键合铜丝 |
CN103681570A (zh) * | 2013-12-05 | 2014-03-26 | 昆山矽格玛材料科技有限公司 | 封装用键合丝及其制备方法 |
CN203834037U (zh) * | 2014-04-21 | 2014-09-17 | 大亚电线电缆股份有限公司 | 线材镀钯金设备 |
CN106086962A (zh) * | 2016-06-06 | 2016-11-09 | 上海铭沣半导体科技有限公司 | 一种封装用镀金钯键合铜线的生产工艺 |
CN108122877A (zh) * | 2017-12-21 | 2018-06-05 | 汕头市骏码凯撒有限公司 | 薄金铜合金线及其制造方法 |
-
2018
- 2018-12-11 CN CN201811511597.0A patent/CN109686713A/zh active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101707194A (zh) * | 2009-11-11 | 2010-05-12 | 宁波康强电子股份有限公司 | 一种镀钯键合铜丝及其制造方法 |
CN102586830A (zh) * | 2011-01-10 | 2012-07-18 | 深圳市奥美特科技有限公司 | 金属丝表面镀金或镀钯的设备及方法 |
CN102263038A (zh) * | 2011-08-19 | 2011-11-30 | 张若京 | 键合铜丝在生产过程中的表面处理技术 |
CN103219312A (zh) * | 2013-03-01 | 2013-07-24 | 溧阳市虹翔机械制造有限公司 | 一种镀钯镀金的双镀层键合铜丝 |
CN103681570A (zh) * | 2013-12-05 | 2014-03-26 | 昆山矽格玛材料科技有限公司 | 封装用键合丝及其制备方法 |
CN203834037U (zh) * | 2014-04-21 | 2014-09-17 | 大亚电线电缆股份有限公司 | 线材镀钯金设备 |
CN106086962A (zh) * | 2016-06-06 | 2016-11-09 | 上海铭沣半导体科技有限公司 | 一种封装用镀金钯键合铜线的生产工艺 |
CN108122877A (zh) * | 2017-12-21 | 2018-06-05 | 汕头市骏码凯撒有限公司 | 薄金铜合金线及其制造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN116657207A (zh) * | 2023-06-25 | 2023-08-29 | 上海万生合金材料有限公司 | 一种铜镀钯金键合线及其电镀工艺 |
CN116657207B (zh) * | 2023-06-25 | 2024-04-26 | 上海万生合金材料有限公司 | 一种铜镀钯金键合线及其电镀工艺 |
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