CN101593734A - 倒装芯片封装及半导体芯片封装 - Google Patents

倒装芯片封装及半导体芯片封装 Download PDF

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CN101593734A
CN101593734A CNA200910143187XA CN200910143187A CN101593734A CN 101593734 A CN101593734 A CN 101593734A CN A200910143187X A CNA200910143187X A CN A200910143187XA CN 200910143187 A CN200910143187 A CN 200910143187A CN 101593734 A CN101593734 A CN 101593734A
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chip
bare chip
flip
package
semiconductor
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CN101593734B (zh
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陈南诚
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MediaTek Inc
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MediaTek Inc
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种倒装芯片封装及半导体芯片封装。其中倒装芯片封装包含：封装载体，具有上表面及下表面；半导体裸芯片，包含裸芯片面与裸芯片边缘，该半导体裸芯片倒装芯片设置于该封装载体的该上表面，其中，该裸芯片面上设置多个接合焊盘；重布线层结构，位于该半导体裸芯片与该封装载体之间，该重布线层结构包含重新布局金属层，其中，该重新布局金属层中的至少一部分凸出于该裸芯片边缘；以及多个凸点，排布于该重布线层结构之上，该多个凸点用以通过该封装载体电性连接于该半导体裸芯片。利用本发明可有效解决封装技术中基板上的凸点间距限制的问题，达到较佳的成本效益。

Description

倒装芯片封装及半导体芯片封装
技术领域
本发明涉及半导体封装技术，更具体地，涉及至少一种倒装芯片(flip-chip)封装及半导体芯片封装，可应用于具有多个引脚(pin)的情形。
背景技术
在本领域中，为了将裸芯片设置于基板上，可通过位于裸芯片及基板上的多个接合焊点来实现，在此过程中，可应用多种芯片封装技术，如球栅阵列(BallGrid Array，BGA)、线结合、倒装芯片等。为了确保电子产品或通信装置的小型化及功能多样化，半导体封装需要尺寸小、多引脚连接、高速率及多功能化。
输入输出(Input-Output，I/O)引脚数目的增加与高性能IC需求的增加，促进了倒装芯片封装技术的发展。倒装芯片技术使用位于芯片的多个接合焊盘上的多个凸点(bumps)与封装介质直接互连。芯片通过最短路径面向接合封装介质。该技术不仅可应用于单芯片封装，也可应用于更高整合水平的尺寸较大的封装，以及可容纳几个芯片以形成较大功能单元的更加精密的基板。倒装芯片技术使用区域阵列，具有实现与装置的互连密度最高与封装的互连电感较低的优点。
图1所示为传统芯片级倒装芯片封装(Flip-Chip Chip Scale Package，以下简称FCCSP)的截面示意图。如图1所示，FFCSP 100包含裸芯片101，裸芯片101倒置(face-down)于载体120的上表面(top surface)并通过多个焊点凸点(solderbump)102连接至载体120。于载体120的底面上提供多个焊球(solder ball)122用以连接电路板。典型的该封装构造在区域阵列或***凸点排布中使用共晶锡/铅倒装芯片互连(eutectic tin/lead flip-chip interconnect)技术，以取代标准的线结合互连。由于线结合回路的消除，使与裸芯片的连接电感较低，同时，路径密度(routingdensity)的增加优化了临界高频信号线路的电气路径。
图2所示为传统倒装芯片球栅阵列(Flip-Chip Ball Grid Array，以下简称FCBGA)封装的截面示意图。如图2所示，FCBGA封装200包含裸芯片201，裸芯片201倒置于芯片载体基板220的上表面并通过多个焊点凸点202连接芯片载体基板220。底胶(underfill)203填充裸芯片201与芯片载体基板220的顶面之间的空隙。芯片载体基板220可包含多层引线(trace)，该多层引线的不同层通过盲孔(blind via)222或埋孔(buried via)224互相连接在一起。例如，盲孔222可通过激光钻孔以实现较高密度。于芯片载体基板220的底面提供多个焊球226。FCBGA封装200允许高阶封装分辨率的设计，对于当前或未来高速网络及数字电视***而言，高阶封装分辨率是理想的。例如，为了维持信号完整性，该封装具有低电感、低介电损耗及阻抗匹配的特点。
然而，传统倒装芯片技术面临基板上的凸点间距限制的挑战。另外，高性能FCBGA封装因昂贵的芯片载体基板(典型的芯片载体基板包含1+2+1层构建材料或更多层构建材料)而价格不菲。由于倒装芯片技术的发展与凸点间距缩小远比裸芯片缩小与引脚数目的增长慢得多，因此，基板的凸点间距成为倒装芯片线路图的瓶颈所在。即便未来裸芯片缩小将超越基板载体的凸点间距分辨率的缩小。为了克服此技术差距，硅中介层(silicon interposer)技术与硅片直通孔技术(Through Silicon Via，TSV)技术是目前唯一且昂贵的解决方案。因此，产业界强烈需求一种改进型倒装芯片封装技术，以符合成本效益并解决基板上的凸点间距限制。
发明内容
有鉴于此，本发明的目的之一在于提供至少一种倒装芯片封装及半导体芯片封装，用以较低成本解决封装技术中基板上的凸点间距限制的问题。
本发明所披露了一种倒装芯片封装，包含：封装载体，具有上表面及下表面；半导体裸芯片，包含裸芯片面与裸芯片边缘，该半导体裸芯片倒装芯片设置于该封装载体的该上表面，其中，该裸芯片面上设置多个接合焊盘；重布线层结构，位于该半导体裸芯片与该封装载体之间，该重布线层结构包含重新布局金属层(re-routed metal layer)，其中，该重新布局金属层中的至少一部分凸出于该裸芯片边缘；以及多个凸点，排布于该重布线层结构之上，该多个凸点用以通过该封装载体电性连接于该半导体裸芯片。
本发明另提供一种半导体芯片封装，包含：半导体裸芯片，于该半导体裸芯片的裸芯片面上包含多个接合焊盘；胶体(mold cap)，包覆该半导体裸芯片的一部分；重新分布层，用以覆盖该裸芯片面及用于重新分布的该胶体的一部分，其中，该重新分布层外扩(fan out)该多个接合焊盘；多个凸点，位于该重新分布层之上；基板，包含两金属布线层，该两布线金属层分别位于该基板的上表面与下表面，其中，该多个凸点设置于该上表面；以及多个焊球，位于该基板的该下表面。
本发明另提供一种半导体芯片封装，包含：半导体裸芯片，包含多个接合焊盘，该多个接合焊盘设置于该半导体裸芯片的裸芯片面上；胶体，用以包覆该半导体裸芯片的一部分；重新分布层，覆盖该裸芯片面及该胶体的一部分，用以重新分布，其中，该重新分布层外扩该多个接合焊盘；多个凸点，位于该重新分布层之上；以及导线架(leadframe)，其中该半导体裸芯片设置于该导线架之上。
本发明另提供一种半导体芯片封装，包含：封装载体，具有上表面及下表面；外扩晶圆级装置，设置于该封装载体的该上表面；以及底胶，该底胶位于该封装载体与该外扩晶圆级装置之间。
本发明另提供一种半导体芯片封装，包含：封装载体，具有上表面与下表面；外扩晶圆级装置，设置于该封装载体的该上表面；以及胶饼，用以包覆该外扩晶圆级装置，以及该胶饼也用以填充该封装载体与该外扩晶圆级装置间的空隙。
本发明利用WLCSP技术并于芯片上外扩小间距的引脚或凸点，以便外扩接合焊盘满足当前的倒装芯片处理的最小间距需求。封装载体用以机械支持外扩重布线层结构，该重布线层结构具有超过三百个或更多个外扩接合焊盘。因此，利用本发明所提供的倒装芯片封装及半导体芯片封装，有效解决了封装技术中基板上的凸点间距限制的问题，并达到较佳的成本效益。
附图说明
图1所示为传统FCCSP的截面示意图。
图2所示为传统FCBGA封装的截面示意图。
图3所示为依据本发明的一实施例的外扩WLP 1a的截面示意图。
图4所示为制造图3所示的外扩WLP 1a的典型步骤的流程图。
图5所示为依据本发明的另一实施例的倒装芯片封装1的截面示意图。
图6所示为依据本发明的另一实施例的倒装芯片封装2的截面示意图。
图7所示为依据本发明的另一实施例的倒装芯片封装3的截面示意图。
图8所示为依据本发明的另一实施例的倒装芯片封装4的截面示意图。
图9所示为依据本发明的另一实施例的倒装芯片封装5的截面示意图。
图10所示为依据本发明的另一实施例的倒装芯片封装6的截面示意图。
图11所示为依据本发明的另一实施例的倒装芯片封装7的截面示意图。
图12所示为依据本发明的另一实施例的倒装芯片封装8的截面示意图。
具体实施方式
在说明书及权利要求当中使用了某些词汇来指称特定的组件。所属领域中具有通常知识者应可理解，硬件制造商可能会用不同的名词来称呼同一个组件。本说明书及权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。在通篇说明书及权利要求当中所提及的“包含”为一开放式的用语，故应解释成“包含但不限定于”。此外，“耦接”一词在此包含任何直接及间接的电性连接手段。因此，若文中描述第一装置耦接于第二装置，则代表该第一装置可直接电性连接于该第二装置，或通过其它装置或连接手段间接地电性连接至该第二装置。说明书后续描述为实施本发明的较佳实施方式，然该描述乃以说明本发明的一般原则为目的，并非用以限定本发明的范围。本发明的保护范围当视所附的权利要求所界定者为准。
本发明有关于应用于具有多个引脚数目的倒装芯片封装，本发明提供的倒装芯片封装可包含晶圆级封装(Wafar-Level Packaging，以下简称WLP)技术。晶圆级封装指于晶圆级别的封装集成电路，不同于晶圆切割后先将每个独立单元封装再进行组合的传统处理。由于WLP最后的封装实际上与裸芯片具有相同的尺寸，因此，WLP实质上是芯片级封装(Chip-Scale Packaging，CSP)技术。此外，晶圆级封装为晶圆级过程整合、封装、测试及烧入作准备，并为从硅开始到客户出货的过程实现最终流线型(streamlining)操作提供便利。
本发明利用WLCSP技术并于芯片上外扩小间距的引脚或凸点，以便外扩接合焊盘满足当前的倒装芯片处理的最小间距需求。封装载体用以机械支持外扩重布线层结构，该重布线层结构具有超过三百个外扩接合焊盘。
图3所示为依据本发明的一实施例的外扩WLP 1a的截面示意图。如图3所示，该外扩WLP 1a包含半导体裸芯片10及胶体16，其中，胶体16包覆(encapsulate)半导体裸芯片10的一部分，例如，半导体裸芯片10的整个表面，除形成接合焊盘11的裸芯片面外，均被胶体16所包覆。以及，直接于该裸芯片面上及胶体16的部分表面上提供重布线层结构12。
重布线层结构12包含重新布局金属层，该重新布局金属层重新分布位于半导体裸芯片10的裸芯片面上的多个接合焊盘11，以形成位于绝缘层上的多个外扩接合焊盘15。然后，焊球14附着于多个接合焊盘15。若图3的该外扩WLP 1a使用倒装芯片技术直接设置于印刷电路板(Printed Circuit Board，PCB)上，例如，典型的FCCSP需要0.5mm的球间距(ball pitch)P，则将外扩WLP 1a的最大焊球数目限制在300或更少。
图4所示为制造图3所示的外扩WLP 1a的典型步骤的流程图。外扩WLP 1a可通过如下几个步骤制造：
步骤52：晶圆切割与分离。
步骤54：晶圆重新配置。
步骤56：重新分布。
步骤58：植入球及封装分离。
需要理解，外扩WLP 1a可通过其它方法来制造。使用重新分布技术的不同公司使用不同材料及处理来制造外扩WLP。但是，所需实现步骤大致相同。
与传统晶圆制造处理相比，重新分布层及凸点技术增加一个额外的步骤，即在位于晶圆上的每个组件(例如芯片)上沉积(deposit)多层薄膜金属重新布局及互连***。该额外步骤在组件本身制造中使用类似并兼容光刻(photolithography)及薄膜沉积(thin film deposition)技术来实现的。互连的额外水平(additional level)将每个芯片的***多个接合焊盘重新分布至多个凸点底垫(Underbump Metal，以下简称UBM)焊盘的区域阵列。该多个凸点底垫焊盘最终配置于芯片表面之上。多个焊球或多个凸点用于将芯片连接至应用电路板，实质上，该多个焊球或多个凸点位于这些凸点底垫焊盘(例如外扩接合焊盘15)之上。
举例来说，覆盖(put over)晶圆的第一层用来封装该组件，该第一层通常为基于苯并环丁烯(benzocyclobutane，以下简称BCB)的聚合物电介质(polymerdielectric)，用以将组件电路与重布线***(例如，重布线层结构)相隔离。重布线金属层(rewiring metallization layer)通常为铜(Cu)、铝(Al)或特别制造的合金，该重布线金属层沉积于该电介质上。接着，该重布线金属层被另一BCB电介质所覆盖，该另一BCB电介质作为防焊剂(solder mask)。然后，凸点底垫覆盖实质上由多个焊球占据的位置。当凸点底垫附着该多个焊球后，使用倒装芯片技术将外扩WLP设置于电路板上。
图5所示为依据本发明的另一实施例的倒装芯片封装1的截面示意图。如图5所示，倒装芯片封装1包含半导体裸芯片10，半导体裸芯片10倒置于封装载体20的上表面(chip side)20a。例如，封装载体20为一封装基板，该封装基板包含金属布线层22a和金属布线层22b，金属布线层22a和金属布线层22b分别排布于上表面20a及下表面(opposite side)20b。金属布线层22a和金属布线层22b通过多个镀通孔(plated through hole)124彼此互连，依据本发明，多个镀通孔124通过机械式钻孔方法形成于封装载体20中。此外，需要理解，封装载体20可包含多层金属布线层，例如四层或六层。在另一实施例中，封装载体20可为导线架。
本发明的优点包含，相比激光钻孔封装载体(如图2所示的芯片载体基板220)，由于通过应用机械式钻孔后的封装载体20，因此，芯片封装的成本大幅降低。另外，如图3所示的原始外扩WLP对I/O引脚数目有限制(一般情况下少于300个)。本实施例可突破这个限制。
如图5所示，半导体裸芯片10可以为重新分布的多引脚数目芯片，例如，具有超过300个I/O引脚。通过举例的方式，倒装芯片封装1特别适用于至少500个I/O引脚数目的芯片。典型地，对于这样的多引脚数目应用，昂贵的芯片载体基板与1+2+1层构建材料(build up)或昂贵的硅中介层的合并是不可避免的。本发明的该实施例可使得如此昂贵的芯片载体基板与1+2+1层构建材料或昂贵的硅中介层的消除变为现实。
与本实施例密切相关的一个特征在于，直接在半导体裸芯片10的裸芯片面上提供至少一个重布线层结构12，以及胶体16包覆半导体裸芯片10的一部分，例如，半导体裸芯片10除形成多个接合焊盘11外的全部表面。依据本发明的实施例，重布线层结构12包含绝缘层12a、重新布局金属层12b及防焊层(solderresist layer)12c。重新布局金属层12b的至少一部分(如数字标号13所指示)突出了裸芯片边缘10a。也就是，重新布局金属层12b横向延伸出了胶体16的表面，胶体16实质上与裸芯片面10b共面，其中，多个接合焊盘11形成于裸芯片面10b之上。
重新布局金属层12b重新分布设置于半导体裸芯片10的裸芯片面上的多个接合焊盘11，以在绝缘层12a上形成多个外扩接合焊盘15，从而突破基板上的凸点间距限制。值得注意的是，多个外扩接合焊盘15可具有不同类型与选择，本发明的范围并不以此为限。上述“在绝缘层12a上”在此指多个外扩接合焊盘15排布于绝缘层12a的表面以及，例如，当绝缘层12a沉积后形成该多个结合焊盘15。
本发明的实施例可解决因裸芯片尺寸小而导致的另一凸点间距限制的问题，这是由于重布线层结构12于晶圆处理及制造期间形成，因此，重布线层结构12提供一更具弹性的间距尺度。相应地，由于重布线层结构12的外扩结构，增加了最大焊盘数目。
半导体裸芯片10通过重新布局金属层12b及多个焊点凸点14电性连接至封装载体20，其中多个焊点凸点14排布于重布线层结构12中定义的多个外扩接合焊盘15之上。焊点凸点14可包含共晶(例如，63％Sn，37％Pb)、高铅(例如，95％Pb，2.5％Ag)或无铅(例如，97.5％Sn，2.5％Ag)成分。依据本发明的实施例，多个焊点凸点14间的凸点间距P1大致为0.15-0.3mm。在下表面20b，多个焊球24的球间距P2大致为0.5mm，例如，FCCSP使用的电路板。
倒装芯片凸点有多种处理方法。以焊点凸点为例，UBM通过溅射(sputtering)、镀层(plating)或类似方式设置于接合焊盘之上。设置UBM的处理移除了接合焊盘上的保护氧化层(passivating oxide layer)，并定义了焊锡附着区域。接着，焊锡可通过适当的方法沉积于UBM之上，例如，蒸发、电镀、丝网印刷或针孔沉积(needle-depositing)等。
焊点凸点裸芯片10通过焊点软熔(solder reflow)附着于封装载体20之上。此后，底胶30添加于重新布线层结构12与封装载体20之间。底胶30可为特别设计的环氧化物(epoxy)，用以填充重布线层结构12与封装载体20之间的空隙，并包覆多个焊点凸点14。该设计用于控制因半导体裸芯片10与封装载体20间的热膨胀差而导致的焊接结合处的压力。一旦固化，则底胶30吸收压力，从而降低多个焊点凸点14上的压力，进而延长最终封装的寿命。
一方面，半导体芯片封装(如倒装芯片封装1)包含半导体裸芯片10、胶体16及重新分布层(例如，重布线层结构12)，其中，于半导体裸芯片10的裸芯片面上具有多个接合焊盘11，胶体16包覆半导体裸芯片10的一部分，以及重新分布层覆盖该裸芯片面及胶体16的一部分，用于重新分布。该重新分布层外扩多个接合焊盘11。多个凸点14排布于该重新分布层之上。半导体芯片封装更包含基板(如封装载体20)，该基板包含金属布线层22a与金属布线层22b，金属布线层22a与金属布线层22b分别位于上表面20a与下表面20b。多个凸点14设置于上表面20a之上。焊球24排布于基板(如封装载体20)的下表面20b。
另一方面，半导体芯片封装(如倒装芯片封装1)包含封装载体20，封装载体20包含金属布线层22a与金属布线层22b，金属布线层22a与金属布线层22b分别排布于封装载体20的上表面20a与下表面20b。外扩晶圆级装置(例如，外扩WLP 1a)设置于封装载体20的上表面20a。底胶30应用于封装体在20与外扩晶圆级装置之间。
对于多引脚数目的芯片，为了降低倒装芯片封装方案的成本，本发明的实施例使用具有成本竞争力的包含两层金属布线层、机械式钻孔的基板(例如，封装载体20)，来取代造价较高的方法，例如，多引脚数目芯片中使用昂贵的硅中介层。本发明的实施例的特征包含于裸芯片面上直接提供重布线层结构12。重布线层结构12的重新布局金属层12b重新分布位于该裸芯片面上的多个接合焊盘11，并形成多个外扩接合焊盘15，从而突破WLP中基板上的凸点间距限制。
图6所示为依据本发明的另一实施例的倒装芯片封装2的截面示意图，其中，相同的数字标号代表类似的层、组件或区域。如图6所示，倒装芯片封装2具有与图5所示的倒装芯片封装1极其相似的结构，所不同的处包含通过移除胶体16的一部分，露出了与裸芯片面10b相对的底面10c，使得胶体16的顶面16a与底面10c齐平。于半导体裸芯片10的露出的底面10c之上可设置外部散热槽(external heatsink)2a。通过此操作，提高了散热效率。当然，如图6所示的外部散热槽2a仅用以举例说明，并非用以限定本发明的变形或其它替代方法。也就是说，可适当设置于露出的底面10c上的其它类型的散热装置，也可应用于本实施例。
图7所示为依据本发明的另一实施例的倒装芯片封装3的截面示意图，其中，相同的数字标号代表类似的层、组件或区域。如图7所示，同样地，倒装芯片封装3具有类似于图5所示的倒装芯片封装1的结构，所不同的处包含露出了与裸芯片面10b相对的底面10c。底面10c通过移除胶体16的一上半部分而露出，使得胶体16的顶面16a实质上与底面10c齐平。倒装芯片封装3更包含散热层(heat-spreading layer)3a，散热层3a设置于半导体裸芯片10的露出的底面10c与胶体16的顶面16a之上。
图8所示为依据本发明的另一实施例的倒装芯片封装4的截面示意图，其中，相同的数字标号代表类似的层、组件或区域。如图8所示，倒装芯片封装4具有类似于图5所示的倒装芯片封装1的结构，所不同的处包含露出了与裸芯片面10b相对的底面10c。底面10c通过移除或切除胶体16的一上半部分而露出，使得胶体16的顶面16a实质上与底面10c齐平。于露出的底面10c之上设置散热盖(heat-spreading lid)302。当设置散热盖302之前，可将散热胶层(layer ofthermal glue)304设置于露出的底面10c之上。在另一实施例中，散热盖302可直接与露出的底面10c相接触。
图9所示为依据本发明的另一实施例的倒装芯片封装5的截面示意图，其中，相同的数字标号代表类似的层、组件或区域。如图9所示，倒装芯片封装5具有类似于图5所示的倒装芯片封装1的结构，所不同的处包含露出了与裸芯片面10b相对的底面10c。底面10c通过移除或切除胶体16的一上半部分而露出，使得胶体16的顶面16a实质上与底面10c齐平。倒装芯片封装5包含屏蔽半导体裸芯片10的一单体、无缝式散热片(heat spreader)402。同样地，当设置散热片402之前，可将散热胶层304应用于露出的底面10c之上。在另一实施例中，散热盖402可直接与露出的底面10c相接触。
图10所示为依据本发明的另一实施例的倒装芯片封装6的截面示意图，其中，相同的数字标号代表类似的层、组件或区域。如图10所示，倒装芯片封装6具有类似于图5所示的倒装芯片封装1的结构，所不同的处包含露出了与裸芯片面10b相对的底面10c。底面10c通过移除或切除胶体16的一上半部分而露出，使得胶体16的顶面16a实质上与底面10c齐平。倒装芯片封装6包含屏蔽半导体裸芯片10的一分体式散热片500，如图6所示，散热片500包含支架502与屏蔽504两部分。同样地，当设置散热片402之前，可将散热胶层304应用于露出的底面10c之上。在另一实施例中，屏蔽504可直接与露出的底面10c相接触。
图11所示为依据本发明的另一实施例的倒装芯片封装7的截面示意图，其中，相同的数字标号代表类似的层、组件或区域。如图11所示，由于多个焊点凸点14的凸点间距P1增大，因此，在一些情形下，节省了底胶。相反，胶饼(molding compound)600包覆外扩WLP 1a，并填充重布线层结构12与封装载体20的上表面20a间的空隙602，从而形成芯片级无底胶倒装芯片封装(mold-only flip-chip CSP)。
图12所示为依据本发明的另一实施例的倒装芯片封装8的截面示意图，其中，相同的数字标号代表类似的层、组件或区域。如图12所示，为了露出与裸芯片面10b相对的底面10c，移除或切除了胶饼600的上半部分与胶体16的上半部分。胶体16的顶面16a实质上与底面10c齐平。于底面10c之上设置外部散热槽2a。
上述的实施例仅用来例举本发明的实施方式，以及阐释本发明的技术特征，并非用来限制本发明的范畴。任何所属领域技术人员可依据本发明的精神轻易完成的改变或均等性的安排均属于本发明所主张的范围，本发明的权利范围应以权利要求为准。

Claims (21)

1.一种倒装芯片封装，其特征在于，该倒装芯片封装包含：
封装载体，具有上表面及下表面；
半导体裸芯片，包含裸芯片面与裸芯片边缘，该半导体裸芯片倒置于该封装载体的该上表面，其中，该裸芯片面上设置多个接合焊盘；
重布线层结构，位于该半导体裸芯片与该封装载体之间，该重布线层结构包含重新布局金属层，其中，该重新布局金属层中的至少一部分凸出于该裸芯片边缘；以及
多个凸点，排布于该重布线层结构之上，该多个凸点用以将该封装载体电性连接于该半导体裸芯片。
2.如权利要求1所述的倒装芯片封装，其特征在于，该封装载体为基板，该基板包含两金属布线层，该两金属布线层分别排布于该封装载体的该上表面与该下表面。
3.如权利要求2所述的倒装芯片封装，其特征在于，该两金属布线层通过多个金属穿孔电性连接，该多个金属穿孔通过机械式钻孔方法形成于该封装载体中。
4.如权利要求1所述的倒装芯片封装，其特征在于，该重新布局金属层重新分布位于该半导体裸芯片的该裸芯片面上的该多个接合焊盘，以形成多个外扩接合焊盘，以及该多个凸点分别设置于该多个外扩接合焊盘之上。
5.如权利要求1所述的倒装芯片封装，其特征在于，更包含底胶，该底胶位于该重布线层结构与该封装载体之间。
6.如权利要求1所述的倒装芯片封装，其特征在于，更包含胶体，该胶体包覆该半导体裸芯片。
7.如权利要求1所述的倒装芯片封装，其特征在于，该封装载体为导线架。
8.如权利要求1所述的倒装芯片封装，其特征在于，设置于该重布线层结构上的该多个凸点具有0.15-0.3mm的凸点间距。
9.一种半导体芯片封装，其特征在于，该半导体芯片封装包含：
半导体裸芯片，包含多个接合焊盘，该多个接合焊盘设置于该半导体裸芯片的裸芯片面上；
胶体，用以包覆该半导体裸芯片的一部分；
重新分布层，覆盖该裸芯片面及该胶体的一部分，用以重新分布，其中，该重新分布层外扩该多个接合焊盘；
多个凸点，位于该重新分布层之上；
基板，包含两金属布线层，该两布线金属层分别位于该基板的上表面与下表面，其中，该多个凸点设置于该上表面；以及
多个焊球，位于该基板的该下表面。
10.如权利要求9所述的半导体芯片封装，其特征在于，该两金属布线层通过多个金属穿孔互相电性连接，该多个金属穿孔通过机械式钻孔方法形成。
11.如权利要求9所述的半导体芯片封装，其特征在于，更包含底胶，该底胶位于该重新分布层与该基板之间。
12.如权利要求9所述的半导体芯片封装，其特征在于，位于该重新分布层上的该多个凸点具有0.15-0.3mm的凸点间距，以及位于该基板的该下表面的该多个焊球具有0.5mm的球间距。
13.一种半导体芯片封装，其特征在于，该半导体芯片封装包含：
半导体裸芯片，包含多个接合焊盘，该多个接合焊盘设置于该半导体裸芯片的裸芯片面上；
胶体，用以包覆该半导体裸芯片的一部分；
重新分布层，覆盖该裸芯片面及该胶体的一部分，用以重新分布，其中，该重新分布层外扩该多个接合焊盘；
多个凸点，位于该重新分布层之上；以及
导线架，其中该半导体裸芯片设置于该导线架之上。
14.一种半导体芯片封装，其特征在于，该半导体芯片封装包含：
封装载体，具有上表面及下表面；
外扩晶圆级装置，设置于该封装载体的该上表面；以及
底胶，该底胶位于该封装载体与该外扩晶圆级装置之间。
15.如权利要求14所述的半导体芯片封装，其特征在于，该外扩晶圆级装置包含：
半导体裸芯片；
胶体，用以包覆该半导体裸芯片的一部分；以及
重新分布层，用于外扩该半导体裸芯片的多个接合焊盘。
16.如权利要求15所述的半导体芯片封装，其特征在于，该外扩晶圆级装置更包含多个凸点，该多个位凸点于该重新分布层之上，该多个凸点具有0.15-0.3mm的凸点间距。
17.如权利要求14所述的半导体芯片封装，其特征在于，该封装载体为基板，该基板包含两金属布线层，该两金属布线层分别位于该封装载体的该上表面与该下表面，其中，该多个凸点排布于该上表面。
18.一种半导体芯片封装，其特征在于，该半导体芯片封装包含：
封装载体，具有上表面与下表面；
外扩晶圆级装置，设置于该封装载体的该上表面；以及
胶饼，用以包覆该外扩晶圆级装置，以及该胶饼也用以填充该封装载体与该外扩晶圆级装置间的空隙。
19.如权利要求18所述的半导体芯片封装，其特征在于，该外扩晶圆级装置包含：
半导体裸芯片；
胶体，用以包覆该半导体裸芯片的一部分；以及
重新分布层，用以外扩该半导体裸芯片的多个接合焊盘。
20.如权利要求19所述的半导体芯片封装，其特征在于，该外扩晶圆级装置更包含排布于该重新分布层上的多个凸点，以及该多个凸点具有0.15-0.3mm的凸点间距。
21.如权利要求18所述的半导体芯片封装，其特征在于，该封装载体为导线架或基板，该基板包含两金属布线层，该两金属布线层分别排布于该封装载体的该上表面与该下表面。
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