CN101436551B - 铜核层多层封装基板的制作方法 - Google Patents
铜核层多层封装基板的制作方法 Download PDFInfo
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- CN101436551B CN101436551B CN2008103054154A CN200810305415A CN101436551B CN 101436551 B CN101436551 B CN 101436551B CN 2008103054154 A CN2008103054154 A CN 2008103054154A CN 200810305415 A CN200810305415 A CN 200810305415A CN 101436551 B CN101436551 B CN 101436551B
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- layer
- copper
- substrate
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- 239000012792 core layer Substances 0.000 title claims description 25
- 229910052802 copper Inorganic materials 0.000 claims abstract description 86
- 239000010949 copper Substances 0.000 claims abstract description 86
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims description 66
- 229910052751 metal Inorganic materials 0.000 claims description 66
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000012800 visualization Methods 0.000 claims description 9
- 238000003466 welding Methods 0.000 claims description 9
- 238000007772 electroless plating Methods 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
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- 229920001721 polyimide Polymers 0.000 claims description 3
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- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
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- 239000003365 glass fiber Substances 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
- HGTDVVTWYKXXMI-UHFFFAOYSA-N pyrrole-2,5-dione;triazine Chemical compound C1=CN=NN=C1.O=C1NC(=O)C=C1 HGTDVVTWYKXXMI-UHFFFAOYSA-N 0.000 claims 1
- 238000004804 winding Methods 0.000 abstract 1
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Abstract
一种铜核层多层封装基板的制作方法,是从铜核基板为基础,开始制作单面、多层封装基板。本发明封装基板的特色在于具有高密度增层线路以提供电子组件相连时所需的绕线,同时并以铜板提供足够的刚性使封装制程可更为简易。待封装制程完成后,移除全部的铜核基板,则可使其电性独立并显露出球侧图案阻障层。藉此,使用本发明所制造的多层封装基板,可依实际需求形成具铜核基板支撑的铜核层多层封装基板,不仅可制作出超薄的封装结构,并且亦可有效达到改善超薄核层基板板弯翘问题、简化传统增层线路板制作流程及降低成品板厚的目的。
Description
技术领域:
本发明涉及一种铜核层多层封装基板的制作方法,尤指一种以铜核基板为基础,开始制作单面、多层封装基板的制作方法,于其中,该多层封装基板的结构包括一具高刚性支撑的铜板,且此铜板的一面具球侧图案阻障层与增层线路,另一面则无任何图案。
背景技术:
在一般多层封装基板的制作上,其制作方式通常是由核心基板开始,经过钻孔、电镀金属、塞孔及双面线路制作等方式,完成双面结构的内层核心板,之后再经由线路增层制程完成多层封装基板。如图23所示,其为一有核层封装基板的剖面示意图。首先,准备核心基板60,其中,该核心基板60由具预定厚度的芯层601及形成于此芯层601表面的线路层602所构成,且该芯层601中形成有数个电镀导通孔603,可藉以连接该芯层601表面的线路层602。
接着如图24~图27所示,对该核心基板60实施线路增层制程。首先,是于该核心基板60表面形成第一介电层61,且该第一介电层61表面形成有数个第一开口62,以露出该线路层602;之后,以无电电镀与电镀等方式于该第一介电层61外露的表面形成晶种层63,并于该晶种层63上形成图案化阻层64,且其图案化阻层64中并有数个第二开口65,以露出部份欲形成图案化线路的晶种层63;接着,利用电镀方式于该第二开口65中形成第一图案化线路层66及数个导电盲孔67,并使其第一图案化线路层66得以透过该数个导电盲孔67与该核心基板60的线路层602做电性导通,然后再进行移除该图案化阻层64与蚀刻,待完成后形成第一线路增层结构6a。同样地,该法可于该第一线路增层结构6a的最外层表面再运用相同的方式形成具有第二介电层68及第二图案化线路层69的第二线路增层结构6b,以逐步增层方式形成多层封装基板。然而,此种制作方法有布线密度低、层数多及流程复杂等缺点。
另外,亦有利用厚铜金属板当核心材料的方法,可于经过蚀刻及塞孔等方式完成一内层核心板后,再经由线路增层制程以完成多层封装基板。如图28~图30所示,其为另一有核层封装基板的剖面示意图。首先,准备核心基板70,该核心基板70为由一具预定厚度的金属层利用蚀刻与树脂塞孔701以及钻孔与电镀通孔702等方式形成的单层铜核心基板70;之后,利用上述线路增层方式,于该核心基板70表面形成第一介电层71及第一图案 化线路层72,藉此构成第一线路增层结构7a。该法亦与上述方法相同,可再利用一次线路增层方式于该第一线路增层结构7a的最外层表面形成第二介电层73及第二图案化线路层74,藉此构成第二线路增层结构7b,以逐步增层方式形成多层封装基板。然而,此种制作方法不仅其铜核心基板制作不易,且亦与上述方法相同,具有布线密度低及流程复杂等缺点。故,一般无法符合使用者于实际使用时所需。
发明内容:
本发明所要解决的技术问题是:针对上述现有技术的不足,提供一种铜核层多层封装基板的制作方法,所制造的多层封装基板,可依实际需求形成具铜核基板支撑的铜核层多层封装基板,不仅可制作出超薄的封装结构,并且亦可有效改善超薄核层基板板弯翘问题,简化传统增层线路板制作流程及降低成品板厚。
本发明的次要目的在于,从铜核基板为基础,开始制作的单面、多层封装基板,其结构包括一具高刚性支撑的铜板,且此铜板的一面具球侧图案阻障层与增层线路,另一面则无任何图案,于其中,各增层线路及置晶侧与球侧连接方式是以数个电镀盲、埋孔所导通。
本发明的另一目的在于,具有高密度增层线路以提供电子组件相连时所需的绕线,同时,并以铜板提供足够的刚性使封装制程可更为简易。
为了解决上述技术问题,本发明所采用的技术方案是:一种铜核层多层封装基板的制作方法,至少包含下列步骤:
(A)提供铜核基板;
(B)分别于该铜核基板的第一面上形成第一阻层,以及于该铜核基板的第二面上形成完全覆盖状的第二阻层,于其中,该第一阻层上形成数个第一开口,并显露其下该铜核基板的第一面;
(C)于数个第一开口中形成数金属层,以形成球侧电性接垫;
(D)移除该第一阻层及该第二阻层;
(E)于该铜核基板的第一面上形成第一介电层及第一金属层;
(F)于该第一金属层及该第一介电层上形成数个第二开口,并显露其下的球侧电性接垫;
(G)于数个第二开口中以及该球侧电性接垫与该第一金属层上形成第二金属层;
(H)分别于该第二金属层上形成第三阻层,以及于该铜核基板的第二面上形成完全覆盖状的第四阻层,于其中,该第三阻层上形成数个第三开口,并显露其下的第二金属层;
(I)移除该第三开口下方的第二金属层及第一金属层,并形成第一线路层;
(J)移除该第三阻层及该第四阻层,至此,完成具有铜核基板支撑并具电性连接的单层增层线路基板;
(L)于该单层增层线路基板上进行线路增层结构制作,于其中,在该第一线路层及该第一介电层上形成第二介电层,并且在该第二介电层上系形成复数个第五开口,以显露其下的第一线路层,接着于该第二介电层与数个第五开口表面形成第一晶种层,再分别于该第一晶种层上形成第六阻层,以及于该铜核基板的第二面上形成完全覆盖状的第七阻层,并于该第六阻层上形成数个第六开口,以显露其下的第一晶种层,之后于该第六开口中已显露的第一晶种层上形成第三金属层,最后移除该第六阻层、该第七阻层及该第一晶种层,以在该第二介电层上形成第二线路层,至此,完成具有铜核基板支撑并具电性连接的双层增层线路基板,并继续本步骤(L)增加线路增层结构,形成具更多层的封装基板;
(K)于该单层增层线路基板上进行置晶侧线路层制作,于其中,在该第一线路层表面形成第一防焊层,并且在该第一防焊层上形成数个第四开口,以显露该第一线路层作为电性连接垫的部分;接着于该铜核基板第二面上形成第五阻层,并于数个第四开口中形成第一阻障层,最后再移除该第五阻层,至此,完成具有完整图案化的置晶侧线路层与已图案化但仍完全电性短路的球侧线路层;
(M)于该双层增层线路基板上完成含封胶体的封装制程后,移除该铜核基板,并显露出预埋的数金属层,以形成球侧电性接垫。
如此,可依实际需求形成具铜核基板支撑的铜核层多层封装基板,不仅可制作出超薄的封装结构,并且可有效改善超薄核层基板板弯翘问题,简化传统增层线路板制作流程及降低成品板厚;具有高密度增层线路以提供电子组件相连时所需的绕线,同时,并以铜板提供足够的刚性使封装制程可更为简易。
附图说明
图1是本发明的制作流程示意图。
图2是本发明一实施例的多层封装基板的剖面示意图一。
图3是本发明一实施例的多层封装基板的剖面示意图二。
图4是本发明一实施例的多层封装基板的剖面示意图三。
图5是本发明一实施例的多层封装基板的剖面示意图四。
图6是本发明一实施例的多层封装基板的剖面示意图五。
图7是本发明一实施例的多层封装基板的剖面示意图六。
图8是本发明一实施例的多层封装基板的剖面示意图七。
图9是本发明一实施例的多层封装基板的剖面示意图八。
图10是本发明一实施例的多层封装基板的剖面示意图九。
图11是本发明一实施例的多层封装基板的剖面示意图十。
图12是本发明一实施例的多层封装基板的剖面示意图十一。
图13是本发明一实施例的多层封装基板的剖面示意图十二。
图14是本发明一实施例的多层封装基板的剖面示意图十三。
图15是本发明一实施例的多层封装基板的剖面示意图十四。
图16是本发明一实施例的多层封装基板的剖面示意图十五。
图17是本发明一实施例的多层封装基板的剖面示意图十六。
图18是本发明一实施例的多层封装基板的剖面示意图十七。
图19是本发明一实施例的多层封装基板的剖面示意图十八。
图20是本发明一实施例的多层封装基板的剖面示意图十九。
图21是本发明一实施例的多层封装基板的剖面示意图二十。
图22是本发明一实施例的多层封装基板的剖面示意图二十一。
图23是已知有核层封装基板的剖面示意图。
图24是已知实施线路增层的剖面示意图一。
图25是已知实施线路增层的剖面示意图二。
图26是已知实施线路增层的剖面示意图三。
图27是已知实施线路增层的剖面示意图四。
图28是另一已知有核层封装基板的剖面示意图。
图29是另一已知第一线路增层结构剖面示意图。
图30是另一已知第二路增层结构剖面示意图。
标号说明:
步骤(A)~(M)11~23 单层增层线路基板3
双层增层线路基板4 多层封装基板5
铜核基板30 第一、二阻层31、32
第一开口33 金属层34
第一介电层35 第一金属层36
第二开口37 第二金属层38
第三、四阻层39、40 第三开口41
第一线路层42 第二介电层43
第四开口44 第一晶种层45
第五、六阻层46、47 第五开口48
第三金属层49 第二线路层50
第一防焊层51 第六开口52
第七阻层53 第一阻障层54
封胶体55
第一、二线路增层结构6a、6b 第一、二线路增层结构7a、7b
核心基板60 芯层601
线路层602 电镀导通孔603
第一介电层61 第一开口62
晶种层63 图案化阻层64
第二开口65 第一图案化线路层66
导电盲孔67 第二介电层68
第二图案化线路层69 核心基板70
树脂塞孔701 电镀通孔702
第一介电层71 第一图案化线路层72
第二介电层73 第二图案化线路层74
具体实施方式:
请参阅图1所示,为本发明的制作流程示意图。如图所示:本发明为一种铜核层多层封装基板的制作方法,其至少包括下列步骤:
(A)提供铜核基板11:提供铜核基板,其中,该铜核基板为不含介电层材料的铜板;
(B)形成第一、二阻层及数个第一开口12:分别于该铜核基板的第一面上形成第一阻层,以及于该铜核基板的第二面上形成完全覆盖状的第二阻层,于其中,并以曝光及显影方式在该第一阻层上形成数个第一开口,以显露其下该铜核基板的第一面;
(C)形成数金属层13:以无电电镀与电镀方式于数个第一开口中形成数金属层,以形成球侧电性接垫;
(D)移除第一、二阻层14:以剥离方式移除该第一阻层及该第二阻层;
(E)形成第一介电层及第一金属层15:于该铜核基板的第一面上直接压合第一介电层及第一金属层,亦或是先采取贴合该第一介电层后,再形成该第一金属层;
(F)形成数个第二开口16:以镭射钻孔方式于该第一金属层及该第一介电层上形成数个第二开口,并显露其下的球侧电性接垫,其中,数个第二开口可先做开铜窗(Conformal Mask)后,再经由镭射钻孔方式形成,亦或是以直接镭射钻孔(LASER Direct)方式形成;
(G)形成第二金属层17:以无电电镀与电镀方式于数个第二开口中以及该球侧电性接垫与该第一金属层上形成第二金属层;
(H)形成第三、四阻层及数个第三开口18:分别于该第二金属层上形成第三阻层,以及于该铜核基板的第二面上形成完全覆盖状的第四阻层,于其中,并以曝光及显影方式在该第三阻层上形成数个第三开口,以显露其下的第二金属层;
(I)形成第一线路层19:以蚀刻方式移除该第三开口下方的第二金属层及第一金属层,并形成第一线路层;
(J)完成具有铜核基板支撑并具电性连接的单层增层线路基板20:以剥离方式移除该第三阻层及该第四阻层。至此,完成具有铜核基板支撑并具电性连接的单层增层线路基板,并可选择直接进行步骤(K)或步骤(L);
(K)进行置晶侧线路层制作21:于该单层增层线路基板上进行置晶侧线路层制作,于其中,在该第一线路层表面涂覆一层具绝缘保护用的第一防焊层,并以曝光及显影方式在该第一防焊层上形成数个第四开口,以显露该第一线路层作为电性连接垫的部分。接着于该铜核基板第二面上形成第五阻层,并于数个第四开口中形成第一阻障层,最后以剥离方式移除该第五阻层。至此,完成具有完整图案化的置晶侧线路层与已图案化但仍完全电性短路的球侧线路层,其中,该第一阻障层可为电镀镍金、无电镀镍金、电镀银或电镀锡中择其一;
?(L)进行线路增层结构制作22:于该单层增层线路基板上进行一线路增层结构制作,于其中,在该第一线路层及该第一介电层上形成第二介电层,并以镭射钻孔方式在该第二介电层上形成数个第五开口,以显露其下的第一线路层。接着以无电电镀与电镀方式于该第二介电层与数个第五开口表面形成第一晶种层,再分别于该第一晶种层上形成第六阻层,以及于该铜核基板的第二面上形成完全覆盖状的第七阻层,并利用曝光及显影方式于该第六阻层上形成数个第六开口,以显露其下的第一晶种层,之后再以电镀方式于该第六开口中已显露的第一晶种层上形成第三金属层,最后以剥离方式移除该第六阻层及该第七阻层,并以蚀 刻方式移除该第一晶种层,以在该第二介电层上形成第二线路层。至此,又再增加一层线路增层结构,完成具有铜核基板支撑并具电性连接的双层增层线路基板。并可继续本步骤(L)增加线路增层结构,形成具更多层的封装基板,亦或直接至该步骤(K)进行置晶侧线路层制作,其中,数个第五开口是可先做开铜窗后,再经由镭射钻孔方式形成,亦或是以直接镭射钻孔方式形成;以及
(M)形成球侧的电性接垫23:于该双层增层线路基板上完成一含封胶体的封装制程后,系以蚀刻方式移除该铜核基板,并显露出预埋的数金属层,以形成球侧电性接垫。
于其中,上述该第一~七阻层为以贴合、印刷或旋转涂布所为的干膜或湿膜的高感旋光性光阻;该第一、二介电层可为环氧树脂绝缘膜(Ajinomoto Build-up Film,ABF)、苯环丁烯(Benzocyclo-buthene,BCB)、双马来亚酰胺-三氮杂苯树脂(BismaleimideTriazine,BT)、环氧树脂板(FR4、FR5)、聚酰亚胺(Polyimide,PI)、聚四氟乙烯(Poly(tetra-floroethylene),PTFE)或环氧树脂及玻璃纤维所组成之一。
请参阅图2~图11所示,分别为本发明一实施例的多层封装基板剖面剖面示意图一、本发明一实施例的多层封装基板剖面示意图二、本发明一实施例的多层封装基板的剖面示意图三、本发明一实施例的多层封装基板剖面示意图四、本发明一实施例的多层封装基板剖面示意图五、本发明一实施例的多层封装基板剖面示意图六、本发明一实施例的多层封装基板剖面示意图七、本发明一实施例的多层封装基板的剖面示意图八、本发明一实施例的多层封装基板的剖面示意图九、及本发明一实施例的多层封装基板的剖面示意图十。如图所示:本发明于一较佳实施例中,是先提供铜核基板30,并分别于该铜核基板30的第一面上贴合高感旋光性高分子材料的第一阻层31,以及于该铜核基板30的第二面上贴合高感旋光性高分子材料制成的第二阻层32。并以曝光及显影方式于该第一阻层31上形成数个第一开口33,以显露其下该铜核基板30的第一面。接着并以电镀方式于数个第一开口33中形成数金属层34,以作为球侧电性接垫用,其中,该数金属层34为金/镍/铜三层复金属结构。
之后以剥离方式移除该第一、二阻层。接着于该铜核基板30的第一面上压合第一介电层35及第一金属层36,并以镭射钻孔方式在该第一金属层36与该第一介电层35上形成数个第二开口37,以显露其下的球侧电性接垫。之后,再以无电电镀与电镀方式于数个第二开口37内及该第一金属层36表面形成第二金属层38,其中,该第一、二金属层36、38皆为铜,且该第二金属层38是作为与该铜核基板30的电性连接用。
接着,分别于该第二金属层38上贴合高感旋光性高分子材料制成的第三阻层39,以 及于该铜核基板30的第二面上贴合高感旋光性高分子材料制成的第四阻层40。并以曝光及显影方式于该第三阻层39上形成数个第三开口41,以显露其下的第二金属层38。之后以蚀刻方式移除该第三开口41下的第一、二金属层,以形成第一线路层42,最后并移除该第三、四阻层。至此,完成具有铜核基板支撑并具电性连接的单层增层线路基板3。
请参阅图12~图16所示,分别为本发明一实施例的多层封装基板剖面示意图十一、本发明一实施例的多层封装基板的剖面示意图十二、本发明一实施例的多层封装基板的剖面示意图十三、本发明一实施例的多层封装基板的剖面示意图十四、及本发明一实施例的多层封装基板剖面示意图十五。如图所示:在本发明较佳实施例中,是先行进行线路增层结构的制作。首先于该第一线路层42与第一介电层35上贴压合为环氧树脂绝缘膜材料的第二介电层43,之后,以镭射钻孔方式于该第二介电层43上形成数个第四开口44,以显露其下的第一线路层42,并在该第二介电层43及该第四开口44表面以无电电镀与电镀方式形成第一晶种层45。之后分别于该第一晶种层45上贴合高感旋光性高分子材料制成的第五阻层46,以及于该铜核基板30的第二面上贴合高感旋光性高分子材料制成的第六阻层47,接着利用曝光及显影方式于该第五阻层46上形成数个第五开口48,然后再于数个第五开口48中电镀第三金属层49,最后移除该第五、六阻层,并再以蚀刻方式移除显露的第一晶种层,以形成第二线路层50。至此,又再增加一层的线路增层结构,完成具有铜核基板支撑并具电性连接的双层增层线路基板4,于其中,该第一晶种层45与该第三金属层49皆为金属铜。
请参阅图17~图20所示,分别为本发明一实施例的多层封装基板的剖面示意图十六、本发明一实施例的多层封装基板的剖面示意图十七、本发明一实施例的多层封装基板的剖面示意图十八、及本发明一实施例的多层封装基板的剖面示意图十九。如图所示:之后,在本发明较佳实施例中是接着进行置晶侧线路层的制作。首先于该第二线路层50表面涂覆一层绝缘保护用的第一防焊层51,然后并以曝光及显影方式于该第一防焊层51上形成数个第六开口52,以显露其线路增层结构作为电性连接垫。接着,于该铜核基板30的第二面上贴合高感旋光性高分子材料制成的第七阻层53,之后于数个第六开口52上形成第一阻障层54,最后,移除该第七阻层。至此,完成具铜核层支撑的多层封装基板5,其中,该第一阻障层54为镍金层。
请参阅图21及图22所示,为本发明一实施例的多层封装基板的剖面示意图二十、及本发明一实施例的多层封装基板的剖面二十一。如图所示:在本发明较佳实施例中接着进行球侧的电性接垫。在该双层增层线路基板上完成一含封胶体55的封装制程后,是以碱性蚀刻方 式移除该铜核基板。至此,即可显露出预埋的金/镍/铜三层金属结构的数金属层作为球侧电性接垫。
由上述可知,本发明是从铜核基板为基础,开始制作的单面、多层封装基板,其结构包括一具高刚性支撑的铜板,且此铜板的一面具球侧图案阻障层与增层线路,另一面则无任何图案。于其中,各增层线路及置晶侧与球侧连接的方式是以数个电镀盲、埋孔所导通。因此,本发明封装基板的特色在于具有高密度增层线路以提供电子组件相连时所需的绕线,同时,并以铜板提供足够的刚性使封装制程可更为简易。虽然各线路在封装制程完成前于电性上是完全短路,但封装制程完成后则可以蚀刻方式移除全部的铜核基板,进而可使其电性独立并显露出已预埋的球侧电性接垫(即球侧图案阻障层)。藉此,使用本发明具高密度的增层线路封装基板方法所制造的多层封装基板,可依实际需求形成具铜核基板支撑的铜核层多层封装基板,不仅可制作出超薄的封装结构,并且亦可有效达到改善超薄核层基板板弯翘问题、简化传统增层线路板制作流程及降低成品板厚的目的。
综上所述,本发明的一种铜核层多层封装基板的制作方法,可有效改善现有技术的种种缺点,以具有高密度增层线路提供电子组件相连时所需的绕线,同时,并以铜板提供足够的刚性使封装制程可更为简易。藉此,使用本发明所制造的多层封装基板,可依实际需求形成具铜核基板支撑的铜核层多层封装基板,不仅可制作出超薄的封装结构,并且亦可有效达到改善超薄核层基板板弯翘问题、简化传统增层线路板制作流程及降低成品板厚的目的,进而使能产生更进步、更实用、更符合使用者所须,确已符合发明专利申请的要件,依法提出专利申请。
Claims (14)
1.一种铜核层多层封装基板的制作方法,其特征在于:至少包含下列步骤:
(A)提供铜核基板;
(B)分别于该铜核基板的第一面上形成第一阻层,以及于该铜核基板的第二面上形成完全覆盖状的第二阻层,于其中,该第一阻层上形成数个第一开口,并显露其下该铜核基板的第一面;
(C)于数个第一开口中形成数金属层,以形成球侧电性接垫;
(D)移除该第一阻层及该第二阻层;
(E)于该铜核基板的第一面上形成第一介电层及第一金属层;
(F)于该第一金属层及该第一介电层上形成数个第二开口,并显露其下的球侧电性接垫;
(G)于数个第二开口中以及该球侧电性接垫与该第一金属层上形成第二金属层;
(H)分别于该第二金属层上形成第三阻层,以及于该铜核基板的第二面上形成完全覆盖状的第四阻层,于其中,该第三阻层上形成数个第三开口,并显露其下的第二金属层;
(I)移除该第三开口下方的第二金属层及第一金属层,并形成第一线路层;
(J)移除该第三阻层及该第四阻层,至此,完成具有铜核基板支撑并具电性连接的单层增层线路基板;
(L)于该单层增层线路基板上进行线路增层结构制作,于其中,在该第一线路层及该第一介电层上形成第二介电层,并且在该第二介电层上形成数个第五开口,以显露其下的第一线路层,接着于该第二介电层与数个第五开口表面形成第一晶种层,再分别于该第一晶种层上形成第六阻层,以及于该铜核基板的第二面上形成完全覆盖状的第七阻层,并于该第六阻层上形成数个第六开口,以显露其下的第一晶种层,之后于该第六开口中已显露的第一晶种层上形成第三金属层,最后移除该第六阻层、该第七阻层及该第一晶种层,以在该第二介电层上形成第二线路层,至此,完成具有铜核基板支撑并具电性连接的双层增层线路基板,并继续本步骤(L)增加线路增层结构,形成具更多层的封装基板;
(K)于该单层增层线路基板上进行置晶侧线路层制作,于其中,在该第一线路层表面形成第一防焊层,并且在该第一防焊层上形成数个第四开口,以显露该第一线路层作为电性连接垫的部分;接着于该铜核基板第二面上形成第五阻层,并于数个第四开口中形成第一阻障层,最后再移除该第五阻层,至此,完成具有完整图案化的置晶侧线路层与已图案化但仍完全电性短路的球侧线路层;
(M)于该双层增层线路基板上完成含封胶体的封装制程后,移除该铜核基板,并显露出预埋的数金属层,以形成球侧电性接垫。
2.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述铜核基板为不含介电层材料的铜板。
3.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述第一~七阻层为以贴合、印刷或旋转涂布所为的干膜或湿膜的高感旋光性光阻。
4.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述数个第一、三、四及六开口以曝光及显影方式形成。
5.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述第一开口中形成的数金属层、该第二、三金属层及该第一晶种层的形成方式为无电电镀与电镀。
6.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述数金属层为金/镍/铜的金属结构。
7.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述第一~七阻层的移除方法为剥离。
8.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述步骤(E)是以直接压合该第一介电层及该第一金属层于其上。
9.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述步骤(E)采取贴合该第一介电层后,再形成该第一金属层。
10.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述第一、二介电层为环氧树脂绝缘膜、苯环丁烯、双马来亚酰胺三氮杂苯树脂、环氧树脂板、聚酰亚胺或聚四氟乙烯之中选择其一加入玻璃纤维组成。
11.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述数个第二、五开口是先做开铜窗后,再经由镭射钻孔方式形成。
12.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述数个第二、五开口是以直接镭射钻孔方式形成。
13.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述步骤(I)移除该第一、二金属层及该步骤(L)移除该第一晶种层的方法为蚀刻。
14.如权利要求1所述的铜核层多层封装基板的制作方法,其特征在于:所述第一阻障层为电镀镍金、无电镀镍金、电镀银或电镀锡中择其一。
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US11/984,263 | 2007-11-15 | ||
US11/984,263 US20080188037A1 (en) | 2007-02-05 | 2007-11-15 | Method of manufacturing semiconductor chip assembly with sacrificial metal-based core carrier |
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CN2008103051404A Expired - Fee Related CN101436548B (zh) | 2007-11-15 | 2008-10-24 | 无核层多层封装基板的制作方法 |
CN2008103051989A Expired - Fee Related CN101436549B (zh) | 2007-11-15 | 2008-10-27 | 铜核层多层封装基板的制作方法 |
CN200810305365XA Expired - Fee Related CN101436550B (zh) | 2007-11-15 | 2008-11-03 | 无核层多层封装基板的制作方法 |
CN2008103054154A Expired - Fee Related CN101436551B (zh) | 2007-11-15 | 2008-11-07 | 铜核层多层封装基板的制作方法 |
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CN2008103051404A Expired - Fee Related CN101436548B (zh) | 2007-11-15 | 2008-10-24 | 无核层多层封装基板的制作方法 |
CN2008103051989A Expired - Fee Related CN101436549B (zh) | 2007-11-15 | 2008-10-27 | 铜核层多层封装基板的制作方法 |
CN200810305365XA Expired - Fee Related CN101436550B (zh) | 2007-11-15 | 2008-11-03 | 无核层多层封装基板的制作方法 |
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Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8183095B2 (en) | 2010-03-12 | 2012-05-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation |
US8343809B2 (en) | 2010-03-15 | 2013-01-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die |
US9318441B2 (en) | 2007-12-14 | 2016-04-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die |
US7767496B2 (en) * | 2007-12-14 | 2010-08-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer |
US8456002B2 (en) | 2007-12-14 | 2013-06-04 | Stats Chippac Ltd. | Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief |
US20090166858A1 (en) * | 2007-12-28 | 2009-07-02 | Bchir Omar J | Lga substrate and method of making same |
US8415203B2 (en) * | 2008-09-29 | 2013-04-09 | Freescale Semiconductor, Inc. | Method of forming a semiconductor package including two devices |
TWI421992B (zh) * | 2009-08-05 | 2014-01-01 | Unimicron Technology Corp | 封裝基板及其製法 |
US9548240B2 (en) | 2010-03-15 | 2017-01-17 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package |
US8298863B2 (en) | 2010-04-29 | 2012-10-30 | Texas Instruments Incorporated | TCE compensation for package substrates for reduced die warpage assembly |
CN102259544A (zh) * | 2010-05-27 | 2011-11-30 | 禹辉(上海)转印材料有限公司 | 一种镭射信息层的制造方法 |
TWI496258B (zh) * | 2010-10-26 | 2015-08-11 | Unimicron Technology Corp | 封裝基板之製法 |
US8698303B2 (en) | 2010-11-23 | 2014-04-15 | Ibiden Co., Ltd. | Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device |
US20120286416A1 (en) * | 2011-05-11 | 2012-11-15 | Tessera Research Llc | Semiconductor chip package assembly and method for making same |
TW201248745A (en) * | 2011-05-20 | 2012-12-01 | Subtron Technology Co Ltd | Package structure and manufacturing method thereof |
CN103348361B (zh) * | 2011-12-12 | 2017-05-24 | Ev 集团 E·索尔纳有限责任公司 | 用于制造单独编码的读结构的方法和装置 |
CN103681384B (zh) | 2012-09-17 | 2016-06-01 | 宏启胜精密电子(秦皇岛)有限公司 | 芯片封装基板和结构及其制作方法 |
CN103717009A (zh) * | 2012-10-08 | 2014-04-09 | 苏州卓融水处理科技有限公司 | 一种无核封装基板种子层附着力的方法 |
TWI500125B (zh) * | 2012-12-21 | 2015-09-11 | Unimicron Technology Corp | 電子元件封裝之製法 |
CN103903990B (zh) * | 2012-12-28 | 2016-12-28 | 欣兴电子股份有限公司 | 电子组件封装的制法 |
US8802504B1 (en) * | 2013-03-14 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
CN107170689B (zh) | 2013-06-11 | 2019-12-31 | 唐山国芯晶源电子有限公司 | 芯片封装基板 |
CN103887184B (zh) * | 2014-03-28 | 2016-09-07 | 江阴芯智联电子科技有限公司 | 新型高密度高性能多层基板内对称结构及制作方法 |
CN105931997B (zh) * | 2015-02-27 | 2019-02-05 | 胡迪群 | 暂时性复合式载板 |
DE102015116807A1 (de) * | 2015-10-02 | 2017-04-06 | Infineon Technologies Austria Ag | Funktionalisierte Schnittstellenstruktur |
CN108257875B (zh) * | 2016-12-28 | 2021-11-23 | 碁鼎科技秦皇岛有限公司 | 芯片封装基板、芯片封装结构及二者的制作方法 |
TWI643532B (zh) * | 2017-05-04 | 2018-12-01 | 南亞電路板股份有限公司 | 電路板結構及其製造方法 |
JP7046639B2 (ja) * | 2018-02-21 | 2022-04-04 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
US10573572B2 (en) * | 2018-07-19 | 2020-02-25 | Advanced Semiconductor Engineering, Inc. | Electronic device and method for manufacturing a semiconductor package structure |
CN111326494A (zh) * | 2020-02-28 | 2020-06-23 | 维沃移动通信有限公司 | 封装结构、制作方法、电路板结构及电子设备 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6294731B1 (en) * | 1999-03-16 | 2001-09-25 | Performance Interconnect, Inc. | Apparatus for multichip packaging |
US6278618B1 (en) * | 1999-07-23 | 2001-08-21 | National Semiconductor Corporation | Substrate strips for use in integrated circuit packaging |
JP3983146B2 (ja) * | 2002-09-17 | 2007-09-26 | Necエレクトロニクス株式会社 | 多層配線基板の製造方法 |
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US20080188037A1 (en) | 2008-08-07 |
TWI380422B (zh) | 2012-12-21 |
TW200921819A (en) | 2009-05-16 |
TWI380428B (zh) | 2012-12-21 |
TW200922433A (en) | 2009-05-16 |
TWI361481B (zh) | 2012-04-01 |
TW200921875A (en) | 2009-05-16 |
TW200921881A (en) | 2009-05-16 |
CN101436547B (zh) | 2011-06-22 |
CN101436548A (zh) | 2009-05-20 |
CN101436550A (zh) | 2009-05-20 |
TWI348743B (zh) | 2011-09-11 |
CN101436549B (zh) | 2010-06-02 |
TW200921816A (en) | 2009-05-16 |
TW200921818A (en) | 2009-05-16 |
CN101436550B (zh) | 2010-09-29 |
TW200921876A (en) | 2009-05-16 |
TW200921817A (en) | 2009-05-16 |
CN101436551A (zh) | 2009-05-20 |
TWI364805B (zh) | 2012-05-21 |
CN101436548B (zh) | 2011-06-22 |
TWI373115B (zh) | 2012-09-21 |
CN101436547A (zh) | 2009-05-20 |
TW200921884A (en) | 2009-05-16 |
TWI380387B (zh) | 2012-12-21 |
CN101436549A (zh) | 2009-05-20 |
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