CN101436550B - 无核层多层封装基板的制作方法 - Google Patents
无核层多层封装基板的制作方法 Download PDFInfo
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- CN101436550B CN101436550B CN200810305365XA CN200810305365A CN101436550B CN 101436550 B CN101436550 B CN 101436550B CN 200810305365X A CN200810305365X A CN 200810305365XA CN 200810305365 A CN200810305365 A CN 200810305365A CN 101436550 B CN101436550 B CN 101436550B
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- 239000000758 substrate Substances 0.000 title claims abstract description 150
- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000010410 layer Substances 0.000 title claims description 401
- 239000012792 core layer Substances 0.000 title claims description 23
- 238000005538 encapsulation Methods 0.000 title claims description 23
- 229910052802 copper Inorganic materials 0.000 claims abstract description 67
- 239000010949 copper Substances 0.000 claims abstract description 67
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 claims abstract description 27
- 238000004806 packaging method and process Methods 0.000 claims description 64
- 239000002184 metal Substances 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 49
- 150000001879 copper Chemical class 0.000 claims description 32
- 230000004888 barrier function Effects 0.000 claims description 29
- 239000013078 crystal Substances 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 238000003466 welding Methods 0.000 claims description 15
- 238000007747 plating Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 10
- 238000012800 visualization Methods 0.000 claims description 10
- 238000007772 electroless plating Methods 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- -1 polytetrafluoroethylene Polymers 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 229920001343 polytetrafluoroethylene Polymers 0.000 claims description 3
- 239000004810 polytetrafluoroethylene Substances 0.000 claims description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000003365 glass fiber Substances 0.000 claims description 2
- 239000004922 lacquer Substances 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
- HGTDVVTWYKXXMI-UHFFFAOYSA-N pyrrole-2,5-dione;triazine Chemical compound C1=CN=NN=C1.O=C1NC(=O)C=C1 HGTDVVTWYKXXMI-UHFFFAOYSA-N 0.000 claims 1
- 238000009713 electroplating Methods 0.000 abstract description 3
- 238000004804 winding Methods 0.000 abstract 1
- 239000011162 core material Substances 0.000 description 14
- 239000011469 building brick Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000004224 protection Effects 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract
一种无核层多层封装基板的制作方法,是从一铜核基板为基础,开始制作的多层封装基板,其包括具球侧平面电性接脚接垫与至少一增层线路。于其中,各增层线路及置晶侧与球侧连接的方式是以数个电镀盲、埋孔所导通。因此,本发明封装基板的特色在于具有高密度增层线路以提供电子组件相连时所需的绕线。藉此,使用本发明具高密度的增层线路封装基板方法所制造的无核层多层封装基板,可有效改善超薄核层基板板弯翘问题,简化传统增层线路板的制作流程。
Description
技术领域:
本发明涉及一种无核层多层封装基板的制作方法,尤指一种以铜核基板为基础,开始制作多层封装基板的方法,于其中,该多层封装基板包括具球侧平面电性接脚接垫与至少一增层线路。
背景技术:
在一般多层封装基板的制作上,其制作方式通常是由一核心基板开始,经过钻孔、电镀金属、塞孔及双面线路制作等方式,完成一双面结构的内层核心板,之后再经由一线路增层制程完成一多层封装基板。如图23所示,其为一有核层封装基板的剖面示意图。首先,准备一核心基板70,其中,该核心基板70由一具预定厚度的芯层701及形成于此芯层701表面的线路层702所构成,且该芯层701中形成有数个电镀导通孔703,可藉以连接该芯层701表面的线路层702。
接着如图24~图27所示,对该核心基板70实施线路增层制程。首先,是于该核心基板70表面形成第一介电层71,且该第一介电层71表面并形成有数个第一开口72,以露出该线路层702;之后,以无电电镀或电镀等方式于该第一介电层71外露的表面形成晶种层73,并于该晶种层73上形成图案化阻层74,且其图案化阻层74中并有数个第二开口75,以露出部份欲形成图案化线路的晶种层73;接着,利用电镀方式于该第二开口75中形成第一图案化线路层76及数个导电盲孔77,并使其第一图案化线路层76得以透过该数个导电盲孔77与该核心基板70的线路层702做电性导通,然后再进行移除该图案化阻层74与蚀刻,待完成后形成第一线路增层结构7a。同样地,该法可于该第一线路增层结构7a的最外层表面再运用相同的方式形成具有第二介电层78及第二图案化线路层79的第二线路增层结构7b,以逐步增层方式形成多层封装基板。然而,此种制作方法有布线密度低、层数多及流程复杂等缺点。
另外,亦有利用厚铜金属板当核心材料的方法,可于经过蚀刻及塞孔等方式完成内层核心板后,再经由线路增层制程以完成多层封装基板。如图28~图30所示,其为另一有核层封装基板的剖面示意图。首先,准备核心基板80,该核心基板80是由具预定厚度的金属层利用蚀刻与树脂塞孔801以及钻孔与电镀通孔802等方式形成的单层铜核心基板80;之后,利用上述线路增层方式,于该核心基板80表面形成第一介电层81及第一图案化线路层82,藉此构成具第一线路增层结构8a。该法亦与上述方法相同,可再利用一次线路增层方式于该第一线路增层结构8a的最外层表面形成第二介电层83及第二图案化线路层84,藉此构成第二线路增层结构8b,以逐步增层方式形成多层封装基板。然而,此种制作方法不仅其铜核心基板制作不易,且亦与上述方法相同,具有布线密度低及流程复杂等缺点。故,一般无法符合使用者于实际使用时所需。
发明内容:
本发明所要解决的技术问题是:针对上述现有技术的不足,提供一种无核层多层封装基板的制作方法,其采用具高密度的增层线路封装基板方法所制造,可有效改善超薄核层基板板弯翘问题,简化传统增层线路板的制作流程。
本发明的次要目的在于,以铜核基板为基础,开始制作多层封装基板。其包括具球侧平面电性接脚接垫与至少一增层线路。于其中,各增层线路及置晶侧与球侧连接的方式以数个电镀盲、埋孔所导通。
本发明的另一目的在于,具有高密度增层线路以提供电子组件相连时所需的绕线。
为了解决上述技术问题,本发明所采用的技术方案是:一种无核层多层封装基板的制作方法,其至少包含下列步骤:
A、提供铜核基板;
B、分别于该铜核基板的第一面上形成第一阻层,以及于该铜核基板的第二面上形成完全覆盖状的第二阻层,于其中,该第一阻层上形成数个第一开口,并显露其下该铜核基板的第一面;
C、于数个第一开口下方形成数个第一凹槽;
D、移除该第一阻层及该第二阻层;
E、于数个第一凹槽内形成第一电性阻绝层;
F、于该铜核基板的第一面与该第一电性阻绝层上形成第一介电层及第一金属层;
G、于该第一金属层与该第一介电层上形成数个第二开口,并显露其下的铜核基板的第一面;
H、于数个第二开口中及该第一金属层上形成第二金属层;
I、分别于该第二金属层上形成第三阻层,以及于该铜核基板的第二面上形成完全覆盖状的第四阻层,于其中,该第三阻层上形成数个第三开口;
J、移除该第三开口下方的第二金属层及第一金属层,并形成第一线路层;
K、移除该第三阻层及该第四阻层,至此,完成具有铜核基板支撑并具电性连接的单层增层线路基板;
M、于该单层增层线路基板上进行线路增层结构制作,于其中,在该第一线路层与该第一介电层表面形成第二介电层,并且该第二介电层上形成有数个第四开口,以显露其下的第一线路层,接着于该第二介电层与数个第四开口表面形成第一晶种层,再分别于该第一晶种层上形成第五阻层,以及于该铜核基板的第二面上形成完全覆盖状的第六阻层,其中,该第五阻层上形成有数个第五开口,以显露其下的第一晶种层,之后于该第五开口中已显露的第一晶种层上形成第三金属层,最后再移除该第五阻层、该第六阻层及该第一晶种层,以在该第二介电层上形成第二线路层;至此,完成具有铜核基板支撑并具电性连接的双层增层线路基板,再进行步骤(L);或者继续步骤(M)增加线路增层结构,形成具多层的封装基板,再进行该步骤(L);
L、接着进行置晶侧线路层与球侧平面电性接脚接垫的制作,于其中,在该第二线路层表面形成第一防焊层,并且在该第一防焊层上形成数个第六开口,以显露线路增层结构作为电性连接垫的部分,接着再分别于该铜核基板的第二面上形成第七阻层,并且在该第七阻层上形成数个第七开口,以及于该第一防焊层上形成完全覆盖状的第八阻层,之后移除数个第七开口下方的铜核基板,以形成数个第二凹槽,并再移除该第七阻层与该第八阻层,接着于数个第二凹槽中形成第二电性阻绝层,并显露出平面电性连接垫,最后,分别于数个第六开口上形成第一阻障层,以及于该平面电性连接垫上形成第二阻障层,至此,完成具有完整图案化的置晶侧线路层与球侧平面电性连接垫。
如此,本发明的封装基板具有高密度增层线路以提供电子组件相连时所需的绕线;且使用本发明具高密度的增层线路封装基板方法所制造的无核层多层封装基板,可有效改善超薄核层基板板弯翘问题,及简化传统增层线路板的制作流程。
附图说明:
图1是本发明的制作流程示意图。
图2是本发明实施例的多层封装基板的剖面示意图一。
图3是本发明实施例的多层封装基板的剖面示意图二。
图4是本发明实施例的多层封装基板的剖面示意图三。
图5是本发明实施例的多层封装基板的剖面示意图四。
图6是本发明实施例的多层封装基板的剖面示意图五。
图7是本发明实施例的多层封装基板的剖面示意图六。
图8是本发明实施例的多层封装基板的剖面示意图七。
图9是本发明实施例的多层封装基板的剖面示意图八。
图10是本发明实施例的多层封装基板的剖面示意图九。
图11是本发明实施例的多层封装基板的剖面示意图十。
图12是本发明实施例的多层封装基板的剖面示意图十一。
图13是本发明实施例的多层封装基板的剖面示意图十二。
图14是本发明实施例的多层封装基板的剖面示意图十三。
图15是本发明实施例的多层封装基板的剖面示意图十四。
图16是本发明实施例的多层封装基板的剖面示意图十五。
图17是本发明实施例的多层封装基板的剖面示意图十六。
图18是本发明实施例的多层封装基板的剖面示意图十七。
图19是本发明实施例的多层封装基板的剖面示意图十八。
图20是本发明实施例的多层封装基板的剖面示意图十九。
图21是本发明实施例的多层封装基板的剖面示意图二十。
图22是本发明实施例的多层封装基板的剖面示意图二十一。
图23是已知有核层封装基板的剖面示意图。
图24是已知实施线路增层的剖面示意图一。
图25是已知实施线路增层的剖面示意图二。
图26是已知实施线路增层的剖面示意图三。
图27是已知实施线路增层的剖面示意图四。
图28是另一已知有核层封装基板的剖面示意图。
图29是另一已知的第一线路增层结构的剖面示意图。
图30是另一已知的第二路增层结构剖面示意图。
标号说明:
步骤(A)~(M)11~23 铜核基板30
第一、二阻层31、32 第一开口33
蚀刻凹槽34 第一电性阻绝层35
第一介电层36 第一金属层37
第二开口38 第二金属层39
第三、四阻层40、41 第三开口42
第一线路层43 第二介电层44
第四开口45 第一晶种层46
第五、六阻层47、48 第五开口49
第三金属层50 第二线路层51
第一防焊层52 第六开口53
第七、八阻层54、55 第七开口56
第二凹槽57 第二电性阻绝层58
平面电性连接垫59 第一、二阻障层60、61
第一、二线路增层结构7a、7b 第一、二线路增层结构8a、8b
核心基板70 芯层701
线路层702 电镀导通孔703
第一介电层71 第一开口72
晶种层73 图案化阻层74
第二开口75 第一图案化线路层76
导电盲孔67 第二介电层68
第二图案化线路层69 核心基板80
树脂塞孔801 电镀通孔802
第一介电层81 第一图案化线路层82
第二介电层83 第二图案化线路层84
具体实施方式:
请参阅图1所示,为本发明的制作流程示意图。如图所示:本发明为一种无核层多层封装基板的制作方法,其至少包括下列步骤:
(A)提供铜核基板11:提供铜核基板;
(B)形成第一、二阻层及数个第一开口12:分别于该铜核基板的第一面上形成第一阻层,以及于该铜核基板的第二面上形成完全覆盖状的第二阻层,于其中,并以曝光及显影方式在该第一阻层上形成数个第一开口,以显露其下该铜核基板的第一面;
(C)形成第一凹槽13:以蚀刻方式于数个第一开口下方形成数个第一凹槽;
(D)移除第一、二阻层14:以剥离方式移除该第一阻层及该第二阻层,形成具有接脚第一面的铜核基板;
(E)形成第一电性阻绝层15:以直接压合或印刷的方式于数个第一凹槽内形成第一电性阻绝层;
(F)形成第一介电层及第一金属层16:于该铜核基板的第一面与该第一电性阻绝层上直接压合第一介电层及第一金属层,亦或是先采取贴合该第一介电层后,再形成该第一金属层的方式;
(G)形成数个第二开口17:以镭射钻孔方式于该第一金属层与该第一介电层上形成数个第二开口,并显露其下的铜核基板第一面,其中,数个第二开口可先做开铜窗(Conformal Mask)后,再经由激光钻孔的方式形成,亦或是以直接激光钻孔(LASER Direct)的方式形成;
(H)形成第二金属层18:以无电电镀与电镀的方式于数个第二开口中及该第一金属层上形成第二金属层,其中,该第二金属层作为与该铜核基板第一面的电性连接用;
(I)形成第三、四阻层及数个第三开口19:分别于该第二金属层上形成第三阻层,以及于该铜核基板的第二面上形成完全覆盖状的第四阻层,于其中,并以曝光及显影方式在该第三阻层上形成数个第三开口,以显露其下的第二金属层;
(J)形成第一线路层20:以蚀刻方式移除该第三开口下方的第二金属层及第一金属层,并形成第一线路层;
(K)完成具有铜核基板支撑并具电性连接的单层增层线路基板21:以剥离方式移除该第三阻层及该第四阻层。至此,完成具有铜核基板支撑并具电性连接的单层增层线路基板,并可选择直接进行步骤(L)或步骤(M);
(L)进行置晶侧线路层与球侧平面电性接脚接垫的制作22:于该单层增层线路基板上进行置晶侧线路层与球侧平面电性接脚接垫的制作,于其中,在该第一线路层表面形成第一防焊层,并以曝光及显影方式在该第一防焊层上形成数个第四开口,以显露线路增层结构作为电性连接垫的部分,接着再分别于该铜核基板的第二面上形成第五阻层,并且在该第五阻层上以曝光及显影方式形成数个第五开口,以及于该第一防焊层上形成完全覆盖状的第六阻层。之后移除数个第五开口下方的铜核基板,以形成数个第二凹槽,并再以剥离方式移除该第五阻层与该第六阻层,接着于数个第二凹槽中形成第二电性阻绝层,并显露出平面电性连接垫。最后,分别于数个第四开口上形成第一阻障层,以及于该平面电性连接垫上形成第二阻障层。至此,完成具有完整图案化的置晶侧线路层与球侧平面电性连接垫,其中,该第一、二阻障层可为电镀镍金、无电镀镍金、电镀银或电镀锡中择其一;以及
(M)进行线路增层结构制作23:于该单层增层线路基板上进行线路增层结构的制作,于其中,在该第一线路层与该第一介电层表面形成第二介电层,并以激光钻孔的方式在该第二介电层上形成数个第六开口,以显露其下的第一线路层,接着以无电电镀与电镀方式于该第二介电层与数个第六开口表面形成第一晶种层,再分别于该第一晶种层上形成第七阻层,以及于该铜核基板的第二面上形成完全覆盖状的第八阻层,并利用曝光及显影方式于该第七阻层上形成数个第七开口,以显露其下的第一晶种层,之后再以电镀方式于该第七开口中已显露的第一晶种层上形成第三金属层,最后以剥离方式移除该第七阻层与该第八阻层,并以蚀刻方式移除该第一晶种层,以在该第二介电层上形成第二线路层。至此,又再增加一层的线路增层结构,完成具有铜核基板支撑并具电性连接的双层增层线路基板。并可继续本步骤(M)增加线路增层结构,形成具更多层的封装基板,亦或直接至该步骤(L)进行置晶侧线路层与球侧单面电性接脚接垫的制作,其中,数个第六开口是可先做开铜窗后,再经由激光钻孔方式形成,亦或是以直接激光钻孔的方式形成。
于其中,上述该第一~八阻层是以贴合、印刷或旋转涂布所为的干膜或湿膜的高感旋光性光阻;该第一、二电性阻绝层及该第一、二介电层可为防焊绿漆、苯环丁烯(Benzocyclo-buthene,BCB)、双马来亚酰胺-三氮杂苯树脂(Bismaleimide Triazine,BT)、聚酰亚胺(Polyimide,PI)、聚四氟乙烯(Poly(tetra-floroethylene),PTFE)、环氧树脂(如环氧树脂绝缘膜(Ajinomoto Build-up Film,ABF)、或环氧树脂板(FR4、FR5))、或玻璃纤维所组成之一。
请参阅图2~图12所示,分别为本发明一实施例的多层封装基板的剖面剖面示意图一、本发明一实施例的多层封装基板的剖面示意图二、本发明一实施例的多层封装基板的剖面示意图三、本发明一实施例的多层封装基板的剖面示意图四、本发明一实施例的多层封装基板的剖面示意图五、本发明一实施例的多层封装基板的剖面示意图六、本发明一实施例的多层封装基板的剖面示意图七、本发明一实施例的多层封装基板的剖面示意图八、本发明一实施例的多层封装基板的剖面示意图九、本发明一实施例的多层封装基板的剖面示意图十、及本发明一实施例的多层封装基板的剖面示意图十一。如图所示:本发明于一较佳实施例中,是先提供铜核基板30,并分别于该铜核基板30的第一面上贴合高感旋光性高分子材料制成的第一阻层31,以及于该铜核基板30的第二面上贴合高感旋光性高分子材料制成的第二阻层32,并以曝光及显影方式在该第一阻层31上形成数个第一开口33,以显露其下该铜核基板30的第一面,而其第二面上的第二阻层32则为完全覆盖状。接着以蚀刻方式制作蚀刻凹槽34,其中,该铜核基板30为一不含介电层材料的铜板;该第一、二阻层31、32为干膜光阻层。
接着,移除该第一、二阻层,以形成具有接脚第一面的铜核基板30。之后印刷第一电性阻绝层35于该蚀刻凹槽中,并在该铜核基板30的第一面上压合第一介电层36及第一金属层37,再以激光钻孔方式于该第一金属层37与该第一介电层36上形成数个第二开口38,之后以无电电镀与电镀方式于数个第二开口38及该第一金属层37表面形成第二金属层39,其中,该第一、二金属层37、39皆为铜,且该第二金属层39是作为与该铜核基板30第一面的电性连接用。
接着,分别于该第二金属层39上贴合高感旋光性高分子材料制成的第三阻层40,以及于该铜核基板30的第二面上贴合高感旋光性高分子材料制成的第四阻层41,并以曝光及显影方式于该第三阻层40上形成数个第三开口42,以显露其下的第二金属层39。之后以蚀刻方式移除该第三开口42下的第一、二金属层,以形成第一线路层43,最后并移除该第三、四阻层。至此,完成具有图案化线路并与该铜核基板30的接脚第一面连接的单层增层线路基板3。
请参阅图13~图17所示,分别为本发明一实施例的多层封装基板的剖面示意图十二、本发明一实施例的多层封装基板的剖面示意图十三、本发明一实施例的多层封装基板的剖面示意图十四、本发明一实施例的多层封装基板的剖面示意图十五、及本发明一实施例的多层封装基板的剖面示意图十六。如图所示:在本发明较佳实施例中,是先行进行线路增层结构的制作。首先于该第一线路层43与该第一介电层36上贴压合为环氧树脂绝缘膜材料的第二介电层44,之后并以激光钻孔方式于该第二介电层44上形成数个第四开口45,以显露其下的第一线路层43,并在该第二介电层44与该第四开口45表面以无电电镀与电镀方式形成第一晶种层46。之后分别于该第一晶种层46上贴合为高感旋光性高分子材料的第五阻层47,以及于该铜核基板30的第二面上贴合为高感旋光性高分子材料的第六阻层48,接着利用曝光及显影方式于该第五阻层47上形成数个第五开口49,然后再于数第五开口49中电镀第三金属层50,最后移除该第五、六阻层,并再以蚀刻方式移除显露的第一晶种层,以形成第二线路层51。至此,又再增加一层的线路增层结构,完成具有铜核基板支撑并具电性连接的双层增层线路基板4,于其中,该第一晶种层46与该第三金属层50皆为金属铜。
请参阅图18~图22所示,分别为本发明一实施例的多层封装基板的剖面示意图十七、本发明一实施例的多层封装基板的剖面示意图十八、本发明一实施例的多层封装基板的剖面示意图十九、本发明一实施例的多层封装基板的剖面示意图二十、及本发明一实施例的多层封装基板的剖面示意图二十一。如图所示:之后,在本发明较佳实施例中接着进行置晶侧线路层与球侧平面电性接脚接垫的制作。首先于该第二线路层51表面涂覆一层绝缘保护用的第一防焊层52,并以曝光及显影方式于该第一防焊层52上形成数个第六开口53,以显露线路增层结构作为电性连接垫。接着分别于该铜核基板30的第二面上贴合为高感旋光性高分子材料的第七阻层54,以及于该第一防焊层52上贴合为高感光高分子材料的第八阻层55,且该第七阻层54上并形成有数个第七开口56。之后移除数个第七开口56下方的铜核基板30,以形成数个第二凹槽57,并再移除该第七、八阻层。接着于数个第二凹槽57中形成第二电性阻绝层58,以显露出平面电性连接垫59。最后,分别于数个第六开口53上形成第一阻障层60,以及于平面电性连接垫59上形成第二阻障层61。至此,完成无核层多层封装基板5,其中,该第一、二阻障层60、61皆为镍金层。
由上述可知,本发明是从铜核基板为基础,开始制作的多层封装基板,其结构包括具球侧平面电性接脚接垫与至少一增层线路。于其中,各增层线路及置晶侧与球侧连接的方式是以数个电镀盲、埋孔所导通。因此,本发明封装基板的特色在于具有高密度增层线路以提供电子组件相连时所需的绕线。藉此,使用本发明具高密度的增层线路封装基板方法所制造的无核层多层封装基板,可有效改善超薄核层基板板弯翘问题,及简化传统增层线路板的制作流程。
综上所述,本发明为一种无核层多层封装基板的制作方法,可有效改善现有技术的种种缺点,其结构具有球侧平面电性接脚接垫与至少一增层线路。可利用具有高密度增层线路提供电子组件相连时所需的绕线。藉此,使用本发明具高密度的增层线路封装基板方法所制造的无核层多层封装基板,可有效改善超薄核层基板板弯翘问题,及简化传统增层线路板的制作流程,进而使能产生更进步、更实用、更符合使用者的所须,确已符合发明专利申请的要件,依法提出专利申请。
Claims (12)
1.一种无核层多层封装基板的制作方法,其特征在于:至少包含下列步骤:
A、提供铜核基板;
B、分别于该铜核基板的第一面上形成第一阻层,以及于该铜核基板的第二面上形成完全覆盖状的第二阻层,于其中,该第一阻层上形成数个第一开口,并显露其下该铜核基板的第一面;
C、于数个第一开口下方形成数个第一凹槽;
D、移除该第一阻层及该第二阻层;
E、于数个第一凹槽内形成第一电性阻绝层;
F、于该铜核基板的第一面与该第一电性阻绝层上形成第一介电层及第一金属层;
G、于该第一金属层与该第一介电层上形成数个第二开口,并显露其下的铜核基板的第一面;
H、于数个第二开口中及该第一金属层上形成第二金属层;
I、分别于该第二金属层上形成第三阻层,以及于该铜核基板的第二面上形成完全覆盖状的第四阻层,于其中,该第三阻层上形成数个第三开口;
J、移除该第三开口下方的第二金属层及第一金属层,并形成第一线路层;
K、移除该第三阻层及该第四阻层,至此,完成具有铜核基板支撑并具电性连接的单层增层线路基板;
M、于该单层增层线路基板上进行线路增层结构制作,于其中,在该第一线路层与该第一介电层表面形成第二介电层,并且该第二介电层上形成有数个第四开口,以显露其下的第一线路层,接着于该第二介电层与数个第四开口表面形成第一晶种层,再分别于该第一晶种层上形成第五阻层,以及于该铜核基板的第二面上形成完全覆盖状的第六阻层,其中,该第五阻层上形成有数个第五开口,以显露其下的第一晶种层,之后于该第五开口中已显露的第一晶种层上形成第三金属层,最后再移除该第五阻层、该第六阻层及该第一晶种层,以在该第二介电层上形成第二线路层;至此,完成具有铜核基板支撑并具电性连接的双层增层线路基板,再进行步骤(L);或者继续步骤(M)增加线路增层结构,形成具多层的封装基板,再进行该步骤(L);
L、接着进行置晶侧线路层与球侧平面电性接脚接垫的制作,于其中,在该第二线路层表面形成第一防焊层,并且在该第一防焊层上形成数个第六开口,以显露线路增层结构作为电性连接垫的部分,接着再分别于该铜核基板的第二面上形成第七阻层,并且在该第七阻层上形成数个第七开口,以及于该第一防焊层上形成完全覆盖状的第八阻层,之后移除数个第七开口下方的铜核基板,以形成数个第二凹槽,并再移除该第七阻层与该第八阻层,接着于数个第二凹槽中形成第二电性阻绝层,并显露出平面电性连接垫,最后,分别于数个第六开口上形成第一阻障层,以及于该平面电性连接垫上形成第二阻障层,至此,完成具有完整图案化的置晶侧线路层与球侧平面电性连接垫。
2.如权利要求1所述的无核层多层封装基板的制作方法,其特征在于:所述铜核基板为不含介电层材料的铜板。
3.如权利要求1所述的无核层多层封装基板的制作方法,其特征在于:所述第一~八阻层是以贴合、印刷或旋转涂布所为的干膜或湿膜的高感旋光性光阻。
4.如权利要求1所述的无核层多层封装基板的制作方法,其特征在于:所述数个第一、三、四、五及七开口是以曝光及显影方式形成。
5.如权利要求1所述的无核层多层封装基板的制作方法,其特征在于:所述步骤C形成的数个第一凹槽、步骤J移除该第一、二金属层、步骤L形成的数个第二凹槽及步骤M移除该第一晶种层的方法为蚀刻。
6.如权利要求1所述的无核层多层封装基板的制作方法,其特征在于:所述第一~八阻层的移除方法为剥离。
7.如权利要求1所述的无核层多层封装基板的制作方法,其特征在于:所述第一、二电性阻绝层以直接压合或印刷方式形成。
8.如权利要求1所述的无核层多层封装基板的制作方法,其特征在于:所述第一、二电性阻绝层及该第一、二介电层为防焊绿漆、苯环丁烯、双马来亚酰胺-三氮杂苯树脂、聚酰亚胺、聚四氟乙烯、环氧树脂或玻璃纤维所组成之一。
9.如权利要求1所述的无核层多层封装基板的制作方法,其特征在于:所述步骤F直接压合该第一介电层及该第一金属层于其上,或是贴合该第一介电层后,再形成该第一金属层。
10.如权利要求1所述的无核层多层封装基板的制作方法,其特征在于:所述数个第二、六开口是先做开铜窗后,再经由激光钻孔方式形成,亦或是直接以激光钻孔方式形成。
11.如权利要求1所述的无核层多层封装基板的制作方法,其特征在于:所述第二、三金属层及该第一晶种层的形成方式为无电电镀与电镀。
12.如权利要求1所述的无核层多层封装基板的制作方法,其特征在于:所述第一、二阻障层为电镀镍金、无电镀镍金、电镀银或电镀锡。
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US11/984,263 US20080188037A1 (en) | 2007-02-05 | 2007-11-15 | Method of manufacturing semiconductor chip assembly with sacrificial metal-based core carrier |
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CN2008103051404A Expired - Fee Related CN101436548B (zh) | 2007-11-15 | 2008-10-24 | 无核层多层封装基板的制作方法 |
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TW200922433A (en) | 2009-05-16 |
CN101436551B (zh) | 2010-12-01 |
TWI361481B (zh) | 2012-04-01 |
TW200921875A (en) | 2009-05-16 |
TW200921881A (en) | 2009-05-16 |
CN101436547B (zh) | 2011-06-22 |
CN101436548A (zh) | 2009-05-20 |
CN101436550A (zh) | 2009-05-20 |
TWI348743B (zh) | 2011-09-11 |
CN101436549B (zh) | 2010-06-02 |
TW200921816A (en) | 2009-05-16 |
TW200921818A (en) | 2009-05-16 |
TW200921876A (en) | 2009-05-16 |
TW200921817A (en) | 2009-05-16 |
CN101436551A (zh) | 2009-05-20 |
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CN101436548B (zh) | 2011-06-22 |
TWI373115B (zh) | 2012-09-21 |
CN101436547A (zh) | 2009-05-20 |
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