TWI373115B - - Google Patents
Info
- Publication number
- TWI373115B TWI373115B TW097102733A TW97102733A TWI373115B TW I373115 B TWI373115 B TW I373115B TW 097102733 A TW097102733 A TW 097102733A TW 97102733 A TW97102733 A TW 97102733A TW I373115 B TWI373115 B TW I373115B
- Authority
- TW
- Taiwan
Links
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0376—Etching temporary metallic carrier substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/984,263 US20080188037A1 (en) | 2007-02-05 | 2007-11-15 | Method of manufacturing semiconductor chip assembly with sacrificial metal-based core carrier |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200921884A TW200921884A (en) | 2009-05-16 |
TWI373115B true TWI373115B (zh) | 2012-09-21 |
Family
ID=39675451
Family Applications (9)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW097102733A TW200921884A (en) | 2007-11-15 | 2008-01-24 | Method for making copper-core layer multi-layer encapsulation substrate |
TW097102734A TW200921816A (en) | 2007-11-15 | 2008-01-24 | Method of making multi-layer package board of copper nuclear layer |
TW097106965A TW200921817A (en) | 2007-11-15 | 2008-02-29 | Method of manufacturing multi-layer package substrate of copper nuclear layer |
TW097108808A TW200921875A (en) | 2007-11-15 | 2008-03-13 | Manufacturing method of copper-core multilayer package substrate |
TW097108810A TW200921818A (en) | 2007-11-15 | 2008-03-13 | Method of manufacturing multi-layer package substrate of non-nuclear layer |
TW097110928A TW200921819A (en) | 2007-11-15 | 2008-03-27 | Method of producing multi-layer package substrate having a high thermal dissipation capacity |
TW097110927A TW200921881A (en) | 2007-11-15 | 2008-03-27 | Manufacturing method of high heat-dissipation multilayer package substrate |
TW097123918A TW200921876A (en) | 2007-11-15 | 2008-06-26 | Method for making copper-core layer multi-layer encapsulation substrate |
TW097141807A TW200922433A (en) | 2007-11-15 | 2008-10-30 | Manufacturing method of copper-core multilayer package substrate |
Family Applications After (8)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW097102734A TW200921816A (en) | 2007-11-15 | 2008-01-24 | Method of making multi-layer package board of copper nuclear layer |
TW097106965A TW200921817A (en) | 2007-11-15 | 2008-02-29 | Method of manufacturing multi-layer package substrate of copper nuclear layer |
TW097108808A TW200921875A (en) | 2007-11-15 | 2008-03-13 | Manufacturing method of copper-core multilayer package substrate |
TW097108810A TW200921818A (en) | 2007-11-15 | 2008-03-13 | Method of manufacturing multi-layer package substrate of non-nuclear layer |
TW097110928A TW200921819A (en) | 2007-11-15 | 2008-03-27 | Method of producing multi-layer package substrate having a high thermal dissipation capacity |
TW097110927A TW200921881A (en) | 2007-11-15 | 2008-03-27 | Manufacturing method of high heat-dissipation multilayer package substrate |
TW097123918A TW200921876A (en) | 2007-11-15 | 2008-06-26 | Method for making copper-core layer multi-layer encapsulation substrate |
TW097141807A TW200922433A (en) | 2007-11-15 | 2008-10-30 | Manufacturing method of copper-core multilayer package substrate |
Country Status (3)
Country | Link |
---|---|
US (1) | US20080188037A1 (zh) |
CN (5) | CN101436547B (zh) |
TW (9) | TW200921884A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108811301A (zh) * | 2017-05-04 | 2018-11-13 | 南亚电路板股份有限公司 | 电路板结构及其制造方法 |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
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US8183095B2 (en) | 2010-03-12 | 2012-05-22 | Stats Chippac, Ltd. | Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation |
US8343809B2 (en) | 2010-03-15 | 2013-01-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die |
US9318441B2 (en) | 2007-12-14 | 2016-04-19 | Stats Chippac, Ltd. | Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die |
US7767496B2 (en) * | 2007-12-14 | 2010-08-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer |
US8456002B2 (en) | 2007-12-14 | 2013-06-04 | Stats Chippac Ltd. | Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief |
US20090166858A1 (en) * | 2007-12-28 | 2009-07-02 | Bchir Omar J | Lga substrate and method of making same |
US8415203B2 (en) * | 2008-09-29 | 2013-04-09 | Freescale Semiconductor, Inc. | Method of forming a semiconductor package including two devices |
TWI421992B (zh) * | 2009-08-05 | 2014-01-01 | Unimicron Technology Corp | 封裝基板及其製法 |
US9548240B2 (en) | 2010-03-15 | 2017-01-17 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package |
US8298863B2 (en) | 2010-04-29 | 2012-10-30 | Texas Instruments Incorporated | TCE compensation for package substrates for reduced die warpage assembly |
CN102259544A (zh) * | 2010-05-27 | 2011-11-30 | 禹辉(上海)转印材料有限公司 | 一种镭射信息层的制造方法 |
TWI496258B (zh) * | 2010-10-26 | 2015-08-11 | Unimicron Technology Corp | 封裝基板之製法 |
US8698303B2 (en) | 2010-11-23 | 2014-04-15 | Ibiden Co., Ltd. | Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device |
US20120286416A1 (en) * | 2011-05-11 | 2012-11-15 | Tessera Research Llc | Semiconductor chip package assembly and method for making same |
TW201248745A (en) * | 2011-05-20 | 2012-12-01 | Subtron Technology Co Ltd | Package structure and manufacturing method thereof |
CN103348361B (zh) * | 2011-12-12 | 2017-05-24 | Ev 集团 E·索尔纳有限责任公司 | 用于制造单独编码的读结构的方法和装置 |
CN103681384B (zh) | 2012-09-17 | 2016-06-01 | 宏启胜精密电子(秦皇岛)有限公司 | 芯片封装基板和结构及其制作方法 |
CN103717009A (zh) * | 2012-10-08 | 2014-04-09 | 苏州卓融水处理科技有限公司 | 一种无核封装基板种子层附着力的方法 |
TWI500125B (zh) * | 2012-12-21 | 2015-09-11 | Unimicron Technology Corp | 電子元件封裝之製法 |
CN103903990B (zh) * | 2012-12-28 | 2016-12-28 | 欣兴电子股份有限公司 | 电子组件封装的制法 |
US8802504B1 (en) * | 2013-03-14 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US9299649B2 (en) | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
CN107170689B (zh) | 2013-06-11 | 2019-12-31 | 唐山国芯晶源电子有限公司 | 芯片封装基板 |
CN103887184B (zh) * | 2014-03-28 | 2016-09-07 | 江阴芯智联电子科技有限公司 | 新型高密度高性能多层基板内对称结构及制作方法 |
CN105931997B (zh) * | 2015-02-27 | 2019-02-05 | 胡迪群 | 暂时性复合式载板 |
DE102015116807A1 (de) * | 2015-10-02 | 2017-04-06 | Infineon Technologies Austria Ag | Funktionalisierte Schnittstellenstruktur |
CN108257875B (zh) * | 2016-12-28 | 2021-11-23 | 碁鼎科技秦皇岛有限公司 | 芯片封装基板、芯片封装结构及二者的制作方法 |
JP7046639B2 (ja) * | 2018-02-21 | 2022-04-04 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
US10573572B2 (en) * | 2018-07-19 | 2020-02-25 | Advanced Semiconductor Engineering, Inc. | Electronic device and method for manufacturing a semiconductor package structure |
CN111326494A (zh) * | 2020-02-28 | 2020-06-23 | 维沃移动通信有限公司 | 封装结构、制作方法、电路板结构及电子设备 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6294731B1 (en) * | 1999-03-16 | 2001-09-25 | Performance Interconnect, Inc. | Apparatus for multichip packaging |
US6278618B1 (en) * | 1999-07-23 | 2001-08-21 | National Semiconductor Corporation | Substrate strips for use in integrated circuit packaging |
JP3983146B2 (ja) * | 2002-09-17 | 2007-09-26 | Necエレクトロニクス株式会社 | 多層配線基板の製造方法 |
-
2007
- 2007-11-15 US US11/984,263 patent/US20080188037A1/en not_active Abandoned
-
2008
- 2008-01-24 TW TW097102733A patent/TW200921884A/zh not_active IP Right Cessation
- 2008-01-24 TW TW097102734A patent/TW200921816A/zh not_active IP Right Cessation
- 2008-02-29 TW TW097106965A patent/TW200921817A/zh unknown
- 2008-03-13 TW TW097108808A patent/TW200921875A/zh unknown
- 2008-03-13 TW TW097108810A patent/TW200921818A/zh not_active IP Right Cessation
- 2008-03-27 TW TW097110928A patent/TW200921819A/zh not_active IP Right Cessation
- 2008-03-27 TW TW097110927A patent/TW200921881A/zh not_active IP Right Cessation
- 2008-06-26 TW TW097123918A patent/TW200921876A/zh not_active IP Right Cessation
- 2008-09-19 CN CN2008103045916A patent/CN101436547B/zh not_active Expired - Fee Related
- 2008-10-24 CN CN2008103051404A patent/CN101436548B/zh not_active Expired - Fee Related
- 2008-10-27 CN CN2008103051989A patent/CN101436549B/zh not_active Expired - Fee Related
- 2008-10-30 TW TW097141807A patent/TW200922433A/zh unknown
- 2008-11-03 CN CN200810305365XA patent/CN101436550B/zh not_active Expired - Fee Related
- 2008-11-07 CN CN2008103054154A patent/CN101436551B/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108811301A (zh) * | 2017-05-04 | 2018-11-13 | 南亚电路板股份有限公司 | 电路板结构及其制造方法 |
TWI643532B (zh) * | 2017-05-04 | 2018-12-01 | 南亞電路板股份有限公司 | 電路板結構及其製造方法 |
Also Published As
Publication number | Publication date |
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US20080188037A1 (en) | 2008-08-07 |
TWI380422B (zh) | 2012-12-21 |
TW200921819A (en) | 2009-05-16 |
TWI380428B (zh) | 2012-12-21 |
TW200922433A (en) | 2009-05-16 |
CN101436551B (zh) | 2010-12-01 |
TWI361481B (zh) | 2012-04-01 |
TW200921875A (en) | 2009-05-16 |
TW200921881A (en) | 2009-05-16 |
CN101436547B (zh) | 2011-06-22 |
CN101436548A (zh) | 2009-05-20 |
CN101436550A (zh) | 2009-05-20 |
TWI348743B (zh) | 2011-09-11 |
CN101436549B (zh) | 2010-06-02 |
TW200921816A (en) | 2009-05-16 |
TW200921818A (en) | 2009-05-16 |
CN101436550B (zh) | 2010-09-29 |
TW200921876A (en) | 2009-05-16 |
TW200921817A (en) | 2009-05-16 |
CN101436551A (zh) | 2009-05-20 |
TWI364805B (zh) | 2012-05-21 |
CN101436548B (zh) | 2011-06-22 |
CN101436547A (zh) | 2009-05-20 |
TW200921884A (en) | 2009-05-16 |
TWI380387B (zh) | 2012-12-21 |
CN101436549A (zh) | 2009-05-20 |
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