TWI380387B - - Google Patents

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Publication number
TWI380387B
TWI380387B TW097110928A TW97110928A TWI380387B TW I380387 B TWI380387 B TW I380387B TW 097110928 A TW097110928 A TW 097110928A TW 97110928 A TW97110928 A TW 97110928A TW I380387 B TWI380387 B TW I380387B
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TW
Taiwan
Prior art keywords
layer
package substrate
heat dissipation
high heat
substrate
Prior art date
Application number
TW097110928A
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English (en)
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TW200921819A (en
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Publication date
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Publication of TW200921819A publication Critical patent/TW200921819A/zh
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Publication of TWI380387B publication Critical patent/TWI380387B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Description

1380387 % 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種高散熱性封裝基板之製作方 ' & ’尤指―種以銅核基板為基礎’開始製作封裝基板 .之製作方法，於其中’該封裝基板之結構係包括複數 個球側電性接腳接墊、一厚銅蝕刻線路及至少一捭声 線路。 曰曰 • 【先前技術】 /在一般多層圭于裝基板之製作上，其製作方式通常 係由一核心基板開始，經過鑽孔、電鍍金屬塞孔及 雙面線路製作等方<，完成一冑面結構之内層核心 板，之後再經由一線路增層製程完成一多層封裝基 板。如帛2 1目料，其係為一有核層封裝基板之别 面示意圖。首先，準備一核心基板6〇，其中，該核 心基板6 0係由一具預定厚度之芯層6 〇丄及形成於 • 此芯層6 0 1表面之線路層6 〇 2所構成，且該忠層 6 Ο 1中係形成有複數個電鍍導通孔6 3，可藉以 連接該芯層6 0 1表面之線路層6 〇 2。 - 接著如第2 2圖〜第2 5圖所示，對該核心基板 6 0實施線路增層製程。首先，係於該核心基板6 〇 表面形成一第一介電層61，且該第一介電層61表 面並形成有複數個第一開口 6 2，以露出該線路層6 0 2 ;之後’以無電電鍍與電鍍等方式於該第一介電 5 1380387
層6”卜露之表面形成_晶種層63，並於該晶種層 63上形成一圖案化阻層“，且其圖案化阻層U 中並有複數個第二開σ 6 5，以露出部份欲形成圖案 化線路之晶種層6 3 ;接著，制魏之方式於該第 -開口 6 5中形成-第-圖案化線路層6 6及複數個 導電盲孔6 7 ’並使其第一圖案化線路層6 6得以透 過該複數鱗電盲孔6 7與該核基板6 0之線路層 6 0 2做電性導通，然後再進行移除該圖案化阻層g 4錢刻’待完成後係形成—第—線路增層結構6\。 同樣地，該法係可於該第一線路增層結構6a之最外 層表面再運用相同之方式形成—第二介電層6 8及一 第二圖案化線路層6 9之第二線路增層結構6 b，以逐 步增層方式形成一多層封裝基板。然而，此種製作方 法有佈線密度低、層數多及流程複雜等缺點。 另外’亦有利用厚銅金屬板當核心材料之方法， 可於經過舒刻及塞孔等方式完成一内層核心板後，再 經由一線路增層製程以完成一多層封裝基板。如第2 6圖〜第28圖所示，其係為另一有核層封裝基板之 剖面示意圖。首先，準備一核心基板7 〇，該核心基 板70係由一具預定厚度之金屬層利用蝕刻與樹脂塞 孔7 0 1以及鑽孔與電鍍通孔7 〇2等方式形成之單 層銅核心基板7 0 ;之後，利用上述線路增層方式， 於該核心基板7 〇表面形成一第一介電層7 1及一第 一圖案化線路層7 2，藉此構成一具第一線路增層結 6 構7a。該法亦與上述 ^ 增層方式於該第-線路可再利用一次線路 成-第二介電層73及：】、、，。構7a之最外層表面形 .^ θ ^ 第二圖案化線路層74,藉 士一 , 〃第一線路增層結構7 b，以逐步增層方式形 心基板且:而’此種製作方法不僅其銅核 度低及流程複雜等二與：述方法相同，具有佈線密 使用者於實所需故:-般_系_合 【發明内容】 降夕：：：之主要目的係在於’使用本發明具高散熱 H 板之方法所製造之高散熱性封裝基板，係 可效達到改善超薄核層基板板彎輕問題、及簡化傳 統增層線路板製作流程之目的。 本發明之次要目的係在於，從一銅核基板為基 礎，開始製作之封裝基板。其結構係包括複數個球側 電性接腳接墊、-厚銅飯刻線路及至少—增層線路。 於其中，電性接腳接墊與厚銅線路係由銅核基板之兩 面分別蝕刻而成，且各增層線路與厚銅蝕刻線路連接 之方式係以複數個電鐘盲、埋孔所導通。 本發明之另一目的係在於，製作厚銅蝕刻線路時 能具選擇性地保留位於置晶位置下方之厚鋼，以提供 置晶接墊，在該置晶接墊與增層線路上所形成之凹槽 結構位置相符下，可使置晶時晶片能與下方金屬接^ 1380387 〜丨八a日门崎邛吁艮好之散熱結構，進 有效地增加元件之散熱效果；同時並可以其具有 高密度增層線路提供電子元件相連時所需之繞線。 直接結合’以提供晶片運 之
為達以上之目的，本發明係一種高散熱性封裝基 板之製作方去，係先以光學微影及姓刻之方式於—銅 核基板之第一面上形成複數第一凹槽，藉以突顯一第 一線路層，並以此第一線路層作為與增層線路及球側 接腳導通之電性連接墊。之後於該第一線路層上形成 複數導電盲孔以連接至少一增層線路，並在增層線路 之置晶侧形成電性接墊，接著再於該銅核基板之第二 面以相同方式形成複數第二凹槽，以突顯複數接腳之 一部分’最後係填入電性阻絕材料以形成一球側電性 連接墊。其中，該增層線路上係具有至少一凹槽結構， 該凹槽結構係與厚銅钱刻線路上之置晶接塾位置相 符，以提供置晶時晶片能與下方金屬接墊直接結合， 增加其散熱效果。 【實施方式】 請參閱『第1圖』所示’係分別為本發明之製作 流程示意圖。如圖所示：本發明係一種高散熱性封裝 基板之製作方法，其至少包括下列步驟： (A)提供銅核基板11:提供一銅核基板； (B )形成第一、二阻層及複數個第一開口 1 2 : 分別於該銅核基板之第一面上形成一第一阻層，以及 8 於該銅核基板之第二面上形成一完全覆蓋狀之第二阻 曰於/、中，並以曝光及顯影之方式在該第一阻層上 形成複數個第1口，以顯露其下該編基板之第-面， (c )形成第-凹槽1 3 :以蝕刻之方式於複數 個第-開口下方形成複數個第一凹槽； (D) 移除第―、二阻層工4:以剝離之方式移 第P且層及該第二阻層，形成具有第一線路層之 銅核基板； (E) 形成第-電性阻絕層工5 :以直接壓合或 =刷之方式於複數個第—凹槽⑽成—第—電性阻絕 層，並顯露該第一線路層； (F) 形成第-介電層及第一金屬層"：於該 第一線路層與該第一電性阻絕層上直接壓合一第一介 :層及-第-_，亦或係先採取貼合該第一介電 笛2形成該第一金屬層，於其中，該第-介電層 I -金屬層係形成有複數個定義置晶位置之中空 凹槽’並顯露該第一線路層之金屬接墊；
形成複數個第二開口 17:以雷射鑽孔之 一^〜—金屬層與該第—介電層上形成複數個第 r汗^並顯露其下之第一線路層，其中，複數個第 :開口係可先做開銅窗（conformal M 由雷射鑽孔之方式弗占 弋形成亦或係以直接雷射鑽孔 C LASER Direct)之方式形成； 1380387 (Η)形成第三阻層i 8 ··於該銅核基板之第二 面上形成一第三阻層； (I )形成第二金屬層1 9 :以無電電鍍與電鍵 之方式於複數個第二開口中及複數個中空凹槽所顯露 之第一線路層上形成一第二金屬層； (J )移除第三阻層2 〇 :以剝離之方式移除該 第三阻層； (K )形成第四、五阻層及複數個第三開口 2工： 分別於該第二金屬層上形成一第四阻層，以及於該銅 核基板之第二面上形成一完全覆蓋狀之第五阻層，於 其中’並以曝光及顯影之方式在$第四阻層上形成複 數個第三開口，以顯露其下之第二金屬層； (L )移除顯露第— ' 二金屬層2 2 :以蝕刻之 :式移除該第三開口下方之第二金屬層及第一金屬 層； (Μ) Μ具有純錢切之雙層線路基板2 士以剝離之方式移除該第四阻層及該第五阻層，並 :镂：第二線路層。至此’完成一具有銅核基板支擇 θ線路基板，並可直接進行步驟（Ν);以及 势作進行置晶側線路層與球侧電性接腳接墊之 ^乍24 :於該雙層線路基板上 與球側電性接腳接墊之製作，於線:層 層表面形成-第-防靜* 纟該第二線路 該第一防焊層上形成複數個第肪 式在 禾四開口，以顯露線路增 層=構作為電性連接塾之部分，接著再分別於該第_ 防焊層上形成—完全覆蓋狀之第六阻層，以及於該銅 核基板之第二面上形成一第七阻層，並且在該第七阻 層上以曝光及顯影之方式形成複數個第五開口，以顯 露其y該銅核基板之第二面。之後以蝕刻之方式於複 數個第五開口上形成複數個第二凹槽，並顯露複數個 第五開口下方之第一電性阻絕層或第一線路層，接著 再以剝離之方式移除該第六阻層及該第七阻層，以形 成^·數個柱狀接腳，之後並於複數個第二凹槽内以直 接壓合或印刷之方式形成一第二電性阻絕層，以顯露 球侧複數個電性接腳接墊，最後，分別於複數個第四 開口上形成一第一阻障層，以及於複數個電性接腳接 墊上形成一第二阻障層。至此，完成一具有完整圖案 化之置晶側線路層與球側複數電性接腳接墊之封裝基 板，其中，該第一防焊層係以印刷、旋轉塗佈或噴塗 φ 所為之高感光性液態光阻；該第一、二阻障層係可為 電鍍鎳金、無電鍍鎳金、電鍍銀或電鍍錫中擇其一。 於其中’上述該第一〜七阻層係以貼合、印刷或 旋轉塗佈所為之乾膜或溼膜之高感光性光阻；該第 一、二電性阻絕層及該第一介電層係可為防焊綠漆、 玉衣氧樹脂絕緣膜（Ajinomoto Build-up Film, ABF)、苯 裱丁烯（Benzocyclo-buthene，BCB)、雙馬來亞醯胺_ 一氮雜本樹脂（Bismaleimide Triazine，BT )、環氧樹脂 板（FR4、FR5 )、聚酿亞胺（p〇iyimide，PI)、聚四氟 11 1380387 乙烯（Poly(tetra-floroethylene)，PTFE)或環氧樹脂及 玻璃纖維所組成之一者。 請參閱『第2圖〜第1 4圖』所示，係分別為本 發明一實施例之封裝基板（一）剖面剖面示意圖、本 發明一實施例之封裝基板（二）剖面示意圖、本發明 一實施例之封裝基板（三）剖面示意圖、本發明一實 施例之封裝基板（四）剖面示意圖、本發明一實施例 之封裝基板（五）剖面示意圖、本發明一實.施例之封 裝基板（六）剖面示意圖、本發明一實施例之封裝基 板（七）剖面示意圖、本發明一實施例之封裝基板（八） 剖面示意圖、本發明一實施例之封裝基板（九）剖面 示意圖、本發明一實施例之封裝基板（十）剖面示意 圖、本發明一實施例之封裝基板（十一）剖面示意圖、 本發明一實施例之封裝基板（十二）剖面示意圖及本 發明一實施例之封裝基板（十三）剖面示意圖。如圖 所示：本發明於一較佳實施例中，係先提供一銅核基 板3 0 a，並分別於該銅核基板3 〇3之第一面上貼合 一高感光性高分子材料之第一阻層3 i，以及於該銅 核基板3 Oa之第二面上貼合一高感光性高分子材料 之第二阻層3 2，並以曝光及顯影之方式在該第一阻 層3 1上形成複數個第一開口33，以顯露其下該銅 核基板3〇a《第一面’而其第二面上之第二阻層3 2則為完全覆蓋狀。接著以㈣之方式製作___第—凹 槽3 4 ’並移除該第_、二阻層，以形成具有第一線 12 1380387 路層之銅核基板3 Ob，隨後，印刷— 35於該第-e?槽34中，以顯露細:電性阻絕層 出該第一续致_思 其中，該銅核基板3 0a、3〇b係為一不入二曰’ 料之厚銅板；該第一、二阻層3 i、 ，"電層材 阻層；該第-電性阻絕層3 5係為防焊=為乾膜光 接著，於該第一線路層與該第一 上壓合一第一介電層36及一第:全屬電=層35 該第-介電層36及該第-金屬層37^:’其中 =形出複數個預作為定義置晶位置之中空凹=刀 露出Γ 一線路層之金屬接藝，藉以增加 二:文果。之後再以雷射鑽孔之方式於該第 曰3 7與該第一介電層3 6上形成複 9,接著並於該鋼核基板3〇b之第二面：：Γ! 感先性尚分子材料之第三阻層4q，並以 : 電鍍之方式於複數個第二開口 3 9 鍍與 38下方之第一飨改思主二 I數個中空凹槽 之第線路層表面形成一第二金屬芦 之後移除該第三阻層，盆中， 曰 4 1皆A柄口 ，、T該第-、一金屬層3 7、 4 1白為銅，且該第二金屬層4丄係作 路層之電性連接用。 一。第線 接著，分別於該第二金屬層4 i 性高分子材料“丄上貼--尚感光 ◦b之第：面四 2，以及於該鋼核基板3 層43,拍膜“合一尚感光性高分子材料之第五阻 、光及顯影之方式於該第四阻層42上來 弟-開口44 ’以顯露其下之第二金屬層4 13 1380387 % 1。最後係以蝕刻之方式移除該第三開口 4 4下之第 一、二金屬層，並再移除該第四、五阻層，以形成一 第二線路層4 5。至此’完成一具有該銅核基板支樓 之雙層線路基板3。 請參閱『第1 5圖〜第2 0圖』所示，係分別為 本發明一實施例之封裝基板（十四）剖面示意圖、本 發明一實施例之封裝基板（十五）剖面示意圖、本發 明一實施例之封裝基板（十六）剖面示意圖、本發明 一實施例之封裝基板（十七）剖面示意圖、本發明一 實施例之封裝基板（十八）剖面示意圖及本發明一實 施例之封裝基板（十九）剖面示意圖。如圖所示：在 本發明較佳實施例中，係接著進行置晶侧線路層與球 側電性接腳接墊之製作。首先於該第二線路層4 5'表 面塗覆一層絕緣保護用之第一防焊層4 6，並以曝光 及顯影之方式於該第-防焊6上形成複數個第四 開口 4 7，以顯露線路增層結構作為電性連接墊。接 著分別於該第-防焊層4 6上貼合—高感光性高分子 材料之第六阻層4 8，以及於該銅核基板3 〇b之第 一面上貼合一高感光性高分子材料之第七阻層49， =曝光及㈣之方式在該第七阻層㈠上形成複數 _五開口5 0，以顯露其下該銅核基板3〇b之第 =’而該第-防焊層46則以該第六阻層48完全 。之後係以蝕刻之方式製作一第二凹槽 移除該第六、七阻層’以形成具複數個柱狀接腳之銅 1380387 核基板3 0 c，然後係印刷一第二電性阻絕層5 2於該 第二凹槽5 1中，以顯露出複數個電性接腳接墊5 3，最後，分別於複數個第四開口 4 7上形成一第一 阻障層5 4，以及於複數個電性接腳接墊5 3上形成 -第二阻障層5 5。至此，完成一具高散熱性之封裝 基板5，其中，該第二電性阻絕層5 2係為防焊綠漆； 該第一、二阻障層54、55皆為鎳金層。 由上述可知，本發明係從銅核基板為基礎，開始 製作之封裝基板，其結構係包括複數個球側電性接腳 接墊、一厚銅蝕刻線路及至少一增層線路。於其中， 電性接腳接墊與厚銅線路係由銅核基板之兩面分別蝕 刻而成，且各增層線路與厚銅蝕刻線路連接之方式係 以複數個電鍍盲、埋孔所導通。因此，本發明封裝基 板之特色係在於，製作厚銅蝕刻線路時能具選擇性地 保留位於置晶位置下方之厚銅，以提供置晶接墊，同 時，並於該增層線路上形成至少一凹槽結構，且該凹 槽結構並與厚銅蝕刻線路上之置晶接墊位置相符，可 提供置晶時晶片能與下方金屬接墊直接結合，以提供 晶片運作時良好之散熱結構，進而有效增加元件之散 熱敗果；並且，其具有之高密度增層線路更可提供電 子元件相連時所需之繞線。藉此，使用本發明具高散 熱性之封裝基板之方法所製造之高散熱性封裝基板， 係可有效達到改善超薄核層基板板彎翹問題、及簡化 傳統增層線路板製作流程之目的。 Ι38Θ387 綜上所述，本發明係一種高散熱性封裝基板之製 作方法，可有效改善習用之種種缺點，利用於厚銅蝕 刻線路時所選擇性地保留位於置晶位置下方之厚銅， 以及增層線路上所形成之中空凹槽，可使晶片能與下 方金屬接墊直接結合，有效地提供元件散熱之所需， 同時並可以其高密度增層線路提供電子元件相連時所 需之繞線，因此可有效改善超薄核層基板板彎翹問題 及簡化傳統增層線路板製作流程之目的，進而使本發 明之産生能更進步、更實用、更符合使用者之所須， 確已符合發明專利申請之要件，爰依法提出專利申請。 惟以上所述者，僅為本發明之較佳實施例而已， 當不能以此限定本發明實施之範圍；故，凡依本發明 申請專利範圍及發明說明書内容所作之簡單的等效變 化與修飾，皆應仍屬本發明專利涵蓋之範圍内。
16 【圖式簡單說明】 第1圖，係本發明之製作流程示意圖。 第2圖，係本發明一實施例之封裝基板（一）剖面示 意圖。 第3圖，係本發明一實施例之封裝基板（二）剖面示 意圖。 第4圖’係本發明一實施例之封裝基板（三）剖面示 意圖。 第5圖’係本發明一實施例之封裝基板（四）剖面示 意圖。 第6圖’係本發明一實施例之封裝基板（五）剖面示 意圖。 第7圖’係本發明一實施例之封裝基板（六）剖面示 意圖。 第8圖’係本發明一實施例之封裝基板（七）剖面示 意圖。 第9圖’係本發明—實施例之封裝基板（八）剖面示 意圖。 第1 0圖’係本發明一實施例之封裝基板（九）剖面 1380387 、 第1 1.圖，係本發明一實施例之封裝基板（十）剖面 示意圖。 第1 2圖，係本發明一實施例之封裝基板（十一）剖 面示意圖。 第1 3圖，係本發明一實施例之封裝基板（十二）剖 面示意圖。 第1 4圖，係本發明一實施例之封裝基板（十三）剖 • 面示思圖。 第1 5圖，係本發明一實施例之封裝基板（十四）剖 面示意圖。 第1 6圖，係本發明一實施例之封裝基板（十五）剖 面示意圖。 第1 7圖，係本發明一實施例之封裝基板（十六）剖 Φ 面示意圖。 第1 8圖，係本發明一實施例之封裝基板（十七）剖 面示意圖。 第1 9圖，係本發明一實施例之封裝基板（十八）剖 面示意圖。 第2 0圖，係本發明一實施例之封裝基板（十九）剖 面示意圖。 18 1380387 第2 1圖，係習用有核層封裝基板之剖面示意圖。 第2 2圖’係習用實施線路增層（一）剖面示意圖。 第2 3圖，係習用實施線路增層（二）剖面示意圖。 第2 4圖，係習用實施線路增層（三）剖面示意圖。 第2 5圖，係習用實施線路增層（四）剖面示意圖。 第2 6圖，係另-習用有核層封|基板之剖面示意圖 第2 7圖’係另-習用之第一線路增層結構剖面示意 圖。 第2 8圖，係另一習用之第二路増層結構剖面示意圖。 【主要元件符號說明】 (本發明部分） 鲁 步驟（A)〜（N) 11〜24 雙層線路基板3 封裴基板5 銅核基板3 0 a 具第一線路層之銅核基板3 〇b 具柱狀接腳之銅核基板3 〇 c 第一、二阻層3 1、3 2 _ 第一開口 3 3 19 1380387 第一凹槽3 4 第一電性阻絕層3 5 第一介電層3 6 第一金屬層3 7 中空凹槽3 8 第二開口 3 9 第三阻層4 0 第二金屬層4 1 第四、五阻層4 2、4 3 第三開口 4 4 第二線路層4 5 第一防焊層4 6 第四開口 4 7 第六、七阻層48、49 第五開口 5 0 第二凹槽5 1 第二電性阻絕層5 2 電性接腳接墊5 3 第一、二阻障層54、55 (習用部分） 20 1380387 第一、二線路增層結構6a、6b 第一、二線路增層結構7a、7b 核心基板6 Ο 芯層6 Ο 1 線路層6 0 2 電鍍導通孔6 0 3 第一介電層6 1 第一開口 6 2 該晶種層6 3 圖案化阻層6 4 第二開口 6 5 第一圖案化線路層6 6 導電盲孔6 7 第二介電層6 8 第二圖案化線路層6 9 核心基板7 0 樹脂塞孔7 0 1 電鍍通孔7 0 2 第一介電層7 1 第一圖案化線路層7 2 21 1380387 第二介電層7 3 第二圖案化線路層7 4
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Claims (1)

1380387 7 ·依據申請專利範圍第1項所述之高散熱性封裝基板 之製作方法，其中，該第一、二電性阻絕層係以直 接壓合或印刷之方式形成。 8 ·依據申請專利範圍第1項所述之高散熱性封裝基板 之製作方法’其中，該第一、二電性阻絕層及該第 一介電層係可為防焊綠漆、環氧樹脂絕緣膜 C Ajinomoto Build-up Film, ABF )、苯環丁烯 (Benzocyclo-buthene，BCB )、雙馬來亞醯胺-三氮 雜苯樹脂（BismaleimideTriazine’BT)、環氧樹脂 板（FR4、FR5)、聚醯亞胺（P〇iyimide，pi)、聚 四氟乙烯（Poly(tetra-floroethylene)，PTFE )或環氧 樹脂及玻璃纖維所組成之一者。
9 ·依據申請專利範圍第i項所述之高散熱性封装基板 之製作方法’其中’該步驟（F )係以直接壓合該 第一介電層及該第-金屬層於其上，或係採取貼合 該第一介電層後，再形成該第一金屬層。 1 0 ·依據申請專利範圍第 板之製作方法，其中， 層係一具有複數個中空 1項所述之高散熱性封裝基 該第一介電層及該第一金屬 凹槽結構之材料。 基範所述之高散熱 /、中，複數個中空凹槽結構之子 成方式係可為沖壓、雷射或銑刀成形。 26 1380387 1 2 .依據申請專利範圍第1項所述之高散熱性封裝基 板之製作方法，其中，複數個第二開口係可先做開 銅窗（Conformal Mask)後，再經由雷射鑽孔之方 式形成’亦或係以直接雷射鑽孔（LASER Direct) 之方式形成。 I •依據申請專利範圍第1項所述之高散熱性封裝基 板之製作方法，其中，該第二金屬層之形成方式係 可為無電電鍍與電鍍。 4 ·依據申請專利範㈣1項所述之高散熱性封裏基 =之製作方法’其中，該第—㈣層係以印刷、旋 塗佈或噴塗所為之高感光性液態光阻。 5板第所述之高散熱性封裝基 鍵鎳金'無電缠錄金、電：或電 27
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