TWI361481B - - Google Patents

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Publication number
TWI361481B
TWI361481B TW097108808A TW97108808A TWI361481B TW I361481 B TWI361481 B TW I361481B TW 097108808 A TW097108808 A TW 097108808A TW 97108808 A TW97108808 A TW 97108808A TW I361481 B TWI361481 B TW I361481B
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TW
Taiwan
Prior art keywords
layer
copper core
substrate
copper
forming
Prior art date
Application number
TW097108808A
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English (en)
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TW200921875A (en
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Publication of TW200921875A publication Critical patent/TW200921875A/zh
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Publication of TWI361481B publication Critical patent/TWI361481B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Description

1361481 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種銅核層多層封裝基板之势 方法，尤指一種以銅核基板為基礎，開始製作之單、 多層封裝基板之製作方法。 早面、 【先前技術】 在一般多層封裝基板之製作上，其製 係由-核心基板開始，經過鑽孔、電鑛金屬、 雙面線路製作等方式，完成—雙面結構之内層核心 板’之後再經由一線路增層掣茲—士 沭峪曰層裏私凡成一多層封裝基 板。如第2i圖所示，其係為一有核層封裝基板之剖 面示意圖。首先，準備-核心基板5 〇，其中，仙 由一具預定厚度之芯層5 01及形成於 二! 面之線路層5 0 2所構成，且該芯層 5 0 1中係形成有複數個電鍍導通 連㈣層5〇1表面之線路層5〇2〇3 了錯 ς η -著余第2 2圖〜第2 5圖所示，對該核心基板 表面形成-第曰，:該核心基板50 面並形成有複數個第: °玄弟一介電層51表 n 9 . . ,. U第開口 5 2，以露出該線路層5 Η ; /ΐ’以無電電鑛與電鍵等方式於該第一介電 “1:二表面形成一晶種層53，並於該晶種詹 圖案化阻層54其圖案化阻層54 1361481 個第二開口55，以露出部份欲形成圖案 -門口 3 ’接著’利用電鍍之方式於該第 :::55中形成一第_圖案化線路層5 導電盲孔57，並使其第一圖案化線路層56得以透 過該複數個導電盲孔5 7與該核心基板5 〇之線路声 5 〇 2做電性導通，然後再進行移除該圖案化阻層5Θ 刻’待完成後係形成一第一線路增層結構二。 ^地’該㈣可於該第―線路增層結構5a之最外 層表面再運用相同之方式形成一第二介電層5 8及一 =二圖案化線路層59之第二線路增層結構5b，以逐 乂增層方式形成一多屬封裝基板。然而，此種譽作方 法有佈線錢低、層數多及流程㈣等缺點。 另外，亦有利用厚銅金屬板當核心材料之方法， 可於經過#刻及塞孔等方式完成一内層核心板後再 經由-線路增層製程以完m封裝基板。如第2 6圖帛28圖所示’其係為另一有核層封裝基板之 剖面示意圖。首先’準備一核心基板6〇，該核心基 〇係由具預疋厚度之金屬層利用餘刻與樹脂塞 孔6 〇 1以及鑽孔與電鍵通孔6 0 2等方式形成之單 層鋼核〜基板6 Q ;之後，利用上述線路增層方式， 於°亥核〜基板6 0表面形成一第一介電層6 1及一第 圖案化線路層6 2，藉此構成-具第—線路增層结 構6 a。該法亦與上述方法相同，係可制用—次線路 增層方式於該第—線路增層結構6 a之最外層表面形 1361481 成一第二介電層6 3及一第二圖案化線路層6 4 ,藉 此構成一具第二線路增層結構6b，以逐步增層方式^ 成一多層封裝基板。然❿，此種製作方法不僅盆銅核 心基板製作不易，且亦與上述方法相同，具有佈線密 度低及流程複雜等缺點。故，一般習用者係無法符合 使用者於實際使用時之所需。 … ° 【發明内容】 本發明之主要目的係在於，使用本發明具高密度 之增層線路封裝基板方法所製造之多層封裝基板，係 可依實際需求形成具銅核基板支樓之銅核層多層封裝 基板，並可有效達到改善超薄核層基板板彎翹問題、 及簡化傳統增層線路板製作流程，進而達到提高封裝 體接合基板時之可靠度（Board Leve丨ReHabi丨办）。 本發明之次要目的係在於’從銅核基板為基礎， 開始製作之單面、多層封裝基板，其結構係包括一具 高剛性支狀銅板，且此銅板之—㈣具增層線路， 另一面則具球側圖案阻障層，於其中，各增層線路及 置晶側與球側連接之方式係以複數個電鍵盲、埋孔所 導通。 本發明之另-目的係在於，具有高密度增層線路 以提供電子元件相連時所需之繞線，同時，並以銅板 提供足夠之剛性使製程可更為簡易。 1361481 為達以上之目的’本發明係一種銅核層多層封裝 基板之製作方法，係於一銅核基板之第一面上壓合二 $電層材料與一金屬層，之後於該面上形成複數電鍍 s孔以連接該銅核基板與至少一增層線路並在増層 線路之置晶側形成電性接墊；而該銅核基板之第 則形成球侧圖案阻障層，以作為封裝流程完成後移除 該銅核基板所形成之柱狀電性接腳接墊。其中，雖然 各線路在封裝製程完成前於電性上係完全短路但^ 裝製程完成後則可利用該球側圖案阻障層，以蝕刻之 方式移除部份之銅板，進而可使電性獨立並形成具保 護作用之柱狀接腳。 【實施方式] 一叫參閱『第1圖』所示，係為本發明之製作流程 示意圖。如圖所示：本發明係一種銅核層多層封 板之製作方法，其至少包括下列步驟： (A) 提供銅核基板:提供一銅核基板； (B) 形成第一介電層及第一金屬層12:於該 銅核基板之第—面上直㈣合—第-介電層及—第二 金屬層’亦或係先採取貼合該第一介電層後 該第一金屬層； 战 (C )形成複數個第一開口丄3 :以雷射鑽孔之 =式於該第—金屬層及該第—介電層上形成複數個第 開口，並顯露部分之銅核基板第一面，其中，複數 1361481 個第一開口係可先做開銅窗（Conformal Mask )後， 再經由雷射鑽孔之方式形成，亦或係以直接雷射鑽孔 (LASER Direct)之方式形成； (D)形成第二金屬層14:以無電電鍍與電鑛 之方式於複數個第一開口中及該第一金屬層上形成一 第二金屬層；
(E )形成第一、二阻層及複數個第二開口 1 5 : 为別於δ玄第二金屬層上形成一第一阻層，以及於該銅 核基板之第二面上形成一完全覆蓋狀之第二阻層，於 其中，並以曝光及顯影之方式在該第一阻層上形成複 數個第一開口，以顯露部分之第二金屬層； (F )形成第一線路層1 6 :以蝕刻之方式移除 該第二開口下方之第二金屬層及第一金制，並形成 一第一線路層； (G)完成具有銅核基板支撐並具電性連接之單
層增層線路基板17:以剝離之方式移除該第-阻層 亥第一阻層。至此，完成一具有銅核基板支撐並且 =接之單層增層線路基板，並可選擇直接進行； 驟（Η)或步驟（I ); ()進仃置日曰側與球側線路層製作 早層增層線路基板上進行一罢s ν丨^ 及 ^ 退仃置晶側與球側線路層势 也 第、線路層表面形成塗覆-芦且绍 緣保護用之第一防焊層，並 "^ 第一防焊層上形成複數個第= 在4 , 弟—開口，以顯露該第一線 9 ^61481 :為電性連接墊之部分。接著以刷磨絲刻之方 二、低該銅核基板第二面之銅厚度，並於減鋼後之銅 广土板第二面上形成-第三阻層’且在該第三阻層上 以曝光及顯影之方式形成複數個第四㈤口， 別於複數個第三開口中形成一第一阻障層，以及於二 口中形成-第二阻障層，最後以剝離之方式移除 j 一且層。至此，完成一具有完整圖案化之置晶側 =層與已®案化但仍完全電性短路之球側線路層， 二中，該第-、二阻障層係可為電鍍鎳金、無電鍍鎳 金、電鍍銀或電鍍錫中擇其一；以及 (1 )進行線路增層結構製作1 9 :於該單邦 曰線路基板上進行-線路增層結構製作H中^ :第-線路層及該第一介電層表面形成一第二介電 :第射鑽孔之方式在該第二介電層上形成複數 %電鑛之方式於該第二介電層與複數個第五開口 、面形成-第-晶種層’再分別於該第一晶種層上形 第：阻層’以及於該銅核基板之第二面上形成二 2覆盍狀之第五阻層’並利用曝光及顯影之方式於 二第四阻層上形成複數個第六開口，以顯露部 :晶種層’之後再以電鍍之方式於該第六開口 ::第-晶種層上形成一第三金屬層，最後以剝離之 方式移除該帛四阻料該帛五阻層，細㈣ 移除該第-晶種層’以在該第二介電層上形成—第^ 1361481 線路層。至此，又再增加—層料增層結構，完成一 具有銅核基板支撑並具電性連接之雙層增層線路基 板。並可繼續本步驟（1)增加線路增層結構形成 具更夕層之封裝基板’亦或直接至該步驟（H)進行 置晶側與球側線路層製作，纟中，複數個第五開口係 可先做開銅窗後’再經由雷射鑽孔之方式形成，亦或 係以直接雷射鑽孔之方式形成。
於其中，上述該第一〜五阻層係以貼合、印刷或 旋轉塗佈所為之乾臈或溼膜之高感光性光阻；該第 一、二介電層係可為環氧樹脂絕緣臈（Ajin〇m〇t〇 Build-up FUm，ABF)、苯環丁烯（Benz〇cyci〇 buthene, BCB)、雙馬來亞醯胺·三氮雜苯樹脂（此―丨心 Triazine，BT)、環氧樹脂板（FR4、FR5)、聚醯亞胺 (Polyimide， PI ),聚四氟乙烯 (P〇ly(tetra_fl〇roethyiene)，PTFE)或環氧樹脂及玻璃 纖維所組成之一者。 請參閱『第2圖〜第8圖』所示，係分別為本發 明一實施例之多層封裝基板（一）剖面剖面示意圖、 本發明一實施例之多層封裝基板（二）剖面示意圖、 本發明一實施例之多層封裝基板（三）剖面示意圖、 本發明一實施例之多層封裝基板（四）剖面示意圖、 本發明一實施例之多層封裝基板（五）剖面示意圖、 本發明一實施例之多層封裝基板（六）剖面示意圖、 及本發明一實施例之多層封裝基板（七）剖面示意圖。 1361481 如圖所示··本發明於一較佳實施例中，係先提供一鋼 核基板2 〇a，並於該銅核基板2 〇a之第—面上塵合 -第-介電層21及一第一金屬層22，並以雷射鑽 孔之方式在該第一金屬層22與該第一介電層21上 形成複數個第一開口 2 3 ’以顯露其下之銅‘基板2 第面之後，再以無電電鍍與電鍍之方式於複 數個第-開口 2 3内及該第-金屬層2 2表面形成一 第二金屬層2 4 ’其中，該銅核基板2 Qa係為一不 含介電層材料之銅板；該第一、二金屬層2 2、2 4 皆為銅，且該第二金屬層2'4係作為與該第一金屬層 2 2之電性連接用。
接著，分別於該第二金屬層2 4上貼合一高感光 性高分子材料之第一阻層2 5，以及於該銅核基板2 0 a之第二面上貼合一高感光性高分子材料之第二阻 層2 6。並以曝光及顯影之方式於該第一阻層2 5上 形成複數個第二開口 2 7，以顯露其下之第二金屬層 2 4。之後係以蝕刻之方式移除該第二開口 2 7下之 第一、二金屬層，以形成一第一線路層2 8，最後並 移除該第一、二阻層。至此，完成一具有銅核基板支 撐並具電性連接之單層增層線路基板2。 請參閱『第9圖〜第1 3圖』所示’係分別為本 發明貫知例之多層封裝基板（八）剖面示意圖、本 發明一實施例之多層封裝基板（九）剖面示意圖、本 12 1361481 發明一實施例之多層封裝基板（十）剖面示意圖本 發明-實施例之多層封裝基板（十一）剖面示意圖、 及本發明一實施例之多層封裝基板（十二）剖面示音 圖。如圖所示：在本發明較佳實施例中，係先行進g 線路增層結構之製作。首先於該第一線路層2 8與^ -介電層2 1上貼壓合-為環氧樹脂絕緣膜材料^第 二介電層2 9 ’之後，以雷射鑽孔之方式於該第二介 電層2 9上形成複數個第三開口 3 〇，以顯露其下之 第一線路層2 8，並在該第二介電層2 9及該第三開 口 3 0表面以無電電鍍與電鍍之方式形成一第一晶種 層3 1。之後分別於該第一晶種層3工上貼合一 光性高分子㈣之第三_32 1錄該銅核基板 2 0a之第二面上貼合—高感光性高分子材料之第四 阻層3 3 ’接著利用曝光及顯影之方式於該第三阻層 3 2上形成複數個第四開σ 3 4，然後再於複數個^ 四開口 3 4中電鑛-第三金屬層3 5，最㈣除_ 三、四阻層，並再以_之方式移除顯露之第一晶種 層3 1，以形成-第二線路層3 6。至此又再增加 -層之線路增層結構’完成—具有銅核基板支樓並且 電性連接之雙層增層線路基板3，於其中，該第一晶 種層3 1與該第三金屬層3 5皆為金屬銅。Λ日日 請參閱『第14圖〜第2〇圖』所示，係分別為 本發明-實關之多層料基板（十三）剖面示意圖、 本發明-實施例之多㈣裝基板（十四）剖面示意圖、 13 =一^例之多層封裝基板(十五)剖面示意圖 m施例之多層封裝基板(十六)到面示意圖， m施例之多層封裝基板(十七)剖面示意圖、 =明—實施例之多層封裝基板（十A)剖面示意圖、 二二月一實施例之多層封裝基板（十九）剖面示意 圖。如圖所示：之後’在本發明較佳實施例t係接著 ::置晶侧與球側線路層之製作。首先於該第二線路 曰3 6表面塗覆一層絕緣保護用之第一防焊層3 7， :後”曝光及顯影之方式於該第-防浮層3曰7上形 =數個第五開口3 8 ’以顯露其線路增層結構作為 欠連接塾。接著’於該第一防焊層3 7及該第二線 層3 6上貼合-高感光性高分子材料之第五阻層3 9 ’並於該銅核基板20a之第二面上以钱刻或刷磨 之方式做減銅，待減低該鋼核基板第二面之銅厚度 後，再以剝離之方式移除該第五阻層，並於減銅後之 銅核基板20b第二面上貼合—高感光性高分子材料 之第六阻層40 ’之後以曝光及顯影之方式於該第六 阻層4 0上形成複數個第六開"工，再分別於複數 個第五開口 3 8上形成一第一阻障層4 2，以及於複 數個第六開口 4 1上形成一以，最後， 移-除δ玄第六阻層。至此，完成—具銅核層支撐之多層 封震基板4，其中，該第-、二阻障層4 2、4 3皆 為鎳金層。 14 1361481 j由上述可知，本發明係從銅核基板為基礎，開始 製作之單面、多層封裝基板’其結構係包括一具高剛 支樓之銅板，且此銅板之一面係具增層線路，另一 .面則具球侧圖案阻障層。於其中，各增層線路及置晶 . 側與球側連接之方式係以複數個電鍍盲'埋孔所導 • 通。因此，本發明封裝基板之特色係在於具有高密度 ， 增層線路以提供電子元件相連時所需之繞線，同時， 並以銅板提供足夠之剛性使封裝製程可更為簡易。雖 然各線路在封裝製程完成前於電性上係完全短路，但 封裝製程完成後則可利用球側圖案阻障層，以蝕刻之 方式移除部份之銅板，進而可使電性獨立並形成具保 濩作用之柱狀接腳。藉此，使用本發明具高密度之增 f線路封裝基板方法所製造之多層封裝基板，係可^ 實際需求形成具銅核基板支撐之銅核層多層封裝基 板，並可有效達到改善超薄核層基板板彎翹問題及 φ 簡化傳統增層線路板製作流程，進而達到提高封裝體 接合基板時之可靠度（Board Levei ReHabinty)之目 * 的。 . 综上所述，本發明係一種銅核層多層封裝基板之 製作方法，可有效改善習用之種種缺點，以具有高密 度增層線路提供電子元件相連時所需之繞線，同時， 並以銅板提供足夠之剛性使封裝製程可更為簡易。藉 此，使用本發明所製造之多層封裝基板，係可依實際 需求形成具銅核基板支撐之銅核層多層封裝基板，並 1361481 可有政達到改善超薄核層基板板彎翹問題、及簡化傳 路板製作流程’以達到提高封裝體接合基板 j可罪度，進而使本發明之産生能更進步更實用、 更付合使用者之所須，確已符合發明專利申請之要 件，爰依法提出專利申請。 米:隹以上所述者’僅為本發明之較佳實施例而已， :不能以此限定本發明實施之範圍；&，凡依本發明 申^利範圍及發明說明書内容所作之簡單的等效變 4傅，皆應仍屬本發明專利涵蓋之範圍内。 1361481 【圖式簡單說明】 第1圖’係本發明之製作流程示意圖。 第2圖’係本發明一實施例之多層封裝基板（一）刮 面不意圖 第3圖’係本發明一實施例之多層封裝基板（二）剖 面示意圖。 第4圖’係本發明一實施例之多層封裝基板（三）刳 面示意圖。 第5圖，係本發明—實施例之多層封裝基板（四）刮 面不意圖。 第6圖，係本發明一實施例之多層封裝基板（五）剖 面示意圖。 第7圖’係本發明—實施例之多層封裝基板（六）剖 面示意圖。 第8圖’係本發明—實施例之多層封裝基板（七）剖 面示意圖。 第9圖，係本發明一實施例之多層封裝基板（八）剖 面示意圖。 第1 0圖，係本發明一實施例之多層封裝基板（九） 剖面示意圖。 第1 1圖，係本發明一實施例之多層封裝基板（十） 剖面示意圖。 17 1361481 第1 2圖’係本發明一實施例之多層封裝基板（十一） 剖面示意圖。 第1 3圖，係本發明一實施例之多層封裝基板（十二） 剖面示意圖。 第1 4圖，係本發明一實施例之多層封裝基板（十二） 剖面示意圖。
第1 5圖，係本發明一實施例之多層封裝基板（十四） 剖面示意圖。 第1 6圖，係本發明一實施例之多層封裝基板（十五） 剖面示意圖。 第1 7圖，係本發明-實施例之多層封裝基板（十六） 剖面示意圖。 第1 8圖’係本發明-實闕之多層封裝基板（十七） 剖面示意圖。
第1 9圖，係本發明-實施例之多層封裝基板（十八） 剖面示意圖。 第20圖，係、本發明-實施例之多層封裝基板（十九） 剖面示意圖。 第2 1圖，係習用有核層封裝基板之剖面示音圖。 第22圖’係習用實施線路增層（-）剖面示意圖。 第2 3圖’係習用實施線路增層（二）剖面示意圖。 第2.4圖，係習.用實施線路增層（三）剖面示意圖。 18 1361481 第2 5圖，係習用音# & 第2fi圖r“ 增層（四）剖面示意圖。 〃 另—f用有核層封裝基板之剖面示意圖。 第2 7圖’係另—習用之第一線路增層結構剖面示意 圖。 第2 8圖’係另一習用之第二路增層結構剖面示意圖。 【主要元件符號說明】 (本發明部分）
步驟（A)〜（I) 11〜19 單層增層線路基板2 雙層增層線路基板3 多層封裝基板4 銅核基板2〇a、2〇b 第一介電層2 1 第一金屬層2 2
第一開口 2 3 第二金屬層2 4 第一、二阻層2 5、2 6 第二開口 2 7 第一線路層2 8 第二介電層2 9 第三開口 3 0 . 19 1361481 第一晶種層3 1 第三、四阻層32、33 第四開口 3 4 第三金屬層3 5 第二線路層3 6 第一防焊層3 7 第五開口 3 8 第五、六阻層39、40 第六開口 4 1 第一、二阻障層42、43 (習用部分） 第一、二線路增層結構5 a、5 b 第一、二線路增層結構6 a、6 b 核心基板5 0 芯層5 0 1 線路層5 0 2 電鍍導通孔5 0 3 第一介電層5 1 第一開口 5 2 晶種層5.3 20 1361481 圖案化阻層5 4 第二開口 5 5 第一圖案化線路層5 6 導電盲孔5 7 第二介電層5 8 第二圖案化線路層5 9 核心基板6 ◦ 樹脂塞孔6 0 1 電鏟通孔6 0 2 第一介電層6 1 第一圖案化線路層6 2 第二介電層6 3 第二圖案化線路層6 4 21

Claims (1)

  1. 映年^月蚵日{;常一，:¾頁 -—20ΪΪ79/2Γ IJ61481 十、申請專利範圍： 1 · 一種銅核層多層封裝基板之製作方法，係至少包含 下列步驟： (A)提供一銅核基板； (B )於該銅核基板之第一面上形成一第一介 電層及一第一金屬層； (C )於該第一金屬層及該第一介電層上形成 複數個第一開口，並顯露部分之銅核基板第一面； (D )於複數個第一開口中及該第一金屬層上 形成一第二金屬層； (E )分別於該第二金屬層上形成一第一阻層 ，以及於該銅核基板之第二面上形成一完全覆蓋狀 之第二阻層，於其中，該第一阻層上並形成複數個 第二開口’並顯露部分之第二金屬層； (F )移除該第二開口下方之第二金屬層及第 一金屬層’並形成一第一線路層； (G)移除該第一阻層及該第二阻層，至此， 完成一具有銅核基板支樓並具電性連接之單層增 層線路基板，並可選擇直接進行步驟（H)或步驟 22 I>61481
    2011/9/29 (Η )於該單層增層線路基板上進行一置晶側 與球側線路層製作，於其中，在該第一線路層表面 形成一第一防焊層，並且在該第一防焊層上係形成 複數個第三開口，以顯露該第一線路層作為電性連 接墊之部分，接著減低該銅核基板第二面之銅厚度 ，並於減銅後之銅核基板第二面上形成一第三阻層 ，且在該第三阻層上係形成複數個第四開口，之後 再分別於複數個第三開口中形成一第一阻障層，以 及於第四開口中形成一第二阻障層，最後移除該第 三阻層，至此，完成一具有完整圖案化之置晶側線 路層與已圖案化但仍完全電性短路之球側線路層 ;以及 (I )於該單層增層線路基板上進行一線路增 層結構製作，於其中，在該第一線路層及該第一介 電層表面形成一第二介電層，並且在該第二介電層 上係形成複數個第五開口，以顯露部分之第一線路 層，接著於該第二介電層與複數個第五開口表面形 成一第一晶種層，再分別於該第一晶種層上形成一 第四阻層，以及於該銅核基板之第二面上形成一完 全覆蓋狀之第五阻層，並於該第四阻層上形成複數 個第六開口，以顯露部分之第一晶種層，之後於該 23
    2011/9/29 IJ6I481 該第六開口中已顯露之第一晶種層上形成一第三 . 金屬層，最後移除該第四阻層、該第五阻層及該第 一晶種層，以在該第二介電層上形成一第二線路 層，至此，完成一具有銅核基板支撐並具電性連接 •之雙層增層線路基板，並可繼續本步驟（I )增加 線路增層結構，形成具更多層之封裝基板，亦或直 接至該步驟（Η)進行置晶側與球側線路層製作。 φ 2·依據申請專利範圍第1項所述之銅核層多層封裝基 板之製作方法，其中，該銅核基板係為一不含介電 層材料之銅板。 3 ·依據申請專利範圍第1項所述之銅核層多層封裝基 板之製作方法，其中，該步驟（Β)係以直接壓合 該第一介電層及該第一金屬層於其上，或係採取貼 合該第一介電層後，再形成該第一金屬層。 φ 4 ·依據申請專利範圍第1項所述之銅核層多層封裝基 板之製作方法，其中，該第一、二介電層係可為環 氧樹脂絕緣膜（Ajinomoto Build-up Film, ABF)、 • 苯環丁稀（Benzocyclo-buthene, BCB )、雙馬來亞 酿胺-三 IL雜苯樹脂（Bismaleimide Triazine，BT)、 環氧樹脂板（FR4、FR5)、聚醯亞胺（Polyimide，PI)、 聚四氟乙稀（Poly(tetra-floroethylene)，PTFE )或環 氧樹脂及玻璃纖維所組成之一者。 24 5依據申清專利範圍第1項所述之銅核層多層封裝基 板之製作方法，其中，複數個第一、五開口係可先 做開銅窗（C〇nformal Mask)後，再經由雷射鑽孔 之方式形成’亦或係以直接雷射鑽孔（laser Direct)之方式形成。 6依據申請專利範圍第1項所述之銅核層多層封裝基 ，之製作方法，其中，該第二、三金屬層及該第一 BB種層之形成方式係可為無電電鍍與電鍍。 7.依據申請專利範圍第1項所述之銅核層多層封裝基 板之製作方法’其中’該第--五阻層係以貼合' 印刷或旋轉塗佈所為之乾膜或溼膜之高感光性光 8 · 虞申1專利範圍第1項所述 < 銅核層多 板之製作方法，其中，複數個第二、三、四及3 口係以曝光及顯影之方式形成。 •依據申請專利範圍第 板之製作方法，其中 二金屬層及該步驟（ 係可為钱刻。 1項所述之銅核層多層封褒基 ’該步驟（F )移除該第—、 I )移除該第一晶種層之方法 0 ·依據申請專利範圍第1項所述之銅核層多層封 基板之製作方法，其中’該第-〜五阻層之移除 决係可為剝離。 “ 25 1361481 •依據申請專利範圍第1項所述之銅核層多層封褒 基板之製作方法，其中，該步驟（Η)減低該鋼核 &板第二面之銅厚度方法係可為刷磨或蝕刻。 1 2 ·依據申請專利範圍第1項所述之銅核層多層封裝 基板之製作方法’其中，該第一、二阻障層係可為 電錢錦金、無電鍍鎳金、電鍍銀或電鍍錫中擇其—。 1 3 ·依據申請專利範圍第1項所述之銅核層多層封裝 基板之製作方法’其中，該步驟（Η)於減低該銅 核基板第二面之銅厚度之前，係可先於該第—防焊 層與4第一線路層表面形成一第六阻層，待減低該 銅核基板第二面之銅厚度之後，再移除該第六阻層。 1 4 .依據申請專利範圍第1 3項所述之銅核層多層封 裝基板之製作方法，其中，該第六阻層係以貼合、 印刷或旋轉塗佈所為之乾膜或溼膜之高感光性光 阻。 1 5 ·依據申請專利範圍第1 3項所述之銅核層多層封 裝基板之製作方法，其中，該第六阻層之移除方法 係可為剝離。 . 26
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