CN101304014B - 半导体芯片及其制造方法 - Google Patents
半导体芯片及其制造方法 Download PDFInfo
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- CN101304014B CN101304014B CN2008100887819A CN200810088781A CN101304014B CN 101304014 B CN101304014 B CN 101304014B CN 2008100887819 A CN2008100887819 A CN 2008100887819A CN 200810088781 A CN200810088781 A CN 200810088781A CN 101304014 B CN101304014 B CN 101304014B
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- layer
- indium
- semiconductor chip
- nickel dam
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 106
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 224
- 229910052738 indium Inorganic materials 0.000 claims abstract description 108
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 104
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 94
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 63
- 229910052802 copper Inorganic materials 0.000 claims abstract description 53
- 239000010949 copper Substances 0.000 claims abstract description 53
- 238000005275 alloying Methods 0.000 claims abstract description 22
- 229910000765 intermetallic Inorganic materials 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 41
- 238000010438 heat treatment Methods 0.000 claims description 30
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 25
- 239000010936 titanium Substances 0.000 claims description 25
- 229910052719 titanium Inorganic materials 0.000 claims description 25
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 23
- YLZGECKKLOSBPL-UHFFFAOYSA-N indium nickel Chemical compound [Ni].[In] YLZGECKKLOSBPL-UHFFFAOYSA-N 0.000 claims description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 229910045601 alloy Inorganic materials 0.000 claims description 12
- 239000000956 alloy Substances 0.000 claims description 12
- 238000010992 reflux Methods 0.000 claims description 9
- 150000002471 indium Chemical class 0.000 claims 6
- 150000002815 nickel Chemical class 0.000 claims 6
- 150000002736 metal compounds Chemical class 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 205
- 238000005530 etching Methods 0.000 description 14
- 235000012431 wafers Nutrition 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 12
- 238000004544 sputter deposition Methods 0.000 description 9
- 241000309551 Arthraxon hispidus Species 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 229910052697 platinum Inorganic materials 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- HVMJUDPAXRRVQO-UHFFFAOYSA-N copper indium Chemical compound [Cu].[In] HVMJUDPAXRRVQO-UHFFFAOYSA-N 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910000846 In alloy Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000001351 cycling effect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000004626 scanning electron microscopy Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000010008 shearing Methods 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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Abstract
本发明公开了一种半导体芯片及其制造方法。该半导体芯片形成有对应于焊盘电极的凸点。该焊盘电极覆盖有镍层。该凸点具有铟层和在铟层与镍层之间设置的中间金属化合物层,并且中间金属化合物层通过合金化铟层和铜层而形成,铜层包含的铜原子相对于铟层中的铟原子具有不低于0.5原子百分比且不高于5原子百分比。
Description
技术领域
本发明涉及半导体芯片及其制造方法。特别是,本发明涉及其中对应于焊盘电极形成有凸点(bump)的半导体芯片及其制造方法。
背景技术
取代引线键合方法(wire bonding method),倒装方法(face down method)应用于密集安装半导体芯片。在倒装方法中,对应于半导体芯片的焊盘电极形成的凸点热压在配线板的端子上(例如,参照专利文件1,日本专利2697116号,以及专利文件2,日本未审查专利申请公开2000-349123号)。
具体地讲,凸点形成在半导体芯片的基板表面上,从而该凸点对应于在基板表面上提供的焊盘电极。其上形成有凸点的基板表面面朝下地由结合设备的结合头支撑。然后,配线板支撑在结合设备上,从而提供有端子的表面面对所支撑的半导体芯片且在该表面上安装半导体芯片。其后,半导体芯片的凸点和配线板的端子对准,以便它们彼此对应,然后凸点热结合(thermallybond)到端子。例如,在焊料凸点在溶化状态时,二者通过无焊剂连接(fluxlessconnection)彼此结合,在该连接中,结合头在面对的方向上垂直运动或者在平面方向上横向运动。
发明内容
图14示意性地展示了半导体芯片101的一部分,其中凸点121形成在焊盘电极111上。
如图14所示,半导体芯片101具有焊盘电极111和凸点121。例如,钛层112、铜层113和镍层114依次层叠在焊盘电极111上,以覆盖电极的表面。镍层114通过电解电镀法等形成,厚度为3至5μm。凸点121包括铟层122,并且由铟镍合金层形成的中间金属化合物(intermediate metalcompound)层123夹置在铟层122和镍层114之间。
由铟镍合金层形成的中间金属化合物层123通过合金化铟层122和镍层114来制造。例如,为了处理耐热温度低的半导体芯片,当铟层122由200℃或之下的温度热处理15秒以回流(reflow)时,中间金属化合物层123形成为厚度为0.1μm至0.2μm的In7Ni3。
然而,当半导体芯片101通过倒装法安装在配线板上时,在中间金属化合物层123中会产生断裂。
这会降低通过将半导体芯片安装在配线板上所制造的半导体器件的可靠性。
特别是,在以200℃或之下的耐热温度进行回流时,如上所述,In7Ni3可以形成只有0.1μm至0.2μm的厚度。因此,缺陷的产生变得突出。该缺陷在由无焊剂结合(fluxless bonding)的安装工艺中更为突出。
专利文件1揭示了形成铟焊料凸点的方法。即揭示了在铬或钛基层上形成铂层作为阻挡金属,以达到抑制铟合金生长的目的。因此,铂仅用作相对于铟和铬或钛的扩散保护膜,使其在铟和铂之间难于获得合金生长。因此,铟和铂可能彼此分离,特别是在无焊剂结合中。除此,由于铂层膜厚和成分上的变化,变得难于控制要生成合金的成分和厚度。具体地讲,当生成多种成分的合金时,在合金中会产生裂纹,导致可靠性的降低。另外,铂镀覆很昂贵,使其难于取得成本降低。
因此,在某些情况下,在半导体芯片安装中已经难于取得高可靠性。
所希望的是提供半导体芯片及其制造方法,其允许半导体芯片的精确安装,还能改善可靠性。
根据本发明实施例的半导体芯片是具有对应于焊盘电极形成的凸点的半导体芯片。焊盘电极覆盖有镍层。凸点具有铟层和在铟层与镍层之间设置的中间金属化合物层。中间金属化合物层通过使铟层和铜层合金化而形成,铜层包含的铜原子相对于铟层中的铟原子具有不小于0.5原子百分比且不大于5原子百分比。
优选地,镍层形成在焊盘电极上,使得该层的厚度成为不大于0.5μm。
根据本发明的半导体芯片的制造方法是制造其中凸点形成为对应于焊盘电极的半导体芯片的制造方法,并且包括下面的步骤:镍层形成步骤,形成镍层以覆盖焊盘电极;以及凸点形成步骤,形成凸点以使凸点对应于覆盖有镍层的焊盘电极。凸点形成步骤包括在镍层上形成铜层的铜层形成步骤、在铜层上形成铟层的铟层形成步骤,以及通过进行热处理使得铜层和铟层合金化以形成中间金属化合物层从而形成凸点的热处理步骤。在铜层形成步骤中,形成铜层使得铜层中的铜原子相对于铟层形成步骤中形成的铟层中的铟原子的比率不小于0.5原子百分比且不大于5原子百分比。
优选地,在镍层形成步骤中,在焊盘电极上形成镍层的厚度不大于0.5μm。
优选地,在镍层形成步骤中,通过溅射法的溅射镍形成镍层。
优选地,在铜层形成步骤中,通过电解电镀将铜镀覆到镍层上形成铜层,并且在铟层形成步骤中,通过电解电镀将在铟镀覆到铜层上形成铟层。
因此,中间金属化合物层的剪切强度通过由合金化铟层和铜层形成的层得到改善,相对于铟层中的铟原子,该铜层包含不少于0.5原子百分比且不大于5原子百分比的铜原子。
在本发明实施例中的半导体芯片是具有凸点的半导体芯片,该凸点形成为对应于焊盘电极。焊盘电极覆盖有镍层。凸点具有铟层和夹置在铟层与镍层之间的中间金属化合物层。中间金属化合物层是通过合金化铟层与镍层而形成厚度为1μm或者更大的铟镍合金层,该铟镍合金层包括In7Ni3。
本发明实施例的半导体芯片的制造方法是制造其中凸点形成为对应于焊盘电极的半导体芯片的方法,并且该方法包括镍层形成步骤,形成镍层以覆盖焊盘电极,以及凸点形成步骤,对应于覆盖有镍层的焊盘电极形成凸点。凸点形成步骤包括在镍层上形成铟层的铟层形成步骤,以及通过进行热处理形成凸点的热处理步骤,该热处理步骤将铟层和镍层合金化为铟镍合金层以获得中间金属化合物层,该铟镍合金层包括具有1μm或者更大厚度的In7Ni3。
优选地,热处理步骤包括第一热处理步骤,进行热处理使得铟层回流;以及第二热处理步骤,进行热处理使得铟层和镍层合金化以在铟层回流后产生In7Ni3。
优选地,在第二热处理步骤中,在156℃或者更高而低于400℃的温度进行热处理。
在本发明中,铟层和镍层合金化以形成厚度为1μm或者更大且包括In7Ni3的铟镍合金层,由此改善铟镍合金层的剪切强度。
因此,本发明能提供允许精确安装半导体芯片并改善可靠性的半导体芯片及其制造方法。
附图说明
图1是展示根据本发明第一实施例的半导体芯片的部分的截面图,在该半导体芯片中凸点形成在焊盘电极上;
图2A至2D是展示在本发明第一实施例的每个步骤中要制造的半导体芯片关键部分的截面的截面图;
图3A至3C是展示在第一实施例的每个步骤中要制造的半导体芯片关键部分的截面的截面图;
图4A至4C是展示在第一实施例的每个步骤中要制造的半导体芯片关键部分的截面的截面图;
图5是展示根据本发明第二实施例的半导体芯片的部分的截面图,在该半导体芯片中凸点形成在焊盘电极上;
图6A至6D是展示在本发明第二实施例的每个步骤中要制造的半导体芯片关键部分的截面的截面图;
图7A至7C是展示在本发明第二实施例的每个步骤中要制造的半导体芯片关键部分的截面的截面图;
图8A至8C是展示在本发明第二实施例的每个步骤中要制造的半导体芯片关键部分的截面的截面图;
图9A至9C是展示在本发明第二实施例中半导体芯片安装在其它半导体芯片上的状态的侧视图;
图10是展示在本发明第二实施例中In7Ni3厚度与凸点剪切强度之间关系的图;
图11A和11B是展示在本发明第二实施例中的温度循环测试中铟和镍是否彼此分离的观查结果的扫描电子显微镜(SEM)照片;
图12是展示在本发明第二实施例中热处理条件例如热处理温度和时间与在该热处理条件下生成的In7Ni3厚度之间关系的图;
图13是在本发明第二实施例中要合金化的铟和镍的相图;和
图14是展示其中在焊盘电极上形成凸点的半导体芯片的部分的截面图。
具体实施方式
下面将参照附图描述本发明的实施例。
第一实施例
<构造>
图1是展示根据本发明第一实施例的半导体芯片1的部分的截面图,在该半导体芯片1中凸点21形成在焊盘电极11上。
如图1所示,半导体芯片1具有焊盘电极11和凸点21,并且凸点21形成为对应于焊盘电极11。钛层12和镍层14依次层叠在焊盘电极11上以覆盖其表面。凸点21包括铟层22,并且由铟铜合金层组成的中间金属化合物层23夹置在铟层22和镍层14之间。
下面将依次描述各部件。
焊盘电极11例如由铝制成,并且经由层间绝缘膜I连接到形成在半导体芯片1的晶片W上的电路(未示出)。如图1所示,焊盘电极11的表面用钝化膜P覆盖周边,并且钛层12和镍层14依次形成在焊盘电极11的表面的中间部分。
钛层12形成为覆盖焊盘电极11的中间部分,如图1所示。例如,钛层12可以通过溅射法将钛溅射成膜而形成在焊盘电极11的表面上。
镍层14形成为覆盖焊盘电极11的中间部分,并且在它们之间具有钛层12,如图1所示。例如,镍层14可以通过溅射法将镍溅射成膜而形成。在本实施例中,镍层14形成的厚度为0.5μm或更小。
凸点21具有铟层22和中间金属化合物层23,并且从在其上形成有焊盘电极11的晶片W表面突出,如图1所示。
铟层22与镍层14重叠,在它们之间有中间金属化合物层23,如图1所示。铟层22形成为球形。
中间金属化合物层23形成在铟层22和镍层14之间,如图1所示。稍后将描述此细节。在本实施例中,中间金属化合物层23是铟铜合金层,并且通过使铟层22和铜层20合金化来形成,铜层20包含的铜原子相对于铟层中的铟原子具有不少于0.5原子百分比且不大于5原子百分比。
<制造方法>
下面将描述制造第一实施例中半导体芯片1的方法的关键部分。
图2A-2D、图3A-3C和图4A-4C是展示在本发明第一实施例每个步骤中所制造的半导体芯片1的关键部分截面的截面图。就是说,图1所示半导体芯片1通过依次进行图2A至2D、图3A至3C和图4A至4C中的制造步骤来制造。
如图2A所示准备晶片W。
准备晶片W,在该晶片W的主表面上形成焊盘电极11和钝化膜P,在中间有层间绝缘膜I。在晶片W中,焊盘电极11由例如铝膜的金属膜形成。钝化膜P由绝缘膜例如氧化硅膜形成,并且覆盖在焊盘电极11的周围。形成开口以暴露焊盘电极11的中间部分。其后,进行逆向溅射(inversesputtering)以去除自然氧化膜。
如图2B所示形成钛层12。
钛层12通过溅射法溅射钛来形成,以便覆盖晶片W的表面,包括在焊盘电极11暴露的表面。
如图2C所示形成镍层14。
镍层14通过溅射法溅射镍来形成,以便覆盖晶片W的表面,包括在焊盘电极11暴露的表面。例如,镍层14形成的厚度不大于0.5μm。
如图2D所示涂敷光致抗蚀剂膜R。
通过旋涂法涂敷光致抗蚀剂膜R来形成膜以覆盖晶片W的表面。具体地讲,涂敷包括光敏材料的涂敷溶液,以覆盖晶片W的表面来形成膜。然后使该膜干燥,以形成光致抗蚀剂膜R。例如,光致抗蚀剂膜R形成的厚度为50至100μm。
随后,进行光致抗蚀剂膜R的曝光工艺,如图3A所示。
采用光掩模PM,曝光照射到光致抗蚀剂膜R的一部分,该部分对应于形成凸点21和在晶片W上形成焊盘电极11的区域。
进行光致抗蚀剂膜R的显影工艺,以形成抗蚀剂掩模层RM,如图3B所示。
通过对光致抗蚀剂膜R进行显影工艺,去除光致抗蚀剂膜R的被曝光照射的区域,以形成抗蚀剂掩模层RM。具体地讲,形成开口使得它们对应于光致抗蚀剂膜R中形成凸点21的部分,从而暴露焊盘电极11的中间部分。其后,进行清除抗蚀剂浮渣。
随后,如图3C所示,形成铜层20。
铜层20通过电解电镀法对在抗蚀剂掩模层RM的开口暴露的焊盘电极11的中间部分使用铜进行镀覆而形成。在本实施例中,形成铜层20使得相对于要在下面的步骤中形成的铟层22中的铟原子,铜层20中的铜原子的比率不小于0.5原子百分比且不大于5原子百分比。例如,铜层20形成的厚度为0.1μm。
如图4A所示,形成铟层22。
铟层22通过进行电解电镀铟到在抗蚀剂掩模层RM的开口暴露的焊盘电极11的中间部分而形成。在本实施例中,如上所述,形成铟层22为使得相对于铟层22中的铟原子,铜层20中的铜原子的比率变为不小于0.5原子百分比且不大于5原子百分比。例如,铟层22形成的厚度为10μm。在此情况下,相对于铟层22的铟原子,铜层20包含1原子百分比的铜原子。在相同面积的情况下,铜层20的厚度相对于铟层22的厚度的比率为不小于百分之0.5且不大于百分之5。当铜层20的铜原子相对于铟层22的铟原子的比率低于0.5原子百分比时,这不是优选的,这是因为除了铟铜合金化外,还可能促使铟镍合金化。另一方面,如果铜层20的铜原子相对于铟层22的铟原子的比率超过5原子百分比,则也不是优选的,这是因为可能升高熔点,并且由此妨碍了铟铜合金化。
然后,如图4B所示去除抗蚀剂掩模层RM。
就是说,去除抗蚀剂掩模层RM以暴露被抗蚀剂掩模层RM覆盖的镍层14。
随后,如图4C所示,去除镍层14和钛层12。
例如,镍层14表面上暴露的部分通过使用铟层22作为硬掩模蚀刻来去除。同样,然后钛层12表面上暴露的部分也通过蚀刻去除。
随后,进行回流工艺(reflow process)以完成半导体芯片1,如图1所示。
就是说,热处理以这样的方式进行,铟层22可以球状回流,而铜层20和铟层22可以合金化以产生中间金属化合物层23,从而可以形成凸点21。
具体地讲,在下述条件下进行热处理。
热处理温度:180℃
热处理时间:15秒
因此,在本实施例中,在形成镍层14以覆盖焊盘电极11后,凸点21对应于覆盖有镍层14的焊盘电极11形成。在此情况下,铜层20首先形成在镍层14上,然后铟层22形成在铜层20上。其后,通过进行热处理形成凸点21,从而铜层20和铟层22合金化以产生中间金属化合物层23。此时,形成铜层20,使得铜层20中的铜原子相对于铟层22中的铟原子的比率不小于0.5原子百分比且不大于5原子百分比。就是说,根据本实施例,铜层20和铟层22形成的比率能够实现合适的合金化。
在本实施例中,采用比铟镍合金层脆性较小的铟铜合金层取代脆性的铟镍合金层,用于形成中间金属化合物层23。通过在铟层22和镍层14之间设置中间金属化合物层23,当如上制造的半导体芯片1通过倒装方法安装时,能够防止在中间金属化合物层23中引起裂缝。具体地讲,测量了本实施例中所形成的凸点21的剪切强度,并且与相关技术的情况进行了比较,结果,前者具有的剪切强度为后者的约四至五倍高。
因此,本实施例可以改善通过在配线板上安装半导体芯片1所制造的半导体器件的可靠性。
另外,镍层14以不大于0.5μm的厚度形成在焊盘电极11上。就是说,因为在本实施例中镍层14不与铟层合金化,所以镍层14可以形成为薄膜。这能够通过溅射法使镍层14形成薄膜。因此,包含铜的铟凸点具有220℃或者更低的熔点,其低于Sn基无铅焊料的熔点,由此允许低温结合。因此,本实施例适用于任何具有低耐热温度的半导体芯片,并且具有高水平的通用性(general versatility)。这能够有效地制造半导体芯片。
第二实施例
下面将描述本发明的第二实施例。
<构造>
图5是展示根据本发明第二实施例的半导体芯片1b的部分的截面图,在该半导体芯片1b中凸点21形成在焊盘电极11上。
如图5所示,与第一实施例相类似,半导体芯片1b具有焊盘电极11和凸点21,并且凸点21形成为对应于焊盘电极11。钛层12、铜层13和镍层14依次层叠在焊盘电极11上以覆盖其表面。凸点21包括铟层22,并且中间金属化合物层23夹置在铟层22和镍层14之间。
在第二实施例的半导体芯片1b中,铜层13位于镍层14之下,并且镍层14的厚度不同于第一实施例中镍层的厚度。同样,中间金属化合物层23的成分不同于第一实施例的中间金属化合物层的成分。除上述外,第二实施例与第一实施例相类似,并且在此省略重复部分的描述。
下面将依次描述各部件。
与第一实施例相类似,焊盘电极11例如由铝制成,并且连接到形成在半导体芯片1b上的电路(未示出)。如图5所示,钛层12、铜层13和镍层14依次形成在焊盘电极11的表面上。
与第一实施例相类似,钛层12形成为覆盖焊盘电极11。
铜层13形成为覆盖焊盘电极11,在它们之间有钛层12,如图5所示。例如,铜层13通过溅射法溅射铜来形成。
镍层14形成为覆盖焊盘电极11,在它们之间有钛层12和铜层13,如图5所示。例如,镍层14通过溅射法溅射镍形成在焊盘电极11的表面上。在本实施例中,例如,镍层14形成的厚度为3至5μm。
凸点21具有铟层22和中间金属化合物层23,并且在半导体芯片1b中从其上形成有焊盘电极11的晶片W的表面突出,如图5所示。
形成铟层22使得该层和镍层14将中间金属化合物层23夹在中间,如图5所示。例如,铟层22的高度为10μm,并且以通过回流成为球形的方式形成。
中间金属化合物层23设置在铟层22和镍层14之间,如图5所示。其详细情况稍后描述。在本实施例中,中间金属化合物层23通过使铟层22和镍层14合金化而形成。具体地讲,中间金属化合物层23是铟镍合金层,其中使铟层和镍层合金化以包括In7Ni3,并且铟镍合金层的厚度不小于1μm。或者,In7Ni3可以是具有In27Ni10、In6.4Ni3或In72Ni28的成分比的合金。
<制造方法>
下面将描述制造本发明第二实施例中半导体芯片1b的方法的关键部分。
图6A-6D、图7A-7C和图8A-8C是展示在本发明第二实施例每个步骤中所要制造的半导体芯片1b的关键部分截面的截面图。就是说,图5所示的半导体芯片1b可通过依次进行图6A至6D、图7A至7C和图8A至8C中的制造步骤来制造,这些图示出了在每个步骤中要制造的器件的关键部分的截面。
与第一实施例相类似,如图6A所示,准备晶片W,其后,如图6B所示形成钛层12。
如图6C所示,形成铜层13。
铜层13通过溅射法溅射铜而形成,以覆盖晶片W的表面,包括在焊盘电极11所暴露的表面。
与第一实施例相类似,如图6D所示,涂敷光致抗蚀剂膜R,并且如图7A所示,在光致抗蚀剂膜R上进行曝光工艺。其后,在光致抗蚀剂膜R上进行显影工艺以形成抗蚀剂掩模层RM,如图7B所示。
如图7C所示,形成镍层14。
镍层14通过进行电解电镀镍到在抗蚀剂掩模层RM的开口暴露的焊盘电极11的中间部分而形成。
与第一实施例相类似,如图8A所示,形成铟层22。在如图8B所示去除抗蚀剂掩模层RM后,如图8C所示去除铜层13和钛层12。
例如,铜层13的表面上暴露的部分通过使用铟层22为硬掩模蚀刻来去除。类似地,然后钛层12的表面上暴露的部分通过蚀刻去除。
随后,进行回流工艺以完成半导体芯片1b,如图5所示。
就是说,以这样的方式进行热处理,铟层22回流成球形形状,而镍层14和铟层22合金化,用于产生中间金属化合物层23,从而可以形成凸点21。具体地讲,在从156℃或者之上到400℃之下的温度范围内进行热处理。
此外,在本实施例中,以这样的方式进行热处理,使铟层22和镍层14合金化成铟镍合金层,该铟镍合金层包括厚度为1μm或之上的In7Ni3,从而可以产生中间金属化合物层23。就是说,进行热处理以进一步增加In7Ni3的厚度。In7Ni3生长的高度低于铟焊料的高度。就是说,进行热处理使得铟层22中可以包括未合金化的部分。
具体地讲,在下述条件下进行热处理。
热处理温度:从156℃或者之上到400℃之下的范围
热处理时间:不少于60分
在凸点21如此形成在半导体芯片1b上后,安装半导体芯片1b。
就是说,通过倒装方法将半导体芯片1b安装在半导体芯片200上。半导体芯片200提供有与半导体芯片1b的凸点相类似的凸点221。具体地讲,通过无焊剂结合进行安装。
图9A至9C是展示在本发明第二实施例中半导体芯片1b安装在另一个半导体芯片200上的情形的侧视图。
半导体芯片1b安装到结合头BH上,如图9A所示。
就是说,半导体芯片1b安装到结合设备的结合头BH,使得提供有凸点21的芯片的表面朝下。设置其上要安装半导体芯片1b的半导体芯片200,使其提供有凸点221的表面朝上,并且面对半导体芯片1b提供有凸点21的表面。提供有凸点221的半导体芯片200类似于上述设置。随后,设置半导体芯片1b中的凸点21和半导体芯片200中的芯片221,以使它们通过对准而彼此对应。
随后,移动结合设备的结合头BH,如图9B所示。
通过加热半导体芯片1b和安装半导体芯片1b的半导体芯片200,使凸点21和221处于熔化状态。具体地讲,通过加热这些芯片到超过铟的熔点156℃的温度,来熔化凸点21和221。然后,向下移动结合头BH,使半导体芯片1b对半导体芯片200施加压力来安装半导体芯片1b。在本实施例中,在焊料凸点处于熔化状态期间,通过在面对的方向上垂直地移动和/或平面方向上横向地移动结合头BH,以无焊剂结合工艺来将它们结合在一起。
随后,半导体芯片1b安装在半导体芯片200上,如图9C所示。
就是说,通过使两个凸点处于熔化状态并且然后使两个凸点彼此接触,来进行半导体芯片1b的凸点21与用于安装半导体芯片1b的半导体芯片200的凸点221之间的结合。如图9C所示,进行热处理,从而半导体芯片1b的凸点21和半导体芯片200的凸点221的所有铟合金化为In7Ni3合金,两个凸点用在它们之间的In7Ni3层300结合在一起。
因此,在本实施例中,在形成镍层14以覆盖焊盘电极11后,凸点21对应于覆盖有镍层14的焊盘电极11而形成。在此情况下,铟层22形成在镍层14上。其后,进行热处理,使铟层22和镍层14合金化为包括厚度不小于1μm的In7Ni3的铟镍合金层,以形成为中间金属化合物层23。因此,本实施例能够使结合强度提高,由此改善装置的可靠性。
图10是展示本发明第二实施例中In7Ni3厚度D(μm)与凸点剪切强度(gf)之间关系的图。就是说,镍层14之上大约1μm的位置定义为剪切测试位置,并且在设置为平行于该位置的平面而施加到凸点21的剪切力下使凸点21断裂时,测量凸点21的剪切强度。
图11A和11B是展示在本发明第二实施例中进行温度循环测试中铟和镍是否彼此分离的观察结果的SEM照片。具体地讲,图11A展示了In7Ni3的厚度D为0.2μm时的结果,图11B展示了In7Ni3的厚度D为1.0μm时的结果。
In7Ni3的厚度D为0.2μm时,凸点的剪切强度很小,如图10所示。结果,铟层22和镍层14之间设置的中间金属化合物层23中发生分离,由此引起差的结合,如图11A所示。另一方面,In7Ni3的厚度D为1.0μm时,凸点的剪切强度增加,如图10所示。结果,铟层22和镍层14之间设置的中间金属化合物层23中不发生分离,并且没有引起差的结合,如图11B所示。就是说,厚度D为不小于1.0μm的In7Ni3保证了良好的结合特性,如图11B所示。出于这个原因,发现通过使In7Ni3的厚度不小于0.3μm可以防止铟和镍之间的分离,优选为不小于0.5μm,更优选为不小于1.0μm。
因此,在本实施例中,通过合金化成包括厚度不小于1μm的In7Ni3的铟镍合金层,产生中间金属化合物层23。因此,在半导体芯片1b通过倒装方法安装时,能够防止中间金属化合物层23中的裂缝。
在本实施例中,In7Ni3作为由热处理生长的铟镍合金可以增加铟和铟镍之间的结合强度。这使得其能够在无焊剂结合时防止铟和铟镍合金之间的分离,由此实现高产率的结合。
另外,在本实施例中,在回流后进行热处理,从而铟层22和镍层14进一步合金化以产生In7Ni3。该热处理在从156℃或者之上到400℃之下的温度范围内进行。因此易于制造能够实现高可靠性的装置。
图12是展示在本发明第二实施例中热处理条件例如热处理温度T和热处理时间t与在该热处理条件下的In7Ni3的厚度D之间的关系的图。
图13是在本发明第二实施例中合金化铟和镍的相图。该相图引自″Ph.Durussel et al.,″The binary system Ni-In,″Journal of Alloys and Compounds 257,pp.253-258.″。
如图12所示,在铟熔点以上的160℃或180℃的热处理,与在低于铟熔点的150℃进行热处理的情况相比,增加了In7Ni3的生成速度。具体地讲,当在不低于铟的熔点的温度进行热处理时,通过约一个小时的热处理,产生厚度为1μm的In7Ni3。另一方面,当在低于铟的熔点的温度进行热处理时,通过约24小时的热处理,产生厚度为1μm的In7Ni3。因此,因为在铟的熔点156℃或者之上的温度进行热处理,所以本实施例可以有效地生成In7Ni3。
如图13的相图所示,当在400℃或者之上的温度进行热处理时,In7Ni3再次熔化,并且再次熔化的In7Ni3冷却时,生成具有复杂成分的In-Ni合金。在此情况下,由于线性膨胀系数差引起的肯德尔孔隙(Kirkendall void),会使可靠性变坏。然而,因为在400℃之下的温度的热处理可以适宜地产生In7Ni3,所以本实施例可以防止缺陷的产生。
在本实施例中,由In7Ni3组成的中间金属化合物层23可以形成为有效显示适合的凸点剪切强度的厚度。因此,在如此制造的半导体芯片1b通过倒装方法安装时,能够防止中间金属化合物层23中的裂缝。
因此,本实施例可以改善通过在配线板上安装半导体芯片1b所制造的半导体器件的可靠性。
因为即使在低至200℃或者更低的热处理条件下也可以达到效果,所以本实施例是特别优选的。另外,In7Ni3的厚度可以通过调整热处理温度和时间很容易地得到控制。这在防止由复杂工艺引起的合金成分和厚度的变化是有效的。
尽管通过前述的实施例已经描述了本发明,但是应当理解的是,本发明不限于这些实施例,并且可以进行各种修改。
尽管在实施例中针对都提供有铟焊料凸点的半导体芯片之间的结合的情况进行了描述,但是本发明不限于这些情况。即使铟焊料凸点形成在半导体芯片的任何一个上,本发明也是适用的。
本领域的技术人员应当理解的是,在如权利要求或者其等同特征的范围内,根据设计需要和其它因素可以进行各种修改、结合、部分结合和替换。
本文件包含2007年5月7日提交至日本专利局的日本专利申请第2007-122156号的相关主题,将其全部内容引用结合于此。
Claims (4)
1.一种具有对应于焊盘电极形成的凸点的半导体芯片,其中
该焊盘电极依次覆盖有钛层、铜层和镍层;
该凸点具有铟层和在该铟层与该镍层之间设置的中间金属化合物层;以及
该中间金属化合物层是厚度为1μm或者之上的铟镍合金层,该铟镍合金层通过合金化该铟层和该镍层以包括In7Ni3而形成。
2.一种制造半导体芯片的方法,在该半导体芯片中对应于焊盘电极形成凸点,该方法包括:
钛层、铜层和镍层形成步骤,依次形成钛层、铜层和镍层以覆盖该焊盘电极;以及
凸点形成步骤,对应于覆盖有该镍层的焊盘电极形成该凸点,其中该凸点形成步骤包括:
铟层形成步骤,在该镍层上形成铟层;以及
热处理步骤,通过进行热处理使该铟层和该镍层合金化成包括厚度为1μm或者之上的In7Ni3的铟镍合金层以生成中间金属化合物层而形成该凸点。
3.根据权利要求2所述的形成半导体芯片的方法,其中该热处理步骤包括:
第一热处理步骤,以使该铟层回流的方式进行热处理;以及
第二热处理步骤,在回流该铟层后,进行热处理以使该铟层和该镍层合金化以生成In7Ni3。
4.根据权利要求3所述的形成半导体芯片的方法,其中在该第二热处理步骤中,在从156℃或者之上到400℃之下的温度范围内进行该热处理。
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CN106282619B (zh) * | 2015-05-18 | 2018-04-27 | 吕传盛 | 耐磨耗高强度无镀层的铝基线材及其制备方法 |
JP6538596B2 (ja) * | 2016-03-14 | 2019-07-03 | 東芝メモリ株式会社 | 電子部品の製造方法及び電子部品の製造装置 |
MY192389A (en) | 2016-07-01 | 2022-08-18 | Intel Corp | Systems, methods, and apparatuses for implementing a pad on solder mask (posm) semiconductor substrate package |
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JP4275806B2 (ja) | 1999-06-01 | 2009-06-10 | 株式会社ルネサステクノロジ | 半導体素子の実装方法 |
TW578217B (en) * | 2002-10-25 | 2004-03-01 | Advanced Semiconductor Eng | Under-bump-metallurgy layer |
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JP2005175128A (ja) * | 2003-12-10 | 2005-06-30 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2007234841A (ja) * | 2006-02-28 | 2007-09-13 | Kyocera Corp | 配線基板、実装部品、電子装置、配線基板の製造方法および電子装置の製造方法 |
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- 2008-04-08 US US12/078,893 patent/US7863741B2/en not_active Expired - Fee Related
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CN101304014A (zh) | 2008-11-12 |
TWI380388B (zh) | 2012-12-21 |
US7863741B2 (en) | 2011-01-04 |
KR101477596B1 (ko) | 2014-12-30 |
JP4998073B2 (ja) | 2012-08-15 |
KR20080099139A (ko) | 2008-11-12 |
US20080277784A1 (en) | 2008-11-13 |
TW200908175A (en) | 2009-02-16 |
JP2008277677A (ja) | 2008-11-13 |
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