JPS647639A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS647639A
JPS647639A JP62162563A JP16256387A JPS647639A JP S647639 A JPS647639 A JP S647639A JP 62162563 A JP62162563 A JP 62162563A JP 16256387 A JP16256387 A JP 16256387A JP S647639 A JPS647639 A JP S647639A
Authority
JP
Japan
Prior art keywords
layer
electrode
onto
plating
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62162563A
Other languages
Japanese (ja)
Inventor
Kosuke Tange
Yutaka Okuaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62162563A priority Critical patent/JPS647639A/en
Publication of JPS647639A publication Critical patent/JPS647639A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To decrease plating processes and shorten the plating time, and to prevent the generation of cracks in a passivation film by forming a metallic layer onto a current conductive layer, heating and melting a dummy electrode layer shaped onto the metallic layer and a bump plating layer and forming a bump electrode. CONSTITUTION:A passivation film 34 having an opening section where corresponding to an electrode pad 33 is formed onto a semiconductor substrate 31 to which a field oxide film 32 and an electrode pad 33 are shaped, and a current conductive layer 35 is formed onto the electrode pad 33 and the passivation film 34. A metallic layer 36 is shaped where corresponding to the electrode pad 33 on the current conductive layer 35 and a resist film 37 is formed around the layer 36, and a dummy electrode layer 38 is shaped onto the metallic layer 36 and a bump plating layer 39 is formed onto the layer 38, using the dummy electrode layer 38 as an electrode for plating. The resist film 37 is removed and the current conductive layer 35 exposed by getting rid of the resist film 37 is taken off, the dummy electrode layer 35 and the bump plating layer 39 are heated and melted, and a eutectic-alloyed bump electrode 40 having an approximately spherical surface-shaped outside surface is formed.
JP62162563A 1987-06-30 1987-06-30 Manufacture of semiconductor device Pending JPS647639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62162563A JPS647639A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62162563A JPS647639A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS647639A true JPS647639A (en) 1989-01-11

Family

ID=15756968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62162563A Pending JPS647639A (en) 1987-06-30 1987-06-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS647639A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6369490B1 (en) * 1999-04-28 2002-04-09 Murata Manufacturing Co., Ltd Surface acoustic wave device having bump electrodes
JP2008277677A (en) * 2007-05-07 2008-11-13 Sony Corp Semiconductor chip, and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6369490B1 (en) * 1999-04-28 2002-04-09 Murata Manufacturing Co., Ltd Surface acoustic wave device having bump electrodes
JP2008277677A (en) * 2007-05-07 2008-11-13 Sony Corp Semiconductor chip, and manufacturing method thereof

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