CN101211878B - 互连结构及其形成方法 - Google Patents
互连结构及其形成方法 Download PDFInfo
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- CN101211878B CN101211878B CN2007101869419A CN200710186941A CN101211878B CN 101211878 B CN101211878 B CN 101211878B CN 2007101869419 A CN2007101869419 A CN 2007101869419A CN 200710186941 A CN200710186941 A CN 200710186941A CN 101211878 B CN101211878 B CN 101211878B
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Abstract
一种适用于将微电子器件芯片倒装芯片地附着到封装上的互连结构包括两层、三层或四层焊球受限冶金,该焊球受限冶金包括粘合/反应阻挡层,并且具有与含锡无铅焊料的组分反应的焊料可润湿层,从而在焊接的过程中可焊接层可以全部被消耗掉,但是,在焊接的过程中阻挡层在其被放置成与无铅焊料接触之后保留下来。一个或多个无铅焊球,其选择性地位于所述焊料可润湿层上,所述无铅焊球包含作为主要组分的锡和一种或多种合金组分。
Description
技术领域
本发明涉及微电子集成电路(IC)器件到封装的互连,具体地涉及常称为C4(控制塌陷芯片连接(controlled collapse chipconnection))的区域阵列倒装芯片互连技术。由于使用无铅的焊料合金和环保的制造工序,本发明还涉及环保的互连方案。此外,本发明涉及这样的互连方案,该互连方案通过除去与微电子电路接触的焊料中的α粒子源来消除芯片上电路中的软错误源。
背景技术
在半导体芯片的封装中,多层次的互连是必要的。在芯片和衬底(或者芯片载体)之间的互连级别上,广泛地使用三种不同的互连技术:载带自动键合(TAB)、引线键合和区域阵列倒装芯片互连。
凸焊点(solder bump)区域阵列互连方案常常称为倒装芯片焊料连接或C4,集成电路器件(IC)到芯片载体的朝下焊接。与引线键合不同,为了最高可能的输入/输出(I/O)计数,区域阵列凸焊点结构允许芯片的整个表面被C4凸点覆盖,从而满足对IC技术的电功能性和可靠性的日益增加的需求,这是引线键合或TAB不能实现的,引线键合或TAB将互连限制到芯片***。更具体地说,C4技术使用沉积在称为焊球受限冶金(BLM)(也称为凸点下冶金(UBM))的图形化的焊料可湿性层状结构上的凸焊点。焊球受限冶金(下文称为“BLM)限定端子金属垫在制程前端(front-end-of-line)和制程后端(back-end-of-line)(FEOL和BEOL)引线层的顶面上,该引线层制造在这样的芯片上,该芯片是可以被焊料弄湿的,并且还限制远离端子垫区域的熔融焊料的横向流动。在芯片上的图形化的UBM垫上制造凸焊点以形成焊球之后,将芯片连接到芯片载体上的焊料可湿性垫的匹配覆盖区。芯片在载体上的朝下放置导致C4技术称为倒装芯片连接。与其它互连方法相比较,C4技术提供明显的优点,包括下述优点:1)较短的互连距离,从而允许更快的信号响应并减少感应耦合和串扰;2)更均匀的功率和热分布;3)降低的同步开关噪声;以及4)在最高可能的总输入/输出计数的同时具有更大的设计灵活性。
自从二十世纪六十年代以来,IBM开发并完成了通过金属掩模蒸发来制造Pb-Sn C4互连。通过图形化的金属掩模来蒸发C4凸点和BLM垫,以形成高度可靠的、高密度的互连结构,这证明由最早的低密度的、低输入/输出计数较小IC器件可以扩展成二十一世纪的高密度的、高输入/输出计数IC产品。然而,普遍认为,对扩展到较大的晶片尺寸、更密的阵列和无铅应用的限制几乎通过蒸发方法来实现。
可替代蒸发的其它方法是电镀、焊膏丝网印刷、焊料喷射以及更近来的C4NP,该C4NP代表C4“新工序”,这里仅举几个例子。C4的电化学镀敷制造是选择性的有效的工序,这在(例如)Yung的美国专利No.5,162,257文献中有所报道,该专利以引用方式并入本文中。Datta等人在J.Electrochem.Soc.,142,3779(1995)中描述了电化学制造的C4的制造性和其它集成问题,该文献以引用的方式并入文本中。使用电镀和蚀刻工序,通过开发精细的工具,有可能得到成分和体积高度均匀的电镀焊料、均匀尺寸的焊球受限冶金(BLM)以及受控的BLM边缘分布。
电化学工序比蒸发的C4技术更加容易扩展到较大的晶片和更精细的C4尺寸。通过光致蚀刻剂掩模的电沉积仅仅在掩模开口处以及在UBM的顶面上产生焊料。与蒸发不同的是,电沉积可以扩展到高锡含量的无铅合金和300mm的大晶片。
C4NP制造的C4凸焊点在Gruber等人的美国专利No.6,231,333文献中有所描述,该专利以引用方式并入本文中。在Gruber等人的IBM J.RES&DEV.49,4/5(2005)中也描述了C4NP制造的C4的制造和其它集成问题,该文献以引用的方式并入本文中。该技术有效地使用体型焊料,该体型焊料容易结合三元和四元多组分含铅和不含铅的焊料合金,该焊料合金具有被精确地控制的焊料组合物和低α粒子控制以进行环保的晶片凸起,从而实现既高密度又低成本的应用。这样可以得到高度的尺寸和体积均匀性,并且可以扩展到300mm的大晶片。
一般的C4结构由以焊球受限冶金(下文称为“BLM”)开始的所有元件构成。多层BLM结构通常包括粘合层、反应阻挡层和可润湿层,以促进形成连接在IC器件和互连结构、芯片载体之间的凸焊点。选择BLM结构中的不同金属层,以使它们相互可以相容并且可以与焊料合金相容,从而不仅满足C4连接中的严格的电性、机械和可靠性要求,而且也可以容易地制造。
下面总结对包括三层BLM结构和C4凸点的元件的详细描述。
1)要沉积在晶片的顶面上的第一层是BLM的粘合层,该粘合层提供与下面的衬底的粘附。该层也可以充当扩散/反应阻挡层,以防止制程后端(BEOL)引线层与焊料之间的任何相互作用。这是通常通过溅射、蒸发或感应加热而沉积在晶片钝化层表面的薄层,该薄层通常由聚合物、氧化物或氮化物材料或其组合制成。用于粘合层的候选材料是Cr、Ti、W、TiW、Ta、TiN、TaN、Zr等,这仅举几个例子,该粘合层的厚度在数百埃至数千埃的数量级上。
2)BLM的下一层是反应阻挡层,该反应阻挡层可以通过熔融焊料焊接,但是慢慢反应(受限控制的反应),以允许多个热回流循环(或再工作循环(rework cycle)),而没有全部被消耗。反应阻挡层的候选材料是Ni、Co、W、Ru、Hf、Nb、Mo、V、Ta及它们的合金。这里仅举几个例子。该层的厚度通常在数千埃至数微米的数量级上,该层通过溅射、蒸发、无电镀或电镀来沉积。
3)BLM的最后层是可润湿层,从而使得焊料的可湿性好并且与焊料快速反应。典型的例子是铜、钯、金、锡及它们的合金,该层的厚度通常在几百埃至几千埃的范围内,该层通过溅射、蒸发、无电镀或电镀来沉积。在一些特殊芯片连接应用中,Cu厚度可以提高到数微米厚的范围。
4)关于形成在BLM结构顶部上的C4凸点,已经开发了很多制造工艺,包括蒸发、电镀、模版印刷、焊膏丝网印刷和焊料喷射以及熔融焊料注射,这里仅举几个例子。
5)在形成凸点之后,回流凸焊点。通常在带炉(belt furnace)或真空炉或烘箱中的惰性或者还原气氛(N2或H2/N2混合物气体)下进行回流。在回流的过程中,在焊料和反应阻挡层之间形成金属互化物。这种化合物为可靠的焊料连接提供了良好的机械完整性。
6)最后,对晶片进行测试,并且,通过切割、分类和挑选(DSP)操作将晶片切成芯片。挑选好的芯片(通过电测试规格的那些芯片)并将它们进行排列,通过使用合适的焊剂或无焊剂连接来将该芯片倒装连接到芯片载体上。
发明内容
因此,本发明的一个方面是提供一种用于倒装芯片附着的BLM结构,该BLM结构适合与无铅和含铅焊料一起使用,并且既使用无铅焊料又使用含铅焊料。
本发明的另一目的是提供倒装芯片电连接,该倒装芯片电连接减少了计算机芯片中的软错误的出现。
本发明关注用于C4连接的无铅焊料中的成本有效的、环境无害的可靠的BLM。本发明还提供能够用于制造集成的C4结构的工序,即,选择BLM和用来生成最终的BLM结构的沉积及图形化过程。
无铅C4通常含有Sn作为主要成分(通常,大于90重量%)以及一种或多种成合金元素。由于Sn的高反应性的性质,无铅焊料需要更结实的反应阻挡层,以保护焊球受限冶金中的端子金属和下面的引线层免受富含Sn的焊料冲击。用于无铅焊料的最可能的候选材料是基于锡的合金,该合金掺杂有小量的银、铜、钴、镍、铋、锑,这里仅举几个例子。
由于铅的毒性,希望从电子焊料中除去铅。广泛地报道在酸雨的条件下从垃圾场(lanfill)中的电子组件滤出铅到地下水。使用无铅焊料也有助于限制由于从含铅的焊料中排放的α粒子所引起的IC器件中软错误率的手段。
焊料可以通过电镀、蒸发、焊膏丝网印刷或注模的焊料工艺来生产,这在美国专利5,244,143、5,775,569、6,003,757和6,056,191中有所公开。
因此,本发明涉及:互连结构,适用于将微电子器件芯片倒装芯片地附着到芯片载体上;三层焊球受限冶金,包括用于沉积在晶片或衬底上的粘合层;焊料反应阻挡层,优选由选自包括Ni、Co、W、Ru、Hf、V、Mo、Nb及它们的合金的组中的物质构成;以及焊料可润湿层。该粘合层可以优选由选自包括Cr、Ti、TiW、TiN、TaN、Ta、Zr和ZrN的组中的物质形成。焊料可润湿层,顶层,可以优选由选自包括Cu、Pd、Au、Pt和Sn的组中的物质形成。互连结构还可以包括可任选的第四层,该第四层优选由选自包括Au和Sn的组中的物质形成(如果在前面的层中尚未使用Au或Sn)。在一个实施例中,粘合层优选包含Cr、Ti和TiW中的一种;反应阻挡层包含Ni、Co、Ru、Hf、Nb、V、W及它们的合金,焊料可润湿层优选包含Cu、Au、Sn、Pd和Pt中的一种。
本发明还涉及一种适用于将微电子器件芯片倒装芯片地附着到封装上的互连结构,该互连结构包括:两层BLM结构,该两层BLM结构包括粘合层和反应阻挡层,其中,该两层结构将多层薄膜结构的粘附性、反应性和可湿性浓缩到两层上,从而简化了工艺步骤并降低了生产成本。在一个实例中,粘合/阻挡层与焊料可润湿层组合,该焊料可润湿层是容易与含锡的无铅焊料反应的金属层,从而在焊接的过程中所述焊料可润湿层被消耗,其中,在焊接的过程中,在将所述粘合/反应阻挡层放置成与所述无铅焊料接触之后,粘合/反应阻挡层保留下来;一个或多个无铅焊球选择性地位于所述焊料可润湿层上,所述无铅焊球含有锡,作为主要组分,该锡掺杂有一种或多种合金组分。所述粘合/反应阻挡层可以优选包含选自包括TiW、TiN和Ti之一的组中的物质。所述焊料可润湿层可以优选包含选自包括Cu、Au、Pd、Ni、Co、Ru和Sn及它们的合金的组中的物质。该互连结构还可以包括可任选的第三层,该第三层优选包含Au或Sn,如果在第二层中尚未使用Au和Sn。优选地,无铅焊球包含基本上消除了α粒子发射的物质。该焊料合金具有作为主要成分的锡以及优选选自包括Cu、Ag、Bi、Ni、Co、Fe和Sb的组中的一种或多种合金组分。
本发明还涉及一种适用于将微电子IC器件芯片倒装芯片地附着到封装上的互连结构,该互连结构包括:三层BLM、粘合层、在粘合层上面的反应阻挡层以及焊料可润湿层,其中,所述粘合/阻挡层位于微电子器件和所述焊料可润湿层之间,并且,其中,所述焊料可润湿层是与含锡的无铅焊料的组分充分反应的组合物,在焊接过程中,在将所述反应阻挡层与所述焊料接触之后,所述反应阻挡层基本上很少与焊料反应;以及一个或多个无铅焊球,其选择性地位于所述焊料可润湿层上,从而所述无铅焊球基本上消除了α粒子发射以及由此引起的感应软逻辑错误(induced soft logic error)。
本发明还涉及一种形成互连结构的方法,该互连结构适用于将微电子器件芯片倒装芯片地附着到封装上,该方法包括:在晶片或衬底上形成覆盖式(blanket)的焊球受限冶金;在覆盖式BLM层上形成抗蚀剂图形;通过使用抗蚀剂作为蚀刻掩模来蚀刻BLM;剥离该抗蚀剂,以形成焊料可湿BLM端子垫;以及在BLM垫上沉积焊料。该焊料可以基本上不含铅。该BLM垫可以通过下述方式来形成:在衬底上沉积粘合层;在粘合层上沉积反应阻挡层;以及在阻挡层上沉积焊料可润湿层。该反应阻挡层可以包含优选选自包括Ni、Co、Ru、W、Hf、Nb、V、Mo及它们的合金的组中的物质。该粘合层可以通过溅射、蒸发或感应加热来沉积,并且可以具有在100埃或约5000埃的厚度。所述反应阻挡层可以通过溅射、电镀或蒸发来沉积,并且可以具有在约1000埃至约30000埃的厚度。所述焊料可润湿层也可以通过溅射、电镀或蒸发来沉积,并且具有约100埃至约20000埃的厚度。
该方法还可以包括在所述焊料可润湿层上沉积可任选的层,该可任选的层优选包含Au、Pd或Sn。在所述焊料可润湿层上沉积的该层可以具有在基本上100埃至基本上10000埃之间的厚度,并且可以优选通过溅射、电镀或无电镀或蒸发中的一种方法来沉积。该方法还优选包括在150-350摄氏度下对焊球受限冶金退火30至90分钟。
本发明还涉及一种形成互连结构的方法,该互连结构适用于将微电子器件芯片倒装芯片地附着到芯片载体上,该方法包括:将粘合层沉积在充当芯片载体的晶片或衬底上;在该粘合层上沉积焊料反应阻挡层;在该反应阻挡层上沉积焊料可润湿层;在该焊料可润湿层上沉积无铅焊料;以及使所述焊料回流,使得所述焊料可润湿层扩散到无铅焊料。所述焊料可润湿层可以优选包含Cu。当在回流过程中Cu溶解到纯Sn焊料时,形成二元Sn-Cu无铅焊料。无铅焊料候选者基本上可以是二元Sn-Ag,因此,在回流过程中在含Cu的可润湿层上形成三元Sn-Ag-Cu无铅焊料。
通过Cu的溶解,焊料中的元素种数增加至少一种元素。可以形成二元共晶或近三元共晶焊料。该方法还可以包括在150-350摄氏度下退火30至90分钟。
附图说明
结合附图阅读本发明的以下的详细描述,本发明的这些和其它方面、特征和优点将显而易见,在附图中:
图1是根据本发明的C4结构的第一实施例的剖视图。
图1A是在焊料回流之后的图1的实施例的剖视图。
图2A至图2D示出根据本发明的用于形成C4结构的第一方法的步骤。
图3A至图3D示出根据本发明的用于形成C4结构的第二方法的步骤。
图4是根据本发明的C4结构的第二实施例的剖视图。
图4A是在焊料回流之后的图4的实施例的剖视图。
图5是在250摄氏度与三层TiW/NiSi/Cu BLM连续地反应40分钟之后二元共晶Sn0.7重量%Cu无铅焊料的SEM横截面图。图5A对应于低放大率,图5B对应于高放大率。
图6是在250摄氏度与三层TiW/NiW/Cu BLM连续地反应40分钟之后二元共晶Sn0.7%Cu无铅焊料的SEM横截面图。图6A对应于低放大率,图6B对应于高放大率。
图7是在250摄氏度与两层TiW/Ru BLM连续地反应20分钟之后二元Sn3.8%Ag无铅焊料的SEM横截面图;TiW充当粘合层,Ru既充当反应阻挡层又充当焊料可润湿层。
具体实施方式
以适宜每一个具体应用的任何组合的形式可以实现对本发明所述的变型。因此,本文所述的可以对特定应用具有特殊的优势的特定限制和/或实施改进,未必一定都用于所有的应用。此外,应该认识到,并不是所有的限制都必须实施于包括本发明的一个或多个构思的方法、***和/或设备中。
参照图1,通过本发明,提供一种适用于将微电子集成电路(IC)芯片连接到封装上的互连结构10。具体来说,本发明属于常称为C4(控制塌陷芯片连接)的区域阵列或倒装芯片技术。BLM(也称为凸点下冶金(UBM))11沉积在钝化的集成电路(IC)器件12(例如,硅晶片)上。BLM 11的第一层是粘合/扩散阻挡层14,该第一层可以优选是选自包括Cr、Ti、TiW、V、Zr、Ta及它们的合金(或化合物)的组中的金属、合金或化合物,可以具有约100埃至5000埃的厚度,并且可以通过蒸发、溅射或其它已知的技术来沉积。随后,优选选自包括Ni、Co、Ru、Hf、Nb、Mo、W、V及它们的合金(或化合物)的组中的金属或化合物的焊料反应阻挡层16可以优选通过(例如)溅射、电镀或蒸发沉积在粘合层上约500埃至30000埃的厚度。顶层18是优选包含选自Cu、Au、Pd、Pt、Sn及它们的合金的组中的金属的可焊接层,通过(例如)溅射、电镀或者蒸发达到约500埃至2000埃的厚度。在一些特殊应用中,如果当选择相同的元素用于第二层和第三层时,则三层BLM结构可以简化为两层,这同样也适用于第一层和第二层。可任选的第四层38,例如,优选由金或Sn构成的薄层,可以沉积在层18上,以充当防止氧化或腐蚀的保护层。然后,施加焊料40,如图1所示。
可以用无铅的焊球20完成C4结构10,该焊球含有锡,作为主要成分,并且优选包含选自Ag、Cu、Bi、Ni、Co、In和Sb中的一种或多种合金元素。
实例1-三层BLM
根据本发明,优选的粘合层14是TiW或Ti,优选被溅射或蒸发成约100埃至5000埃的优选厚度。只要既保持良好的粘附性又保持良好的阻挡性,粘合层14的厚度可以大幅度地改变。如果在形成图形化的BLM结构11的过程中沉积覆盖式TiW并随后进行蚀刻作为最后的步骤,则在保持充足的性能的情况下应当使膜厚度最小。其它可选的粘合层是厚度为约100埃至5000埃的Cr、Ta、W或及它们的合金。
第二层16是焊料反应阻挡层,其厚度通常优选为几千埃至几微米,其优选通过溅射、蒸发或电镀来进行沉积。因为高锡含量的无铅焊料的反应性比共晶富含铅的Pb-Sn焊料的反应性高,所以需要厚的反应阻挡层,以能够经受多个热循环,而没有全部被消耗掉。BLM的总消耗将导致“浮动BLM”的故障,从而降级焊料连接的机械完整性。因为Cu与高含量Sn的焊料反应性强,所以对于无铅应用而言,在BLM中低反应性的金属(例如Ni或其合金)是优选的。
根据本发明,已经发现,适合的焊料反应阻挡层可以优选由Ni、Ru、Co、W、Hf、Nb、Mo、V及它们的合金形成。
第三层18是焊料可润湿层。在回流连接过程中,层18容易被熔融焊料弄湿并潜在地完全被溶解入熔融焊料中,从而允许通过与反应阻挡层形成金属互化物来与BLM垫形成可靠的冶金连接。可润湿层优选是选自包括Cu、Au、Pd、Pt、Sn及它们的合金的组中的金属。铜和金二者与高含量锡的焊料非常快速地反应,并且不提供合适的反应阻挡层。然而,这些金属都反应并与焊料很好地弄湿,从而充当用于氧化保护的顶层,弄湿并连接到C4焊料。
另外的好处是,溶解入焊料中的Cu可以用作用于焊料的合金元素。例如,当Cu溶解入纯Sn焊料时,其形成二元Sn-Cu焊料合金。当溶解入二元SnAg合金时,其形成三元近共晶Sn-Ag-Cu焊料。Sn-Cu和Sn-Ag-Cu是用于微电子组件中的首选的无铅焊料候选材料。示出了Cu作为焊料中的附加合金元素的溶解和结合,简化了电镀过程。对二元SnAg合金可以容易地进行简单的电镀,而不用非常复杂地电镀三元合金Sn-Ag-Cu,其中,合金元素Cu来自BLM垫。将同样的方法应用到电镀纯Sn,这是非常简单,然后,纯Sn与来自BLM垫的Cu反应,从而形成简单的二元合金***,这比电镀二元Sn-Cu合金简单,从而有助于制造。在电镀多组分焊料合金的过程中维持对焊料组合物的池化学(bath chemisty)和精确控制是非常复杂的,使用该方法可以简化此复杂性。请注意,在此过程的回流部分中,Cu基本上快速地溶解在液体焊料中,从而确保焊球的组合物相对比较均匀。
对于本发明的第一范例实施例,焊料可润湿层溶解在焊球中的方式在图1A中示出,对于本发明的第二实施例,其在图4A中示出。
使用与用于沉积其它BLM层相同的过程,可以溅射、蒸发或电镀可焊接层。随后,必须对覆盖式膜进行图形化,以在图1所示的成品结构中形成BLM 11.
实例2-四层BLM
在本实例中,第一层优选是TiW、Cr或Ti。第二层优选是Ni、Co、Ru、W或其合金(或化合物)。第三层优选是Cu、Pd、Pt或其合金。第四层可以优选是Au或Sn。
实施例3-简单的两层BLM
在本实例中,第一层优选是TiW、Ti或Cr,充当粘合/反应阻挡层。第二层优选选自包括Ru、Ni、Cu、Co、Sn或其合金的组中。
在所有的三层或四层结构中,Cu是优选的可润湿层,在回流连接期间Cu快速反应并溶解入熔融焊料合金中,形成Cu-Sn金属互化物,很好地粘附在BLM/焊料界面上,从而提高了焊料连接的机械完整性。
用于UBM上的焊料合金的熔性必须与制造要求兼容。用于焊料的优选的沉积方法是C4NP、电沉积(直接电沉积合金,或者依次沉积各个合金组分)、模版印刷(stencil printing)或焊膏丝网印刷(pastescreening)。
图2A至图2D示出生产图1的结构的步骤。在图2A中,如上所述,在晶片或衬底12上制造图1的BLM 11,包括层14、16和18。C4图形以合适的光致抗蚀剂图形24限定在晶片上,该C4图形的厚度至少与要沉积的焊料的厚度一样大。
参照图2B,通过熔融焊料注射、电镀、焊膏丝网印刷、模版印刷或焊料喷射(这里仅举几个例子),无铅焊料26转移沉积到BLM上。在回流混合之后,依次电镀各焊料组分,这是直接电镀合金的另一可选方法。如图2D所示,随后蚀刻在焊料下没有被覆盖的图2c中的覆盖式BLM层。
在合适的气氛下回流焊料,以形成焊球如图1所示。
然后,切割、分类和挑选晶片12,利用合适的焊剂或无焊剂连接,将好的芯片连接到陶瓷或有机芯片载体上。
图3A至图3D示出形成图1的结构的另一可选的工艺。在图3A中,光致抗蚀剂图形24沉积在覆盖式BLM 11上。图3B示出对在光致抗蚀剂24下没有被覆盖的BLM 11的层的蚀刻。光致抗蚀剂图形24用作图形化BLM的蚀刻掩模。在图3C中,从图形化的BLM层剥离光致抗蚀剂图形24。在图3D中,通过C4NP熔融焊料转移、焊膏丝网印刷、模版印刷等,在晶片或衬底上,将凸焊点选择性地沉积在图形化的BLM 11上。
然后,在合适的气氛下回流凸焊点26。
然后,切割、分类和挑选晶片。选择好的芯片并利用合适的焊剂或无焊剂连接将其连接到芯片载体上。
图4是根据本发明的C4结构的第二范例实施例的剖视图。BLM30是两层结构,适合沉积在具有氧化物、氮化物或聚酰亚胺钝化32的衬底或晶片上。沉积在钝化晶片或衬底的表面上的第一层34可以优选是Cr、Ti、TiW、Zr、V或其合金。下一层36既充当反应阻挡层又充当可焊接层,沉积在层34上,并且可以优选选自Ru、Ni、Co、Cu、Pd、Pt或其合金。可任选的第三层38,例如金或Sn的第三层,可以沉积在层36上,充当氧化保护层。可任选的层38应当是与已经选择用于第二层的材料不同的材料。此外,在上述的层状结构中,如果所选择的元素已经用于前面的层,则它将不用于后面的层,以避免复制。然后,施加焊料40,如图1所示。如上所述,当没有施加可任选的层38并且图4的顶层是(例如)Cu时,焊料可润湿层溶解入焊球40中的方式示于图4A中。
可以使用图2A至图2D或者图3A至图3D所示的任一种方法来形成图4所示的实施例。
图5是在250摄氏度与三层TiW/NiSi/Cu BLM连续地反应40分钟之后二元Sn0.7%Cu无铅焊料的SEM横截面图。图5A是低放大率,图5B是高放大率。TiW是粘合层;NiSi是反应阻挡层;Cu是可焊接层,在回流连接之后,该可焊接层全部溶解入焊料。
图6是在250摄氏度与三层TiW/NiW/Cu BLM连续地反应40分钟之后二元Sn0.7%Cu无铅焊料合金的SEM横截面图。图5A对应于低放大率,图5B对应于高放大率。TiW是粘合层,NiW是反应阻挡层,Cu是可焊接层,其通过与焊料反应全部被消耗掉。
图7是在250摄氏度与两层TiW/Ru BLM连续地反应20分钟之后二元Sn3.8%Ag无铅焊料的SEM横截面图;TiW是粘合层,Ru既充当反应阻挡层又充当焊料可润湿层。薄层的金属互化物形成在焊料和BLM界面上。
实例4-两层BLM
第一层优选是TiW、Ti或Cr或其合金。第二层优选是Ru、Cu、Ni、Co、Sn或其合金,充当反应阻挡层又充当可湿表面。
实例5-三层BLM结构
三层BLM结构优选包含:TiW、Ti或Cr,作为沉积在衬底上的粘合层;Ni或其合金,充当在粘合层上的反应阻挡层;以及Cu牺牲层,用于电镀焊料沉积。Sn或SnAg二元合金的无铅焊料沉积在Cu层上。当如上所述的那样回流时,Cu层溶解入所得到的焊球,以与焊料成合金。焊料优选是无铅的,当Cu溶解入焊料时,形成二元Sn-Cu合金或三元Sn-Ag-Cu合金,其中,原始焊料分别是纯Sn和二元Sn-Ag。
通过在BLM图形化之前或之后在150-350摄氏度下退火30至90分钟,可以进一步地提高本发明的BLM冶金的鲁棒性。
因此,虽然已经示出、描述和指出了本发明的基本的新颖特征(如应用到本发明的当前的优选实施例的那些特征),但是,应该理解,在不脱离本发明的实质的情况下,本领域的技术人员可以对所示的方法和产品的形式和细节及其操作进行各种删除、替换和改变。另外,应该理解,所述附图并不一定是按比例绘制的。因此,本发明应当仅仅由附属权利要求及其等同形式限制。
请注意,前面概述了本发明的多个相应目的和实施例的一些。本发明的构思可以用于很多应用。因此,尽管对特定布置和方法进行了描述,但是,本发明的目的和构思适合应用于与其它的布置和应用中。本领域的技术人员应该清楚,在不脱离本发明的实质和范围的情况下,可以对所披露的实施例进行其它的修改。所描述的实施例应该解释为仅仅示出本发明的多个显著特征和应用中的一些。通过以不同的方式实施所披露的发明或者以本领域技术人员所知的方式修改本发明,可以实现其它的有益的结果。因此,应该理解,这些实施例是作为例子而不是为了限制的目的而提供的。本发明的范围由附属权利要求限定。
Claims (37)
1.一种适用于将微电子器件芯片倒装芯片地附着到芯片载体上的互连结构,包括三层焊球受限冶金,该三层焊球受限冶金包括:
粘合层,用于沉积在晶片或衬底上;
选自包括Co、Ru、W、Nb、Hf、Mo及它们的合金的组中的物质的焊料反应阻挡层;以及
焊料可润湿层。
2.根据权利要求1所述的互连结构,其中,所述粘合层由选自包括TiW、Ti、Cr、Ta及它们的合金的组中的物质形成。
3.根据权利要求1所述的互连结构,其中,所述焊料可润湿层由选自包括Cu、Pd、Au、Pt、Sn及它们的合金的组中的物质形成。
4.根据权利要求1所述的互连结构,还包括由选自包括Au和Sn的组中的物质形成的第四层。
5.根据权利要求1所述的互连结构,其中,所述粘合层选自包括Ti和TiW的组中,所述反应阻挡层选自包括Ni及其合金的组中,所述焊料可润湿层选自包括Cu、Sn、Pd、Pt及它们的合金的组中。
6.根据权利要求5所述的互连结构,其中,所述Ni合金是通过将Ni和选自包括W、Si、Ru、Ti、La、Zr、Hf、V、Cr、Cu、Rh、Ir、Re、Mo、Nb、Ta、Au、Pd和Pt的组中的一种或多种元素成合金来形成的,从而形成二元、三元或四元合金反应阻挡层。
7.根据权利要求6所述的互连结构,其中,所述Ni合金反应阻挡层是通过将Ni和W成合金形成的,从而形成二元非磁性NiW合金层,其中,W组分大于17重量%,以利于从非磁性靶进行溅射沉积。
8.根据权利要求6所述的互连结构,其中,所述Ni合金反应阻挡层是通过将Ni和Si成合金形成的,从而形成二元非磁性NiSi合金层,其中,所述合金中的Si大于3.8重量%,以利于从非磁性靶进行溅射沉积。
9.根据权利要求6所述的互连结构,其中,所述无铅焊球包含消除α粒子发射的物质。
10.根据权利要求6所述的互连结构,其中,所述焊料合金组分选自包括Sn、Bi、Cu、Ag、Ni、Co、La、Fe和Sb的组中。
11.一种适用于将微电子器件芯片倒装芯片地附着到封装上的互连结构,包括两层焊球受限冶金,该两层焊球受限冶金包括:
粘合/反应阻挡层,其中,该粘合/反应阻挡层既充当粘合层又充当反应层;以及
焊料可润湿层;
所述粘合/反应阻挡层放置在微电子器件和所述焊料可润湿层之间,其中,所述粘合/反应阻挡层包含选自包括W、Cr、V及它们的合金的组中的物质,并且其中,所述焊料可润湿层是与含锡的无铅焊料的组分反应的金属,从而在焊接的过程中所述焊料可润湿层被消耗,其中,在焊接的过程中所述粘合/反应阻挡层在其被放置成与所述无铅焊料接触之后保留下来,并且,其中,所述焊料可润湿层是与含锡的无铅焊料的组分反应的金属;并且
一个或多个无铅焊球,其选择性地位于所述焊料可润湿层上,所述无铅焊球包含作为主要组分的锡和一种或多种合金组分。
12.根据权利要求11所述的互连结构,其中,所述焊料可润湿层包含选自包括Cu、Ru、Au、Pd、Pt、Sn及它们的合金的组中的物质。
13.根据权利要求11所述的互连结构,其中,所述粘合金属是与选自包括Ti、W、Cu、Ni、Co、Pd、Pt、Au、Zr、Hf和N的组中的一种或多种元素成合金的。
14.一种适用于将微电子器件芯片倒装芯片地附着到封装上的互连结构,包括:
两层焊球受限冶金,该两层焊球受限冶金包括:粘合层,其中,粘合层起到促进BLM到衬底的粘附性的作用;以及焊料反应阻挡层/可润湿层,所述反应阻挡层/可润湿层起到有利于焊料可湿性和减慢焊料反应的作用,该反应阻挡层/可润湿层放置在微电子器件和所述焊料之间,并且,其中,所述焊料反应阻挡层/可润湿层是容易与含锡的无铅焊料的组分反应的金属,从而,在焊接的过程中所述焊料反应阻挡层/可润湿层仅仅部分被消耗,其中,在焊接的过程中,在将所述焊料反应阻挡层/可润湿层放置成与所述无铅焊料接触之后,剩余的不反应的反应阻挡层/可润湿层仍保留下来;以及
一个或多个无铅焊球,其选择性地位于所述焊料可润湿层上,所述无铅焊球包含作为主要组分的锡和一种或多种合金组分。
15.根据权利要求14所述的互连结构,其中,所述粘合层包含选自包括Cr、TiW、Ti、TiN、TaN、Ta和V的组中的物质。
16.根据权利要求14所述的互连结构,其中,所述焊料反应阻挡层/可润湿层包含选自包括Ru、Ni、Co、Pt及它们的合金的组中的物质。
17.根据权利要求14所述的互连结构,还包括包含Au或Sn的第三层。
18.根据权利要求14所述的互连结构,其中,所述可焊接层由选自包括Cu、Ni、Co、Pd、Ru、Au、Pt、Sn及它们的合金的组中的物质形成。
19.一种适用于将微电子器件芯片倒装芯片地附着到封装上的互连结构,包括:
三层焊球受限冶金,该三层焊球受限冶金包括:粘合层、在所述粘合层顶部的反应阻挡层以及焊料可润湿层,其中,所述粘合/阻挡层位于微电子器件和所述焊料可润湿层之间,并且,其中,所述焊料可润湿层是与含锡的无铅焊料的组分充分反应的组合物,在焊接过程中,在将所述反应阻挡层与所述焊料接触之后,所述反应阻挡层很少与焊料反应;以及
一个或多个无铅焊球,其选择性地位于所述焊料可润湿层上,所述无铅焊球包含作为主要组分的锡和选自包括Co、La、Fe和Ni的组中的一种或多种合金组分,从而所述无铅焊球消除了α粒子发射以及由此所引起的感应软逻辑错误。
20.一种形成适用于将微电子器件芯片倒装芯片地附着到封装上的互连结构的方法,包括:
在衬底上形成焊球受限冶金,所述焊球受限冶金通过下述方式形成:
在所述衬底上沉积粘合层;
在所述粘合层上沉积反应阻挡层,所述反应阻挡层包含选自包括Co、W、Ru、Nb、Mo、Hf及它们的合金的组中的物质;以及
在所述阻挡层上沉积焊料可润湿层;
在所述焊球受限冶金上形成抗蚀剂图形;
通过使用所述抗蚀剂图形作为蚀刻掩模,蚀刻所述焊球受限冶金;
从剩余的焊球受限冶金上除去所述抗蚀剂;以及
在所述焊球受限组合物上沉积焊料。
21.根据权利要求20所述的方法,其中,所述焊料不含铅。
22.根据权利要求20所述的方法,其中,所述粘合层是通过溅射或蒸发而沉积的。
23.根据权利要求20所述的方法,其中,所述粘合层被沉积成具有100埃至5000埃的厚度。
24.根据权利要求20所述的方法,其中,所述反应阻挡层是通过溅射、电镀或蒸发而沉积的。
25.根据权利要求24所述的方法,其中,所述反应阻挡层被沉积成具有1000埃至40000埃的厚度。
26.根据权利要求20所述的方法,其中,所述焊料可润湿层是通过溅射、电镀或蒸发而沉积的。
27.根据权利要求20所述的方法,其中,所述焊料可润湿层被沉积成具有200埃至20000埃的厚度。
28.根据权利要求20所述的方法,还包括在所述焊料可润湿层上沉积包含Au或Sn的层。
29.根据权利要求28所述的方法,沉积在所述焊料可润湿层上的层具有在100埃至2000埃之间的厚度。
30.根据权利要求28所述的方法,沉积在所述焊料可润湿层上的层是通过溅射、电镀或无电镀或蒸发中的一种方法而沉积的。
31.根据权利要求20所述的方法,还包括在150-350摄氏度下对所述焊球受限冶金退火30至90分钟。
32.一种形成适用于将微电子器件芯片倒装芯片地附着到芯片载体上的互连结构的方法,包括:
在充当所述芯片载体的晶片或衬底上形成粘合层;
在所述粘合层上沉积焊料反应阻挡层,所述焊料反应阻挡层包含选自包括Co、W、Ru、Nb、Mo、Hf及它们的合金的组中的物质;
在所述反应阻挡层上沉积焊料可润湿层;
在所述焊料可润湿层上沉积无铅焊料;以及
对所述焊料进行回流,使得所述焊料可润湿层扩散到所述无铅焊料中。
33.根据权利要求32所述的方法,所述焊料可润湿层包含Cu,所述Cu扩散到所述焊料中。
34.根据权利要求32所述的方法,其中,所述无铅焊料是纯的Sn,在回流的过程中形成二元Sn-Cu无铅焊料。
35.根据权利要求32所述的方法,其中,所述无铅焊料是二元Sn-Ag,在回流的过程中形成三元Sn-Ag-Cu无铅焊料。
36.根据权利要求32所述的方法,其中,形成近共晶的二元或三元焊料。
37.根据权利要求32所述的方法,其中,所述粘合层、所述焊料反应阻挡层和所述焊料可润湿层构成焊球受限冶金,所述方法还包括在150-350摄氏度下对构成的焊球受限冶金退火30至90分钟。
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Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7897515B2 (en) * | 2009-04-20 | 2011-03-01 | Seagate Technology Llc | Method of fabricating structures |
US8378485B2 (en) * | 2009-07-13 | 2013-02-19 | Lsi Corporation | Solder interconnect by addition of copper |
TWI391037B (zh) * | 2009-11-09 | 2013-03-21 | Advance Materials Corp | 接墊結構及其製法 |
US9082762B2 (en) * | 2009-12-28 | 2015-07-14 | International Business Machines Corporation | Electromigration-resistant under-bump metallization of nickel-iron alloys for Sn-rich solder bumps in Pb-free flip-clip |
US8259464B2 (en) * | 2010-06-24 | 2012-09-04 | Maxim Integrated Products, Inc. | Wafer level package (WLP) device having bump assemblies including a barrier metal |
US8518815B2 (en) | 2010-07-07 | 2013-08-27 | Lam Research Corporation | Methods, devices, and materials for metallization |
US20120068345A1 (en) * | 2010-09-16 | 2012-03-22 | Infineon Technologies Ag | Layer stacks and integrated circuit arrangements |
US20120325671A2 (en) * | 2010-12-17 | 2012-12-27 | Tel Nexx, Inc. | Electroplated lead-free bump deposition |
JP5659821B2 (ja) * | 2011-01-26 | 2015-01-28 | 三菱マテリアル株式会社 | Sn合金バンプの製造方法 |
CN102330056A (zh) * | 2011-06-13 | 2012-01-25 | 星弧涂层科技(苏州工业园区)有限公司 | Led倒装晶元金属膜层及制备方法 |
US9142520B2 (en) * | 2011-08-30 | 2015-09-22 | Ati Technologies Ulc | Methods of fabricating semiconductor chip solder structures |
CN102496604A (zh) * | 2011-12-19 | 2012-06-13 | 南通富士通微电子股份有限公司 | 高可靠芯片级封装结构 |
EP2840596B1 (en) * | 2012-04-17 | 2017-11-22 | Tanigurogumi Corporation | Forming method of solder bumps and manufacturing method for substrate having solder bumps |
CN104465574B (zh) * | 2013-09-12 | 2017-09-26 | 中国科学院金属研究所 | 一种以FeP合金作为接焊层的凸点封装结构 |
US9515010B2 (en) | 2014-02-24 | 2016-12-06 | Nantong Fujitsu Microelectronics., Ltd. | Semiconductor packaging structure and forming method therefor |
US9627335B2 (en) * | 2014-05-08 | 2017-04-18 | Infineon Technologies Ag | Method for processing a semiconductor workpiece and semiconductor workpiece |
US9804498B2 (en) * | 2014-06-09 | 2017-10-31 | International Business Machines Corporation | Filtering lead from photoresist stripping solution |
JP6648468B2 (ja) * | 2014-10-29 | 2020-02-14 | Tdk株式会社 | Pbフリーはんだ及び電子部品内蔵モジュール |
JP6259023B2 (ja) | 2015-07-20 | 2018-01-10 | ウルトラテック インク | 電極系デバイス用のald処理のためのマスキング方法 |
TWI607587B (zh) * | 2016-09-13 | 2017-12-01 | 台灣琭旦股份有限公司 | 固晶穩固製程 |
CN107845713A (zh) * | 2016-09-19 | 2018-03-27 | 戴莉霞 | 固晶稳固方法 |
US11470727B2 (en) * | 2016-10-24 | 2022-10-11 | Jaguar Land Rover Limited | Apparatus and method relating to electrochemical migration |
US10629334B2 (en) * | 2017-09-20 | 2020-04-21 | Texas Instruments Incorporated | Nanostructure barrier for copper wire bonding |
US11011483B2 (en) * | 2018-02-21 | 2021-05-18 | Texas Instruments Incorporated | Nickel alloy for semiconductor packaging |
JP2020047775A (ja) * | 2018-09-19 | 2020-03-26 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法および半導体装置 |
US10937735B2 (en) * | 2018-09-20 | 2021-03-02 | International Business Machines Corporation | Hybrid under-bump metallization component |
CN112582333A (zh) * | 2019-09-27 | 2021-03-30 | 中芯长电半导体(江阴)有限公司 | 一种重新布线层及其制备方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1681099A (zh) * | 2004-03-31 | 2005-10-12 | 国际商业机器公司 | 使用无铅焊料并具有反应阻挡层用于倒装芯片的互连结构 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5376584A (en) * | 1992-12-31 | 1994-12-27 | International Business Machines Corporation | Process of making pad structure for solder ball limiting metallurgy having reduced edge stress |
JP3682758B2 (ja) * | 1998-12-24 | 2005-08-10 | 富士通株式会社 | 半導体装置及びその製造方法 |
US6801128B1 (en) * | 2000-09-21 | 2004-10-05 | Robert B. Houston | Perimeter beam tower |
JP4656275B2 (ja) * | 2001-01-15 | 2011-03-23 | 日本電気株式会社 | 半導体装置の製造方法 |
US20020151164A1 (en) * | 2001-04-12 | 2002-10-17 | Jiang Hunt Hang | Structure and method for depositing solder bumps on a wafer |
JP2003091784A (ja) * | 2001-09-19 | 2003-03-28 | Optex Co Ltd | 多段式能動型赤外線センサ |
TWI239578B (en) * | 2002-02-21 | 2005-09-11 | Advanced Semiconductor Eng | Manufacturing process of bump |
TW531869B (en) * | 2002-02-27 | 2003-05-11 | Advanced Semiconductor Eng | Manufacturing process of lead-free soldering bump |
TW533521B (en) * | 2002-02-27 | 2003-05-21 | Advanced Semiconductor Eng | Solder ball process |
US6806811B1 (en) * | 2002-03-27 | 2004-10-19 | Blaine C. Readler | Infra-red perimeter alarm |
TWI307152B (en) * | 2002-04-03 | 2009-03-01 | Advanced Semiconductor Eng | Under bump metallurgy |
JP3896406B2 (ja) * | 2002-04-11 | 2007-03-22 | オプテックス株式会社 | 防犯用センサ装置 |
US6744142B2 (en) * | 2002-06-19 | 2004-06-01 | National Central University | Flip chip interconnection structure and process of making the same |
TW546805B (en) * | 2002-07-18 | 2003-08-11 | Advanced Semiconductor Eng | Bumping process |
TWI281718B (en) * | 2002-09-10 | 2007-05-21 | Advanced Semiconductor Eng | Bump and process thereof |
TW571411B (en) * | 2002-12-25 | 2004-01-11 | Advanced Semiconductor Eng | Bumping process |
US7064446B2 (en) * | 2004-03-29 | 2006-06-20 | Intel Corporation | Under bump metallization layer to enable use of high tin content solder bumps |
US7325716B2 (en) * | 2004-08-24 | 2008-02-05 | Intel Corporation | Dense intermetallic compound layer |
JP4882229B2 (ja) * | 2004-09-08 | 2012-02-22 | 株式会社デンソー | 半導体装置およびその製造方法 |
TWI242867B (en) * | 2004-11-03 | 2005-11-01 | Advanced Semiconductor Eng | The fabrication method of the wafer and the structure thereof |
US7321140B2 (en) * | 2005-03-11 | 2008-01-22 | Applied Materials, Inc. | Magnetron sputtered metallization of a nickel silicon alloy, especially useful as solder bump barrier |
-
2006
- 2006-12-28 US US11/616,919 patent/US8314500B2/en not_active Expired - Fee Related
-
2007
- 2007-11-15 CN CN2007101869419A patent/CN101211878B/zh not_active Expired - Fee Related
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- 2009-10-05 US US12/587,301 patent/US7932169B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1681099A (zh) * | 2004-03-31 | 2005-10-12 | 国际商业机器公司 | 使用无铅焊料并具有反应阻挡层用于倒装芯片的互连结构 |
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