JP2004207685A - 無鉛ソルダバンプの製造方法 - Google Patents

無鉛ソルダバンプの製造方法 Download PDF

Info

Publication number
JP2004207685A
JP2004207685A JP2003356862A JP2003356862A JP2004207685A JP 2004207685 A JP2004207685 A JP 2004207685A JP 2003356862 A JP2003356862 A JP 2003356862A JP 2003356862 A JP2003356862 A JP 2003356862A JP 2004207685 A JP2004207685 A JP 2004207685A
Authority
JP
Japan
Prior art keywords
solder
copper
layer
base layer
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003356862A
Other languages
English (en)
Inventor
Se-Young Jang
世映 張
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR10-2003-0015503A external-priority patent/KR100534108B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2004207685A publication Critical patent/JP2004207685A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01063—Europium [Eu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

【課題】 ソルダのリフロー時に銅がソルダに拡散されることによって、１元界または２元界のすずめっきだけでも２元界または３元界の無鉛ソルダバンプを容易に製造することができ、工程コストが低くて、めっきの管理が容易な無鉛ソルダバンプの製造方法。
【解決手段】 無鉛ソルダバンプの製造方法において、電極パッド12が開放された保護層14を有するウェーハ10を提供する段階と；前記ウェーハ上に金属基底層20を形成する段階と；前記電極パッドに対応する部分を除いた前記金属基底層上にフォトレジスト30をリソグラフィーする段階と；前記電極パッドに対応する金属基底層上に銅層を形成する段階と；前記銅層上にソルダをめっきする段階と；前記フォトレジストを除去する段階と；前記ソルダをマスクと利用して、前記金属基底層をエッチングする一方、前記ソルダをリフローしてソルダバンプを製造する段階と；を含むことを特徴とする無鉛ソルダバンプの製造方法。
【選択図】 図１Ｃ

Description

本発明は、フリップチップ（Ｆｌｉｐ Ｃｈｉｐ）方式の半導体素子の接触端子であるバンプを形成する方法に係り、さらに詳しくは、無鉛ソルダバンプの形成が容易であり、工程コストが低くてめっきの管理の容易な無鉛ソルダバンプの製造方法に関する。
既存のワイヤボンディング方式は、金ワイヤが、半導体ウェーハの電極パッドと鉛フレームの内部鉛を電気的に連結させる方式である。また、フリップチップ方式は、半導体ウェーハ上に形成されたバンプが、半導体ウェーハと半導体ウェーハが実装される印刷回路基板の接触端子を連結させる方式である。
バンプを半導体ウェーハの電極パッド上に形成するために、従来では、鉛（Ｐｂ）とすず（Ｓｎ）を主成分とするソルダ（Ｓｏｌｄｅｒ）が利用された。
しかし、日々に増大される環境問題により、電子製品において鉛の使用を制限する法律の施行が、ヨロッパと日本を始めとして全世界に具体化されており、ヨロッパの自動車廃車のリサイクル法案は、２００４年から鉛含有ソルダを規制対象としており、日本も廃車法と家電製品のリサイクル法を制定して廃家電製品に対する鉛の回収を義務化している。これにより、既存の鉛を含む家電製品の工程を無鉛ソルダに転換し、半導体ウェーハのソルダバンプも無鉛ソルダを使用して形成しなければならない必要性が増加している。
したがって、従来に一般に使用された鉛−すずのソルダ材料を代替するために、すず―銀―銅、すず−銀またはすず−銅の造成を有する２元界または３元界合金のソルダ材料が使用されている。
しかし、前記のような無鉛ソルダめっき液は、すずと銅等の合金造成の変化により溶解点が急激に変わるので、２７０℃のリフロー工程温度で使用できるソルダの造成領域が約３乃至７％範囲に狭くなるという短所がある。また、微量に添加される銅と銀の場合、１乃至２％の追加含量が、合金の溶解点を１０℃以上に増加させて接触不良の恐れがあるため、これら合金の造成比は極めて正確に合わせなければならない。また、従来の２元界または３元界の合金無鉛ソルダは、すずより還元電位値の高い銀と銅が優先的にめっきされる現状があるので、これを抑制するためには錯化剤（Ｃｏｍｐｌｅｘｉｎｇ Ａｇｅｎｔ）が使用されたが、このような錯化剤は、そのコストが高くて工程コストが高まるという問題がある。
本発明の目的は、無鉛ソルダの構成元素の中で一つである銅をソルダバンプの下端部に位置する金属基底層上に積層することにより、ソルダをリフローする時、銅がソルダに拡散されるようにして、１元界すずめっきだけで２元界無鉛ソルダバンプを、或いは２元界すず−銀めっきだけですず−銀−銅の３元界の無鉛ソルダバンプを容易に製造することができる無鉛ソルダバンプの製造方法を提供することである。
上記目的を達成するために、本発明は、無鉛ソルダバンプの製造方法において、電極パッドが開放された保護層を有するウェーハを提供する段階と；前記ウェーハ上に金属基底層を形成する段階と；前記電極パッドに対応する部分を除いた前記金属基底層上にフォトレジストをリソグラフィーする段階と；前記電極パッドに対応する金属基底層上に銅層を形成する段階と；前記銅層上にソルダをめっきする段階と；前記フォトレジストを除去する段階と；前記ソルダをマスクと利用して、前記金属基底層をエッチングする一方、前記ソルダをリフローしてソルダバンプを製造する段階と；を含むことを特徴とする。
ここで、前記ソルダは、すずであり、ここに銀をさらに含むことができる。
一方、前記リフロー段階は、２３０℃乃至２７０℃で１分間乃至２０分間行うことが好ましい。
また、前記銅層は、５μm乃至２０μmの厚さで形成されることが効果的である。
前記金属基底層は、前記ウェーハに最初に接触される層がチタニウム（Ｔｉ）、タングステン（Ｗ）、クロム（Ｃｒ）またはタングステン化チタニウム（ＴｉＷ）の中で一つであり、前記ウェーハの最初の接触層の上部の層が銅（Ｃｕ）、ニッケル（Ｎｉ）、ニッケル−バナジウム（Ｎｉ−Ｖ）または銅−ニッケル（Ｃｕ−Ｎｉ）合金の中でいずれか一つであることが好ましい。
前述したように、本発明によると、金属基底層上に銅を積層することにより、ソルダのリフロー時に銅がソルダに拡散されることにして、１元界または２元界のすずめっきだけでも２元界または３元界の無鉛ソルダバンプをように製造することができる。これにより、工程コストが低くて、めっきの管理が容易な無鉛ソルダバンプを製造することができる。
以下、添付の図面を参照して本発明を詳細に説明する。
図１Ａは、電極パッド１２が開放された保護層１４を有する半導体ウェーハ１０の断面図であり、図１Ｂはその上部に金属基底層（ＵＢＭ：Ｕｎｄｅｒ Ｂｕｍｐ Ｍｅｔａｌｌｉｚａｔｉｏｎ）２０が形成されている断面図である。金属基底層は、ソルダーをアルミニウム（Ａｌ）のような金属性の電極パッド１２上に電気めっきした後リフロー（ｒｅｆｌｏｗ）過程を経る時、この過程で電極パッド１２とソルダとの間に発生される拡散を防止し、電解めっき工程時にウェーハの全面積を連結する電気的な通路を提供し、フリップチップの接合時に電極パッド１２とソルダバンプ３４（図２Ａ、図２Ｂ参照）との間の界面接合力を増大させるために介されることである。金属基底層２０で、ウェーハに最初に接触される層である第１層１６は、チタニウム（Ｔｉ）、タングステン（Ｗ）、クロム（Ｃｒ）またはタングステン化チタニウム（ＴｉＷ）の中のいずれか一つであり、前記ウェーハの最初接触層の上部の層である第２層１８は、銅（Ｃｕ）、ニッケル（Ｎｉ）、ニッケル−バナジウム（Ｎｉ−Ｖ）または銅−ニッケル（Ｃｕ−Ｎｉ）合金中いずれか一つに構成することができる。このような金属基底層２０は、スパッターを利用して順次的に形成させれ、半導体ウェーハ１０との接着力及び続いた工程遂行でも損傷されない等を考慮しなければならない。
また、図１Ｃに示すように、電極パッド１２に対応する部分を除いた前記金属基底層２０上にフォトレジスト３０をリソグラフィーし、図１Ｄに示すように、電極パッド１２の対応する金属基底層２０上に銅層２２を形成する。これにより、ソルダ３２を銅層２２上にめっきすると（図１Ｃ参照）、ソルダ３２が銅層２２と直に接触することができる。ここで、ソルダ３２は、すずを主元素とする。この時、銅層２２は、５μm乃至２０μmの厚さが好ましい。
その後、図１Ｆに示すように、フォトレジストリ３０を除去し、最後にソルダ３２をマスクと利用して金属基底層２０をエッチング（図示せず）する。次に、最終的に、ソルダ３２をリフローする。図２Ａはリフロー過程で銅層２２の銅がソルダ３２に拡散されることを示し、図２Ｂは銅がソルダ３２に拡散されてすず−銅の２元界のソルダバンプ３４が形成されることを示す。
リフローは、２３０℃乃至２７０℃の温度を有する有機溶媒の内で行われることが好ましい。ソルダ３２がすずだけで行われる場合、ソルダをリフローする時の温度が２３２℃以上、即ちすずの溶融点より以上になると、金属基底層２０上に積層された銅層２２の銅がすず側に拡散されるとともにソルダ３２のすずも銅側に拡散される。これら拡散された二種の原子の中の一部は、界のエネルギーを低めるために界面で銅−すず間の金属化合物層を形成されるが、一部の銅原子はリフロー後にもソルダバンプ３４内に一定量が存在する。
一方、ソルダ３２は、すずを主元素としてここに銀をさらに含むことができる。これは、酒席−銀の２元界無鉛合金として、すず−銀−銅の３元界無鉛合金に比べて相対的に比率調整が容易である。本発明では、リフローの温度及び時間を調整することにより、ソルダ３２に銅が拡散される量を調節するので、工程コストが高く、品質管理が難しい３元界のバンプ形成工程を２元界のバンプ形成工程に短縮することができる。
次の表１は、層の構造が異なる金属基底層にすず／３．５銀（Ｓｎ／３．５Ａｇ）合金を電解めっきした後、温度及び時間を異なりにして、リフローを経た後、ソルダバンプの上端部の銅の含量をＥＤＸ（Ｅｎｅｒｇｙ Ｄｉｓｐｅｒｓｉｖｅ Ｘ−ｒａｙ Ｓｐｅｃｔｒｏｓｃｏｐｙ）で分析した結果である。表１によると、リフロー工程後、ソルダバンプの銅含量が熱処理条件により約１．５％乃至３％に至ることが分かる。この結果は、約１５０μm以下の小さい大きさを有する無鉛ソルダバンプを形成する時に、約１％の微量の銅を添加するために銅をめっき工程で別途に投入する必要がないことは明白である。
Figure 2004207685
一方、大気中の酸素の含量を除いた窒素の雰囲気の一般的なリフローにオーブンでフラックスを塗布し、ソルダバンプを溶融させることもできる。このようなソルダバンプのリフローは、金属基底層のエッチング後、またその以前に行うことができる。
上記に具体的に説明したように、本発明によると、２元界または３元界ソルダ合金めっき液を製造せずにも、金属基底層上の銅をソルダに拡散させることにより、ソルダバンプに含有されている銅の比率を容易に合わせることができる。
本発明による無鉛ソルダバンプの製造工程を示す断面図である。 本発明による無鉛ソルダバンプの製造工程を示す断面図である。 本発明による無鉛ソルダバンプの製造工程を示す断面図である。 本発明による無鉛ソルダバンプの製造工程を示す断面図である。 本発明による無鉛ソルダバンプの製造工程を示す断面図である。 本発明による無鉛ソルダバンプの製造工程を示す断面図である。 本発明によるソルダのリフロー時に、銅がソルダに拡散されることを示す断面図である。 本発明によるソルダのリフロー時に、銅がソルダに拡散されることを示す断面図である。
符号の説明
１０ 半導体ウェーハ
１２ 電極パッド
１４ 保護層
１６ 第１層
１８ 第２層
２０ 金属基底層
２２ 銅層
３０ フォトレジスト
３２ ソルダ
３４ ソルダバンプ

Claims (6)

  1. 無鉛ソルダバンプの製造方法において、
    電極パッドが開放された保護層を有するウェーハを提供する段階と、
    前記ウェーハ上に金属基底層を形成する段階と、
    前記電極パッドに対応する部分を除いた前記金属基底層上にフォトレジストをリソグラフィーする段階と、
    前記電極パッドに対応する金属基底層上に銅層を形成する段階と、
    前記銅層上にソルダをめっきする段階と、
    前記フォトレジストを除去する段階と、
    前記ソルダをマスクと利用して、前記金属基底層をエッチングする一方、前記ソルダをリフローしてソルダバンプを製造する段階と、を含むことを特徴とする、無鉛ソルダバンプの製造方法。
  2. 前記ソルダは、すずであることを特徴とする、請求項１に記載の無鉛ソルダバンプの製造方法。
  3. 前記ソルダは、銀をさらに含むことを特徴とする、請求項２に記載の無鉛ソルダバンプの製造方法。
  4. 前記リフロー段階は、２３０℃乃至２７０℃で１分間乃至２０分間行うことを特徴とする、請求項１に記載の無鉛ソルダバンプの製造方法。
  5. 前記銅層は、５μm乃至２０μmの厚さで形成されることを特徴とする、請求項１に記載の無鉛ソルダバンプの製造方法。
  6. 前記金属基底層は、前記ウェーハに最初に接触される層がチタニウム（Ｔｉ）、タングステン（Ｗ）、クロム（Ｃｒ）またはタングステン化チタニウム（ＴｉＷ）の中で一つであり、前記ウェーハの最初の接触層の上部の層が銅（Ｃｕ）、ニッケル（Ｎｉ）、ニッケル−バナジウム（Ｎｉ−Ｖ）または銅−ニッケル（Ｃｕ−Ｎｉ）合金の中のいずれか一つであることを特徴とする、請求項１に記載の無鉛ソルダバンプの製造方法。

JP2003356862A 2002-12-23 2003-10-16 無鉛ソルダバンプの製造方法 Pending JP2004207685A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20020082446 2002-12-23
KR10-2003-0015503A KR100534108B1 (ko) 2002-12-23 2003-03-12 무연 솔더범프 제조 방법

Publications (1)

Publication Number Publication Date
JP2004207685A true JP2004207685A (ja) 2004-07-22

Family

ID=32599377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003356862A Pending JP2004207685A (ja) 2002-12-23 2003-10-16 無鉛ソルダバンプの製造方法

Country Status (3)

Country Link
US (1) US20040121267A1 (ja)
JP (1) JP2004207685A (ja)
CN (1) CN1254862C (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009524928A (ja) * 2006-02-20 2009-07-02 ネペス コーポレーション 金属間化合物の成長を抑制したはんだバンプが形成された半導体チップ及びはんだバンプの製造方法
US8242597B2 (en) 2008-08-29 2012-08-14 Kabushiki Kaisha Toshiba Crystal structure of a solder bump of flip chip semiconductor device
US8922008B2 (en) 2012-05-07 2014-12-30 Samsung Electronics Co., Ltd. Bump structure, having concave lateral sides, semiconductor package having the bump structure, and method of forming the bump structure

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547623B2 (en) 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
TWI230989B (en) * 2004-05-05 2005-04-11 Megic Corp Chip bonding method
JP2006131926A (ja) * 2004-11-02 2006-05-25 Sharp Corp 微細孔に対するメッキ方法、及びこれを用いた金バンプ形成方法と半導体装置の製造方法、並びに半導体装置
US8308053B2 (en) * 2005-08-31 2012-11-13 Micron Technology, Inc. Microfeature workpieces having alloyed conductive structures, and associated methods
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
KR100850212B1 (ko) * 2007-04-20 2008-08-04 삼성전자주식회사 균일한 무전해 도금 두께를 얻을 수 있는 반도체 소자의제조방법
US20100319967A1 (en) * 2007-06-28 2010-12-23 Agere Systems Inc. Inhibition of copper dissolution for lead-free soldering
JP4724192B2 (ja) * 2008-02-28 2011-07-13 株式会社東芝 電子部品の製造方法
US7994043B1 (en) 2008-04-24 2011-08-09 Amkor Technology, Inc. Lead free alloy bump structure and fabrication method
CN101592876B (zh) * 2008-05-30 2011-07-06 中芯国际集成电路制造(北京)有限公司 凸点下金属层和连接垫层的形成方法
US20100099250A1 (en) * 2008-10-21 2010-04-22 Samsung Electronics Co., Ltd. Methods of Forming Integrated Circuit Contact Pads Using Electroless Plating of Diffusion Barrier Layers
US8581420B2 (en) * 2010-10-18 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Under-bump metallization (UBM) structure and method of forming the same
US9142520B2 (en) * 2011-08-30 2015-09-22 Ati Technologies Ulc Methods of fabricating semiconductor chip solder structures
JP2014241320A (ja) * 2013-06-11 2014-12-25 ソニー株式会社 半導体装置、半導体装置の製造方法
KR102233334B1 (ko) 2014-04-28 2021-03-29 삼성전자주식회사 주석 도금액, 주석 도금 장치 및 상기 주석 도금액을 이용한 반도체 장치 제조 방법
KR102307062B1 (ko) 2014-11-10 2021-10-05 삼성전자주식회사 반도체 소자, 반도체 소자 패키지 및 조명 장치
CN105225977B (zh) * 2015-11-03 2018-05-04 中芯长电半导体（江阴）有限公司 一种铜柱凸块结构的制作方法
US20170197270A1 (en) * 2016-01-08 2017-07-13 Rolls-Royce Corporation Brazing titanium aluminum alloy components
CN106783756B (zh) * 2016-11-29 2019-06-04 武汉光迅科技股份有限公司 一种带金属凸点的陶瓷载片及其制作方法
WO2019086496A1 (en) 2017-10-31 2019-05-09 Koninklijke Philips N.V. Ultrasound scanner assembly

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5904555A (en) * 1998-02-02 1999-05-18 Motorola, Inc. Method for packaging a semiconductor device
US6146984A (en) * 1999-10-08 2000-11-14 Agilent Technologies Inc. Method and structure for uniform height solder bumps on a semiconductor wafer
US6638847B1 (en) * 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
US6750133B2 (en) * 2002-10-24 2004-06-15 Intel Corporation Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009524928A (ja) * 2006-02-20 2009-07-02 ネペス コーポレーション 金属間化合物の成長を抑制したはんだバンプが形成された半導体チップ及びはんだバンプの製造方法
US8242597B2 (en) 2008-08-29 2012-08-14 Kabushiki Kaisha Toshiba Crystal structure of a solder bump of flip chip semiconductor device
US8922008B2 (en) 2012-05-07 2014-12-30 Samsung Electronics Co., Ltd. Bump structure, having concave lateral sides, semiconductor package having the bump structure, and method of forming the bump structure

Also Published As

Publication number Publication date
US20040121267A1 (en) 2004-06-24
CN1509838A (zh) 2004-07-07
CN1254862C (zh) 2006-05-03

Similar Documents

Publication Publication Date Title
JP2004207685A (ja) 無鉛ソルダバンプの製造方法
US7391112B2 (en) Capping copper bumps
JP4195886B2 (ja) 無鉛はんだを用い反応バリア層を有するフリップ・チップ用相互接続構造を形成するための方法
US7547623B2 (en) Methods of forming lead free solder bumps
US8580621B2 (en) Solder interconnect by addition of copper
US6622907B2 (en) Sacrificial seed layer process for forming C4 solder bumps
CN100416784C (zh) 形成无铅凸点互连的方法
US6281106B1 (en) Method of solder bumping a circuit component
US7932169B2 (en) Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers
TWI431702B (zh) 半導體元件及其形成方法
EP1766673A1 (en) Methods of forming lead free solder bumps and related structures
CN111052362A (zh) 合金扩散阻挡层
US6617237B1 (en) Lead-free bump fabrication process
TWI242866B (en) Process of forming lead-free bumps on electronic component
US8252677B2 (en) Method of forming solder bumps on substrates
KR100534108B1 (ko) 무연 솔더범프 제조 방법
JP3916850B2 (ja) 半導体装置
TWI313051B (en) Method and structure to enhance height of solder ball
TWI353030B (en) Tin processing method for surfaces of copper pads
WO2001063668A2 (en) Method of forming lead-free solder alloys by electrochemical deposition process

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20051024

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20051101

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060201

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20060228