CN101044613A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN101044613A
CN101044613A CNA2006800010558A CN200680001055A CN101044613A CN 101044613 A CN101044613 A CN 101044613A CN A2006800010558 A CNA2006800010558 A CN A2006800010558A CN 200680001055 A CN200680001055 A CN 200680001055A CN 101044613 A CN101044613 A CN 101044613A
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有田洁
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Abstract

一种制造半导体芯片的方法，该方法是通过从半导体晶片切割单个半导体器件而进行的，利用研磨头机械掩膜为等离子体切割而形成的掩膜，在等离子体切割中，通过进行等离子体蚀刻分割半导体晶片。于是，通过利用机械研磨去除用于等离子体切割的掩膜，防止了在去除掩膜时产生反应产物，使得切割可以在不会由于积累颗粒而导致质量下降的情况下进行。

Description

半导体器件的制造方法
技术领域
本发明涉及通过从形成半导体器件的半导体晶片中切分单个半导体器件来制造半导体芯片的方法。
背景技术
安装在电子装置等的电路板上的半导体芯片是通过将半导体期间从其中形成电路图案的晶片状态切分成单独的片而制造的。伴随着半导体期间厚度减小带来的操纵晶片状态的半导体期间的难度增加，近年来已经采用了等离子体切割，在这种情况下，将半导体晶片切分成单独的半导体芯片是通过等离子体蚀刻来进行的(例如，参见JP-A-2004-172364专利申请公开说明书)。
等离子体切割是通过在除了网格图案的显示分割位置的分割线(streetline)外，半导体晶片掩盖有抗蚀膜的掩膜的情况下进行的，使得半导体晶片沿着该分割线切割。在切割后，为了去掉掩膜，在与JP-A-2004-172364专利申请公开说明书的现有技术中进行等离子体切割相同的等离子体处理设备中进行等离子体灰化(ashing)来去掉掩膜。
但是，在等离子体灰化时，在去除掩膜过程中产生的反应产物扩散成颗粒，并积累在等离子体处理设备内部。于是，在相同的等离子体处理设备中反复执行切割过程和灰化过程的情况下，会由于半导体晶片被等离子体处理设备中积累的颗粒污染导致切割过程的质量下降。
发明内容
鉴于上述情形，提出本发明，本发明的目的是提供一种半导体芯片的制造方法，其中，切割可以在不由于积累的颗粒导致质量下降的情况下进行。
上述目的通过这样一种制造半导体芯片的方法来实现，该方法通过从半导体晶片切割单独的半导体期间来完成，在半导体晶片中，半导体期间分别形成在由切割线分隔的多个区域内，所述方法包括以下步骤：
将能够剥离的保护带粘贴到半导体晶片的半导体器件形成表面上的保护带粘贴步骤；
研磨与半导体晶片中的粘贴有保护带的表面相对的后表面以便减薄半导体晶片的后表面研磨步骤；
在后表面掩膜步骤之后形成覆盖半导体晶片的后表面上的多个区域的掩膜形成步骤；
通过从半导体晶片上形成掩膜的一侧产生等离子体来去除半导体晶片上未被掩膜覆盖的部分，将半导体晶片切成多个半导体芯片的等离子体切割步骤，其中，每个所述半导体芯片对应于单个半导体器件；
在等离子体切割步骤之后通过研磨形成掩膜的后表面来去除掩膜的掩膜去除步骤；
去除在掩膜去除步骤中形成在后表面上的损坏层的损坏层去除步骤；以及
从切成的半导体芯片上解脱保护带的带解脱步骤。
根据本发明，通过利用机械研磨去除用于等离子体切割的掩膜，防止了在去除掩膜时产生反应产物，使得可以在不由于积累的颗粒导致质量下降的情况下进行切割。
附图说明
图1是示出根据本发明一个优选实施例的半导体芯片制造方法的流程图；
图2A到2F是示出根据本发明实施例的半导体芯片的制造方法的过程的解释图；
图3是示出根据本发明实施例的半导体芯片制造方法的过程的解释图；
图4是示出根据本发明实施例的半导体芯片制造方法的过程的解释图；
图5是示出根据本发明实施例的半导体芯片制造方法的过程的解释图；
图6是示出根据本发明实施例的半导体芯片制造方法的过程的解释图。
具体实施方式
现在，将参照附图详细描述本发明的优选实施例。图1是示出根据本发明一个优选实施例的半导体芯片制造方法的流程图。图2A到2F、3、4、5和6是示出根据本发明实施例的半导体芯片制造方法的过程的解释图。
参照图1和2A到2F，将描述半导体的制造方法。这个制造方法是通过从半导体晶片切割单个半导体器件而进行的，在所述半导体晶片中，半导体器件分别形成在由切割线分隔的多个区域内。
在图1中，首先执行保护带粘贴步骤，在该步骤中，在机械研磨中用于保护的带粘贴到半导体晶片上(ST1)。即，如图2A所示，能够被剥离的保护带2粘贴到半导体晶片1的半导体器件形成面1a上。随后，执行背面研磨步骤(ST2)。即，如图3所示，半导体晶片1以保护带2的侧面位于下表面上的姿态放置在卡紧台(chuck table)6上。然后，其上粘贴保护带2的半导体晶片1的背面的一侧被研磨头7研磨，使得半导体晶片1被减薄。结果，最初厚度大约750μm的半导体晶片1被减薄到厚度t(大约60μm)，如图2B所示。
接着，执行掩膜形成步骤(ST3)。即，在背面研磨步骤之后，厚度大约5～20μm的抗蚀膜借助于旋涂等通过树脂薄膜粘贴或树脂施加形成在机械研磨的表面上。通过诸如光刻法或激光处理等，仅除去抗蚀膜中对应于分隔单个半导体芯片的切割线的部分。结果，如图2C所示，用于等离子体切割的掩膜，即，被切割线3分隔的掩膜3形成在半导体晶片1的背面上。
随后，执行等离子体切割步骤(ST4)。图4示出了在等离子体切割步骤中使用的干蚀刻设备10的结构。在图4中，在真空腔11的内侧，提供处理室12，在减小压力的条件下进行等离子体处理。通过驱动抽真空装置15，处理室12的内侧可以减压到进行等离子体处理的压力。提供高频电极13和簇射电极(shower electrode)14，使得它们在处理室12内侧彼此相对。在高频电极13的上表面上，作为处理对象的半导体晶片1放置成保护带的侧面位于下表面上而掩膜3的侧面位于上表面上的姿态。
高频电极13电连接到高频电源16。簇射电极14接地到接地部分18。通过驱动高频电源16，高频电压施加在高频电极13和簇射电极14之间。在簇射电极14的下表面上形成多个气体喷射口14a。气体喷射口14a连接到供气部分17，该供气部分17提供用于等离子体处理的氟气。
在等离子体处理时，半导体晶片1放置在高频电极13上。然后，用于产生等离子体的氟气(在这个实施例中，为混合气体，其中，六氟化硫SF6与氦气混合)被吹到处理室12内的半导体晶片1上，同时处理室12被抽真空装置15抽真空。在这个状态下，高频电压施加到高频电极13和簇射电极14之间。结果，通过等离子体产生，而从氟气中产生氟原子团(radical)和离子，并且通过氟原子团的化学作用和加速离子的物理作用执行等离子体切割。
换句话说，通过从上侧向半导体晶片1产生氟气的等离子体，如图3D所示，在半导体晶片1上没有被掩膜3覆盖的切割线3a的部分被氟原子团的化学作用和加速离子的物理作用去除。然后，通过穿过半导体晶片1的整个厚度形成切割沟槽1c，半导体晶片1被分成半导体芯片1d，每个半导体芯片1d对应于单个半导体器件。
随后，执行背面研磨步骤(ST5)。即，如图5所示，其上粘贴被分成单片的半导体芯片1d的保护带2被放置在卡紧台25上，而半导体芯片1d上的掩膜3被研磨头26机械去除，使得半导体芯片1d形成为大约55μm的厚度。此时，半导体芯片1d还与掩膜3一起被局部研磨，使得在半导体芯片1d的上表面上形成损坏层1e。
接着，执行应力释放操作，来去除机械研磨的表面1e上的损坏层(ST6)。如图6所示，在背面研磨除去掩膜之后，粘贴在保护带2上的半导体芯片1d再次被容纳在干蚀刻设备10中，并且在损坏层1e上进行通过氟气的等离子体蚀刻。结果，如图2E所示，除掉了在去除掩膜之后仍保留在半导体芯片1d上表面上的损坏层1e，并且半导体芯片1d被减薄到大约50μm。
即，在应力释放操作中，通过在从其去除了掩膜3的半导体芯片1d的背面上进行等离子体蚀刻，形成在这些背面上的损坏层被去除。顺便提及，在这个损坏层去除步骤中，取代进行等离子体蚀刻，可以进行其他方法，如干抛光、化学抛光和湿蚀刻等。但是，通过利用进行等离子体切割的相同的干蚀刻设备10，可以在不增加设备成本的情况下进行应力释放。
此后，进行保护带的释放(ST2)。即，如图2F所示，被粘贴在保护带2上的半导体芯片1d被传送到切割片3，该切割片4被晶片环(waferring)5膨胀。然后，被粘贴在切割片4上的半导体芯片1d，保护带从被分隔的半导体芯片1d上释放。结果，半导体芯片1d处于被切割片4保持的状态，半导体器件形成面1a向上。
如上所述，在根据本发明一个实施例的半导体芯片制造方法中，形成在半导体晶片上的用于等离子体切割的掩膜通过机械研磨去除。通过这个特征，可以防止通过等离子体灰化去除掩膜时不可避免地产生的反应产物的出现。因此，反应产物不会积累在等离子体处理设备中，使得可以在不会由于积累的颗粒而导致质量下降的情况下进行切割。
工业应用性
根据本发明的半导体器件制造方法优点在于：通过放置去除掩膜时产生反应产物，切割可以在不会由于积累颗粒而导致质量下降的情况下进行，因此，在通过从其中形成半导体器件的半导体晶片切割单个半导体器件来制造半导体芯片的领域中大有可为。

Claims (2)

1.一种制造半导体芯片的方法，该方法通过从半导体晶片中切割单个半导体器件而进行，在该半导体晶片中，半导体器件分别形成在有切割线分隔的多个区域内，所述方法包括以下步骤：
保护带粘贴步骤：能够被剥离的保护带粘贴到半导体晶片的半导体器件形成面上；
背面研磨步骤：研磨半导体晶片中的与其上粘贴保护带的表面相对的背面，以便减薄半导体晶片；
掩膜形成步骤：在背面掩膜步骤之后，在半导体晶片的背面上形成覆盖所述多个区域的掩膜；
等离子体切割步骤：通过从其上形成掩膜的半导体晶片一侧产生等离子体，以去除半导体晶片中的没有被掩膜覆盖的部分，将半导体晶片切割成多个半导体芯片，每个半导体芯片对应于单个半导体器件；
掩膜去除步骤：在等离子体切割步骤之后，通过研磨其上形成掩膜的背面来去除掩膜；
损坏层去除步骤：去除在掩膜去除步骤中形成在所述背面上的损坏层；以及
带释放步骤：从切割的半导体芯片上释放保护带。
2.如权利要求1所述的半导体器件制造方法，其中，在损坏层去除步骤中，形成在背面上的损坏层是通过等离子体蚀刻去除的。
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