CN100524783C - 一种半导体结构及其制造方法 - Google Patents
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Abstract
本发明提供一种半导体结构,包括:具有SOI区域和块Si区域的衬底,其中SOI区域和块Si区域具有相同或者不同的晶体取向;将SOI区域与块Si区域分离的隔离区域;以及位于SOI区域中的至少一个第一器件和位于块Si区域中的至少一个第二器件。SOI区域具有在绝缘层之上的硅层。块Si区域还包括在第二器件下方的阱区域和到阱区域的接触,其中该接触稳定浮体效应。阱接触也用来控制块Si区域中FET的阈值电压以优化从SOI和块Si区域FET的组合中构建的电路的功率和性能。
Description
技术领域
本发明涉及半导体器件,并且更特别地涉及形成于具有薄的绝缘体上硅(SOI)和块Si部分的衬底之上的集成半导体器件,比如互补金属氧化物半导体(CMOS)器件,其中衬底的SOI和块Si部分具有相同或者不同的晶体取向。特别地,本发明在半导体衬底的SOI和块Si区域上形成nFET和pFET器件,该半导体衬底具有在(100)、(110)或者(111)晶体平面上的表面。处理衬底的块Si区域以提供基本上无浮体效应的器件,该浮体效应通常出现在以SOI为衬底形成的器件中。此外,在块区域中能够利用阱接触来控制块nFET和pFET器件的阈值电压(Vt)以改进电路功率和性能。
背景技术
绝缘体上硅(SOI)器件提供相较于更多常规半导体器件而言的数项优点。例如,SOI器件可以具有比执行相似任务的其它类型的器件更低的功率消耗要求。SOI器件也可以具有比非SOI器件更低的寄生电容。这转换成所得电路的更快开关时间。此外,当使用SOI制作工艺来制造电路器件时可以避免互补金属氧化物半导体(CMOS)器件常常表现出的“闩锁(latchup)”现象。SOI器件对于电离辐射的不利效应也不那么敏感,因此往往在电离辐射可能造成操作错误的应用中更可靠。
随着CMOS技术缩小到90nm节点以及更小,芯片功率和性能的优化变得越来越有挑战性。在常规块CMOS中利用的一种技术是自适应阱偏置。例如J.Tschanz等人在2002年的Solid State Circuits第1396页中公开了该自适应阱偏置技术。这一技术涉及到在nFET阱或者体(p-阱)节点、pFET阱或者体(n-阱)节点和电源(Vdd)节点上改变和选择最优偏置以在每芯片的基础上最大化功率和性能。在SOI CMOS中,这一技术由于阱节点(体)漂浮而不可用。在原理上,可以在SOI CMOS中利用体连结(body tie)结构以向浮体节点添加接触。然而,体连结结构的使用引入寄生电阻和电容,这些寄生电阻和电容将消除自适应阱偏置的有利影响。
一种近来革新的混合取向CMOS技术(HOT)使用SOI nFET和pFET以及常规块nFET和pFET。例如M.Yang等人在2003年的IEDM第453页以及标题为High-Performance CMOS Devices on HybridCrystal Oriented Substrates的美国公开第2004 0256700A1(2004)号中描述了该HOT技术。此外,相同或者不同的晶体取向能够用于nFET和pFET器件。不同晶体取向的使用允许独立地优化nFET(在硅中的nFET在(100)取向中具有最高的迁移率和性能)和pFET(在硅中的pFET在(110)取向中具有最高的迁移率和性能)的性能。此外在本领域中已知在(110)晶体平面之上形成的nFET器件具有降低的载流子迁移率和开关速度。
因此需要提供如下集成半导体器件,在该集成半导体器件中利用HOT衬底和自适应阱偏置二者来提供具有功率和性能增强的结构。
发明内容
本发明提供一种半导体结构,包括将在具有能够部分或者完全耗尽电荷载流子的器件沟道的SOI衬底区域上的场效应晶体管(FET)与在基本上消除浮体效应的高度掺杂阱体接触的块Si区域内的FET相组合,并且提供用以使用自适应阱偏置的手段,由此提供用以利用在阱端上的施加偏置来控制块Si区域FET的阈值电压的手段。
具体而言,本发明组合了M.Yang等人在2003年的IEDM第453页中公开的HOT结构的修改,由此针对一个器件类型而产生和接触高度掺杂阱。这提供了然后用于为常规块CMOS区域中设置的器件施加偏置以实施自适应阱偏置技术的手段。此外由于阱是单极的,所以对于实施自适应阱偏置而言没有阱到阱的泄漏或者不利电容,这是相较于用于自适应阱偏置的常规块CMOS方案而言的主要优点。
广而言之,本发明提供一种半导体结构,该半导体结构包括:
包括SOI区域和块Si区域的衬底,其中所述SOI区域和所述块Si区域具有相同或者不同的晶体取向;
将所述SOI区域与所述块Si区域分离的隔离区域;
位于所述SOI区域中的至少一个第一器件和位于所述块Si区域中的至少一个第二器件;以及
位于所述至少一个第二器件下方的阱区域和到所述阱区域的接触,其中所述接触稳定浮体效应并且提供用于通过施加偏置电压来调节所述块Si区域中场效应晶体管(FET)内阈值电压的手段。
根据本发明,衬底的SOI区域包括具有如下厚度的SOI层,该厚度在器件被正向偏置时能够完全或者部分耗尽电荷载流子。SOI区域可以包括至少一个nFET器件、至少一个pFET器件或者其组合。块Si区域可以包括至少一个nFET、pFET、电阻器、电容器、二极管或者其组合。
能够通过利用一种包括晶片键合、掩模、蚀刻以及半导体层再生长的方法来提供上述结构。具体而言,本发明的方法包括以下步骤:提供衬底,该衬底至少包括通过绝缘层来分离的第一半导体层和第二半导体层,所述第一半导体层和所述第二半导体层具有相同或者不同的晶体取向;保护衬底的一部分以限定SOI区域,而留下衬底的另一部分不受保护,衬底的所述不受保护的部分限定块Si区域;蚀刻衬底的所述不受保护的部分以暴露第二半导体层的表面;在第二半导体层的所述暴露的表面上再生长半导体材料,所述半导体材料具有所述相同的晶体取向;平坦化包含所述半导体材料的衬底,使得第一半导体层的上表面与半导体材料的上表面基本上共面;以及在所述SOI区域中形成至少一个第一器件,而在所述块Si区域中在所述半导体材料上形成至少一个第二器件。
根据本发明,能够通过如下步骤来形成在块Si区域中的第二器件:以第一类型的掺杂剂注入块Si区域以提供阱区域;在块Si区域的表面之上形成至少一个栅极区域;以第二类型的掺杂剂形成与至少一个栅极区域相邻的源极和漏极区域;以及形成到阱区域的接触,其中该接触稳定浮体效应并且提供可以用来调节块Si区域中器件阈值电压的阱接触。形成到阱区域的接触包括:蚀刻块Si区域的表面的一部分以提供到阱区域的过孔;以及以导电材料填充到阱区域的过孔。
附图说明
图1A-1F是图示了在形成CMOS器件中使用的基本处理步骤的表示图(横截面图),该CMOS器件包含具有体接触的高性能SOI沟道MOSFET半导体器件。
图2A-2C是可以键合在一起并且在图1A-1F中描述的方法中使用的各种晶片的表示图。
具体实施方式
现在通过参照以下讨论以及本申请的附图来更具体地描述提供一种用于自适应阱偏置和功率/性能增强的混合晶体取向CMOS结构的本发明。在附图中,相似的和对应的元件通过相同的标号来指代。注意到出于说明的目的而提供本发明的附图,因此这些附图没有按比例绘制。
图1A图示了可以在本发明中利用的衬底10即混合衬底。如图所示,衬底10包括表面电介质层18、第一半导体层16、绝缘层14和第二半导体层12。
衬底10的表面电介质层18是通过热工艺(即氧化、氮化或者氮氧化)或者通过沉积而在键合之前存在于初始晶片之一中或者在晶片键合之后形成在第一半导体层16之上的氧化物、氮化物、氮氧化物或者其它绝缘层。无论表面电介质层18的来源如何,表面电介质层18都具有从约3nm到约500nm的厚度,其中从约5nm到约20nm的厚度更为典型。
第一半导体层16包括任何半导体材料,该半导体材料例如包括Si、SiC、SiGe、SiGeC、Ge合金、GaAs、InAs、InP以及其它III-V或者II-VI族化合物半导体。第一半导体层16也可以包括预形成的SOI衬底的SOI层或者分层的半导体例如Si/SiGe。在本发明的一个优选实施例中,第一半导体层16是含Si半导体材料。第一半导体层16具有与第二半导体层12相同或者不同的晶体取向,优选地在(100)晶体平面中。虽然优选(100)晶体取向,但是第一半导体层16可以具有(111)晶体平面、(110)晶体平面或者其它晶体平面,只要第一半导体层16不是如下含Si材料,该含Si材料随后被处理以在(110)晶体平面上提供nFET器件。
第一半导体层16的厚度可以根据用来形成衬底10的初始晶片而变化。然而通常第一半导体层16具有从约5nm到约100nm的初始厚度,该厚度然后变薄为少于40nm的厚度。通过平坦化、研磨、湿蚀刻、干蚀刻或者其任何组合来使第一半导体层16变薄。在优选实施例中,通过氧化和湿蚀刻来使第一半导体层16变薄以实现所需厚度从而针对本发明的目的来提供薄的绝缘体上硅衬底的上部含Si层。
位于第一半导体层16与第二半导体层12之间的绝缘层14具有视用来产生衬底10的初始晶片而定的可变厚度。然而通常绝缘层14具有从约1nm到约500nm的厚度,其中从约1nm到约100nm的厚度更为典型。绝缘层14是在键合之前形成于一个或者两个晶片上的氧化物或者其它相似的绝缘体材料。
第二半导体层12包括可以与第一半导体层16相同或者不同的任何半导体材料。因此,第二半导体层12可以包括例如Si、SiC、SiGe、SiGeC、Ge合金、GaAs、InAs、InP以及其它III-V或者II-VI族化合物半导体。第二半导体层12也可以包括预形成的SOI衬底的SOI层或者分层的半导体例如Si/SiGe。在本发明的非常优选实施例中,第二半导体层12包括含Si半导体材料。第二半导体层12具有与第一半导体层16相同或者不同的晶体取向,该晶体取向优选地在(100)晶体平面中。虽然优选(100)晶体取向,但是第二半导体层12可以具有(111)晶体平面、(110)晶体平面或者其它晶体平面,只要第二半导体层12不是如下含Si材料,该含Si材料随后被处理以在(110)晶体平面上提供nFET器件。
第二半导体层12的厚度可以根据用来形成衬底10的初始晶片而变化。然而通常第二半导体层12具有从约5nm到约200nm的厚度,其中从约5nm到约100nm的厚度更为典型。
图1A中所示衬底10包括键合在一起的两个半导体晶片。在制作衬底10中使用的两个晶片可以包括:两个SOI晶片(见图2A),其中表示为1的一个晶片包括第一半导体层16,而表示为2的另一晶片包括第二半导体层12;SOI晶片(表示为2)和块半导体晶片(表示为1;见图2B);或者SOI晶片(表示为2)和块晶片(表示为1),该块晶片包括离子注入区域11,比如H2注入区域,该注入区域可以用来在键合过程中***至少一个晶片的一部分。
通过先使两个晶片相互紧密接触、可选地将外力施加到接触的晶片、然后在能够将两个晶片键合在一起的条件之下加热两个接触的晶片来实现键合。可以在有外力或者没有外力时执行加热步骤。典型地在从约2小时至20小时的时间段中在从约200℃至约1050℃的温度下在惰性氛围中执行加热步骤。更典型地在从约2小时至20小时的时间段中在从约200℃至约400℃的温度下执行键合。术语“惰性氛围”在本发明中用来表示其中利用惰性气体如He、Ar、N2、Xe、Kr或者其混合物的环境。在键合过程中使用的优选氛围是N2。
在利用两个SOI晶片的实施例中,可以利用平坦化工艺如化学机械抛光(CMP)或者研磨和蚀刻,在键合之后去除至少一个SOI晶片的一些材料层。平坦化工艺在达到表面电介质层18时停止。在其中一个晶片包括离子注入区域的实施例中,离子注入区域在键合过程中形成有孔区域,该有孔区域使晶片在离子注入区域以上的部分脱离,留下例如在图1A中示出的键合晶片。注入区域通常包括H2离子,其中利用本领域技术人员公知的离子注入条件将这些离子注入到晶片的表面中。
在待键合的晶片中不含电介质层的实施例中,可以通过热工艺如氧化或者通过常规沉积工艺如化学气相沉积(CVD)、等离子增强CVD、原子层沉积、化学溶液沉积以及其它相似的沉积工艺在键合晶片之上形成表面电介质层18。
现在参照图1B,然后在图1A的衬底10的预定部分上形成掩模20以便保护衬底10的一部分而留下衬底10的另一部分不受保护。衬底10中受保护的部分限定了衬底的SOI区域22,而衬底10中不受保护的部分限定了块Si区域24。在一个实施例中,通过将光刻胶掩模施加到衬底10的整个表面而在表面电介质层18的预定部分上形成掩模20。在施加光刻胶掩模之后,通过光刻来对掩模进行构图,该光刻包括将光刻胶暴露于辐射图案以及利用抗蚀显影剂对图案进行显影这些步骤。例如在图1B中示出了包括在衬底10的预定部分上形成的掩模20的所得结构。
在另一实施例中,掩模20是利用光刻和蚀刻来形成和构图的氮化物或者氮氧化物层。可以在限定衬底10的块Si区域24之后去除氮化物或者氮氧化物掩模20。
在衬底10之上形成掩模20之后,对该结构进行一个或者多个蚀刻步骤以便暴露第二半导体层12的表面。具体而言,在本发明的这一点使用的一个或者多个蚀刻步骤去除了表面电介质层18中不受保护的部分以及下方的第一半导体层16的部分和将第一半导体层16与第二半导体层12分离的绝缘层14的部分。可以利用单个蚀刻工艺来执行蚀刻或者可以利用多个蚀刻步骤。在本发明的这一点使用的蚀刻可以包括干蚀刻工艺,比如反应离子蚀刻、离子束蚀刻、等离子蚀刻或者激光蚀刻,也可以包括其中利用化学蚀刻剂的湿蚀刻工艺,或者其任何组合。在本发明的优选实施例中,在有选择地去除块Si区域24中表面电介质层18、第一半导体层16和绝缘层14的不受保护部分时,使用反应离子蚀刻(RIE)。例如在图1C中示出了在已经执行蚀刻工艺之后的所得结构。注意到在这一蚀刻步骤之后暴露受保护的SOI区域22即表面电介质层18、第一半导体层16和绝缘层14的侧壁。如图所示,层18、16和14的暴露侧壁与掩模20的最外沿对准。
然后利用常规抗蚀剂剥离工艺从图1C中所示结构中去除掩模20,然后通常但并非总是在暴露侧壁上形成衬垫或者间隔物25。通过沉积和蚀刻来形成可选的衬垫或者间隔物25。衬垫或者间隔物25包括绝缘材料例如氧化物。
在形成可选的衬底或者间隔物25之后,在暴露的第二半导体层12上形成半导体材料26。根据本发明,半导体材料26具有与第二半导体层12的晶体取向相同的晶体取向。例如在图1D中示出了所得结构。
半导体材料26可以包括能够利用有选择的外延生长方法来形成的任何含Si半导体,比如Si、应变Si、SiGe、SiC、SiGeC或者其组合。在一些优选实施例中,半导体材料26包括Si。在本发明中,半导体材料26可以称为再生长半导体材料26。
接着对图1D中所示结构进行平坦化工艺如化学机械抛光(CMP)或者研磨,使得半导体材料26的上表面与第一半导体层16的上表面基本上共面。注意在这一平坦化工艺过程中去除了表面电介质层18中先前受保护的部分。
在提供基本上平坦的表面之后,通常形成隔离区域27如浅沟槽隔离区域以便将SOI区域22与块Si区域24相隔离。利用本领域技术人员公知的处理步骤来形成隔离区域27,这些步骤例如包括限定和蚀刻沟槽、可选地将沟槽与扩散阻挡层排成一行以及用沟道电介质如氧化物填充沟槽。在沟槽填充之后,可以平坦化该结构以及可以执行可选的致密化处理步骤以使沟槽电介质致密化。
例如在图1E中示出了所得的包含隔离区域27的基本上平坦的结构。如图所示,图1E的结构包括在SOI区域22内的暴露的第一半导体层16以及在块Si区域24内的再生长的半导体材料26,其中第一半导体层16和半导体材料26具有相同或者不同的晶体取向。在一个优选实施例中,层16和层26具有相同的晶体取向。在该实施例中非常优选的是层16和26具有在(100)晶体平面中的表面。
参照图1F,在下一工艺步骤中,处理SOI区域22以提供SOIMOSFET以及处理块Si区域24以提供具有基本上消除浮体效应的体接触的器件并且提供用以调节块Si区域24中FET阈值电压的手段。
在处理SOI区域22和块Si区域24之前,可以在衬底10内形成器件隔离区域27’。通过结合常规阻挡掩模来利用常规干蚀刻工艺如反应离子蚀刻(RIE)或等离子体蚀刻有选择地蚀刻衬底中的沟槽,能够提供器件隔离区域27’。器件隔离区域27’在块Si区域24和SOI区域22内提供隔离并且与将块Si区域24与SOI区域22相分离的隔离区域27相似。可选地,器件隔离区域27’可以是使用硅局部氧化工艺来形成的场隔离区域。
可以利用常规阻挡掩模技术来单独地处理SOI区域22和块Si区域24。阻挡掩模可以包括常规软和/或硬掩模材料并且能够使用沉积、光刻和蚀刻来形成。在优选实施例中,阻挡掩模包括光刻胶。能够通过将匀厚光刻胶层施加到衬底10的表面、将光刻胶层暴露于辐射图案、然后使用常规抗蚀显影剂将图案显影到光刻胶层中来产生光刻胶阻挡掩模。
可选地,阻挡掩模能够是硬掩模材料。硬掩模材料包括可以通过化学气相沉积(CVD)和有关方法来沉积的电介质。通常,硬掩模组成包括氧化硅、碳化硅、氮化硅、氮碳化硅和其它相似材料。旋涂电介质也可以用作硬掩模材料,包括但不限于硅倍半氧烷、硅氧烷和硼磷硅玻璃(BPSG)。
可以通过将p型或者n型掺杂剂有选择地注入衬底10的块Si区域24中而在成块Si区域24中形成阱区域37、38,其中如上所述衬底10的SOI区域22可以受阻挡掩模保护。在图1F中所示例子中,注入pFET块Si区域35以提供n型阱37而注入nFET块Si区域36以提供p型阱38。
也可以在SOI区域22中有选择地注入SOI层。在图1F中所示例子中,注入pFET SOI区域41以提供n型沟道区域而注入nFET SOI区域42以提供p型沟道区域。
然后能够通过先在衬底表面之上匀厚沉积栅极电介质层、然后在栅极电介质层之上沉积栅极导体层而在SOI区域22和块Si区域24内形成栅极导体堆叠28、29。栅极电介质层可以包括任何常规栅极电介质材料如SiO2或者任何高k栅极电介质材料如HfO2。栅极导体层可以包括任何导电材料如掺杂多晶硅。然后使用常规沉积、光刻和蚀刻来蚀刻栅极导体层和栅极电介质层以在衬底10的SOI区域22和块Si区域24内提供栅极导体堆叠28,29,如图1F中所示。可选地,可以使用阻挡掩模来分别在SOI区域22内提供栅极导体堆叠28而在块Si区域24内提供栅极导体堆叠29。
在图1F中所示实施例中以及在接下来的一连串工艺步骤过程中,然后在SOI区域22内有选择地形成SOI MOSFET器件,而块Si区域24受硬或者软阻挡掩模保护。例如,能够在注入之前形成构图的光刻胶所提供的阻挡掩模以在SOI区域22内为利用一个掺杂剂类型进行掺杂的栅极导体和/或源极/漏极扩散区40预先选择衬底区域。能够重复阻挡掩模施加和注入过程以利用不同的掺杂剂类型如n型或者p型掺杂剂来掺杂栅极导体堆叠28、源极/漏极扩散区域40、源极/漏极扩展区域或者晕环(halo)区域(未示出)的所选导电材料。在每次注入之后,可以使用常规光刻胶剥离化学过程来去除阻挡掩模抗蚀剂。在一个优选实施例中,可以重复构图和注入工艺步骤以提供至少一个pFET器件41和至少一个nFET器件42,其中通过隔离区域27’来分离pFET 41和nFET器件42。
在注入之前,邻近于栅极导体堆叠28形成间隔物6,其中可以调节间隔物的宽度以补偿p型和n型掺杂剂的不同扩散速率。此外,可以处理在SOI区域22内的pFET和nFET器件以提供硅化物区域或者在超薄沟道MOSFET中通常利用的任何其它常规结构。在SOI区域22内形成器件41、42之后,可以从块Si区域24剥离硬掩模,然后在衬底10的SOI区域22之上形成另一硬掩模,留下块Si区域24被暴露。
然后处理块Si区域24以在块Si衬底上提供与SOI衬底相比具有增强性能的器件。例如,可以处理块Si区域24以提供在半导体制造中通常普遍的器件,比如:电阻器;电容器,包括去耦合电容器、平面式电容器和深沟槽电容器;二极管;以及存储器器件,比如动态随机存取存储器(DRAM)和嵌入式动态随机存取存储器(eDRAM)。在优选实施例中,块Si区域24包括体接触50、51。在一个例子中,如图1F中所示,处理块Si区域24以提供具有体接触50、51的MOSFET。
在图1F中所示实施例中,处理块Si区域24以提供各具有体接触50、51的至少一个p型MOSFET 35和至少一个n型MOSFET 36,其中通过器件隔离区域27’将p型MOSFET 35与n型MOSFET 36相分离。与在SOI区域22内形成的器件相似,可以利用构图的阻挡掩模有选择地注入块Si区域24以提供p型MOSFET 35和n型MOSFET 36。
在注入之后,然后将体接触50、51形成到衬底10的块Si区域24内的至少一个器件。到块Si区域24内各MOSFET器件35、36的体接触50、51与器件的阱区域电接触并且通过隔离区域26与MOSFET的源极和漏极区域40相分离。
可以使用光刻、蚀刻和沉积来形成体接触50、51。更具体地,可以通过对衬底10中块Si区域24内的一部分进行构图并且蚀刻暴露的表面以形成到至少一个MOSFET 35、36的至少一个阱区域37、38的过孔来形成体接触50,51。蚀刻工艺可以是定向蚀刻如反应离子蚀刻。在过孔形成之后,然后通过使用常规处理如CVD或者电镀将导电材料沉积到过孔中来形成体接触50、51。在形成体接触50、51中使用的导电材料可以是掺杂多晶硅或者导电金属。导电金属可以包括但不限于钨、铜、铝、银、金及其合金。在优选实施例中,到nFET SOI器件36的体接触51是p型掺杂多晶硅而到pFET SOI器件35的体接触50是n型掺杂多晶硅。
注意到在SOI区域22内形成的器件和在衬底10的块Si区域24内形成的器件均形成于具有相同晶体取向的表面之上。在一个优选实施例中,在SOI区域22内的器件和在块Si区域24内形成的器件均形成于具有(100)晶体平面的表面上。在另一优选实施例中,在SOI区域22内的nFET和pFET器件形成于具有(100)晶体平面的表面上,而在块Si区域24内形成的pFET器件均形成于具有(110)晶体平面的表面上。在另一优选实施例中,在SOI区域22内的pFET器件形成于具有(110)晶体平面的表面上,而在块Si区域24内形成的nFET和pFET器件均形成于具有(100)晶体平面的表面上。
尽管已经参照其优选实施例特别地示出和描述了本发明,但是本领域技术人员将理解可以在不脱离本发明的精神和范围的情况下做出形式和细节上的前述以及其它变化。因此本意在于使本发明不限于描述和图示的准确形式及细节而落入所附权利要求的范围内。
Claims (29)
1.一种半导体结构,包括:
包括绝缘体上硅SOI区域和块Si区域的衬底,其中所述SOI区域和所述块Si区域具有相同或者不同的晶体取向;
将所述SOI区域与所述块Si区域分离的隔离区域;
位于所述SOI区域中的至少一个第一器件和位于所述块Si区域中的至少一个第二器件;以及
位于所述至少一个第二器件下方的阱区域和到所述阱区域的接触,
其中所述接触稳定浮体效应并且提供用于通过施加偏置电压来调节所述块Si区域中场效应晶体管FET内阈值电压的手段。
2.根据权利要求1所述的半导体结构,其中所述SOI区域包括在绝缘层之上的SOI层,其中所述SOI层具有少于40nm的厚度。
3.根据权利要求1所述的半导体结构,其中位于所述SOI区域中的所述至少一个第一器件包括至少一个nFET器件、至少一个pFET器件或者其组合。
4.根据权利要求1所述的半导体结构,其中位于所述块Si区域中的所述至少一个第二器件包括至少一个nFET、pFET、电阻器、电容器、二极管或者其组合。
5.根据权利要求1所述的半导体结构,其中所述相同的晶体取向是(100)、(110)或者(111)。
6.根据权利要求1所述的半导体结构,其中所述不同的晶体取向包括(100)、(110)或者(111)。
7.根据权利要求1所述的半导体结构,其中所述块Si层和所述SOI层包括从Si、SiGe、SiC、SiGeC和其组合组成的组中选择的相同或者不同的含硅材料。
8.根据权利要求1所述的半导体结构,其中所述块Si层和所述SOI层包括从应变Si、应变SiGe、SiC、SiGeC和其组合组成的组中选择的相同或者不同的含硅材料。
9.一种半导体结构,包括:
包括绝缘体上硅SOI区域和块Si区域的衬底,其中所述SOI区域和所述块Si区域具有相同的晶体取向;
将所述SOI区域与所述块Si区域分离的隔离区域;
位于所述SOI区域中的至少一个第一器件和位于所述块Si区域中的至少一个第二器件;以及
位于所述至少一个第二器件下方的阱区域和到所述阱区域的接触,
其中所述接触稳定浮体效应并且提供用于通过施加偏置电压来调节所述块Si区域中场效应晶体管FET内阈值电压的手段。
10.根据权利要求9所述的半导体结构,其中所述SOI区域包括在绝缘层之上的SOI层,其中所述SOI层具有少于40nm的厚度。
11.根据权利要求9所述的半导体结构,其中位于所述SOI区域中的所述至少一个第一器件包括至少一个nFET器件、至少一个pFET器件或者其组合。
12.根据权利要求9所述的半导体结构,其中位于所述块Si区域中的所述至少一个第二器件包括至少一个nFET、pFET、电阻器、电容器、二极管或者其组合。
13.根据权利要求9所述的半导体结构,其中所述相同的晶体取向是(100)、(110)或者(111)。
14.根据权利要求9所述的半导体结构,其中所述块Si层和所述SOI层包括从Si、SiGe、SiC、SiGeC和其组合组成的组中选择的相同或者不同的含硅材料。
15.根据权利要求9所述的半导体结构,其中所述块Si层和所述SOI层包括从应变Si、应变SiGe、SiC、SiGeC和其组合组成的组中选择的相同或者不同的含硅材料。
16.一种形成半导体结构的方法,包括:
提供衬底,所述衬底至少包括通过绝缘层来分离的第一半导体层和第二半导体层,所述第一半导体层和所述第二半导体层具有相同或者不同的晶体取向;
保护所述衬底的一部分以限定绝缘体上硅SOI区域,而留下所述衬底的另一部分不受保护,所述衬底的所述不受保护的部分限定块Si区域;
蚀刻所述衬底的所述不受保护的部分以暴露所述第二半导体层的表面;
在所述第二半导体层的所述暴露的表面上再生长半导体材料,所述半导体材料具有所述相同的晶体取向;
平坦化包含所述半导体材料的所述衬底,使得所述第一半导体层的上表面与所述半导体材料的上表面共面;以及
在所述SOI区域中形成至少一个第一器件,而在所述块Si区域中在所述半导体材料上形成至少一个第二器件,其中所述在所述块Si区域中形成至少一个第二器件包括:以第一掺杂剂注入所述块Si区域以提供阱区域;在所述块Si区域的表面之上形成至少一个栅极区域;以第二类型的掺杂剂形成与所述至少一个栅极区域相邻的源极和漏极区域;以及形成到所述阱区域的接触,其中所述接触稳定浮体效应。
17.根据权利要求16所述的方法,其中所述第一半导体层具有少于40nm的厚度。
18.根据权利要求16所述的方法,其中形成到所述阱区域的所述接触包括:蚀刻所述块Si区域的所述表面的一部分以提供到所述阱区域的过孔;以及以导电材料填充到所述阱区域的所述过孔。
19.根据权利要求16所述的方法,其中所述在所述块Si区域内形成所述至少一个第二器件还包括提供电容器、电阻器、二极管或者其组合。
20.根据权利要求16所述的方法,其中在所述SOI区域内的所述至少一个器件包括nFET、pFET或者其组合。
21.根据权利要求16所述的方法,其中由两个SOI晶片、SOI晶片和块半导体晶片、两个块半导体晶片或者SOI晶片和包含在加热之后形成空穴的离子注入区域的块半导体晶片来形成所述衬底,其中通过使两个晶片相互紧密接触以及在惰性氛围中加热所述接触的晶片来形成所述衬底。
22.根据权利要求16所述的方法,其中利用有选择的外延生长方法来形成所述半导体材料,所述半导体材料是从Si、SiGe、SiC、SiGeC和其组合组成的组中选择的含硅半导体。
23.根据权利要求16所述的方法,其中利用有选择的外延生长方法来形成所述半导体材料,所述半导体材料是从应变Si、SiGe、SiC、SiGeC和其组合组成的组中选择的含硅半导体。
24.根据权利要求16所述的方法,其中所述第一半导体层和所述第二半导体材料包括相同或者不同的含Si材料,其中所述含Si材料是从Si、SiGe、SiC、SiGeC和其组合组成的组中选择的。
25.根据权利要求16所述的方法,其中所述第一半导体层和所述第二半导体材料包括相同或者不同的含Si材料,其中所述含Si材料是从应变Si、SiGe、SiC、SiGeC和其组合组成的组中选择的。
26.根据权利要求16所述的方法,还包括:在蚀刻之后但是在形成至少一个半导体器件之前形成隔离区域。
27.根据权利要求16所述的方法,其中所述相同的晶体取向是(100)或者(111)。
28.根据权利要求16所述的方法,其中所述不同的晶体取向包括(100)、(110)或者(111)。
29.根据权利要求16所述的方法,其中通过氧化和湿蚀刻使所述第一半导体层变薄。
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US9786606B2 (en) | 2014-05-28 | 2017-10-10 | Globalfoundries Inc. | Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method |
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WO2006113077A3 (en) | 2007-04-12 |
TW200636909A (en) | 2006-10-16 |
US20080009114A1 (en) | 2008-01-10 |
JP2008536335A (ja) | 2008-09-04 |
WO2006113077A2 (en) | 2006-10-26 |
US20060231893A1 (en) | 2006-10-19 |
EP1875507A4 (en) | 2009-08-05 |
CN101147259A (zh) | 2008-03-19 |
EP1875507A2 (en) | 2008-01-09 |
US7605429B2 (en) | 2009-10-20 |
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