CN100456386C - 半导体存储器 - Google Patents
半导体存储器 Download PDFInfo
- Publication number
- CN100456386C CN100456386C CNB2005100017662A CN200510001766A CN100456386C CN 100456386 C CN100456386 C CN 100456386C CN B2005100017662 A CNB2005100017662 A CN B2005100017662A CN 200510001766 A CN200510001766 A CN 200510001766A CN 100456386 C CN100456386 C CN 100456386C
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- CN
- China
- Prior art keywords
- signal
- address
- input buffer
- latch
- chip enable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 230000007704 transition Effects 0.000 claims abstract description 4
- 230000015654 memory Effects 0.000 claims description 51
- 230000004044 response Effects 0.000 claims description 11
- 230000003111 delayed effect Effects 0.000 abstract description 2
- 230000007257 malfunction Effects 0.000 abstract 1
- 230000001360 synchronised effect Effects 0.000 description 16
- 230000000630 rising effect Effects 0.000 description 14
- 230000004913 activation Effects 0.000 description 11
- 230000014759 maintenance of location Effects 0.000 description 7
- 230000008859 change Effects 0.000 description 4
- 230000003213 activating effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 108010032595 Antibody Binding Sites Proteins 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/225—Clock input buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/406—Refreshing of dynamic cells
- G11C2211/4067—Refresh in standby or low power modes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
Abstract
Description
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004150561A JP4717373B2 (ja) | 2004-05-20 | 2004-05-20 | 半導体メモリ |
JP150561/2004 | 2004-05-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1700350A CN1700350A (zh) | 2005-11-23 |
CN100456386C true CN100456386C (zh) | 2009-01-28 |
Family
ID=35476350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100017662A Expired - Fee Related CN100456386C (zh) | 2004-05-20 | 2005-01-19 | 半导体存储器 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7002875B2 (zh) |
JP (1) | JP4717373B2 (zh) |
KR (1) | KR100615413B1 (zh) |
CN (1) | CN100456386C (zh) |
TW (1) | TWI282983B (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008072649A1 (ja) * | 2006-12-12 | 2008-06-19 | Nec Corporation | 論理回路とアドレスデコーダ回路及び半導体記憶装置 |
KR100924356B1 (ko) | 2008-06-05 | 2009-11-02 | 주식회사 하이닉스반도체 | 커맨드 디코더 및 커맨드 신호 생성회로 |
US8000165B2 (en) * | 2008-09-09 | 2011-08-16 | Qualcomm Incorporated | Self reset clock buffer in memory devices |
US7894290B2 (en) * | 2008-10-22 | 2011-02-22 | Qimonda Ag | Method and apparatus for performing internal hidden refreshes while latching read/write commands, address and data information for later operation |
KR101136936B1 (ko) * | 2009-10-26 | 2012-04-20 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 동작방법 |
KR101789077B1 (ko) * | 2010-02-23 | 2017-11-20 | 삼성전자주식회사 | 온-다이 터미네이션 회로, 데이터 출력 버퍼, 반도체 메모리 장치, 메모리 모듈, 온-다이 터미네이션 회로의 구동 방법, 데이터 출력 버퍼의 구동 방법 및 온-다이 터미네이션 트레이닝 방법 |
JP4988048B1 (ja) * | 2011-02-14 | 2012-08-01 | 株式会社東芝 | 半導体記憶装置 |
KR20130050852A (ko) * | 2011-11-08 | 2013-05-16 | 에스케이하이닉스 주식회사 | 어드레스 디코딩 방법과 이를 이용한 반도체 메모리 장치 |
US9992010B2 (en) * | 2015-11-24 | 2018-06-05 | The Charles Stark Draper Laboratory, Inc. | System and method for augmenting duplexed replicated computing |
KR20190001097A (ko) * | 2017-06-26 | 2019-01-04 | 에스케이하이닉스 주식회사 | 어드레스 제어회로 및 이를 포함하는 반도체 장치 |
KR20190024205A (ko) * | 2017-08-31 | 2019-03-08 | 에스케이하이닉스 주식회사 | 링 오실레이터를 포함하는 메모리 장치 및 링 오실레이터 배치 방법 |
CN113053428A (zh) * | 2019-12-26 | 2021-06-29 | 台湾积体电路制造股份有限公司 | 锁存电路、存储器设备和方法 |
US11442875B2 (en) | 2020-05-18 | 2022-09-13 | Integrated Silicon Solution, (Cayman) Inc. | Arbitration control for pseudostatic random access memory device |
CN111934655B (zh) * | 2020-07-28 | 2023-03-28 | 新华三半导体技术有限公司 | 一种脉冲时钟产生电路、集成电路和相关方法 |
TWI754569B (zh) * | 2021-03-24 | 2022-02-01 | 開曼群島商芯成半導體(開曼)有限公司 | 偽靜態隨機存取記憶體裝置之仲裁控制 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1089054A (zh) * | 1992-10-02 | 1994-07-06 | 三星电子株式会社 | 半导体存贮器 |
CN1162182A (zh) * | 1996-01-17 | 1997-10-15 | 三菱电机株式会社 | 减少其输入缓冲电路所消耗的电流的同步型半导体存储器 |
JP2000057770A (ja) * | 1999-07-19 | 2000-02-25 | Hitachi Ltd | 半導体メモリ |
US6230250B1 (en) * | 1991-10-24 | 2001-05-08 | Texas Instruments Incorporated | Synchronous memory and data processing system having a programmable burst order |
US6269050B1 (en) * | 1999-06-15 | 2001-07-31 | Samsung Electronics Co., Ltd. | Internal clock generating circuit of synchronous type semiconductor memory device and method thereof |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3319120B2 (ja) * | 1994-02-17 | 2002-08-26 | 富士通株式会社 | 同期型半導体記憶装置 |
JP3125685B2 (ja) | 1996-08-13 | 2001-01-22 | 日本電気株式会社 | 同期型半導体記憶装置 |
JP2000057776A (ja) * | 1998-08-14 | 2000-02-25 | Nkk Corp | 入力レジスタ回路 |
KR100358121B1 (ko) * | 1999-05-13 | 2002-10-25 | 주식회사 하이닉스반도체 | 반도체장치의 신호 입력회로 |
KR100319892B1 (ko) * | 1999-06-30 | 2002-01-10 | 윤종용 | 데이터 출력 패스의 데이터 라인 상의 데이터를 래치하는 회로를 구비하는 반도체 메모리 장치 예컨대, 동기식 디램 및 이 반도체 메모리 장치의 데이터 래칭 방법 |
JP2002157883A (ja) * | 2000-11-20 | 2002-05-31 | Fujitsu Ltd | 同期型半導体装置及び同期型半導体装置における入力信号のラッチ方法 |
JP4727073B2 (ja) * | 2001-07-09 | 2011-07-20 | 富士通セミコンダクター株式会社 | 半導体メモリ |
JP4078119B2 (ja) * | 2002-04-15 | 2008-04-23 | 富士通株式会社 | 半導体メモリ |
WO2004088667A1 (ja) * | 2003-03-31 | 2004-10-14 | Fujitsu Limited | 半導体メモリ |
JP2005141845A (ja) * | 2003-11-07 | 2005-06-02 | Fujitsu Ltd | 半導体装置 |
-
2004
- 2004-05-20 JP JP2004150561A patent/JP4717373B2/ja not_active Expired - Fee Related
- 2004-11-25 TW TW093136354A patent/TWI282983B/zh not_active IP Right Cessation
- 2004-11-29 US US10/997,881 patent/US7002875B2/en not_active Expired - Fee Related
- 2004-12-10 KR KR1020040103937A patent/KR100615413B1/ko not_active IP Right Cessation
-
2005
- 2005-01-19 CN CNB2005100017662A patent/CN100456386C/zh not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6230250B1 (en) * | 1991-10-24 | 2001-05-08 | Texas Instruments Incorporated | Synchronous memory and data processing system having a programmable burst order |
CN1089054A (zh) * | 1992-10-02 | 1994-07-06 | 三星电子株式会社 | 半导体存贮器 |
CN1162182A (zh) * | 1996-01-17 | 1997-10-15 | 三菱电机株式会社 | 减少其输入缓冲电路所消耗的电流的同步型半导体存储器 |
US6269050B1 (en) * | 1999-06-15 | 2001-07-31 | Samsung Electronics Co., Ltd. | Internal clock generating circuit of synchronous type semiconductor memory device and method thereof |
JP2000057770A (ja) * | 1999-07-19 | 2000-02-25 | Hitachi Ltd | 半導体メモリ |
Also Published As
Publication number | Publication date |
---|---|
JP2005332496A (ja) | 2005-12-02 |
US20050281129A1 (en) | 2005-12-22 |
JP4717373B2 (ja) | 2011-07-06 |
TWI282983B (en) | 2007-06-21 |
CN1700350A (zh) | 2005-11-23 |
KR20050111522A (ko) | 2005-11-25 |
KR100615413B1 (ko) | 2006-08-25 |
US7002875B2 (en) | 2006-02-21 |
TW200539181A (en) | 2005-12-01 |
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Legal Events
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee |
Owner name: FUJITSU SEMICONDUCTORS CO., LTD Free format text: FORMER NAME: FUJITSU MICROELECTRON CO., LTD. |
|
CP03 | Change of name, title or address |
Address after: Kanagawa Patentee after: Fujitsu Semiconductor Co., Ltd. Address before: Tokyo, Japan, Japan Patentee before: Fujitsu Microelectronics Ltd. |
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ASS | Succession or assignment of patent right |
Owner name: SUOSI FUTURE CO., LTD. Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20150512 |
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C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150512 Address after: Kanagawa Patentee after: Co., Ltd. Suo Si future Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090128 Termination date: 20180119 |
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CF01 | Termination of patent right due to non-payment of annual fee |