CN100388478C - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN100388478C
CN100388478C CNB031493548A CN03149354A CN100388478C CN 100388478 C CN100388478 C CN 100388478C CN B031493548 A CNB031493548 A CN B031493548A CN 03149354 A CN03149354 A CN 03149354A CN 100388478 C CN100388478 C CN 100388478C
Authority
CN
China
Prior art keywords
fuse
silicon oxide
semiconductor device
oxide layer
laser beam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB031493548A
Other languages
English (en)
Other versions
CN1494144A (zh
Inventor
井户康弘
河野和史
岩本猛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN1494144A publication Critical patent/CN1494144A/zh
Application granted granted Critical
Publication of CN100388478C publication Critical patent/CN100388478C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

在半导体基片(2)上形成硅氧化膜(8)。在该硅氧化膜(8)上形成沟(8a)。在沟(8a)内隔着阻挡层金属(10)形成作为隔断层的铜反射层(12a)。形成硅氧化膜(14),以覆盖该铜反射层(12a)。在该硅氧化膜(14)上设置含多个熔丝(16a)的熔丝形成区(15)。在铜反射层(12a)上形成为使激光光线反射而向下方凹入的凹状反射面。铜反射层(12a)被平面地配置,大致重叠在熔丝形成区的整个区域上。抑制熔丝熔断时激光光束的影响波及熔丝形成区近旁,获得可实现小型化的半导体装置。

Description

半导体装置
技术领域
本发明涉及半导体装置,特别是关于设有包含熔丝的冗余电路的半导体装置。
背景技术
伴随着半导体装置的微细化,异物对半导体装置的合格率带来了极大的影响。在设有动态随机存取存储器等的存储单元的半导体存储装置中,在存储器内部由于异物等原因形成特定的电路单元不合格的场合,为了连接预先形成的备用合格单元来替换该不合格的单元,使用了冗余电路。
为了把不合格单元置换成合格单元,就要切断设置在冗余电路上的预定的熔丝。作为熔丝,一般使用形成于半导体存储器上层部分的布线层。
在切断熔丝时,广泛采用着用激光的激光修整方式,用激光光束对准特定的熔丝进行照射,就可切断熔丝。
作为在冗余电路上形成熔丝部分的一种结构是仅在熔丝与半导体基片之间形成绝缘膜的结构(第一例)。考虑到切断熔丝时的影响,其方法是在熔丝的正下方区域和近旁的区域不配置布线和半导体元件。
而作为其它的结构,为了阻止切断熔丝时波及下层的影响,有在熔丝与半导体基片之间设置阻挡层的办法(第二例)。
特别是适合第二例的半导体装置,例如在特开平11-345880号公报、特开2000-114382号公报、特开2000-68377号公报、特开平10-242280号公报、特开平10-294372号公报、特开平2-25055号公报、特开昭63-3432号公报和特开平9-17877号公报等中提出了议案。
但是,在上述的以前的半导体装置中,存在着以下的问题。近年来,作为半导体装置,***LSI(大规模集在电路)需求的增长。在***LSI中,有在熔丝的下方形成不少于6层的结构。
这样一来,由于熔丝的下方形成多层,从配置熔丝的位置起至半导体基片的表面的距离也就变得更长。于是,在第一例的半导体装置中,在切断熔丝时照射的激光光束中,就有透过位于熔丝下方的层,由半导体基片的表面反射而返回的激光光束的成分,分布在偏离形成熔丝的位置的宽范围上。
因此,反射后的激光光束照射到形成在熔丝近旁的半导体元件和布线上,给半导体元件和布线带来坏的影响。
另外,在第二例的半导体装置中,由于形成在熔丝的正下方的阻挡层会有规则地反射激光光束。因此,例如特别是照射到多个熔丝中位于边缘的熔丝上,并由阻挡层反射的激光光束会对形成在位于其边缘的熔丝近旁的布线和半导体元件带来影响。
其结果,在形成熔丝的区域,就不能配置接近该区域的半导体元件和布线,这成为妨碍半导体装置小型化的原因之一。
发明内容
本发明为解决上述问题而构思,其目的在于抑制切断预定的熔丝时的激光光束对形成熔丝区域的近旁带来的影响,提供实现小型化的半导体装置。
有关本发明的一个半导体装置中,设有含主表面的半导体基片、熔丝形成区以及隔断层。熔丝形成区配设有形成在半导体基片的主表面上方的多个熔丝。隔断层形成在熔丝形成区与半导体基片之间,其作用是反射切断熔丝时所照射到达的激光光束以阻止光束进入到下方的区域。该隔断层设有用以反射激光光束的向下凹陷形状的反射面,它被平面地适当配置,以大致重叠在熔丝形成区的整个区域上。
依据本发明的一个半导体装置,隔断层设有用以反射激光光束的向下方凹陷的反射面,在经反射面反射的反射光中,从熔丝形成区水平方向地偏离的区域行进的反射光减少。另外,隔断层被平面地适当配置,以大致重叠在平面熔丝形成区的整个区域上,激光光束也不能透过到位于隔断层正下方的区域上。于是,可以在接近熔丝形成区形成布线和半导体元件或向隔断层的正下方的区域形成布线和半导体元件,能够实现半导体装置的小型化。
本发明的另一半导体装置中,设有含主表面的半导体基片、熔丝以及反射阻止层。熔丝形成在半导体基片的主表面的上方。反射阻止层具有凹凸表面,形成于熔丝的下方,通过使切断熔丝时照射并到达的激光光束在相邻的凸部之间重复反射,阻止激光光束向上方反射。
依据本发明的另一半导体装置,由于形成凹凸部表面,由熔丝衍射而到达反射阻止层的激光光束,在相互邻接的凸部与凸部之间进行重复反射,其间,激光光束有透过凸部的部分或被凸部吸收的部分,最终抑制了向上方的反射。因此,阻止了向形成熔丝的区域的周边反射激光光束,就可以在接近形成熔丝的区域配置布线和半导体元件,谋求半导体装置的小型化。
附图说明
图1是本发明实施例1的半导体装置的平面图。
图2是同一实施例中图1的剖面线II-II处的剖面图。
图3是同一实施例中图1的剖面线III-III处的剖面图。
图4是表示同一实施例中铜反射层结构的剖面图。
图5是表示同一实施例中半导体装置的制造方法一工序的剖面图。
图6是表示同一实施例中图5的工序之后进行的工序的剖面图。
图7是表示同一实施例中图6的工序之后进行的工序的剖面图。
图8是表示同一实施例中图7的工序之后进行的工序的剖面图。
图9是表示同一实施例中图8的工序之后进行的工序的剖面图。
图10是表示同一实施例中图9的工序之后进行的工序的剖面图。
图11是表示同一实施例中图10的工序之后进行的工序的剖面图。
图12是表示同一实施例中图11的工序之后进行的工序的剖面图。
图13是表示同一实施例中在铜反射层上激光光束的反射状况的局部放大剖面图。
图14是表示同一实施例中用于比较的铜反射层上激光光束反射状况的局部放大剖面图。
图15是说明同一实施例中的铜反射层的效果的局部放大剖面图。
图16是说明同一实施例中的铜反射层的效果的硅氧化膜厚与在各种金属表面上的光吸收率的关系的曲线图。
图17是说明同一实施例中的铜反射层的效果的激光光束的照射时间与各种金属表面上的温度的关系的曲线图。
图18是说明同一实施例中的铜反射层的效果的铜反射层的膜厚与激光光束的衰减率的关系的曲线图。
图19是本发明实施例2的半导体装置的剖面图。
图20是表示同一实施例中反射阻止层结构之一例的平面图。
图21是同一实施例中图20的剖面线XXI-XXI处的剖面图。
图22是表示同一实施例中反射阻止层结构之另一例的平面图。
图23是同一实施例中图22的剖面图XXIII-XXIII上的剖面图。
图24是表示同一实施例中半导体装置的制造方法的一个工序的剖面图。
图25是表示在同一实施例中图23的工序之后进行的工序的剖面图。
图26是表示同一实施例中图24的工序之后进行的工序的剖面图。
图27表示在同一实施例中半导体装置的另一制造方法的一个工序的剖面图。
图28是表示同一实施例中图26的工序之后进行的工序的剖面图。
图29是表示在同一实施例中图27的工序之后进行的工序的剖面图。
图30是表示同一实施例中图28的工序之后进行的工序的剖面图。
图31是说明在同一实施例中反射阻止层的效果的局部放大剖面图。
图32是说明同一实施例中反射阻止层的效果的俯视图。
图33是说明同一实施例中反射阻止层的效果的反射阻止层的折射率的变化的图。
图34是表示同一实施例中入射到反射阻止层的激光光束的光路的一例的图。
图35是表示同一实施例中反射阻止层结构的变形例的平面图。
图36是表示同一实施例中图35的剖面线XXXVI-XXXVI处的剖面图。
图37是表示同一实施例中的变形例的半导体装置的制造方法的一个工序的剖面图。
图38是表示同一实施例中的图37的工序之后进行的工序的剖面图。
图39是表示同一实施例中图38的工序之后进行的工序的剖面图。
具体实施方式
实施例1
作为本发明的实施例1的冗余电路的半导体装置,我们就设有作为阻止激光光束行进的铜反射层的半导体装置进行说明。如图1-图3所示,在半导体基片2上隔着硅氧化膜4形成预定的布线6。
在硅氧化膜4上进一步形成硅氧化膜8,使其覆盖布线6。在硅氧化膜8上形成沟8a。在沟8a内隔着阻挡层金属10形成作为隔断层的铜反射层12a。铜反射层12a用镶嵌法(damascene)形成。
另外,在硅氧化膜8上形成被连接至熔丝的布线16。用铜布线作为布线16的场合,布线16可用镶嵌法形成。另一方面,用Al、AlCu、WSi等的布线作为布线的场合,布线16采用传统的方法来形成。
在硅氧化膜8上进一步形成硅氧化膜14,使其覆盖铜反射层12a和布线16。在该硅氧化膜14上设置熔丝形成区15。
在该熔丝形成区15上,配置被连接至布线16的多个熔丝16a。在硅氧化膜14上再形成硅氧化膜18,以覆盖熔丝16a。
在上述的半导体装置中,如图4所示,在铜反射层12a上形成为反射激光光束的向下凹陷状的反射面13。如后述那样,该凹状反射面13通过由化学机械研磨法(Chemical mechanical Polishing:以下称CMP)形成铜反射层12a时的凹陷效应(dishing effect)得到。
另外,铜反射层12a被适当配置,平面地大致重叠在熔丝形成区15的整个区域上。再者,所谓平面地重叠,指的是在图1所示那样的二维配置中,铜反射层12a与熔丝形成区15相重叠。
下面就上述半导体装置的制造方法的一例进行说明。如图5所示,首先,在半导体基片2上用如CVD法(化学气相淀积)等形成硅氧化膜4。在该硅氧化膜4上形成构成布线的预定的导电层(未图示)。
对于该导电层,通过照相制版及加工,形成图6所示的布线6。然后,如图7所示,用CVD法等形成硅氧化膜8,以覆盖布线6。在该硅氧化膜8上形成预定的光刻胶图案(未图示)。
把该光刻胶图案作为掩模,在硅氧化膜上施行各向异性的蚀刻,形成如图8所示的沟8a。这时,也同时形成为形成预定布线的布线沟(未图示)。
然后,如图9所示,在该沟8a内和包含布线沟内的硅氧化膜8上隔着预定的阻挡层金属10形成铜膜12。另外,作为阻挡层金属10,最好使用如钽(Ta)和钽氮化物(TaN)等的层叠膜。
接着,在该铜膜12上用CMP法进行研磨处理,除去位于硅氧化膜8的上表面处的铜膜12和阻挡层金属10。通过该研磨处理,铜膜残留在沟8a内和布线沟内,如图10所示,在沟8a内形成铜反射层12a。在布线沟内形成布线16(参看图3)。这样的布线和铜反射层12a的形成方法称为镶嵌法。
该研磨处理中,特别是利用凹陷效应来形成铜反射层12a。亦即由于露出的硅氧化膜8(上面)与沟8a内残留的铜膜材质的不同以及沟8a的区域大小,在铜膜12的表面上,中央部分比周边部分更多地被研磨,于是形成了向下凹入的表面形状。
如图4所示,例如,如果把铜反射层12a的纵向长度L取为10μm,则周边部与中央部的高低差H为50nm~100nm程度。另外,在铜反射层12a的短方向部分(参看图3),其高低差比长方向上的高低差H要稍小一些。
这样,形成铜反射层12a后,如图11所示,用如CVD法等在硅氧化膜8上进一步形成硅氧化膜14,以覆盖铜反射层12a和布线16。
在该硅氧化膜14上方形成与布线16电连接的、构成熔丝的预定的导电层(未图示)。用该导电层形成多个熔丝16a。
作为形成熔丝16a的材料,有Al、AlCu、W、Wsi等为代表的可用蚀刻加工的材料和Cu等用蚀刻加工困难的材料。
为了用可蚀刻加工的材料形成熔丝16a,在形成构成熔丝的预定的导电层以后,在该导电层上形成预定的光刻胶图案形(未图示)。以该光刻胶图案形作为掩模在导电层上进行各向异性蚀刻,如图12所示形成多个熔丝16a。
另一方面,用蚀刻加工困难的Cu等形成熔丝16a时,与形成铜反射层12a的情况一样,用镶嵌法形成多个熔丝16a。
形成多个熔丝16a之后,用如CVD法等在硅氧化膜14上进一步形成硅氧化膜18,以覆盖多个熔丝16a。
如上,完成了设有熔丝的半导体装置的制作。而在该半导体装置的一系列制造工序中,存储信息的存储单元(未图示)也并行地形成。在所形成的存储单元中,在把判定为不合格的存储单元置换成合格的存储单元时的激光修整中,切断预定的熔丝。
接着,作为激光光束照射到熔丝后的光路,就照射到在如图2所示的熔丝形成区中所形成的多个熔丝中位于右端的熔丝上的激光光束的情况进行说明。
如图13所示,由位于右端的熔丝衍射后的激光光束21a、21b、21c分别入射到铜反射层12a上。入射到铜反射层12a上的激光光束,由表面向上方反射。
由凹状的表面反射的反射光23a~23c的各水平方向(平行于半导体基片的主平面的方向)的成分,小于图14所示的传统半导体装置上的铜反射层112a那样由平面的表面反射的反射光25a~25c的各水平方向的成分。
因此,在反射光23a~23c中,从形成熔丝的区域向沿水平方向偏离的区域行进的成分比起反射光25a~25c的更少。另外,图2中位于左端的熔丝,情况也相同。
这样一来,可以在接近形成熔丝的区域形成布线和半导体元件,从而能够实现半导体装置的小型化。
可是,在铜反射层12a上存在激光光束被反射成分与激光光束被吸收成分多少的问题,因此,就铜反射层12a上的激光光束吸收率进行说明。
如图15所示,由熔丝衍射出并透过硅氧化膜的激光光束21入射到铜反射层12a上。另外,在图15中,概念性地示出有预定波长的激光光束入射的情况。
通常,入射到金属材料表面的激光光束的吸收率依赖于位于金属材料表面上硅氧化膜的厚度并呈现周期性变动。再者,所谓吸收率,说的是当把入射的激光光束的强度作为100时,从其强度中扣出反射成分后剩余的成分与入射成分的比值。并且,激光光束的波长设为1.047μm,其强度(能量)设为0.5μJ。
硅氧化膜的膜厚与在各种金属材料的表面上的吸收率的关系示于图16。图16中,纵轴对应于吸收率,横轴对应于硅氧化膜的膜厚。作为金属材料,可以列举铝(Al)、铜(Cu)、钨(W)和钛(Ti)。另外,这时的氧化膜厚是以硅氧化膜计算。
如图16所示,对应于各种金属材料的吸收率依赖于硅氧化膜的膜厚并呈周期性变动。所举出的4种金属材料中,对应于钛的激光吸收率最高,对应于铜的激光吸收率最低。
基于上述原因,与构成熔丝的铝等材料相比,在铜反射层12a上的激光光束的吸收率更低,这就抑制了铜反射层12a的温度上升。
再有,对金属材料的激光光束的照射时间与金属材料的表面的温度上升的关系示于图17。图17中,纵轴对应于温度,横轴对应于激光光束的照射时间。还有,激光光束的波长取为1.047μm,其强度(能量)取为0.5μJ。另外,作为表示温度上升的函数,使用了如下的函数。
式1
ΔT ( z , t ) = 2 H K κt [ ierfc ( z 2 κt ) - ierfc ( z 2 + w 2 / 2 2 κt ) ]
式中,H为每单位面积供给的功率(W/m2)、K为热传导率(W/m·℃)、κ为热扩散系数(m2/s)、w为光束直径(m)、z为距金属表面的垂直距离,在金属表面上z=0。功率中,考虑图16所示的金属的激光光束吸收率中的最大值。
另外,ierfc(x)是用下式表示的函数。
式2
ierfx ( x ) = ∫ x ∞ erfc ( t ) dt
再有,erfc(x)是补余误差函数。
如图17所示,在铝和钨的场合,较短时间(~2nsec)的激光光束照射可分别使它们的表面温度达到沸点。
可知,比起铝和钨来,铜在达到熔点前有足够的时间(10nsec),在达到沸点前更有足够的时间。
由以上所述可知,在本半导体装置中,铜反射层12a不容易被入射到铜反射层12a上的激光光束溶化。
下面就形成铜反射层12a的区域的大小进行说明。如图9和图10所示,铜反射层12a是在形成在硅氧化膜8的沟8a上隔着阻挡层金属10而形成。
因此,铜反射层12a的底面和侧面处于由阻挡层金属10覆盖的状态。特别是在表面上露出的阻挡层金属10上,如果被激光照射,就会使阻挡层金属10被加热而熔化、气化。
如果阻挡层金属10气化,损伤就会波及到铜反射层12a本身。因此,铜反射层12a最好具有足够的尺寸,使激光光束不会入射到露出来的阻挡层金属上,如图1所示,在二维布局中,铜反射层12a最好至少大致重叠在熔丝形成区15的整个区域上。
另外,这样的铜反射层形成在重叠于熔丝形成区15的大致全区域的尺寸上,跟阻挡层金属与铜反射层在多个熔丝各自的正下方各自形成的情况相比,衍射的激光光束不容易入射到表面露出的阻挡层金属上。于是,就可防止铜反射层受到损伤的波及。
下面就铜反射层12a的厚度进行说明。通常,入射到金属表面上的激光光束,其透过金属的多少依赖于金属的厚度。以铜反射层12a的场合入射的激光光束的能量的衰减作为距铜反射层12a的表面的深度的函数表示的曲线示于图18中。激光光束的波长为1.047μm。
为了保护激光修整时的激光光束下方形成的布线和半导体元件,需要用铜反射层12a使激光光束能量的99%以上得到衰减。
从图18所示的曲线图可知,为了使激光光束的能量的约99%以上得到衰减,把铜反射层12a的膜厚至少要设定在60mm以上。这样,才能够在位于铜反射层的正下方的区域形成布线和半导体元件。
在上述半导体装置中,形成了具有向下方凹进形状的反射面的铜反射层12a,在反射光23a~23c中,从形成熔丝的区域向沿水平方向偏离的区域行进的反射光就更少。另外,激光也没有向位于铜反射层的正下方的区域透过。
因此,可以在接近熔丝的区域形成布线和半导体元件或向铜反射层的正下方的区域形成布线和半导体元件,在提高布局的自由度的同时,可以谋求半导体装置的小型化。
实施例2
作为本发明实施例2的半导体装置,就设有阻止激光光束反射的反射阻止层的半导体装置进行说明。如图19所示,在半导体基片2的表面上形成反射阻止层3。
形成覆盖该反射阻止层3的硅氧化膜20。在硅氧化膜20上形成预定的熔丝22。然后,在硅氧化膜20上进一步形成硅氧化膜24,以覆盖熔丝22。
反射阻止层3既可以是半导体基片2本身,也可以是形成于半导体基片2表面的附加层。
在激光光束入射的反射阻止层3的表面,如图20和21所示,形成向一个方向延伸的凹凸部。另外,在反射阻止层3的表面上,也可形成矩阵状的突起部,如图22和图23所示。
下面就上述反射阻止层的形成方法的一例进行说明。如图24所示,首先,在半导体基片2上形成预定的光刻胶图案26。接着,如图25所示那样,把该光刻胶图案作为掩模,在露出的半导体基片(硅)2上施行各向异性蚀刻,形成凹部2a。之后,如图26所示,除去光刻胶图案26。
在除去光刻胶图案26之后,如图19所示那样,在反射阻止层上形成硅氧化膜20,在该硅氧化膜20上形成包含熔丝22的预定的布线。再形成覆盖熔丝22的硅氧化膜24。经过如上步骤,半导体装置即完成。
下面就反射阻止层的形成方法的另一例进行说明。如图27所示,首先,在半导体基片2上形成硅氧化膜28。在该硅氧化膜28上,用如CVD法或溅射法形成非晶形硅层30。
接着,如图28所示,在该非晶型硅层30上形成预定的光刻胶图案26。然后,如图29所示,以光刻胶图案26作为掩模,在露出的非晶形硅30上通过施行各向异性的蚀刻形成凹部30a。之后,如图30所示,除去光刻胶图案26。
在除去光刻胶图案26之后,与前述的方法一样,形成硅氧化膜和包含熔丝的预定的布线等,半导体装置即告完成。
下面就反射阻止层3的详细构造进行说明。如所形成的突起的周期比入射的激光光束的波长更短,就不发生由入射的激光光束产生的衍射光(衍射波)。因此,对于入射的激光光束,形成突起的部分与具有平均折射率的媒质构成同质。
例如,如图31和图32所示的形成矩阵状突起的反射阻止层3上,若把突起的x方向和y方向各自的周期设为Tx、Ty,把突起的高度设为H、突起的折射率设为n1,周围的折射率为n2,则在图33所示的反射阻止层3上的折射率n2→n1构成了从折射率n2向折射率n1连续缓慢地变化。
通常,激光光束等的光反射是由于折射率的急剧变化而产生的。如图33所示,由于折射率连续缓慢地变化。激光基本不向上方反射。
在反射阻止层3上的折射率的变化越缓慢,就越能有效地抑制反射阻止层3上的激光光束的反射。为此,突起的高宽比(H/Tx或H/Ty)最好在2以上。
如图34所示,由于形成这样的突起,由熔丝衍射并到达反射阻止层3的激光光束,在相互邻接的突起与突起之间重复进行反射,其间,激光光束或透过突起部分或被突起部分吸收,最终的效果就是抑制了向上方的反射。
因此,阻止向形成熔丝的区域的周边反射激光光束,就可以在接近形成熔丝的区域配置布线和半导体元件等。
另外,作为反射阻止层,例中举出并说明过的突起形成矩阵状的情况,但是即使在突起向一个方向延伸那样形成的反射阻止层中,通过按照突起被配置成矩阵状来形成突起,也能够抑制激光光束的反射。
如此,由熔丝衍射的激光光束即使在可以向半导体基片2一侧入射,由于形成反射阻止层3,阻止了入射的激光光束向上方的反射。
据此,阻止了激光光束向在熔丝区域的周边形成的布线和半导体元件的照射,阻止了激光光束的影响达到该布线和半导体元件。
特别是在采用***LSI等的多层布线结构的半导体装置中,从形成熔丝的层到半导体基片表面的距离比较长。因而,激光光束在半导体基片的表面附近反射的场合,比起其它的半导体装置来,反射的激光光束被送到距形成被切断熔丝的区域更远的区域。
另外,为了阻止由一个熔丝衍射并反射的激光光束产生的影响波及到该熔丝的相邻熔丝,相邻熔丝的间隔L(参看图19)也需要加宽。
对于具有那种多层布线构造的半导体装置,由于形成了上述的反射阻止层,阻止了因熔丝衍射而到达的激光光束的反射,就可以在接近形成熔丝的区域配置布线和半导体元件。并且,相邻熔丝的间隔也可以变窄。
下面,就反射阻止层的变形例进行说明。在前述的半导体装置中,描述了有意形成凹部作为反射阻止层,而结果形成突起的情况。
这里,就有意形成突部的情况举例加以说明。如图35和图36所示,在反射阻止层的表面上有意地形成突部。该突部可以直接形成在半导体基片2的表面上,也可以形成在半导体基片2的表面上所形成的预定的层上。
下面就其形成方法之一例进行说明。如图37所示,首先,在半导体基片2上形成硅氧化膜28。在该硅氧化膜28上用如CVD法或溅镀法形成非晶形硅层30。
接着,如图38所示,用乙硅烷(Si2H6)气体在非晶形硅30的表面上形成硅核32a。通过在形成硅核32a的半导体基片上施行热处理使硅核生长,如图39所示,在非晶形硅的层30的表面上形成突部32,其表面被粗面化。
即使在如此将非晶形硅的表面粗面化后的反射阻止层上,也与前述的半导体装置的情况一样,在激光修整时照射时到达反射阻止层的激光光束,由于反射阻止层的作用而被阻止向上方反射。
这样一来,可以在接近形成熔丝的区域配置布线和半导体元件,从而能够实现半导体装置的小型化或高集成化。
文中所公开的所有实施例均为示例,不应看作对本发明的限制。本发明的范围由权利要求书示出,并不限定于上述说明的内容,本发明涵盖与权利要求范围相当的以及该范围内的全部更改。

Claims (12)

1.一种半导体装置,它包括:
有主表面的半导体基片;
在所述半导体基片的所述主表面上形成的硅氧化膜;
在所述硅氧化膜上形成的多个熔丝;
在所述硅氧化膜和所述半导体基片的所述主表面之间设置的隔断层,所述隔断层形成有一反射面,总体上在一个面上覆盖所述多个熔丝的整个区域,用以在与所述主表面的方向相反的方向上反射激光光束,从所述隔断层的周边部分向所述阻断层的中心部分看,所述反射面向所述半导基片的所述主表面凹入。
2.如权利要求1所述的半导体装置,其特征在于:所述隔断层中的激光光束的吸收率比所述熔丝中的激光光束的吸收率低。
3.如权利要求2所述的半导体装置,其特征在于:所述隔断层具有使99%以上的入射激光光束衰减的膜厚。
4.如权利要求3所述的半导体装置,其特征在于:所述隔断层由含铜的材料形成。
5.如权利要求3所述的半导体装置,其特征在于:
设置在所述半导体基片与所述硅氧化膜之间的另一个硅氧化膜,以及
在所述另一个硅氧化膜上形成的沟部;
其中所述隔断层在所述沟部内隔着预定的阻挡层形成。
6.如权利要求2所述的半导体装置,其特征在于:所述的隔断层由含铜的材料形成。
7.如权利要求2所述的半导体装置,其特征在于:
设置在所述半导体基片与所述硅氧化膜之间的另一个硅氧化膜,以及在所述另一个硅氧化膜上形成的沟部;
其中所述的隔断层在所述沟部内隔着预定的阻挡层形成。
8.如权利要求1所述的半导体装置,其特征在于:所述隔断层具有使99%以上的入射激光光束衰减的膜厚。
9.如权利要求1所述的半导体装置,其特征在于:所述的隔断层由含铜的材料形成。
10.如权利要求1所述的半导体装置,其特征在于:
设置在所述半导体基片与所述硅氧化膜之间的另一个硅氧化膜,以及在所述另一个硅氧化膜上形成的沟部;
其中所述隔断层在所述沟部内隔着预定的阻挡层形成。
11.一种半导体装置,它包括:
有主表面的半导体基片,
在所述半导体基片的所述主表面上形成的多个熔丝,以及
反射阻止层,它形成于所述熔丝下方并具有有凹凸部的表面、用以接收辐射来的用以熔断所述熔丝并到达所述反射阻止层的激光光束,使激光光束在所述凸部的相邻凸部间重复反射来阻止向上方反射激光光束,所述反射阻止层横过所述多个熔丝。
12.如权利要求11所述的半导体装置,其特征在于:所述反射阻止层形成于所述半导体基片的表面。
CNB031493548A 2002-10-29 2003-06-16 半导体装置 Expired - Fee Related CN100388478C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002314781A JP4297677B2 (ja) 2002-10-29 2002-10-29 半導体装置の製造方法
JP314781/2002 2002-10-29
JP314781/02 2002-10-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CNA2008100865947A Division CN101246848A (zh) 2002-10-29 2003-06-16 半导体装置

Publications (2)

Publication Number Publication Date
CN1494144A CN1494144A (zh) 2004-05-05
CN100388478C true CN100388478C (zh) 2008-05-14

Family

ID=32105383

Family Applications (2)

Application Number Title Priority Date Filing Date
CNA2008100865947A Pending CN101246848A (zh) 2002-10-29 2003-06-16 半导体装置
CNB031493548A Expired - Fee Related CN100388478C (zh) 2002-10-29 2003-06-16 半导体装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CNA2008100865947A Pending CN101246848A (zh) 2002-10-29 2003-06-16 半导体装置

Country Status (6)

Country Link
US (2) US7115966B2 (zh)
JP (1) JP4297677B2 (zh)
KR (1) KR100491854B1 (zh)
CN (2) CN101246848A (zh)
DE (1) DE10326732A1 (zh)
TW (1) TWI291743B (zh)

Families Citing this family (204)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005032916A (ja) * 2003-07-10 2005-02-03 Renesas Technology Corp 半導体装置
JP4587761B2 (ja) * 2004-09-30 2010-11-24 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
CN100390952C (zh) * 2005-05-27 2008-05-28 联华电子股份有限公司 切断熔丝结构的方法
US7759765B2 (en) * 2006-07-07 2010-07-20 Semiconductor Energy Laboratory Co., Ltd Semiconductor device mounted with fuse memory
US8546818B2 (en) 2007-06-12 2013-10-01 SemiLEDs Optoelectronics Co., Ltd. Vertical LED with current-guiding structure
US8362800B2 (en) 2010-10-13 2013-01-29 Monolithic 3D Inc. 3D semiconductor device including field repairable logics
US8754533B2 (en) 2009-04-14 2014-06-17 Monolithic 3D Inc. Monolithic three-dimensional semiconductor device and structure
US8384426B2 (en) 2009-04-14 2013-02-26 Monolithic 3D Inc. Semiconductor device and structure
US8405420B2 (en) 2009-04-14 2013-03-26 Monolithic 3D Inc. System comprising a semiconductor device and structure
US8378715B2 (en) 2009-04-14 2013-02-19 Monolithic 3D Inc. Method to construct systems
US8669778B1 (en) 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
US8395191B2 (en) 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8373439B2 (en) 2009-04-14 2013-02-12 Monolithic 3D Inc. 3D semiconductor device
US9509313B2 (en) 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
US8058137B1 (en) 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9711407B2 (en) 2009-04-14 2017-07-18 Monolithic 3D Inc. Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
US7986042B2 (en) 2009-04-14 2011-07-26 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8427200B2 (en) 2009-04-14 2013-04-23 Monolithic 3D Inc. 3D semiconductor device
US9577642B2 (en) 2009-04-14 2017-02-21 Monolithic 3D Inc. Method to form a 3D semiconductor device
US8362482B2 (en) 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
US9331211B2 (en) * 2009-08-28 2016-05-03 X-Fab Semiconductor Foundries Ag PN junctions and methods
GB0915501D0 (en) * 2009-09-04 2009-10-07 Univ Warwick Organic photosensitive optoelectronic devices
US8476145B2 (en) 2010-10-13 2013-07-02 Monolithic 3D Inc. Method of fabricating a semiconductor device and structure
US8294159B2 (en) 2009-10-12 2012-10-23 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US11984445B2 (en) 2009-10-12 2024-05-14 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
US9099424B1 (en) 2012-08-10 2015-08-04 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
US8536023B2 (en) 2010-11-22 2013-09-17 Monolithic 3D Inc. Method of manufacturing a semiconductor device and structure
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US8450804B2 (en) 2011-03-06 2013-05-28 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US8581349B1 (en) 2011-05-02 2013-11-12 Monolithic 3D Inc. 3D memory semiconductor device and structure
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
US8742476B1 (en) 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
KR101177483B1 (ko) * 2009-12-29 2012-08-27 에스케이하이닉스 주식회사 반도체 소자의 퓨즈 및 그 형성 방법
US8026521B1 (en) 2010-10-11 2011-09-27 Monolithic 3D Inc. Semiconductor device and structure
US8541819B1 (en) 2010-12-09 2013-09-24 Monolithic 3D Inc. Semiconductor device and structure
US8492886B2 (en) 2010-02-16 2013-07-23 Monolithic 3D Inc 3D integrated circuit with logic
US8461035B1 (en) 2010-09-30 2013-06-11 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8373230B1 (en) 2010-10-13 2013-02-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US9219005B2 (en) 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
US8642416B2 (en) 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
US9953925B2 (en) 2011-06-28 2018-04-24 Monolithic 3D Inc. Semiconductor system and device
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
US8901613B2 (en) 2011-03-06 2014-12-02 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8273610B2 (en) 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US8163581B1 (en) 2010-10-13 2012-04-24 Monolith IC 3D Semiconductor and optoelectronic devices
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US8114757B1 (en) 2010-10-11 2012-02-14 Monolithic 3D Inc. Semiconductor device and structure
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US9197804B1 (en) 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US8379458B1 (en) 2010-10-13 2013-02-19 Monolithic 3D Inc. Semiconductor device and structure
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11984438B2 (en) 2010-10-13 2024-05-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US8975670B2 (en) 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
US8687399B2 (en) 2011-10-02 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US9029173B2 (en) 2011-10-18 2015-05-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US8574929B1 (en) 2012-11-16 2013-11-05 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US8686428B1 (en) 2012-11-16 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US11961827B1 (en) 2012-12-22 2024-04-16 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11967583B2 (en) 2012-12-22 2024-04-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
US9385058B1 (en) 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US9871034B1 (en) 2012-12-29 2018-01-16 Monolithic 3D Inc. Semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US8994404B1 (en) 2013-03-12 2015-03-31 Monolithic 3D Inc. Semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
US9117749B1 (en) 2013-03-15 2015-08-25 Monolithic 3D Inc. Semiconductor device and structure
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
CN104851872B (zh) * 2014-02-17 2018-02-13 北大方正集团有限公司 一种集成电路结构及其制作方法
US9917055B2 (en) * 2015-03-12 2018-03-13 Sii Semiconductor Corporation Semiconductor device having fuse element
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US11978731B2 (en) 2015-09-21 2024-05-07 Monolithic 3D Inc. Method to produce a multi-level semiconductor memory device and structure
CN108401468A (zh) 2015-09-21 2018-08-14 莫诺利特斯3D有限公司 3d半导体器件和结构
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
JP6690270B2 (ja) * 2015-10-15 2020-04-28 株式会社ジェイテクト 金属部材の加熱方法、加熱した金属部材の接合方法、及び金属部材の加熱装置
US11991884B1 (en) 2015-10-24 2024-05-21 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US12016181B2 (en) 2015-10-24 2024-06-18 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11128102B2 (en) * 2017-09-07 2021-09-21 Mitsubishi Electric Corporation Semiconductor optical device
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1214549A (zh) * 1997-09-12 1999-04-21 西门子公司 改进的激光熔丝连接及其制造方法
US5986319A (en) * 1997-03-19 1999-11-16 Clear Logic, Inc. Laser fuse and antifuse structures formed over the active circuitry of an integrated circuit
US6160302A (en) * 1998-08-31 2000-12-12 International Business Machines Corporation Laser fusible link
US6320242B1 (en) * 1997-10-22 2001-11-20 Seiko Instruments Inc. Semiconductor device having trimmable fuses and position alignment marker formed of thin film
US6362514B1 (en) * 1999-01-19 2002-03-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984574A (ja) 1982-11-08 1984-05-16 Matsushita Electronics Corp 半導体装置
US4720993A (en) 1984-10-29 1988-01-26 Commonwealth Scientific & Industrial Research Organization Semiconducting oxygen sensors
JPS633432A (ja) 1986-06-24 1988-01-08 Nec Corp 半導体装置
JPH0225055A (ja) 1988-07-13 1990-01-26 Hitachi Ltd 半導体記憶装置
US5235205A (en) * 1991-04-23 1993-08-10 Harris Corporation Laser trimmed integrated circuit
WO1993005514A1 (en) * 1991-09-04 1993-03-18 Vlsi Technology, Inc. Anti-fuse structures and methods for making same
US5608257A (en) 1995-06-07 1997-03-04 International Business Machines Corporation Fuse element for effective laser blow in an integrated circuit device
US5619460A (en) 1995-06-07 1997-04-08 International Business Machines Corporation Method of testing a random access memory
CN1082254C (zh) * 1995-08-22 2002-04-03 松下电器产业株式会社 硅结构体及其制造方法和装置及使用硅结构体的太阳电池
US5602053A (en) * 1996-04-08 1997-02-11 Chartered Semidconductor Manufacturing Pte, Ltd. Method of making a dual damascene antifuse structure
EP0860878A2 (en) 1997-02-20 1998-08-26 Texas Instruments Incorporated An integrated circuit with programmable elements
JPH10294372A (ja) 1997-04-22 1998-11-04 Hitachi Ltd 半導体集積回路装置
JPH11345880A (ja) 1998-06-01 1999-12-14 Fujitsu Ltd 半導体装置及びその製造方法
JP2000031942A (ja) * 1998-07-14 2000-01-28 Mitsubishi Electric Corp 音響再生装置及び音響再生方法
JP3630999B2 (ja) 1998-08-19 2005-03-23 富士通株式会社 半導体装置及びその製造方法
JP3466929B2 (ja) 1998-10-05 2003-11-17 株式会社東芝 半導体装置
US6180503B1 (en) * 1999-07-29 2001-01-30 Vanguard International Semiconductor Corporation Passivation layer etching process for memory arrays with fusible links
US6265257B1 (en) * 1999-10-01 2001-07-24 Taiwan Semiconductor Manufacturing Company Method of making a barrier layer to protect programmable antifuse structure from damage during fabrication sequence
KR100332456B1 (ko) * 1999-10-20 2002-04-13 윤종용 퓨즈를 갖는 반도체 소자 및 그 제조방법
US6124194A (en) * 1999-11-15 2000-09-26 Chartered Semiconductor Manufacturing Ltd. Method of fabrication of anti-fuse integrated with dual damascene process
US6440833B1 (en) * 2000-07-19 2002-08-27 Taiwan Semiconductor Manufacturing Company Method of protecting a copper pad structure during a fuse opening procedure
JP2003060036A (ja) * 2001-08-08 2003-02-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2003086687A (ja) * 2001-09-13 2003-03-20 Seiko Epson Corp 半導体装置
US6737345B1 (en) * 2002-09-10 2004-05-18 Taiwan Semiconductor Manufacturing Company Scheme to define laser fuse in dual damascene CU process

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5986319A (en) * 1997-03-19 1999-11-16 Clear Logic, Inc. Laser fuse and antifuse structures formed over the active circuitry of an integrated circuit
CN1214549A (zh) * 1997-09-12 1999-04-21 西门子公司 改进的激光熔丝连接及其制造方法
US6320242B1 (en) * 1997-10-22 2001-11-20 Seiko Instruments Inc. Semiconductor device having trimmable fuses and position alignment marker formed of thin film
US6160302A (en) * 1998-08-31 2000-12-12 International Business Machines Corporation Laser fusible link
US6362514B1 (en) * 1999-01-19 2002-03-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Also Published As

Publication number Publication date
DE10326732A1 (de) 2004-05-27
US20040080022A1 (en) 2004-04-29
CN101246848A (zh) 2008-08-20
US7115966B2 (en) 2006-10-03
JP2004152894A (ja) 2004-05-27
CN1494144A (zh) 2004-05-05
US20070164394A1 (en) 2007-07-19
TW200406878A (en) 2004-05-01
KR20040040320A (ko) 2004-05-12
KR100491854B1 (ko) 2005-05-27
JP4297677B2 (ja) 2009-07-15
TWI291743B (en) 2007-12-21

Similar Documents

Publication Publication Date Title
CN100388478C (zh) 半导体装置
EP1266405B1 (en) Planarised semiconductor structure including a conductive fuse and process for fabrication thereof
US6124194A (en) Method of fabrication of anti-fuse integrated with dual damascene process
US7666734B2 (en) Semiconductor device having a fuse
JP3989898B2 (ja) 半導体ウエハーにおける自動位置合わせ構造の製造方法
US7973341B2 (en) Fuse of semiconductor device
US7402464B2 (en) Fuse box of semiconductor device and fabrication method thereof
KR20010014513A (ko) 다층 배선 구조의 반도체 장치
US20010055848A1 (en) Fuse area structure having guard ring surrounding fuse opening in semiconductor device and method of forming the same
US5895963A (en) Semiconductor device having opening portion for fuse breakage
US5589706A (en) Fuse link structures through the addition of dummy structures
JP3667507B2 (ja) 半導体装置及びその製造方法
US7728406B2 (en) Semiconductor device
US6531757B2 (en) Semiconductor device fuse box with fuses of uniform depth
US7449764B2 (en) Semiconductor device and method of manufacturing the same
JP2003086687A (ja) 半導体装置
JP2004281612A (ja) 半導体装置
US5110759A (en) Conductive plug forming method using laser planarization
US6822310B2 (en) Semiconductor integrated circuit
JP4390297B2 (ja) 半導体装置
US20060076642A1 (en) Semiconductor device and manufacturing method thereof
JP2005032916A (ja) 半導体装置
JP2007221102A (ja) 半導体装置
KR100340714B1 (ko) 결함구제를 위한 반도체소자의 제조방법
JP2004335735A (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
CI01 Correction of invention patent gazette

Correction item: Inventor

Correct: Ido Yasuhiro

False: Iei Yasuhiro

Number: 18

Volume: 20

CI02 Correction of invention patent application

Correction item: Inventor

Correct: Ido Yasuhiro

False: Iei Yasuhiro

Number: 18

Page: The title page

Volume: 20

COR Change of bibliographic data

Free format text: CORRECT: INVENTOR; FROM: INAGA NAKASONE TO: NAKASONE IDO

ERR Gazette correction

Free format text: CORRECT: INVENTOR; FROM: INAGA NAKASONE TO: NAKASONE IDO

C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: RENESAS ELECTRONICS CORPORATION

Free format text: FORMER OWNER: MISSUBISHI ELECTRIC CORP.

Effective date: 20140416

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20140416

Address after: Kawasaki, Kanagawa, Japan

Patentee after: Renesas Electronics Corporation

Address before: Tokyo, Japan, Japan

Patentee before: Missubishi Electric Co., Ltd.

CP02 Change in the address of a patent holder

Address after: Tokyo, Japan, Japan

Patentee after: Renesas Electronics Corporation

Address before: Kawasaki, Kanagawa, Japan

Patentee before: Renesas Electronics Corporation

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080514

Termination date: 20190616