CN100383936C - 三维器件制造方法 - Google Patents

三维器件制造方法 Download PDF

Info

Publication number
CN100383936C
CN100383936C CNB028300335A CN02830033A CN100383936C CN 100383936 C CN100383936 C CN 100383936C CN B028300335 A CNB028300335 A CN B028300335A CN 02830033 A CN02830033 A CN 02830033A CN 100383936 C CN100383936 C CN 100383936C
Authority
CN
China
Prior art keywords
wafer
hole
opening
front surface
post bolt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB028300335A
Other languages
English (en)
Other versions
CN1708840A (zh
Inventor
H·伯恩哈德·波奇
罗伊·俞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1708840A publication Critical patent/CN1708840A/zh
Application granted granted Critical
Publication of CN100383936C publication Critical patent/CN100383936C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Led Device Packages (AREA)
  • Dicing (AREA)

Abstract

描述了一种用于制造包括多个垂直层叠和互连的晶片三维集成器件的方法。利用如聚酰亚胺的热塑性材料层(26、36)将晶片(1、2、3)键合在一起；通过在晶片中与柱栓(27、37)连接的的通孔(12、22)实现电连接。柱栓连接具有大于通孔的横向尺寸的横向尺寸的在晶片的前表面的开口(13，23)。另外，在各自的晶片中的通孔不需从晶片的前表面垂直延伸至后表面。在晶片中器件区下面提供且横向延伸的导电体(102)可以连接具有在后表面的金属化开口(103)的通孔。因此，通过晶片的导电路径可以引至晶片的器件下面。可以在开口(113)和柱栓(127)之间制造附加的连接以在晶片间形成垂直热传导路径。

Description

三维器件制造方法
技术领域
本发明涉及超大规模集成半导体器件的制造，并且具体地涉及制造三维垂直互连的芯片的方法。
背景技术
微处理器芯片一般包括逻辑单元和高速缓冲存储器。如果以二维(2-D)的图案排列微处理器的逻辑单元和存储器件，芯片物理尺寸上的限制(由大面积芯片的工艺合格率差引起)可能导致高速缓冲存储器的数量上的限制。微处理器的性能因此可能被严重地限制。
为了解决为微处理器提供足够的高速缓冲存储器的问题(更一般的，芯片上2-D不动产(real estate)的问题)，许多的研究者探索制造三维(3-D)集成电路的方法。典型的3-D制造方法包括：在随后减薄至小于20μm的晶片上构建器件；提供通过晶片的垂直互连；层叠晶片以使在不同的水平处的晶片之间建立垂直连接；和用合适的材料键合晶片。参见，例如，J.-Q.Lu等，“Fabrication of via-chain test structures for 3D IC technology usingdielectric glue bonding on 200 mm wafers”，Materials Research Society ULSIXVII Conference Proceedings 151(2002)；P.Ramm等“Interchip via technologyby using copper for vertical system integration”，Materials Research SocietyAdvanced Metallization Conference 159(2002)；和Rahman等，“Thermalanalysis of three-dimensional integrated circuits”，IEEE InternationalInterconnect Technology Conference Proceedings 157(2001)。3-D集成的现有技术的显著问题包括(1)对可靠的晶片键合的需求；(2)严格的晶片清洁度和平整度的要求；(3)对可靠的、低电阻晶片间垂直连接的需求；(4)严格的晶片至晶片横向配准(registration)要求；和(5)对通过3-D器件的有效热传导的需求。
在授让给International Business Machines Corporation的“Process formaking fine pitch connections between devices and structure made by theprocess”，U.S.Pat.No.6,444,560中描述了制造2-D芯片至芯片互连的方法，其公开的内容引入如下作为参考。如在该专利中指出的，可以利用布线层和各自的芯片之间的柱栓(stud)/通孔连接，通过聚酰亚胺的布线层连接具有不同的功能和可能具有不同的材料的芯片。期望扩展在该专利中所讨论的技术以获得3-D芯片级和晶片级集成。
发明内容
本发明通过提供一种制造包括多个垂直层叠和互连的晶片的三维集成器件的方法解决了上述的问题，其中可以将晶片可靠地键合在一起且可以放松对晶片的平整度和晶片间高精度对准的要求。为了垂直连接第一晶片和第二晶片，在第一晶片中形成通孔从前表面延伸，该通孔通过前表面处的横向尺寸表征。从第一晶片在其后表面处去除材料，减薄晶片至小于20μm。在第一晶片的后表面中形成开口，由此暴露通孔；该开口具有比通孔的横向尺寸大的横向尺寸。在该开口中形成导电材料层。在第二晶片的前表面上形成柱栓和键合材料层，该柱栓从其垂直地凸出。然后柱栓对准第一晶片的后表面中的开口；利用键合材料层键合晶片，以使柱栓与通孔电接触。为了互连三个晶片，第二晶片还提供有从晶片的前表面延伸的通孔，且通过从第二晶片在其后表面处去除材料减薄第二晶片。在第二晶片的后表面中形成开口，由此暴露其中的通孔；该开口具有大于通孔的横向尺寸的横向尺寸。在该开口中形成导电材料层。第三晶片具有键合材料层和在其前表面上形成的柱栓；该柱栓对准第二晶片的后表面中的开口。然后利用键合材料层键合第三晶片和第二晶片，以使第三晶片的柱栓电接触第二晶片的通孔、第二晶片的柱栓以及第一晶片的通孔。
依据本发明，在各自的晶片中的通孔不需垂直地从晶片的前表面延伸至后表面。在晶片中器件区下面提供且横向延伸的导电体可以将通孔与后表面中的金属化的开口连接。因此，可以在晶片的器件的下面引入通过晶片的导电路径。键合层优选为热塑性材料，且具体地可以是聚酰亚胺。这允许晶片以对平整度和清洁度较不严格的要求键合。
附加的开口可以形成于第一晶片的后表面中，以与在第二晶片的前表面上的附加的柱栓连接，其中附加的开口和柱栓与通孔绝缘。这些附加的连接用作晶片间的垂直热传导路径。本发明因此实现了具有晶片间的可靠的电连接和改进的热传导的3-D垂直集成。
附图说明
图1A-1I是依据本发明的第一实施例的3-D集成器件的制造工艺的步骤的示意图；
图2A-2F是依据本发明的第二实施例的3-D集成器件的制造工艺的步骤的示意图；
图3图示依据本发明的在晶片的器件区之下横向延伸的晶片间的垂直互连；
图4A-4C图示同样依据本发明的在3-D集成器件中改进热传导的制造工艺；
图5图示包括逻辑单元和3-D叠层的存储单元的完整的微处理器，依据本发明制造该存储单元，其中以利用C4技术的2-D互连方案在多芯片组件(MCM)上连接逻辑和存储单元；
图6图示包括逻辑单元和3-D叠层的存储单元的完整的微处理器，依据本发明制造该存储单元，其中以使用柱栓/通孔连接的2-D转移并结合(T&J)的互连方案连接逻辑和存储单元；
图7图示包括逻辑单元和存储单元的完整的微处理器，其中依据本发明垂直集成所有的单元。
具体实施方式
依据本发明，具有在其上形成的器件的多个减薄的晶片可以被层叠且垂直互连。在此描述的实施例中，制造并且连接了3级层叠；可以理解这只是为了说明的目的，且该方法可以适用于多于或少于三级。3-D垂直地集成的器件可以以两种方法构建，如下所述。
(1)自顶向下晶片层叠方法
图1A显示在靠近晶片的前表面1a的晶片的区域1d中具有器件和几层高密度互连布线11(通常为Cu)的晶片1的剖面。在晶片中形成金属化的通孔12，延伸至器件和横向互连的区域1d之下；这些通孔在晶片1被减薄后将成为垂直通过连接(through-connection)的部分。一般通过在晶片1中蚀刻孔、在孔的侧面和底上形成衬里材料层和用金属(优选为Cu)填充孔来形成通孔12。通孔12的深度小于减薄后的晶片1的最终厚度；由此，如果减薄后晶片约10μm厚，通孔则小于10μm深度。必须选择通孔12的直径以兼顾热传导和空间问题。大致1μm的直径消耗晶片表面上的最小的空间同时提供可接受的通过晶片的热传导；可以使用更小的通孔直径，但是对通过垂直晶片层叠的热传导可能是不足的。
为了说明的方便，显示通孔12以均匀的直径直线向下延伸进入器件之下的晶片区域。在实际中，对通孔的尺寸的要求可以在区域1d以下显著地放松。与在器件下横向延伸的该通过连接有关的其它方案是可能的，如下更详细地讨论。
为了有利于减薄的晶片的操作，操作板(通常为玻璃)15被贴附于晶片的前表面1a。利用优选为聚酰亚胺的热塑性键合材料的层16将晶片1和板15键合在一起。
在操作板15贴附于晶片1的情况下，通过磨制或抛光后表面1b减薄晶片(见图1B)。晶片1的结果的厚度小于20μm，优选为大约10μm。如图1B所示，减薄工艺在暴露通孔12的底部之前停止。
然后在晶片的后表面1b蚀刻开口13，暴露通孔12的底部(图1C)。在通孔中的金属可以自己作为该工艺的蚀刻阻挡；可替换地，可以在晶片的另一部分(未被器件占据)提供蚀刻阻挡层以提供该工艺的控制。应注意到开口13具有大于相应的通孔12的直径的直径。虽然通孔的多种设置是可能的(如下进一步讨论)，在后表面1b处的开口一般大于在前表面1a处的通孔。
然后用金属涂布开口13的内表面14(优选通过溅射)以与相应的通孔12的底端接触，以使形成通过晶片1的导电路径。应注意到开口13具有大于相应的通孔12的直径的直径(通常为两倍大)。这是为了有利于与另一晶片的垂直连接。
图1D显示了将与晶片1垂直集成的第二晶片2。晶片2具有器件和在其上形成的互连布线21，相似于晶片1。另外，金属化的通孔22(通常用铜填充)向下延伸进入晶片2，通孔22具有在表面2a的横向的尺寸221。在晶片2的前表面2a上沉积聚酰亚胺层26。在表面2a上形成柱栓27，在层26的顶表面的上面延伸通常为5μm或更小的距离。柱栓27可以由Ni、Cu、镀Ni的Cu、W或某些其它金属或金属的组合制成。在柱栓的表面上沉积低熔点合金材料层28；这有利于在垂直结合晶片1和2的工艺期间电连接的形成。合金材料通常为90/10Pb/Sn焊料，2μm或更薄的厚度。替换的合金材料包括Au/Sn和Sn/Ag。该合金材料可以经受热回流工艺以使层28获得圆头形状，如图1D所示。这有利于晶片2上的柱栓对相应的在晶片1上的开口的对准。柱栓从晶片2的器件垂直向上延伸电连接，而通孔22垂直向下地延伸电连接。
然后利用键合和层压(lamination)工艺将晶片1(贴附于操作板15)贴附于晶片2。如图1E所示，在晶片2上的柱栓27与晶片1上的开口13校准，以晶片1的后表面1b接触聚酰亚胺层26的前表面。在充分(1)保证晶片1和层26之间的键合以及(2)保证柱栓27和金属14(由此对通孔12)的电接触的温度和压力下进行层叠工艺。依据使用的材料，温度可以在200℃-400℃的范围且压力可以在10psi-200psi的范围。如图1E所示，键合和层压工艺导致焊料28流动以使焊料或者部分地或者全部地填充开口13。
应注意开口13具有大于柱栓27的直径，且由此能容纳相对于晶片1的晶片2的横向定位的不准确。另外，应注意表面1b和2a未直接接触，而是在其间具有层26。聚酰亚胺层26具有足够的厚度以覆盖小表面粒子，填充较小的表面缺陷，或容纳在两个晶片的平整度上的不同。因此，层26在保证晶片间的可靠的机械键合上具有重要的作用，而柱栓/通孔连接27-28-14-12提供可靠的垂直的电连接。
然后减薄晶片2(现与晶片1键合)至小于20μm，优选为约10μm。如图1F所示，在晶片2的后表面2b中形成开口23，暴露通孔22的底部。用金属24涂布开口23的内部表面(优选通过如晶片1的溅射)，以提供与另一晶片3的电连接。
图1G图示与晶片1和晶片2键合的晶片3的制备。晶片3也具有靠近其前表面的器件和互连布线31。为了与晶片2的后表面电接触，在晶片3的前表面3a形成柱栓37。柱栓37具有在其表面的合金材料38，分别相似于晶片2上的柱栓27和合金材料28。在表面3a上也沉积聚酰亚胺层36，相似于层26。在该图示中，晶片3是被键合的垂直叠层的最后晶片。因此，晶片3未被减薄(为了提供叠层的机械强度)且不要求通过晶片的通孔。
图1H显示晶片3的键合和层叠工艺的结果。柱栓37与通孔22电接触，作为合金材料38填充开口23和与金属层24键合的结果。聚酰亚胺层36与晶片2的表面2b键合，相似于晶片1和晶片2之间的层26。由于未减薄的晶片3为减薄的晶片1和2提供机械强度，不再需要操作板15且可以在此刻去除操作板15。这可以通过激光切除方便地完成，即，如果板15对切除辐射透明，则可以使用激光切除板15和层16之间的界面，由此分离该板。
然后可以使垂直互连的晶片叠层1-2-3贴附于外部连接，如图1I所述。图1I显示例如使用C4技术以连接垂直叠层至在更大的器件中的其它元件。在层16中形成开口40以暴露晶片1的金属化的通孔12，然后在开口中沉积金属焊盘41。然后利用(例如)本技术领域中的已知焊料掩模技术，在这些焊盘上形成C4焊料凸点42。然后完成的垂直集成的器件100可以与多芯片组件(MCM)上的C4焊盘等键合。
应注意只是示意性地图示晶片1、2和3的内部结构，其实，这些晶片可以通过不同的方法制造且可以具有不同的功能。例如，所有三个晶片可以具有高速缓冲存储器器件，晶片1和2可以具有存储器而晶片3具有逻辑器件，一个或更多的晶片可以引入微机电***(MEMS)等。
本发明人已经发现成功的晶片级垂直集成由以下因素保证：(1)减薄晶片至约10μm以最小化在通孔中垂直的热传导问题；(2)使用聚酰亚胺作为热塑性键合材料以放松晶片平整度和清洁度要求；和(3)使用其中后表面通孔开口显著大于柱栓的柱栓/通孔连接以放松横向配准要求。
(2)自底而上晶片层叠工艺
在图2A-2E中图示在垂直的叠层中键合晶片的替换的工艺。该工艺将对于三个晶片进行详细说明，但是，如以上所注，可以适用于更多或更少的晶片。首先依据图1A-1C所示的工艺制备晶片1，由此该晶片被减薄至约10μm，该晶片具有在后表面上具有开口13的金属化的通孔12，且该晶片具有贴附于具有聚酰亚胺层16的前表面的操作板15。
然后制备具有横向互连布线51的第二晶片5，如图2A所示。晶片5具有合金材料58的通孔52和柱栓57，相似于在以上所述的工艺中的晶片2(对比图1D)。为晶片5提供操作板55。用聚酰亚胺涂层56覆盖板55，涂层56被构图以容纳柱栓57。然后晶片5与操作板55键合，其允许晶片被减薄(图2B)。在减薄的晶片的后表面56中形成开口53，且用前述的金属层54涂布其内表面。
由于晶片1和5每个分别具有操作板15和55，它们可以被分开地准备、键合与减薄。
如图2C所示，制备具有横向互连布线61的第三晶片6。该晶片具有在其前表面上的聚酰亚胺层66和柱栓67(相似于如图1G所示的晶片3)，在其表面上具有合金材料68，用于使与其它晶片垂直电连接。柱栓67从层66凸出足够的距离以接触晶片5上的金属层54(即，约5μm)。然后晶片5和6被键合且层压在一起，如图2D所示。由于晶片6未减薄，在键合工艺之后不需要操作板55且因此去除操作板55。在此刻，减小晶片5的前表面5a上的层56的厚度以暴露柱栓57的高度约为5μm。然后柱栓57可以用于与晶片1的金属层14的键合。在图2E中显示了该键合工艺的结果，其中层叠的晶片5和6与晶片1结合，合金材料58填充被基本晶片1的开口13，与金属层14电接触且由此与通孔12电接触。在晶片5和6与晶片1键合之后，不再需要操作板15且可以去除操作板15，由此暴露层16。然后层16可以具有在其中形成的开口40和用以与通孔12连接而形成的金属焊盘41和C4焊料凸点42(图2F，对比图1I)。
可以理解用于层叠多个减薄的芯片以及引入从芯片至芯片的垂直互连的上述的技术在不增加其面积(二维)尺寸的情况下极大地提高芯片容量和功能。这些工艺对于具有相同容量的芯片特别有吸引力，由于每个减薄和层叠的芯片将具有相同的尺寸。这依次使器件的总体工艺显著地简单且更经济。应注意这些工艺允许晶片级的芯片至芯片互连，由此当与单一芯片垂直设置、键合和互连的工艺相比时，制造3D芯片的工艺成本显著低。与前述的垂直互连方案不同，在本发明中的芯片至芯片互连没有沿芯片的侧面进行，而是直接通过芯片形成。
值得注意的是在层叠的晶片的减小的厚度(约10μm)的情况下，芯片间(例如在高速缓冲存储单元之间)的互连长度远小于这样的芯片的2-D方案中的长度。这给出除了节省二维空间以外的改进的器件性能的附加的好处。
在图1A-1I和2A-2F中，为了图示的方便，显示通孔以均匀的直径直线向下延伸通过晶片。对于芯片至芯片的垂直互连不需要具有通过晶片全厚的小直径，或甚至对于减薄的晶片的10μm的厚度。例如，如图3所述，可以制备晶片1具有嵌入其中的大金属区102。然后垂直的互连可以包括具有小直径(小于1μm)的垂直的布线12来当其延伸通过晶片的器件区1d时节省空间，和在器件区下面横向延伸且与后表面开口103的金属化的内表面连接的更大的金属区102。由此依据区102的横向的延伸，开口103从通孔12横向地分开。该方案最小化在器件区中对于垂直的互连所需的空间且同时减少互连的电阻。另外，应注意的是该方案使互连区域直接位于晶片上的器件区之下成为可能(例如，通过直接位于在区域1d中的器件之下的开口103与另一晶片的互连)。这依次允许在开口103的尺寸和位置上的弹性，且由此进一步放松了对于晶片间(在该例子中，在晶片1和2之间)的精确对准的需求。
晶片间的金属化的垂直连接可以用于热传导和电信号。例如，如图4A所示，电路径在晶片1的器件区下横向地通过以在晶片的后表面1b上在电连接开口13之间提供附加的空间。在晶片的表面中形成附加的开口113且使它们的内表面114具有金属的涂层，相似于开口13和金属涂层14。(可以以相同的工艺步骤形成开口13、113；相似地对于金属涂层14、114，可以以相同的工艺步骤形成。)附加的开口113不形成电连接的一部分，但是作为提供通过晶片叠层的热传导的路径。在晶片2的前表面2a上形成用低熔点合金材料128为帽的附加的柱栓127，如图4B所示。当在上述的工艺中晶片被键合在一起时，柱栓127与金属114在开口113中连接，以形成在晶片1和2之间的金属化的热传导路径(见图4C)。如图4C所示，柱栓127可以或可以不电连接通孔22或柱栓27。无电信号被传递至晶片1的前表面。
虽然在图4A-4C中的热传导路径显示为在晶片1和2之间形成，可以理解在上述的集成工艺的任何一个中(图1H所示的在晶片2和3之间、图3D所示的晶片5和6之间，等等)，可以使用该技术以改善在层叠中任意晶片间的热传导。
图5图示了具有与芯片(例如逻辑单元)200横向连接的垂直集成的层叠(例如高速缓冲存储单元)100的器件400，使用C4与多芯片组件(MCM)300连接。垂直存储器层叠和逻辑芯片分别具有与MCM上的C4焊盘301键合的C4焊料凸点42和242。然后MCM 300可以被集成入更大和更复杂的器件。
通过使用柱栓/通孔连接可以实现高速缓冲存储器和逻辑单元之间的靠近的连接，如图6所示。依据上述的工艺之一制备高速缓冲存储器单元401，但在聚酰亚胺层411中具有金属化的通孔420(对比图1I和2F)。在逻辑单元402上的聚酰亚胺层412中形成相似的通孔。具有互连布线嵌入其中的绝缘层450(低k介电材料，氧化物或聚酰亚胺)具有在其上形成的柱栓422以配准通孔的位置。在操作板(未显示)上可以构建层450，然后使单元401和402与柱栓422对准。在其中柱栓422与通孔中的金属焊盘421连接的键合工艺之后，从表面450b去除操作板。单元401和402的间隙403可以用合适的材料(例如聚酰亚胺)填充用于增加机械稳定性。然后组合器件(现包括存储单元401、逻辑单元402和互连层450)可以具有在表面450b上形成的C4焊盘451和C4焊料凸点452，以产生器件的外部连接。
可替换地，在引入高速缓冲存储器和逻辑单元的器件中，两者可以被集成为垂直叠层，如图7所示。组合的器件500包括与高速缓冲存储器芯片501和502集成的逻辑单元510。在该方案中，逻辑单元510位于层叠的顶部，在那里它最容易去除过量的热。
可以理解在图5-7中单元100、200、401、402、500不需要只是逻辑和/或存储器件，且实际上可以为不同的任何器件。因此，利用本发明的工艺在3-D集成器件中可以容易地组合不同的器件技术。
工艺应用
本发明一般适用于其中需要器件的高面积密度的半导体器件结构。本发明具体地适用于需要大高速缓冲存储容量的芯片，其由于中间掩模(reticle)尺寸限制或由于有限的工艺合格率不能用现有方法制造。
虽然以具体的实施例描述了本发明，考虑到以前的描述，可以发现对于本领域的技术人员，不同的替换、润饰和改变是显而易见的。因此，本发明意在包括所有这样的落在本发明和所附的权利要求的范围和精神内的替换、润饰和改变。

Claims (14)

1.一种制造包括多个垂直层叠的和互连的晶片的三维集成器件的方法，该方法包括如下步骤：
提供具有前表面(1a)和后表面(1b)的第一晶片(1)，所述第一晶片具有在邻近其所述前表面的区域(1d)中形成的器件；
在所述第一晶片中形成通孔(12)从所述前表面延伸，所述通孔由在所述前表面的横向尺寸(121)表征；
从所述第一晶片在其后表面(1b)去除材料；
在所述第一晶片的后表面中形成开口(13)，由此暴露所述通孔，所述开口具有比所述通孔的横向尺寸大的横向尺寸；
在所述开口中形成导电材料层(14)；
提供具有前表面(2a)和后表面(2b)的第二晶片(2)，所述第二晶片具有靠近其所述前表面在其中形成的器件；
在所述第二晶片的前表面上形成柱栓(27)；
在所述第二晶片的前表面(2a)上形成键合材料层(26)，所述柱栓从其中垂直地凸出；
对准所述柱栓(27)与在所述第一晶片的后表面中的开口(13)；和
利用键合材料层(26)键合所述第二晶片与所述第一晶片，以使所述柱栓与所述通孔电接触。
2.如权利要求1的所述方法，还包括如下步骤：
在所述第二晶片(2)中形成的第二晶片的通孔(22)从所述第二晶片的前表面延伸，所述第二晶片的通孔由在所述第二晶片的前表面(2a)的横向尺寸(221)表征；
从所述第二晶片在其后表面(2b)去除材料；
在所述第二晶片的后表面(2b)中形成第二晶片的开口(23)，由此暴露其中的所述第二晶片的通孔(22)，所述第二晶片的开口(23)具有大于所述第二晶片的通孔(22)的所述横向尺寸(221)的横向尺寸；
在所述第二晶片的开口中形成第二晶片的导电材料层(24)；
提供具有前表面(3a)的第三晶片(3)，所述第三晶片具有靠近其所述前表面在其中形成的器件；
在所述第三晶片的前表面(3a)上形成第三晶片的柱栓(37)；
在所述第三晶片的前表面(3a)上形成键合材料层(36)，所述第三晶片的柱栓从其中垂直地凸出；
对准所述第三晶片的柱栓(37)和在所述第二晶片的后表面中的所述第二晶片的开口(23)；
利用键合材料层(36)键合所述第三晶片和所述第二晶片，以使第三晶片的所述柱栓(37)与所述第二晶片的通孔(22)、所述第二晶片的柱栓(27)以及所述第一晶片的通孔(12)电接触。
3.如权利要求1或权利要求2的所述方法，其特征在于所述去除材料的步骤导致所述晶片具有小于20μm的厚度。
4.如权利要求1或权利要求2的所述方法，还包括如下步骤：
利用键合材料层(16)将操作板(15)贴附于所述第一晶片(1)的前表面(1a)。
5.如权利要求1或权利要求2的所述方法，还包括如下步骤：
在所述第一晶片(1)和所述第二晶片(2)之一中形成导电体(102)且与所述第一晶片(1)和所述第二晶片(2)的所述之一中的通孔(12/22)连接，所述导电体在所述第一晶片(1)和所述第二晶片(2)的所述之一的器件下横向延伸，且其特征在于在所述第一晶片(1)和所述第二晶片(2)的所述之一的后表面中的所述开口(103)依据所述导电体(102)的横向宽度从所述第一晶片(1)和所述第二晶片(2)的所述之一的所述通孔横向地分开。
6.如权利要求1或权利要求2的所述方法，还包括如下步骤：
在所述第一晶片的后表面中形成附加的开口(113)；
在所述附加的开口中形成附加的导电材料层(114)；
在所述第二晶片的前表面上形成附加的柱栓(127)；和
对准第二晶片的所述附加的柱栓(127)与在所述第一晶片的后表面中的第一晶片的附加的开口(113)；
且其特征在于键合所述第二晶片与所述第一晶片的所述步骤形成第二晶片的所述附加的柱栓(127)与第一晶片的所述附加的导电材料层(114)之间的连接用于在所述第二晶片和所述第一晶片之间传导热。
7.如权利要求6的所述方法，其特征在于所述附加的导电材料层(114)与第一晶片的通孔(12)电绝缘。
8.如权利要求2的所述方法，还包括如下步骤：
在所述第二晶片的后表面中形成第二晶片的附加的开口；
在所述第二晶片的附加的开口中形成第二晶片的附加的导电材料层；
在所述第三晶片的前表面上形成第三晶片的附加的柱栓；和
对准第三晶片的所述附加的柱栓与在所述第二晶片的后表面中的第二晶片的附加的开口；
且其特征在于键合所述第三晶片与所述第二晶片的所述步骤形成第三晶片的所述附加的柱栓与第二晶片的所述附加的导电材料层之间的连接用于在所述第三晶片和所述第二晶片之间传导热。
9.如权利要求1或权利要求2的所述方法，其特征在于所述键合材料是热塑性材料。
10.如权利要求9的所述方法，其特征在于所述热塑性材料是聚酰亚胺。
11.如权利要求1或权利要求2的所述方法，还包括如下步骤：
贴附三维集成的器件(100)于多芯片组件(300)。
12.如权利要求1或权利要求2的所述方法，还包括如下步骤：
利用柱栓-通孔连接，贴附三维集成的器件(401)于具有在其中形成的布线的绝缘层(450)。
13.如权利要求2的所述方法，其特征在于所述第一晶片和所述第二晶片具有高速缓冲存储器器件，而所述第三晶片具有逻辑器件。
14.如权利要求2的所述方法，其特征在于所述第一晶片、所述第二晶片和所述第三晶片的至少之一包括MEMS器件。
CNB028300335A 2002-12-20 2002-12-20 三维器件制造方法 Expired - Fee Related CN100383936C (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2002/041181 WO2004059720A1 (en) 2002-12-20 2002-12-20 Three-dimensional device fabrication method

Publications (2)

Publication Number Publication Date
CN1708840A CN1708840A (zh) 2005-12-14
CN100383936C true CN100383936C (zh) 2008-04-23

Family

ID=32679941

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028300335A Expired - Fee Related CN100383936C (zh) 2002-12-20 2002-12-20 三维器件制造方法

Country Status (9)

Country Link
EP (1) EP1573799B1 (zh)
JP (1) JP4575782B2 (zh)
CN (1) CN100383936C (zh)
AT (1) ATE456860T1 (zh)
AU (1) AU2002368524A1 (zh)
DE (1) DE60235267D1 (zh)
IL (1) IL169264A0 (zh)
TW (1) TWI242249B (zh)
WO (1) WO2004059720A1 (zh)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060249753A1 (en) * 2005-05-09 2006-11-09 Matrix Semiconductor, Inc. High-density nonvolatile memory array fabricated at low temperature comprising semiconductor diodes
WO2006018787A2 (en) * 2004-08-20 2006-02-23 Philips Intellectual Property & Standards Gmbh Method of detaching a thin semiconductor circuit from its base
US7262495B2 (en) * 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
US7485968B2 (en) * 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US20090039482A1 (en) * 2005-08-31 2009-02-12 Jiangqi He Package Including a Microprocessor & Fourth Level Cache
US7723759B2 (en) * 2005-10-24 2010-05-25 Intel Corporation Stacked wafer or die packaging with enhanced thermal and device performance
FR2894070B1 (fr) * 2005-11-30 2008-04-11 3D Plus Sa Sa Module electronique 3d
JP4797677B2 (ja) * 2006-02-14 2011-10-19 旭硝子株式会社 マルチチップ素子とその製造方法
US7344959B1 (en) * 2006-07-25 2008-03-18 International Business Machines Corporation Metal filled through via structure for providing vertical wafer-to-wafer interconnection
US8032711B2 (en) * 2006-12-22 2011-10-04 Intel Corporation Prefetching from dynamic random access memory to a static random access memory
GB2449853B (en) 2007-06-04 2012-02-08 Detection Technology Oy Photodetector for imaging system
JP5570689B2 (ja) * 2007-07-23 2014-08-13 ピーエスフォー ルクスコ エスエイアールエル 積層メモリ
EP2075828A1 (en) 2007-12-27 2009-07-01 Interuniversitair Microelektronica Centrum (IMEC) Semiconductor device and a method for aligining and bonding a first and second element for the fabrication of a semiconductor device
US8486823B2 (en) * 2008-03-07 2013-07-16 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming through via
US9136259B2 (en) * 2008-04-11 2015-09-15 Micron Technology, Inc. Method of creating alignment/centering guides for small diameter, high density through-wafer via die stacking
US7821107B2 (en) * 2008-04-22 2010-10-26 Micron Technology, Inc. Die stacking with an annular via having a recessed socket
US8853830B2 (en) * 2008-05-14 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
WO2009146588A1 (en) * 2008-06-05 2009-12-10 Hong Kong Applied Science And Technology Research Institute Co., Ltd.. Bonding method for through-silicon-via based 3d wafer stacking
JP4947316B2 (ja) 2008-08-15 2012-06-06 信越化学工業株式会社 基板の接合方法並びに３次元半導体装置
JP4911143B2 (ja) 2008-08-15 2012-04-04 信越化学工業株式会社 高温耐性接着剤組成物、基板の接着方法、及び３次元半導体装置
US8129256B2 (en) 2008-08-19 2012-03-06 International Business Machines Corporation 3D integrated circuit device fabrication with precisely controllable substrate removal
DE102009004725A1 (de) * 2009-01-15 2010-07-29 Austriamicrosystems Ag Halbleiterschaltung mit Durchkontaktierung und Verfahren zur Herstellung vertikal integrierter Schaltungen
TWI402941B (zh) * 2009-12-03 2013-07-21 Advanced Semiconductor Eng 半導體結構及其製造方法
CN102683265A (zh) * 2011-03-15 2012-09-19 中国科学院微电子研究所 一种将碳纳米管束填充到硅转接板的硅穿孔中的方法
GB201108425D0 (en) 2011-05-19 2011-07-06 Zarlink Semiconductor Inc Integrated circuit package
US8829684B2 (en) 2011-05-19 2014-09-09 Microsemi Semiconductor Limited Integrated circuit package
KR102235927B1 (ko) 2011-05-24 2021-04-05 소니 주식회사 반도체 장치
JP2013042052A (ja) * 2011-08-19 2013-02-28 Nec Corp 半導体装置の製造方法
JP2013098514A (ja) * 2011-11-07 2013-05-20 Seiko Epson Corp 半導体装置の製造方法及び半導体装置、電子機器
JP2013201240A (ja) * 2012-03-23 2013-10-03 Toshiba Corp 半導体装置の製造方法および半導体基板支持用ガラス基板
TWI540710B (zh) 2012-06-22 2016-07-01 Sony Corp A semiconductor device, a method for manufacturing a semiconductor device, and an electronic device
TWI487041B (zh) * 2012-08-08 2015-06-01 Subtron Technology Co Ltd 封裝載板及其製作方法
CN103107128B (zh) * 2013-01-14 2014-12-17 武汉新芯集成电路制造有限公司 一种三维芯片结构的金属键合的方法
JP2014170793A (ja) * 2013-03-01 2014-09-18 Fujitsu Semiconductor Ltd 半導体装置、半導体装置の製造方法及び電子装置
JP5939184B2 (ja) 2013-03-22 2016-06-22 ソニー株式会社 半導体装置の製造方法
US9136233B2 (en) 2013-06-06 2015-09-15 STMicroelctronis (Crolles 2) SAS Process for fabricating a three-dimensional integrated structure with improved heat dissipation, and corresponding three-dimensional integrated structure
CN104008998B (zh) * 2014-06-10 2016-08-03 山东华芯半导体有限公司 多芯片层叠封装方法
WO2015195084A1 (en) * 2014-06-16 2015-12-23 Intel Corporation Embedded memory in interconnect stack on silicon die
US9633917B2 (en) * 2015-08-20 2017-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit structure and method of manufacturing the same
CN107994043A (zh) * 2017-12-11 2018-05-04 德淮半导体有限公司 晶圆、堆叠式半导体装置及其制造方法
CN109727848B (zh) * 2018-12-29 2020-09-01 长江存储科技有限责任公司 一种三维存储器的制造方法
JP7329601B2 (ja) 2019-01-30 2023-08-18 長江存儲科技有限責任公司 半導体デバイス、接合構造および半導体デバイスを形成するための方法
JP7214871B2 (ja) 2019-01-30 2023-01-30 長江存儲科技有限責任公司 半導体デバイス、接合構造および半導体デバイスを形成するための方法
US11545435B2 (en) 2019-06-10 2023-01-03 Qualcomm Incorporated Double sided embedded trace substrate
CN111106022A (zh) * 2019-12-30 2020-05-05 武汉新芯集成电路制造有限公司 一种键合结构及其制造方法
US11581281B2 (en) * 2020-06-26 2023-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Packaged semiconductor device and method of forming thereof
US12040296B2 (en) 2022-01-12 2024-07-16 Changxin Memory Technologies, Inc. Semiconductor structure and method for manufacturing semiconductor structure
CN116469857A (zh) * 2022-01-12 2023-07-21 长鑫存储技术有限公司 一种半导体结构及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4939568A (en) * 1986-03-20 1990-07-03 Fujitsu Limited Three-dimensional integrated circuit and manufacturing method thereof
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5424245A (en) * 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
CN1204154A (zh) * 1997-04-08 1999-01-06 日本电气株式会社 具有多层互连结构的半导体器件
US6093969A (en) * 1999-05-15 2000-07-25 Lin; Paul T. Face-to-face (FTF) stacked assembly of substrate-on-bare-chip (SOBC) modules
US6444560B1 (en) * 2000-09-26 2002-09-03 International Business Machines Corporation Process for making fine pitch connections between devices and structure made by the process

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1514818A1 (de) * 1951-01-28 1969-05-08 Telefunken Patent Festkoerperschaltung,bestehend aus einem Halbleiterkoerper mit eingebrachten aktiven Bauelementen und einer Isolierschicht mit aufgebrachten passiven Bauelementen und Leitungsbahnen
JPS60140850A (ja) * 1983-12-28 1985-07-25 Hitachi Ltd 積層集積型半導体回路装置の製法
JPS60160645A (ja) * 1984-02-01 1985-08-22 Hitachi Ltd 積層半導体集積回路装置
JPS62117316A (ja) * 1985-11-16 1987-05-28 Sharp Corp 半導体装置
JPS63142663A (ja) * 1986-12-04 1988-06-15 Sharp Corp 半導体装置とその製造方法
US4889832A (en) * 1987-12-23 1989-12-26 Texas Instruments Incorporated Method of fabricating an integrated circuit with metal interconnecting layers above and below active circuitry
US4982266A (en) * 1987-12-23 1991-01-01 Texas Instruments Incorporated Integrated circuit with metal interconnecting layers above and below active circuitry
US5091331A (en) * 1990-04-16 1992-02-25 Harris Corporation Ultra-thin circuit fabrication by controlled wafer debonding
US5376561A (en) * 1990-12-31 1994-12-27 Kopin Corporation High density electronic circuit modules
JPH0555534A (ja) * 1991-08-22 1993-03-05 Seiko Instr Inc 積層型半導体装置の製造方法
US5268326A (en) * 1992-09-28 1993-12-07 Motorola, Inc. Method of making dielectric and conductive isolated island
US5426072A (en) * 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
EP1178530A2 (en) * 1993-09-30 2002-02-06 Kopin Corporation Three-dimensional processor using transferred thin film circuits
US5627106A (en) * 1994-05-06 1997-05-06 United Microelectronics Corporation Trench method for three dimensional chip connecting during IC fabrication
US5814889A (en) * 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
US5807783A (en) * 1996-10-07 1998-09-15 Harris Corporation Surface mount die by handle replacement
US5786238A (en) * 1997-02-13 1998-07-28 Generyal Dynamics Information Systems, Inc. Laminated multilayer substrates
JP4032454B2 (ja) * 1997-06-27 2008-01-16 ソニー株式会社 三次元回路素子の製造方法
JP4063944B2 (ja) * 1998-03-13 2008-03-19 独立行政法人科学技術振興機構 ３次元半導体集積回路装置の製造方法
JP2001326325A (ja) * 2000-05-16 2001-11-22 Seiko Epson Corp 半導体装置及びその製造方法
JP4123682B2 (ja) * 2000-05-16 2008-07-23 セイコーエプソン株式会社 半導体装置及びその製造方法
JP3951091B2 (ja) * 2000-08-04 2007-08-01 セイコーエプソン株式会社 半導体装置の製造方法
JP4560958B2 (ja) * 2000-12-21 2010-10-13 日本テキサス・インスツルメンツ株式会社 マイクロ・エレクトロ・メカニカル・システム
US6489217B1 (en) * 2001-07-03 2002-12-03 Maxim Integrated Products, Inc. Method of forming an integrated circuit on a low loss substrate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4939568A (en) * 1986-03-20 1990-07-03 Fujitsu Limited Three-dimensional integrated circuit and manufacturing method thereof
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5424245A (en) * 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
CN1204154A (zh) * 1997-04-08 1999-01-06 日本电气株式会社 具有多层互连结构的半导体器件
US6093969A (en) * 1999-05-15 2000-07-25 Lin; Paul T. Face-to-face (FTF) stacked assembly of substrate-on-bare-chip (SOBC) modules
US6444560B1 (en) * 2000-09-26 2002-09-03 International Business Machines Corporation Process for making fine pitch connections between devices and structure made by the process

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Three- dimensional (3D) ICs: a technology platform forintegrated systems and opportunities for new polymericadhesives. R. J. Gutmann, J. Q. Lu, Y. Kwon, et al..Polymers and Adhesives in Microelectronics and Photonics, 2001. First International IEEE Conference. 2001 *

Also Published As

Publication number Publication date
TW200520108A (en) 2005-06-16
JP2006522461A (ja) 2006-09-28
JP4575782B2 (ja) 2010-11-04
ATE456860T1 (de) 2010-02-15
WO2004059720A1 (en) 2004-07-15
EP1573799B1 (en) 2010-01-27
EP1573799A4 (en) 2009-02-25
IL169264A0 (en) 2007-07-04
EP1573799A1 (en) 2005-09-14
DE60235267D1 (de) 2010-03-18
AU2002368524A1 (en) 2004-07-22
CN1708840A (zh) 2005-12-14
TWI242249B (en) 2005-10-21

Similar Documents

Publication Publication Date Title
CN100383936C (zh) 三维器件制造方法
US7354798B2 (en) Three-dimensional device fabrication method
KR100441698B1 (ko) 반도체 디바이스 및 그 제조 방법
US10177130B2 (en) Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener
US5898223A (en) Chip-on-chip IC packages
US10177090B2 (en) Package-on-package semiconductor assembly having bottom device confined by dielectric recess
US6864165B1 (en) Method of fabricating integrated electronic chip with an interconnect device
CN100495694C (zh) 半导体器件
CN101515554B (zh) 半导体器件的制造方法、半导体器件以及配线基板
TWI619210B (zh) 介電材凹穴內設有半導體元件之面朝面半導體組體
CN108695274A (zh) 三维整合的散热增益型半导体组件及其制作方法
CN101752270A (zh) 堆叠集成电路半导体晶粒的形成方法
WO2021018014A1 (zh) 一种基于tsv的多芯片的封装结构及其制备方法
CN109686715A (zh) 适用于可堆叠式半导体组件的具有凹穴的互连基板及其制法
CN101542701A (zh) 基于硅通孔的三维晶圆叠层的键合方法
CN115312496A (zh) 基于后通孔技术的三维半导体集成封装结构及工艺
KR100621960B1 (ko) 3차원 디바이스 제조 방법
CN107230640A (zh) 具散热座及双增层电路的散热增益型半导体组件及其制法
TWI657555B (zh) 三維整合之半導體組體及其製作方法
TW201940026A (zh) 具有嵌埋式元件及加強層之線路板、其製法及其面朝面半導體組體
TWI611530B (zh) 具有散熱座之散熱增益型面朝面半導體組體及製作方法
CN110223971A (zh) 具有散热特性的三维可堆叠式半导体组体
CN112331635B (zh) 一种基于转接板的垂直封装结构及封装方法
CN108400118A (zh) 三维整合的半导体组件及其制作方法
CN108400117A (zh) 三维整合的散热增益型半导体组件及其制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20080423

Termination date: 20181220

CF01 Termination of patent right due to non-payment of annual fee