TWI242249B - Three-dimensional device fabrication method - Google Patents

Three-dimensional device fabrication method Download PDF

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Publication number
TWI242249B
TWI242249B TW092133840A TW92133840A TWI242249B TW I242249 B TWI242249 B TW I242249B TW 092133840 A TW092133840 A TW 092133840A TW 92133840 A TW92133840 A TW 92133840A TW I242249 B TWI242249 B TW I242249B
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Taiwan
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wafer
channel
opening
wafers
front surface
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TW092133840A
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English (en)
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TW200520108A (en
Inventor
H Bernhard Pogge
Roy Yu
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Ibm
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1242249 玖、發明說明： 【發明所屬之技術領域】 置，更特定言 本發明係關於製造極大規模整合半導體穿 之，係關於三維、垂直互連晶片之製造方法 【先前技術】 你支處理裔晶片一般包含一趣輯單元此％ y 斗早兀及快取記憶體。如果 微處理器的邏輯單元及記憶體萝 奴衣置均以二維 (tW〇-dimensional; 2-D)圖案配置，則晶片實體尺寸的限制 (由曰大面積晶片的不良製程良率所造成）會限制快取記憶體 數量。因此，微處理器的性能會受到嚴格限制。 為了解決向微處理器提供足夠快取記憶體的問題（以及 更一般而言，晶片上的2-D資源問題），許多研究人員正探 究建立三維（three-dimensional ; 3_D)積體電路之方法。一 典型的3—D製造程序包括：在厚度小於2〇 _的晶圓上建立 裝置；提供穿過該等晶圓的垂直互連；堆疊該等晶圓以便 在不同層晶圓之間建立垂直連接；以及使用一適當材料焊 接該等晶圓。請參考（例如）材料研究學會1；1^1 χνπ次會 議學報151(2002)上由J.-Q· Lu等人所著的「在2〇〇 mm晶圓 上使用介電膠水焊接的3D IC技術之通道鏈測試結構之製 造」；材料研究學會先進金屬化會議159(2〇〇2)上由p. Ramm 等人所著的「用於垂直系統整合之使用銅的晶片間通道技 術」，IEEE國際互連技術會議學報〗57 (2〇〇1)上由尺扎⑺抓等 人所著的「二維積體電路之熱分析」。在目前最新的3_d整 合技術中重要的問題包括··（1)需要進行可靠的晶圓焊接；
O:\89\89743.DOC 1242249 (2)要求嚴格的晶圓清潔及平整 曰片Η千古„ (3)而要可罪、低阻抗的 曰曰片間垂直連接；（4)要求嚴格 n rc\^ ^ ^ 日日Q至日日圓橫向配準，·以 及（5)兩要牙過該3_D裝置的有效熱傳導。 ^國專利第MW號「用於在裝置間進行微細間距 連接^方法及根據該方法所製成之結構」中揭示—種Μ晶 片至曰a片互連之方法’該專利⑽渡給目際商業機器公司， 其揭示内容以提及方式併入本文中。如該專利案中指出， 具有不同功能或者不同材料的晶片可經由一聚醯亞胺的佈 線層連接，在該佈線層與各晶4之卩枝用凸塊/通道連接。 可將該專利案中提及的技術延伸，以實現3_d晶片級及晶圓 級整合。 【發明内容】 本發明對上述問題之解決係藉由提供一種製造三維整合 裝置之方法，該裝置包含複數個垂直堆疊並且互連的晶圓， 其中該等晶圓可彼此牢固焊接，因此可放鬆對晶圓平整度 及晶圓間高精確度對準之要求。為了垂直連接第一晶圓及 第二晶圓，在該第一晶圓内形成一從前表面延伸之通道， 遠通道的特徵為在該前表面的一橫向尺度。在第一晶圓的 後表面將材料從該第一晶圓移除，使該晶圓變薄至2〇 μπ1以 下。在該第一晶圓的後表面中形成一開口，從而曝露該通 道，該開口的一橫向尺度大於該通道的橫向尺度。在該開 口内形成一傳導材料層。在第二晶圓的前表面上形成一凸 塊及一焊接材料層，該等凸塊從此處垂直伸出。然後，將 凸塊對準第一晶圓後表面中的開口，使用焊接材料層將該 O:\89\89743.DOC -7 - 1242249 等晶圓焊接，使該凸塊與該通道電接觸。為了使三個晶圓 互連，第二晶圓進一步具有一從該晶圓前表面延伸的通道 並且藉由在第二晶圓後表面將材料從第二晶圓移除，使第 二晶圓變薄。在第二晶圓的後表面形成一開口，從而曝露 其内的通道；該開口的橫向尺度大於該通道的橫向尺度。 在該開口内形成一傳導材料層。第三晶圓的前表面上形成 一焊接材料層及一凸塊，該凸塊與第二晶圓後表面中的開 口對準。然後，使用焊接材料層將第三晶圓焊接至第二晶 圓，使第三晶圓的凸塊與第二晶圓的通道、第二晶圓的凸 塊以及第一晶圓的通道電接觸。 依據本發明，各晶圓中的通道無需從該等晶圓的前表面 垂直延伸至後表面。一傳導體配置於晶圓内裝置區域之下 並且橫向延伸，其可藉由後表面中的金屬化開口連接該通 道。因此，穿過該晶圓的傳導路徑可導入該等裝置之下。 焊接層最好係熱塑材料，特定言之可為聚醯亞胺。其允許 在平整度及清潔度較不嚴格的要求下焊接晶圓。 在第一晶圓的後表面可形成額外的開口，以連接至第二 晶圓前表面上的額外凸塊中該等額外開口及凸塊盘通 道絕緣。此等額外連接係作為晶圓間的垂直熱傳導路徑。 本土月Λ現了具有可靠電連接及晶圓間熱傳導改進 的3-D垂直整合。 【實施方式】 依據本發明，可堆聂月击古=土 隹且及金直互連複數個其上形成有裝置 的薄晶圓。在本文所沭沾目舰命 斤这的具體實施例中會製造及連接一三
O:\89\89743.DOC 1242249 一 $，應明白其僅用於說明之目的，因此該程序適用於 二層以上或以下的情況。3 _ D垂直整合裝置可以兩種方式構 造，說明如下。 (1)頂面朝下的晶圓堆疊程序 ° 、員示θ曰圓1的斷面，在晶圓前表面1 a附近的區域1 d 口 /、有I置及數層南密度的互連佈線11(通常為
Cu),。在該晶圓内形成金屬化通道12，其在裝置區域“下延 伸亚且杈向互連；此等通道在晶圓1變薄後會成為垂直穿過 連接之部分。通道12通常係藉由在晶圓1中蝕刻穿孔而形 成’在穿孔的側邊及底部形成一線性材料層，然後用金屬 (最好為銅）填充穿孔。通道12的深度小於晶圓1變薄後的最 終厚度；因此，如果變薄後的晶圓厚度係大約i〇pm，則通 迢的深度小於10 μιη。通道121的直徑必須經由選擇以平衡 熱傳導及空間問題。大約i μη1的直徑可佔用晶圓表面的最 J工間同日守可提供允許穿過晶圓的熱傳導；可使用更小 的通道直徑，但其可能不足以進行穿過垂直晶圓堆疊的熱 傳導。 為方便說明起見，所示通道12係以均勻直徑直接向下延 伸至晶圓上該等裝置下方的一區域内。在實務中，通道的 尺寸要求實質上可放鬆至區域1(1以下。包括在裝置下方橫 向延伸的穿過連接的其他配置亦可，詳細說明如下。 為了有助於處理變薄晶圓，將一處理板（通常為玻璃）15 附著於晶圓的前表面la。晶圓丨與板15係使用一熱塑焊接材 料（最好為聚酿亞胺）層1 6彼此焊接。
O:\89\S9743.DOC 1242249 褙田對月面lb進行研磨或拋光 (見圖1B)使晶圓變薄。得到的曰 伃則的日日0 1厚度小於20 μηι，最好 為大約10 μηι。如圖1Β所示，響& + 土胃十 又厚％序在未曝露通道12底部 即停止。 接著’在晶圓的後表面叫_開口13，使通道12的底 部曝露(圖1C)。通道内的金屬自身可作為對該程序的一蝕 刻終止；或者，可在晶圓的另一部分（其上沒有裝置）提供一 钱刻終止層，用以控制該程序。應注意，開口㈣直徑大 於通道12的直徑。雖然通道可有大量配置（進-步說明如 下），但後表面lb的開口一般大於前表面“的通道。 然後，用金屬對開口 13的内表面14進行塗佈（最好藉由喷 濺），以便與對應通道12的底端接觸，從而形成一穿過晶圓 1的傳導路徑。應注意，開口 13的直徑大於（通常為兩倍大） 對應通道12的直徑；其有助於與另一晶圓的垂直連接。 圖1D顯示第二晶圓2,其與晶圓}垂直整合。與晶圓}相似， 曰曰圓2上形成有叙置及互連佈線21。此外，金屬化通道κ(通 常填充有銅）向下延伸至晶圓2中；通道22在表面2a處具有 k向尺度221。在晶圓2的前表面2a上沈積一聚醯亞胺層26。 在表面2a上形成凸塊27，其在層26的頂部表面上延伸，距 離通常為5 μηι或以下。凸塊27可由Ni、Cu、鍍Ni的Cu、W 或其他一些金屬或金屬組合而形成。在凸塊表面上沈積一 低炼點的合金材料層28 ;其有助於在垂直接合之晶圓1與晶 圓2的程序中形成電連接。該合金材料通常為90/10 Pb/Sn 的焊料’厚度為2 μπι或以下；替代合金材料包括Au/sn&
O:\89\89743.DOC -10- 1242249 /Ag省合金材料可接受熱回流處理，因此該層μ為圓形 圖1D所示，其有助於晶圓2上的凸塊與晶圓1中的對應開 對準"亥等凸塊使電連接從晶圓2的各裝置垂直向上延 伸，同時通道22使電連接垂直向下延伸。 然後，使料接及層壓程序將晶圓i(其附著於處理板⑺ 寸著於日日圓2。如圖1E所不，晶圓2上的凸塊27係與晶圓工 勺開口 13配準，同時晶圓i的後表面丨b與聚醯亞胺層％ 的前表面接觸。執行層壓程序的溫度與壓力應足以：⑴保 證晶圓i與層26之間的焊接；以及⑺保證凸塊27與金屬 14(及由此至通道12)之間的電接觸。根據所用材料，溫度範 圍可為20(TC至4〇(rC，而壓力範圍可為i〇psi至綱叫。如 圖1E所示，焊接及層壓程序使焊料28流動，從而使焊料部 分或完全地填充開口 13。 應注意’開口 13的直徑大於凸塊27，因此在晶圓2相對於 晶圓1的橫向放置中可允許不精確。此外，應注意表面ib 與2a並非直接接觸，而是有層％在中間。聚酿亞胺層％的 厚度足以覆蓋小的表面顆粒；填滿較小的表面瑕疵；或者 調整兩個晶圓平整度上的不同。因此，保證在晶圓之間進 行可靠機械焊接中的層26的作用重大，同時凸塊/通道連接 27_28-14_12亦提供可靠的垂直電連接。 然後，將晶圓2(現焊接於晶圓υ變薄至小於2〇叫，最好 為大約10 pm。如圖1F所示，在晶圓2的後表面沘中形成開 口 23,使通道22的底部曝露。用金屬24(最好與晶圓i一樣 藉由喷錢）塗佈開口23的内表面’以提供與另一晶圓3的電
O:\89\89743.DOC -11 - 1242249 連接。 。圖1G顯不用於焊接至晶圓丨及2的晶圓3之製備程序。在晶 圓3此的前表面附近亦具有裝置及互連佈線31。為了與晶圓2 勺月面屯接觸，凸塊37係形成於晶圓3的正面3a。凸塊37的 表面上/、有合金材料38 ,分別與晶圓2上的凸塊”及合金材 料28相似。與層26相似，在表面^上亦沈積一聚驢亞胺層 36在該"兄明中，晶圓3係垂直堆疊中要焊接的最後晶圓； 因此’曰曰圓3不用變薄（以提供堆疊的機械強度），並且無需 穿過晶圓的通道。 圖1H顯示晶圓3焊接及㈣程序之結果。用合金材料％ 、、]23並且知接至金屬層24後，其結果使凸塊37與通 道22電接觸。聚酿亞胺層36焊接於晶圓2的表面❹，與晶圓 1及a曰圓2之間的層26相似。由於未變薄的晶圓3向變薄的晶 圓1及2提供機械強度’因此不再需要處理板15，從而可: 此時移除。其可藉由雷射刻除方便地完成；即如果板_ 於刻除輻射係透明的，則可使用-雷射來刻除板與層16 之間的介面，從而使該板分離。 々圖u所不’垂直互連的晶圓堆疊可附著外部連接。 圖11顯示（例如）詩連接垂直堆疊至—較大裝置中其他組 件之C4技術。在層16中形成開口 4()，以曝露晶圓丨的金屬化 通道U後在開口内沈積金屬襯塾41。接著，使用（例如） 本技術中已知的焊料遮罩技術在此等襯墊上形成C4焊塊 42。然後’準備將完整垂直整合裝置1〇〇焊接至一多晶片模 組（multichip module; MCM)或類似物上的c4概墊。、
O:\89\89743.DOC -12 - 1242249 應注意，晶圓1、2及3的内部結構僅為示意性說明；實際 上，此等晶圓可由各種方法製造並且具有不同功能。例如， 全部三個晶圓可具有快取記憶體裝置；晶圓1及2可具有記 $體而晶圓3可具有邏輯裝置；一或多個該等晶圓可併入微 黾子黾機系統（micr〇-electr〇mechanicai systems ; 等。 本务明者已發現要保證成功的晶圓級垂直整合係藉由·· ()將日日圓、交薄至大約1 〇 μιη，以使通道内的垂直熱傳導問 題取小化；（2)將聚醯亞胺用作熱塑焊接材料，以放鬆晶圓 的平整度及清潔度要求；以及（3)使用凸塊/通道連接，其中 为面通道開口實質上大於凸塊，以放鬆橫向配準要求。 (2)底面朝上的晶圓堆疊程序 在圖2Α至2Ε中顯示焊接垂直堆疊晶圓的替代性程序，·該 程序詳細針對三個晶圓，但如上所述，可適用於更多或更 夕的曰曰圓。首先，依據圖1Aslc所示程序製備一晶圓工； 然後將該晶圓變薄至大約1〇μηι ;在後表面上形成金屬化通 迢12及開口 13 ;以及用一聚醯亞胺層16將處理板^附著於 雨表面。 然後’如圖2Α所示製備第二晶圓5，其具有橫向互連佈線 51。與上述程序（與圖1D比較）中的晶圓2相似，晶圓5且有 通道52及連同合金材料58的凸塊57。向晶圓5提供—處理板 Μ ;用聚醯亞胺塗層56覆蓋該板55，圖案化該塗層使其容 =凸塊57。然後’將晶圓5焊接至處理板55，其允許晶圓變 溥(圖2Β)。在變薄晶圓的背面5b中形成開口 ，並且如上 所述用金屬層54塗佈開口的内表面。
O:\89\89743.DOC -13 - 1242249 由於晶圓1及5均具有各自的處理板15及55，因此可分別 製備、焊接及變薄。 如圖2C所示製備第三晶圓6，其具有橫向互連佈線^。該 晶圓（與圖1G所示的晶圓3相似）的前表面上具有聚酿亞胺 層66及凸塊67,並且在凸塊表面上具有合金材料68，用以 與其他晶圓進行垂直電連接。凸塊67從層66伸出—足夠距 離，以便與晶圓5上的金屬層54接觸（即大約為5μιη)。接著， 將晶圓5及6焊接及層壓在一起，如圖2〇所示。由於晶圓6 未文薄，因此在烊接程序後無需處理板55，從而將其移除。 此時，晶圓5前表面5a上的層56的厚度減小，從而使凸塊” 的高度曝露大約5卿。接著，凸塊57準備焊接至晶,的金 屬層14 °圖2E顯不該焊接程序的結果，其中堆疊的晶圓$ 及6接合至晶圓丨；合金材料58填充變薄晶圓！中的開口 η， 以便與金屬層14電接觸，以及由此與通道Η電接觸。晶圓$ 及6焊接至晶圓丨後，不再需要處理板15，於是可將其移除， 從而曝露層16。然後，可在層16中形成開口 40,以及形成 孟屬襯墊41及C4焊塊42以連接至通道12(圖2F，與圖^比 較）。 應明白，上述用於堆疊複數個變薄晶片以及併入晶片至 晶片垂直互連之技術，大大增加了晶片内容及功能，而不 會增加其區域（二維）尺寸。此等程序對於具有相同内容的晶 片而口尤其有利’因為各變薄及堆疊的晶片可具有相同尺 寸/、進而使得裝置的整個處理程序極大簡化且更加經濟。 應主思此等程序允許晶圓級晶片至晶片互連，因此與單
O:\89\89743.DOC -14- 1242249 造3-D晶片的程 比，本發明中 而係直接穿過 晶片的垂直放置、焊接及互連程序相比，製 序更加便宜。與先前所述的垂直互連方案^目 的日曰片至曰日片互連並非沿晶片的側邊進行， 该晶片而形成。 报明顯隨著堆叠晶圓厚度(大約為1〇_)的減小，晶片間 (如快取記憶體單元之間）的互連長度大大切此類晶片的 w配置。除了節約二維空間之外，其亦在改進裝置性能上 提供更多優點。 在圖1A至II及2AS2F中，為了方便說明起見，所示通道 向下-直延伸穿過該等晶圓並且直徑保持一致。對於垂直 的曰曰片至曰曰片互連而言，無需用一小直徑穿過晶圓的全部 厚度，即使係整個厚度為1〇 _的變薄晶圓。例如，如圖3 所不，製備晶圓1時可將一大的金屬區域1〇2後入晶圓i中。 於疋，垂直互連可包含一小直徑（小Mi㈣的垂直線12， 田L伸牙過日日圓的裝置區域丨d時用以節約空間；以及一 大得多的金屬區域102，其在裝置區域下方橫向延伸並且與 月面開口 103的金屬化内表面連接。因此，開口 1〇3根據區 域102的橫向延伸長度與通道12橫向分開。該配置使垂直互 連在裝置區域内所需的空間最小化，同時降低互連的阻抗。 此外，應注意該配置使互連區域直接位於晶圓上裝置區域 的下方成為可能（例如，穿過開口 1〇3而與另一晶圓連接的 互連在區域id内直接位於裝置下方）。其進而允許開口 M3 的尺寸及位置可具有靈活性，因此進一步放鬆晶圓間（在該 範例中為晶圓1與2之間）精確對準的需要。
O:\89\89743.DOC -15- 1242249 曰曰圓間的金屬化垂直連接可用於熱傳導及用於電信號。 例如，如圖4A所示，一電性路徑在晶圓丨的裝置區域下方橫 向订進，以在晶圓背面1b上電連接開口 13之間提供額外空 間。在晶圓表面中形成額外開口 113，並且用金屬塗佈其内 部表面114，與開口 13及金屬塗層14相似。（開口 13、113可 在相同步驟中形成，金屬塗層14、114亦然。）額外開口 113 不冒形成電連接之部分，而用於提供一穿過晶圓堆疊的熱 傳導路徑。如圖4B所示，在晶圓2的前表面。上形成覆蓋有 麟點合金材料128的額外凸塊127。當晶圓在上述程序中 焊接在起時，凸塊127與開口 in内的金屬114連接，從而 在曰曰圓1與2之間形成一金屬化熱傳導路徑（見圖4c)。如圖 4C所不，凸塊127可與或不可與通道或凸塊w電連接；未 有電信號載送至晶圓1的前表面。 雖；、、、;圖4A至4C中所示的熱傳導路徑形成於晶圓i與2之 4應月白’在上述整合程序中該技術可用於改進堆疊 中任何晶圓間的熱傳導（圖1H所示的晶圓2與3之間；圖扣 所示的晶圓5與6之間等）。 圖5顯不具有一垂直整合堆疊（如一快取記憶體單元）100 橫向連接至一晶片（如一邏輯單元）200的裝置400，使用C4 連接將4衣置連接至一多晶片模組（mcm) 。該垂直記 版堆$及邏輯晶片分別具有C4焊塊42及，焊接至 MCM上的C4襯墊301。然後，該MCM 3〇〇整合入一更大且 更複雜的裝置。 如圖6所示，藉由使用凸塊/通道連接可在快取記憶體與
O:\89\89743.DOC -16- 1242249 邏輯單元之間實現較近連接。快取記憶體單元4〇 1根據上述 程序之一進行製備，然而在聚醯亞胺層411中具有金屬化通 道42 0(與圖II及2F比較）。在邏輯單元402上的聚醯亞胺層 412中形成相似通道。一絕緣層45〇(由低匕介電材料、氧化 物或聚酸亞胺製成）中嵌入互連佈線，該絕緣層上形成的凸 塊422係用於匹配通道的位置。隨著單元4〇1及402與凸塊 422對準後，可在處理板（未顯示）上形成層45〇 ;在凸塊422 與通道内的金屬襯墊42 1連接的焊接程序之後，將處理板從 表面45 0b移除。單元401與402之間的間隙403可用適當的材 料（如聚醯亞胺.)填充，以增強機械穩定性。然後，該合併裝 置（現在包含§己憶體單元4〇1、邏輯單元4〇2及互連層45〇)的 表面450b上可形成C4襯墊451&C4焊塊452，用以形成該裝 置的外部連接。 或者，在合併快取記憶體及邏輯單元的裝置中，兩者均 可整合於一垂直堆疊，如圖7所示。合併裝置5〇〇包含整合 有快取記憶體晶片50丨及“]的邏輯單元51〇。在該配置中， 邏輯單元510在堆疊的頂部，該處最易消除過度熱量。 應月白’圖5至7的單元1〇〇、2〇〇、4〇1、4〇2、5〇〇無需僅 僅係邏輯及/或記憶體裝置，實際上可為任何各種裝置。因 此’使用本發明之方法可將不同的裝置技術輕易併入W整 合裝置。 〈工業上可應用性 本t月般可應用於需要高區域密度裝置的半導體裝置 -構本發明尤其可應用於需要大記憶體快取内容的晶片，
O:\89\89743.DOC -17- 1242249 其由於光罩尺寸限制或由於有 可用方法製造。 限的製裎良率 無法用目前的 雖然已根據特定具體實施例對本發明進行了說明，缺而 根據上述說明，很明顯熟悉本技術人士可進行許多 修改及變更。因此，本發明包括屬於隨附申請專利範曰圍及 本發明之範圍及精神内的全部此類替代、修改及變更。 【圖式簡單說明】 圖1Α·係依據本發明之第一項具體實施例顯示… 整合裝置的製造程序中各步驟之示意圖。 圖2Α至2F係依據本發明之第二項具體實施例顯示_3_d 整合裝置的製造程序中各步驟之示意圖。 圖3係顯示晶圓之間的垂直互連，其依據本發明在晶圓的 裝置區域之下橫向延伸。 圖4A至4C顯示一依據本發明之製造程序，亦用於改進一 3-D整合裝置中的熱傳導。 圖5顯示包含一邏輯單元及一 3_!)堆疊記憶體單元的完整 4處理器裝置’该記憶體單元係依據本發明製造，其中該 等邏輯及記憶體單元係以使用C4技術的2-D互連方案連接 於多晶片模組（MCM)上。 圖6顯示包含一邏輯單元及一 3-D堆疊記憶體單元之完整 微處理器裝置，該記憶體單元係依據本發明製造，其中該 等邏輯及記憶體單元係以使用凸塊/通道連接的2-D傳輸與 接合（transfer and join ; T&J)互連方案進行連接。 圖7顯示包含一邏輯單元及一記憶體單元之完整微處理 O:\89\89743.DOC -18- 1242249 器裝置，其中所有單元依據本發明垂直整合。 【圖式代表符號說明】 1 第一晶圓 1 a 前表面 lb 後表面 Id 區域 2 第二晶圓 2a 前表面 2b 後表面 3 第三晶圓 3a 前表面 5 第二晶圓 5a 前表面 5b 背面 6 第三晶圓 11 互連佈線 12 通道 13 開口 14 傳導材料層 15 處理板 16 焊接材料層 21 互連佈線 22 通道 23 開口 O:\89\89743.DOC -19- 1242249 24 傳導材料層 26 焊接材料層 27 凸塊 28 合金材料層 31 互連佈線 36 焊接材料層 37 凸塊 38 合金材料 40 開口 41 金屬襯墊 42 焊塊 51 互連佈線 52 通道 53 開口 54 金屬層 55 處理板 56 聚醯亞胺塗層 57 凸塊 58 合金材料 61 互連佈線 66 聚醯亞胺層 67 凸塊 68 合金材料 100 三維整合裝置 O:\89\89743.DOC -20 1242249 102 傳導體 103 開口 113 開口 114 傳導材料層 121 橫向尺度 127 凸塊 128 合金材料 200 晶片 221 橫向尺度 242 焊塊 300 多晶片模組 301 C4襯墊 400 裝置 401 三維整合裝置 402 邏輯單元 403 間隙 411 聚醯亞胺層 412 聚醯亞胺層 420 通道 421 金屬襯墊 422 凸塊 450 絕緣層 450b 表面 451 C4襯墊 O:\89\89743.DOC -21 1242249 452 C4焊塊 500 合併裝置 501 快取記憶體晶片 502 快取記憶體晶片 510 邏輯單元 O:\89\89743.DOC -22

Claims (1)

1242249 拾、申請專利範圍·· L敕於製造一包含複數個垂直堆疊及互連晶圓的三雉 正σ衣置之方法，該方法包括以下步驟： 提供一目士一 /、一具有一前表面（la)及一後表面（lb)之第一晶圓 ()忒第一晶圓的各裝置形成於與該第一晶圓之該前表 面鄰近的一區域（Id)内； 在°亥第一晶圓内形成一從該前表面延伸之通道（12)，該 、〔的特彳玫為在該前表面的一橫向尺度（121); 在°亥第一晶圓的該後表面（1 b)處將材料從該第一晶圓 移除； 在為第一晶圓的該後表面内形成一開口（13)，從而使該通 運曝路’該開口的一橫向尺度大於該通道的該橫向尺度； 在遠開口内形成一傳導材料層（14); 提供一具有一前表面（2a)及一後表面（2b)之第二晶圓 (2) ’该第二晶圓中形成的各裝置鄰近該第二晶圓之該前 表面； 在該第二晶圓的該前表面上形成一凸塊（27); 在該第二晶圓的該前表面（2a)上形成一焊接材料層 (26)，該等凸塊從此處垂直伸出； 將該凸塊（27)對準該第一晶圓的該後表面中的該開口 (13);以及 使用該焊接材料層（26)將該第二晶圓焊接至該第一晶 圓’使該凸塊與該通道電接觸。 2·如申請專利範圍第1項之方法，其進一步包括以下步驟： O:\89\89743.DOC 1242249 在該第二晶圓（2)内形成一從該第二晶圓之該前表面 (2a)延伸之通道（22)，該通道的特徵為在該前表面（2a)的 一橫向尺度（221); 在該第二晶圓的該後表面（2b)將材料從該第二晶圓移 除； 在該第二晶圓的該後表面（2b)形成一開口（23)，從而曝 露其中的該通道（22)，該開口（23)的一橫向尺度大於該通 道（22)的該橫向尺度（221); 在該開口内形成一傳導材料層（24); 提供一具有一前表面（3a)之第三晶圓（3)，該第三晶圓 中形成的各裝置鄰近該第三晶圓的該前表面； 在該第三晶圓的該前表面（3a)上形成一凸塊（37); 在該第三晶圓的該前表面（3a)上形成一焊接材料層 (3 6)，該等凸塊從此處垂直伸出； 將β亥凸塊（3 7 )對準該第二晶圓的該後表面中的該開口 (23);以及 使用該焊接材料層（36)將該第三晶圓焊接至該第二晶 圓’使該第三晶圓的該凸塊（37)與該第二晶圓的該通道 (22)、該第二晶圓的該凸塊（27)以及該第一晶圓的該通道 (12)電接觸。 3 ·如申請專利範圍第1或2項之方法，其特徵為移除材料之 δ亥步驟使该晶圓的一厚度小於2〇 。 4·如申請專利範圍第1或2項之方法，其進一步包括使用一 焊接材料層（16)將一處理板（15)附著於該第一晶圓（1)的 O:\89\89743.DOC -2- 1242249 該前表面（la)上之步驟。 如申請專利範圍第1或2項之方法，其進一步包括在該第 曰曰圓（1)與该第一晶圓（2)之一中形成一傳導體（ι〇2)並 且連接至該晶圓内的該通道〇2/22)之步驟，該傳導體在 该晶圓的該等裝置之下橫向延伸，其特徵為該晶圓的該 背面中的該開口（103)根據該傳導體（1〇2)的橫向延伸長 度與該通道横向分開。 如申請專利範圍第_項之方法，其進一步包括以下步 μ弟一晶圓的該後表面中形成一額外開口（113); 在4額外開口内形成一額外傳導材料層⑴句； 在該第二晶圓的該前表面上形成-額外凸塊（127广以及 :4卜凸塊（127)對準該第—晶圓的該後表面中的該 額外開口 〇13); :及其特徵為將該第二晶圓谭接至該第一晶圓之該步驟 ^額外凸塊U27)與該額外傳導材料層（ιΐ4)之間形成一 7如申第二晶圓與該第-晶圓之間的熱傳導。 申明專利範圍第6項之古 .貞之方法，其特徵為該額外傳導材料 層⑴4)係與該通道〇2)電性絕緣。 8·如申凊專利範圍第2項 .#… 、方法，其進一步包括以下步驟： 在该第二晶圓的該德矣；+ ._ 曼表面中形成一額外開口； 在額外開口内开3 +、 曰w成-頜外傳導材料層·， 社邊弟二晶圓的兮铪 將节額冰表面上形成-額外凸塊；及 將違頟外凸塊對準 Λ弟一日日圓的該後表面中的該額外 O:\89\89743.DOC 1242249 開口； ’、4寸徵為將該第三晶圓焊接至該第二 在該額外凸塊與該額外傳導材 日、广驟 該第三晶圓與該第二晶圓之間的熱傳導"成一連接’用於 9.10. 11.12. 13. 14. 如申請專利範圍第1或2項之方法 係一熱塑材料。 如申請專利範圍第9項之方法 醯亞胺。 其特徵為該焊接材料 其特徵為該熱塑材料係聚 如申言月專利範圍第以2項之方法，其進括㈣ 維整合裝置⑽）附著於—多晶片模組⑽)之步驟。 如申請專利範圍第⑷項之方法，其進—步包括使用 凸塊-通道連接將該三維整合裝置（401)附著於一其内形 成佈線之絕緣層（4 5 〇 )之步驟。 如申請專利範圍第2項之方法，其特徵為 二晶圓具有快取記憶體裝置，而該第三 置。 該第一晶圓及第 晶圓具有邏輯裝 如申請專利範圍第2項之方法，其特徵為該第一晶圓、第 二晶圓及該第三晶圓之至少一個包含—mems裝置。 O:\89\S9743.DOC -4 -
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US11049834B2 (en) 2019-01-30 2021-06-29 Yangtze Memory Technologies Co., Ltd. Hybrid bonding using dummy bonding contacts
US11205619B2 (en) 2019-01-30 2021-12-21 Yangtze Memory Technologies Co., Ltd. Hybrid bonding using dummy bonding contacts and dummy interconnects
US11462503B2 (en) 2019-01-30 2022-10-04 Yangtze Memory Technologies Co., Ltd. Hybrid bonding using dummy bonding contacts

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ATE456860T1 (de) 2010-02-15
WO2004059720A1 (en) 2004-07-15
EP1573799B1 (en) 2010-01-27
EP1573799A4 (en) 2009-02-25
IL169264A0 (en) 2007-07-04
EP1573799A1 (en) 2005-09-14
DE60235267D1 (de) 2010-03-18
CN100383936C (zh) 2008-04-23
AU2002368524A1 (en) 2004-07-22
CN1708840A (zh) 2005-12-14

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