CN101542701A - 基于硅通孔的三维晶圆叠层的键合方法 - Google Patents

基于硅通孔的三维晶圆叠层的键合方法 Download PDF

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CN101542701A
CN101542701A CN200880000036A CN200880000036A CN101542701A CN 101542701 A CN101542701 A CN 101542701A CN 200880000036 A CN200880000036 A CN 200880000036A CN 200880000036 A CN200880000036 A CN 200880000036A CN 101542701 A CN101542701 A CN 101542701A
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wafer
silicon
hole
layer
adhesive
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CN101542701B (zh
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马薇
史训清
仲镇华
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Hong Kong Applied Science and Technology Research Institute ASTRI
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Abstract

本发明描述了一个基于硅通孔的晶圆叠层的混合键合方法。具有图案的粘胶层将叠层内相邻晶圆连接在一起，同时硅通孔之间的焊接键合被用作晶圆叠层间的电信号互连。粘胶层上设计的图案用以排放焊接过程中产生的气体并消除应力。

Description

基于硅通孔的三维晶圆叠层的键合方法
技术领域
本发明涉及基于硅通孔(through-silicon-via，TSV)的三维晶圆叠层的键合方法，特别涉及采用粘胶和焊接键合的混合键合方法。本发明也涉及形成的晶圆叠层装配。
发明背景
随着电子设备的，特别是便携式设备：如手机等的，体积变得越来越小，提供的功能越来越广泛，很有必要在不增加设备尺寸，保持一个较小的形状的前提下集成更多功能的芯片，。仅在一个二维结构里增加电子组件数目无法实现这些目标，所以三维(3D)封装正日益被采用，以便能够提供更大的功能和更高的组件密度，但仍然保持一个较小的形状。
在这种3D结构里，各种电子组件，如具有不同有源IC装置的半导体芯片被集成在一个多层的叠层结构里。传统的引线键合(如US 6,933,172)被用来建立芯片之间的电信号的互连，而引线键合要求较大的内面尺寸(in-plane size)和外面尺寸(out-of-plane size)，这与最大化组件密度的目标不一致。为了集成不同层上的组件，硅通孔(TSV)技术可以被用来提供电互连，并提供机械支撑。在TSV技术里，通孔是通过半导体工艺过程在其有不同有源IC装置或其它装置的硅芯片上制成，然后被填充金属如铜、金、钨、焊料或高掺杂半导体材料如多晶硅。最后，具有此通孔的多个组件被堆叠并键合在一起。
现有技术
键合技术(bonding method)是制作叠层电子组件的一个重要环节。一个理想的键合方法应该是可靠且低成本的。TSV互连已经被提出作为引线键合互连的一个替代方法，一些键合方法，包括扩散键合(diffusionbonding)、焊接键合、以及粘胶键合(adhesive bonding)，可以与TSV互连一起用来连接晶圆/芯片。
在扩散键合里，一个薄金属键合层(例如，最好由铜制成，但也可能是锡、铟、金、镍、银、钯、钯镍合金或钛)被加到将被连接的半导体组件的各个键合表面。组件被键合时，如果施加合适的温度和压力条件，两个金属键合层相互扩散而形成一个金属间化合物(IMC)，形成键合连接。扩散连接可产生一个良好质量的可靠键合，但此方法的缺点是要求两个半导体组件的键合面有非常好的共平面度，并需要一个高键合温度。所以，实施此方法很困难且昂贵。一个扩散连接方法的典型例子如US 7,157,787所示。
粘胶键合是一个低成本选择，其方法为在将被键合在一起的表面上提供一个粘胶层。一个粘胶键合的例子如US 6,593,645所示。US 6.448,661显示一个现有技术的例子，其中芯片是使用导电胶如各向异性导电膜(ACF)或各向异性导电胶(ACA)进行连接。另一个粘胶键合的例子如US 4,897,708所示，其中晶圆是通过粘胶进行键合，而电互连是通过一种导电液体建立。但是，虽然粘胶键合是低成本的，并且不会发生重大的制造问题，但它在通孔上提供较差的电信号的互连，通常不适用于高电流，因此并不可靠。
一个焊接键合方法的例子如US 6,577,013所示。在焊接键合时，焊料被施加在将被叠层的半导体组件上的通孔结合(junction)处。焊接键合不需要如扩散键合所需要的高温度，但仍能产生一个良好可靠的键合。但是，随着被叠层组件数目的增加，焊接键合将遭遇难题。一个焊接键合的例子可以在US 7,317,256内找到，其描述了多个叠层晶圆的键合，另一个例子是US 7,215,033。但是，在此方法里，当一个新晶圆被添加到叠层中时，需进行焊接过程而形成一个IMC，将新晶圆连接到叠层，在其它晶圆之间之前形成的IMC在高焊接温度下迅速生长。由于IMC通常是一个硬而脆的材料，很易出现失效问题(如在坠落鉴定测试中出现)。此外，如果在制作过程中没有控制好焊料量，在多个焊接步骤上没有形成IMCs的剩余焊料将再次回焊，这样将破坏其可靠性，并产生制造瑕疵，在严重情况下可能导致失效。
发明概述
本发明提供一个形成晶圆叠层的方法，步骤包括：将多个晶圆叠放，每个所述晶圆具有至少一个硅通孔，焊料填充在硅通孔中并延伸至相邻晶圆的硅通孔处，所述晶圆通过在相邻晶圆之间的粘胶层被键合在一起，并使所述叠层仅经历一次焊接过程，从而使所述硅通孔通过所述焊料达成电互连。
为更好地实现键合，粘胶层被图案化以定义从至少一些所述硅通孔延伸到一个叠层边缘的通道。例如，粘胶层需具有感光性，可通过曝光被图案化。
在本发明中，粘胶层被图案化以定义出围住晶圆内每个硅通孔的互连空间。空间可以是环形的，或任何其它合适的形状。在通常情况下，一个晶圆内至少有两个硅通孔，其互连空间通过通道连接。例如，一个晶圆可以具有规则排列的硅通孔，而每个互连空间通过通道被连接到所有相邻硅通孔的互连空间。
在一个特别的实施例里，所述粘胶层的图案依晶圆的芯片设计被分割成多个部分，其分割线在所述粘胶层上形成主通道，并延伸到至少一个晶圆边缘，其中每个所述部分包括至少一个硅通孔，有一个通道从所述硅通孔的互连空间延伸到一个所述主通道。
特别地，叠层在所述焊接键合过程期间需被实施压力(loadingcompression)。
依照本发明另一个方面，一个晶圆叠层，包括在一个叠层内排列的多个晶圆，每个晶圆包括至少一个硅通孔，其中相邻晶圆通过一个介入其间的粘胶层被键合在一起，其中晶圆之间的电互连是通过相邻层上硅通孔之间的焊料而形成。
粘胶层被图案化以定义从至少一些所述硅通孔延伸到叠层装配边缘的通道。特别地，粘胶层可以被图案化以定义一个围住晶圆上每个硅通孔的互连空间。此空间可以是环形的，或任何其它合适的形状。
在特别实施例里，每个晶圆上形成至少两个硅通孔，围住所述硅通孔的互连空间通过通道连接。例如，一个晶圆可以有规则排列的硅通孔，其中每个所述硅通孔的互连空间通过通道被连接到所有相邻互连空间。
在一个特别优选的实施例里，所述粘胶层的图案依晶圆的芯片设计被分割成多个部分，其分割线在所述粘胶层上形成主通道，并延伸到至少一个晶圆边缘，其中每个所述部分包括至少一个硅通孔，有一个通道从所述硅通孔的互连空间延伸到一个所述主通道。
附图说明
现参考附图并通过范例，将描述本发明的一些实施例，其中：
图1是依照本发明一个实施例的一个晶圆叠层的俯视图；
图2是沿着图1内线A-A的截面图；
图3是描述粘胶图案化的一个晶圆的截面图；和
图4到12显示一个建立如图1和2所示的叠层晶圆装配的制作过程。
优选实施例详述
图1显示本发明一个实施例，一个圆形晶圆叠层100，具有四个芯片110-113。图2是沿着线A-A的截面图，显示晶圆叠层的结构，多个TSV通过焊料实现电互连，各个晶圆通过粘胶层被连接在一起，粘胶层被图案化将在以下描述。
在此例子里，每个芯片110-113有不同排列的通孔120(如在110上是一个简单正方形，在111和112上是两行三个通孔，在芯片113上是一个正方形和一个中央通孔)，在每种情况下，粘胶层在每个通孔周围都形成一个互连空间，并直接通过通道或通过另一个互连空间连接到芯片边缘。可以看到，粘胶层被互相垂直的主通道114-119分割成依晶圆上芯片的四个部分，主通道会连接到晶圆边缘。在芯片110-113上的每个通道最终连接到一个主通道114-119，从而连接到晶圆边缘。也可以理解，主通道114-119是由一个图案化的粘胶层形成，使得该粘胶层不是连续延伸覆盖在整个晶圆上，而是被分割成粘胶岛(adhesive island)对应四个芯片和晶圆周围部分。通过这样分割粘胶层，可以在制作过程中释放应力。
图2更详细地显示叠层晶圆的结构。在此例子里，晶圆叠层包括6个晶圆10，其通过硅通孔(TSV)12实现电互连。TSV又通过位于TSV 12下端和金属焊盘15之间的焊料13而互相键合，金属焊盘15在晶圆10上表面并覆盖TSV 12上端。晶圆10通过粘胶层16被物理键合在一起。
为了便于理解，图3显示一个很简单的例子，其中TSV 12是一个简单的2x 3阵列。从图3可以看到，粘胶16被图案化以至在每个金属焊盘周围留下一个环形空间17。此外，粘胶16被图案化以定义互连通道18，其在每个环形空间17之间延伸，使得每个环形空间17通过这种互连通道都被连接到所有相邻的环形空间17，这样做的目的将在以下描述。也会认识到，除了提供环形空间17之间的连接，还有一个互连通道18从每个环形空间17通向叠层边缘19。
但是，应该注意到，图3仅显示本发明的一个简单实施例，其中TSV被安排成一个简单的规则的2x3阵列，其中每个TSV至少有一个互连通道18通向一个边缘19(并且在四个角的TSV，有两个互连通道18通向两个边缘19)。在更复杂或更大的结构里，可能有TSV被其它TSV围住所有边，所以可能无法直接连接到一个边缘，而是仅连接到其它周围的TSV。此外，虽然图3的例子是一个简单的规则阵列，其中互连通道互成直角，并且每个环形空间17连接四个互连通道18，在更复杂的图案里，可能有不同数目的通道18。优选地，每个TSV都有互连通道18连接一个给定TSV到它的所有紧邻TSV，如果TSV在晶圆边缘的情况下，那么互连通道18就连接到边缘。尽管这可能不是必需的，但是，重要的是提供了一个互连通道网络，使得对每个TSV而言，不管在不在晶圆边缘，都存在一个连续路径从围住TSV的环形空间17到晶圆边缘19，无论是直接地或经由其它环形空间17。也可以理解，尽管在图1-3所示的实施例里，通过粘胶图案化环绕每个TSV 12的空间17是环形的，但这不是必需的，空间可以是其它可能的形状。但是，可以理解，如果没有其它晶圆10被添加到叠层，将不会提供其它的粘胶层16到上表面。
以下描述将解释如何能够制作这种结构。
起始点是一个由合适材料如硅制成的晶圆10(图4)。接着，一个光刻胶层11被加在晶圆10的上表面，然后图案化，然后使用一个深反应离子蚀刻工艺来建立通孔12。在为通孔12制备了隔离层(如SiO2)、粘附层(如Ti/W)和晶种层(如铜)之后，它们随后通过焊料电镀被填充满金属，通常是铜(Cu)或钨(W)或的其它合适材料，在完成填充金属的电镀之后，继续电镀一个薄焊料层(图5)。应该注意到，在此阶段，通孔12没有延伸穿过晶圆10的完全深度。然后，光刻胶层11被去除(图6)，接着，晶圆10通过一个粘胶层20被安装在一个晶圆保持架14上(图7)，然后，晶圆10经历一个去削过程如机械研磨、化学机械抛光、或化学或等离子蚀刻)，直到通孔12的金属一直延伸穿过晶圆10(图8)。
仍然被系缚在托架14的晶圆10被倒转，接着在通孔12的露出端上形成金属焊盘15(图9)，在焊盘15和晶圆10之间有一个绝缘层。然后，一个粘胶层16被加到晶圆10的露出表面，并参照图1到3的以上所述和所示被图案化，使得一个环形空间17被定义在每个金属焊盘15周围。图案化粘胶层16也将包括如图1到3所示的互连通道18，其互连金属焊盘15周围的环形空间17，并且定义了将环形空间17连接到晶圆10边缘的通道。特别地，粘胶层16是一个感光聚合物粘胶(如SU-8)，其能够通过曝光被图案化。当然，可以理解，空间17不一定是环形，可能是其它形状。
如图11所示，接着，晶圆托架14被倒转，通过一层胶19连接被图案化的粘胶16，晶圆10被固定到一个硬基板18。然后，移走晶圆保持架14，并再次用于制作第二晶圆。一旦制成第二晶圆后，会利用第二晶圆的图案化粘胶层16接触连接第一晶圆顶表面，第二晶圆被固定到第一晶圆10。再次移走晶圆保持架14，按要求重复过程，直到如图12所示完成晶圆叠层。
在完成晶圆叠层装配之后，接着，该装配仅经历一个焊接过程，使得所有焊接部分被键合连接到各个金属焊盘。同时，此焊接过程也用来充当粘胶层的后固化(post-cure)。可选地，在焊接/后固化过程期间，该晶圆叠层装配在负载压力(compression loading)之下，通过粘胶层增强晶圆键合连接。使用一个焊接过程能够避免由现有技术中多个焊接步骤引起的问题。
可以理解，以上所述的过程是一个混合焊接键合/粘胶键合过程。焊接键合用来提供通孔之间的良好电互连，其能够在高电流上运行，并具有良好的可靠性。叠层装配时粘胶层提供层之间的机械支撑，从而更便于晶圆加工，并在最后的晶圆叠层内提供额外的键合强度。粘胶层的图案化提供了通道，使得焊接期间释放的气体能够排出，而通过将粘胶层分割成不同区域，压力得以释放，而对称的夹层结构(粘胶-硅-粘胶)能够平衡由CTE不匹配引起的潜在弯曲。在焊接键合过程之后，晶圆叠层将分割成单个芯片(singularity process)，将底部填充剂注入到图案化的粘胶层后，每个芯片被注膜成型。

Claims (17)

1.一个形成晶圆叠层的方法，步骤包括：将多个晶圆叠放，每个所述晶圆具有至少一个硅通孔，焊料填充在硅通孔中并延伸至相邻晶圆的硅通孔处，晶圆首先被相邻晶圆之间的粘胶层键合在一起，并使所述叠层仅经历一次焊接过程，使所述硅通孔通过所述焊料达成电互连。
2.根据权利要求1所述的方法，其中所述粘胶层被图案化以定义从至少一些所述硅通孔延伸到一个叠层边缘的通道。
3.根据权利要求2所述的方法，其中所述粘胶是一个感光粘胶，并通过曝光而被图案化。
4.根据权利要求2所述的方法，其中所述粘胶层被图案化以定义一个围住晶圆内每个硅通孔的互连空间。
5.根据权利要求4所述的方法，其中所述互连空间是环形的，或者是其它合适的形状。
6.根据权利要求4所述的方法，其中在一个晶圆上形成至少两个硅通孔，围住所述硅通孔的互连空间通过通道互连。
7.根据权利要求4所述的方法，其中一个所述晶圆具有规则排列的硅通孔，其中每个互连空间通过通道被连接到所有相邻的互连空间。
8.根据权利要求4所述的方法，其中所述粘胶层的图案依晶圆的芯片设计被分割成多个区域，其分割线在所述粘胶层上形成主通道，并延伸到至少一个晶圆边缘，其中每个所述区域包括至少一个硅通孔，有一个通道从所述硅通孔的互连空间延伸到一个所述主通道。
9.根据权利要求1所述的方法，其中所述叠层在所述焊接过程期间会接受压力负荷(compression loading)。
10.根据权利要求1所述的方法，其中在键合过程完成之后，晶圆被分割成个别芯片，然后其经历一个底部填充及注膜成型过程。
11.一个晶圆叠层装配，包括多个晶圆排列在一个叠层内，每个所述晶圆包括至少一个硅通孔，其中相邻晶圆通过一个介于其间的粘胶层而被键合在一起，其中所述晶圆之间的电互连是由在相邻层里的硅通孔之间的焊料形成。
12.根据权利要求11所述的一个晶圆叠层装配，其中所述粘胶层被图案化以定义从至少一些所述硅通孔延伸到一个叠层装配边缘的通道。
13.根据权利要求12所述的一个晶圆叠层装配，其中所述粘胶层被图案化以定义一个围住晶圆上每个硅通孔的互连空间。
14.根据权利要求13所述的一个晶圆叠层装配，其中所述互连空间是环形的，或者任何其它合适的形状。
15.根据权利要求14所述的一个晶圆叠层装配，其中在一个晶圆上形成至少两个硅通孔，其互连空间通过通道连接。
16.根据权利要求15所述的一个晶圆叠层装配，其中一个所述晶圆具有规则排列的硅通孔，其互连空间通过通道被连接到所有相邻硅通孔的互连空间。
17.根据权利要求11所述的一个晶圆叠层装配，其中所述粘胶层上的图案依晶圆的芯片设计被分割成多个区域，其分割线在粘胶层上形成主通道，并延伸到至少一个晶圆边缘，其中每个所述区域包括至少一个硅通孔，有一个通道从其互连空间延伸到一个所述主通道。
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