CN108695274A - 三维整合的散热增益型半导体组件及其制作方法 - Google Patents

三维整合的散热增益型半导体组件及其制作方法 Download PDF

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CN108695274A
CN108695274A CN201810155277.XA CN201810155277A CN108695274A CN 108695274 A CN108695274 A CN 108695274A CN 201810155277 A CN201810155277 A CN 201810155277A CN 108695274 A CN108695274 A CN 108695274A
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radiating seat
line structure
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type semiconductor
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CN108695274B (zh
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林文强
王家忠
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Yuqiao Semiconductor Co Ltd
Bridge Semiconductor Corp
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Yuqiao Semiconductor Co Ltd
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Abstract

本发明的三维整合的散热增益型半导体组件包含有通过接合线相互电性耦接的叠层式半导体次组件及线路板。散热座设置于线路结构的贯穿开口中，用于提高该叠层式半导体次组件的散热性。设置于散热座上的另一线路结构不仅提供机械支撑，其亦可通过金属化盲孔对散热座进行散热及接地电连接。接合线提供次组件与线路板间的电性连接，以将组装于次组件中的装置互连至线路板的端子垫。

Description

三维整合的散热增益型半导体组件及其制作方法
技术领域
本发明是关于一种半导体组件及其制作方法，尤指一种三维整合的散热增益型半导体组件及其制作方法，其将叠层式半导体次组件打线连接并热性导通至线路板，其中线路板具有与双线路结构整合的散热座。
背景技术
多媒体装置的市场趋势倾向于更迅速且更薄型化的设计需求。其中一种方法是以叠层方式以互连两装置，使两装置间具有最短的路由距离。由于叠置的装置间可直接相互传输，以降低延迟，故可大幅改善组件的信号完整度，并节省额外的耗能。然而，由于半导体装置易于高操作温度下发生效能劣化现象，因此若叠层式芯片未进行适当散热，则会使装置的热环境变差，导致操作时可能出现立即失效的问题。
美国专利案号8,008,121、8,519,537及8,558,395揭露各种具有中介层的组件结构，其将中介层设于面朝面设置的芯片间。虽然其无需于叠层芯片中形成硅穿孔(TSV)，但中介层中用于提供芯片间电性路由的硅穿孔会导致工艺复杂、生产良率低及高成本。
为了上述理由及以下所述的其他理由，目前亟需发展一种三维半导体组件，以达到高封装密度、较佳信号完整度及高散热度的要求。
发明内容
本发明的目的在于提供一种散热增益型半导体组件，其通过多条接合线，将叠层式半导体次组件电性连接至线路板，并使叠层式半导体次组件与线路板内建的散热座热性导通。该散热座设置于线路结构的贯穿开口中，并由额外的线路结构对散热座提供机械支撑，且散热座可与该额外的线路结构电性连接，并通过该额外的线路结构进行散热，进而可改善组件的机械、热性及电性校能。
依据上述及其他目的，本发明提供一种散热增益型半导体组件，其通过接合线，使叠层式半导体次组件电性连接至线路板。该叠层式半导体次组件包括一第一装置、一第二装置及一路由电路。该线路板包括一散热座、一第一线路结构及一第二线路结构。于一较佳实施例中，第一装置与散热座热性导通，且第一装置与第二装置间是以路由电路相隔，并通过路由电路相互电性连接；路由电路对第一装置及第二装置提供初级的扇出路由及最短的互连距离；第一线路结构侧向环绕散热座及次组件的***边缘，并通过接合线电性耦接至路由电路，以提供进一步的扇出路由；第二线路结构覆盖第一线路结构及散热座，以提供机械支撑，且第二线路结构热性导通至散热座，并电性耦接至第一线路结构。
据此，本发明提供一种三维整合的散热增益型半导体组件，其包含：一叠层式半导体次组件，其包括一第一装置、一第二装置及一路由电路，其中该第一装置电性耦接至该路由电路的一第一表面，而该第二装置电性耦接至该路由电路的一相反第二表面；一线路板，其包括一第一线路结构、一第二线路结构及一散热座，其中(i)该第一线路结构具有一第一表面、一相反第二表面、及从该第一表面延伸至该第二表面的一贯穿开口，(ii)该散热座设置于该贯穿开口中，且该散热座的一背侧表面与该第一线路结构的该第一表面呈实质上共平面，(iii)该第二线路结构设置于该散热座的该背侧表面及该第一线路结构的该第一表面上，并通过金属化盲孔电性连接至该第一线路结构且热性导通至该散热座，且(iv)该叠层式半导体次组件设置于该贯穿开口中；以及多条接合线，其电性耦接该路由电路至该线路板。
此外，本发明提供一种三维整合的散热增益型半导体组件的制作方法，其包括下述步骤：提供一叠层式半导体次组件，其包括一第一装置、一第二装置及一路由电路，其中该第一装置电性耦接至该路由电路的一第一表面，而该第二装置电性耦接至该路由电路的一相反第二表面；提供一线路板，其包括一第一线路结构、一第二线路结构及一散热座，其中(i)该第一线路结构具有一第一表面、一相反第二表面、及从该第一表面延伸至该第二表面的一贯穿开口，(ii)该散热座设置于该贯穿开口中，且该散热座的一背侧表面与该第一线路结构的该第一表面呈实质上共平面，且(iii)该第二线路结构设置于该散热座的该背侧表面及该第一线路结构的该第一表面上，并通过金属化盲孔电性连接至该第一线路结构且热性导通至该散热座；将该叠层式半导体次组件设置于该第一线路结构的该贯穿开口中及该散热座上；以及提供多条接合线，以电性耦接该路由电路及该线路板。
除非特别描述或步骤间使用“接着”字词，或者是必须依序发生的步骤，上述步骤的顺序并无限制于以上所列，且可根据所需设计而变化或重新安排。
本发明的半导体组件及其制作方法具有许多优点。举例来说，将第一装置及第二装置叠层并电性耦接至路由电路的相反两侧，可提供第一装置与第二装置间的最短互连距离。将次组件***线路板第一线路结构的贯穿开口是特别具有优势的，其原因在于，线路板可对次组件提供机械外壳，而位于贯穿开口中且被第二线路结构支撑的散热座可提供第一装置散热途径。此外，将接合线接至该次组件及该线路板的做法，可提供可靠的连接通道，以将组装于次组件中的装置互连至线路板的端子垫。
本发明的上述及其他特征与优点可通过下述较佳实施例的详细叙述更加清楚明了。
附图说明
参考附图，本发明可通过下述较佳实施例的详细叙述更加清楚明了，其中：
图1为本发明第一实施方案中，于牺牲载板上形成路由线的剖视图；
图2为本发明第一实施方案中，图1结构上形成介电层及盲孔的剖视图；
图3为本发明第一实施方案中，图2结构上形成导线的剖视图；
图4为本发明第一实施方案中，图3结构上接置第一装置的剖视图；
图5为本发明第一实施方案中，图4结构上形成模封材的剖视图；
图6为本发明第一实施方案中，自图5结构移除牺牲载板的剖视图；
图7为本发明第一实施方案中，图6结构上接置第二装置以完成叠层式半导体次组件制作的剖视图；
图8为本发明第一实施方案中，第一线路结构的剖视图；
图9为本发明第一实施方案中，图8结构中还设置散热座的剖视图；
图10为本发明第一实施方案中，图9结构上形成第二线路结构以完成线路板制作的剖视图；
图11为本发明第一实施方案中，图10结构上设置图7叠层式半导体次组件的剖视图；
图12为本发明第一实施方案中，图11结构上接置接合线以完成半导体组件制作的剖视图；
图13为本发明第一实施方案中，图12结构上形成密封材的剖视图；
图14为本发明第一实施方案中，图13结构上接置第三装置的剖视图；
图15为本发明第一实施方案中，图14结构上接置焊球的剖视图；
图16为本发明第一实施方案中，图13结构上接置无源元件、另一散热座及焊球的剖视图；
图17为本发明第一实施方案中，颠倒的图13结构上接置第三装置、另一散热座及焊球的剖视图；
图18为本发明第一实施方案中，图13结构上接置额外线路板的剖视图；
图19为本发明第一实施方案中，图18结构上接置第三装置及焊球的剖视图；
图20为本发明第一实施方案中，图13结构上接置另一方案的额外线路板剖视图；
图21为本发明第二实施方案中，线路板的剖视图；
图22为本发明第二实施方案中，图21结构中设置图7叠层式半导体次组件的剖视图；
图23为本发明第二实施方案中，图22结构上接置接合线以完成半导体组件制作的剖视图；
图24为本发明第二实施方案中，图23结构上形成密封材的剖视图；
图25为本发明第二实施方案中，颠倒的图24结构上设置第三装置及无源元件的剖视图；
图26为本发明第二实施方案中，图25结构上形成密封材的剖视图；
图27为本发明第二实施方案中，图26结构上设置焊球的剖视图；
图28为本发明第三实施方案中，叠层式半导体次组件贴附至图10线路板的剖视图；
图29为本发明第三实施方案中，图28结构上接置接合线以完成半导体组件制作的剖视图；
图30为本发明第三实施方案中，图29结构上设置垂直连接件的剖视图；
图31为本发明第三实施方案中，图30结构上形成密封材以完成半导体组件制作的剖视图；
图32为本发明第三实施方案中，图31结构上设置第三装置的剖视图；
图33为本发明第三实施方案中，图32结构上设置焊球的剖视图；
图34为本发明第三实施方案中，另一半导体组件方案的剖视图；
图35为本发明第三实施方案中，再一半导体组件方案的剖视图；
图36为本发明第四实施方案中，叠层式半导体次组件的剖视图；
图37为本发明第四实施方案中，图36次组件打线至图10线路板的剖视图；
图38为本发明第四实施方案中，图37结构上形成密封材的剖视图；
图39为本发明第四实施方案中，图38结构上设置第三装置的剖视图；
图40为本发明第四实施方案中，颠倒的图38结构上设置第三装置、散热座及焊球的剖视图；
图41为本发明第五实施方案中，半导体组件的剖视图；
图42为本发明第五实施方案中，图41结构上设置第三装置及焊球的剖视图；
图43为本发明第五实施方案中，图41结构上设置透镜及焊球的剖视图；
图44为本发明第六实施方案中，半导体组件的剖视图；
图45为本发明第六实施方案中，图44结构上设置第三装置及焊球的剖视图；
图46为本发明第六实施方案中，图44结构上设置透镜及焊球的剖视图。
【符号说明】
半导体组件 110、210、310、320、330、410、510、610
牺牲载板 10
叠层式半导体次组件 20
第一表面 201、311、911
第二表面 202、312、912
路由电路 21
路由线 212
介电层 215、331、341、361、911、961
盲孔 216
导线 217、333、343、363、913、963
金属化盲孔 218、334、344、364、964
第一装置 22
第一凸块 223
无源元件 23、65
金属柱 24、583
模封材 25
第二装置 27
第二凸块 273
接合线 276、41
线路板 30、90
第一线路结构 31
贯穿开口 315、915
凹穴 316、811
间隙 317
互连基板 32
核心层 321
第一路由层 323
第二路由层 324
金属化贯孔 327、927
第一增层电路 33
第二增层电路 34
散热座 35、81、95
背侧表面 351、952
第二线路结构 36
导热垫 366
金属层 37
导电材 38
导热材 39、89、99
密封材 51、85
开孔 511
垂直连接件 58
第三装置 61
焊球 71、73、75、77、581
透镜 88
接合材 881
第三线路结构 91
核心层 921
第一路由层 923
第二路由层 924
第四线路结构 96
具体实施方式
在下文中，将提供一实施例以详细说明本发明的实施方案。本发明的优点以及功效将通过本发明所揭露的内容而更为显著。在此说明附图是简化过且作为例示之用。附图中所示的元件数量、形状及尺寸可依据实际情况而进行修改，且元件的配置可能更为复杂。本发明中也可进行其他方面的实践或应用，且不偏离本发明所定义的精神及范畴的条件下，可进行各种变化以及调整。
[实施例1]
图1-12为本发明第一实施方案中，一种半导体组件的制作方法图，其包括一路由电路21、一第一装置22、一模封材25、一第二装置27、一线路板30及接合线41。
图1为牺牲载板10上形成路由线212的剖视图。该牺牲载板10通常由铜、铝、铁、镍、锡、不锈钢、硅或其他金属或合金制成，但亦可使用任何其他导电或非导电材料制成。于本实施方案中，该牺牲载板10由含铁材料所制成。路由线212通常由铜所制成，且可通过各种技术进行图案化沉积，如电镀、无电电镀、蒸镀、溅射或其组合，或者通过薄膜沉积而后进行金属图案化步骤而形成。就具导电性的牺牲载板10而言，一般是通过金属电镀方式沉积，以形成路由线212。金属图案化技术包括湿蚀刻、电化学蚀刻、激光辅助蚀刻及其组合，并使用蚀刻光罩(图未示)，以定义出路由线212。
图2为具有介电层215及盲孔216的剖视图，其中介电层215位于牺牲载板10及路由线212上，而盲孔216于介电层215中。介电层215一般可通过层压或涂布方式沉积而成，并接触牺牲载板10及路由线212，且介电层215由上方覆盖并侧向延伸于牺牲载板10及路由线212上。介电层215通常具有50微米的厚度，且可由环氧树脂、玻璃环氧树脂、聚酰亚胺、或其类似物所制成。于沉积介电层215后，可通过各种技术形成盲孔216，如激光钻孔、电浆蚀刻、及微影技术，且通常具有50微米的直径。可使用脉冲激光提高激光钻孔效能。或者，可使用扫描激光束，并搭配金属光罩。盲孔216延伸穿过介电层215，并对准路由线212的选定部位。
参考图3，通过金属沉积及金属图案化工艺形成导线217于介电层215上。导线217自路由线212朝上延伸，并填满盲孔216，以形成直接接触路由线212的金属化盲孔218，同时侧向延伸于介电层215上。因此，导线217可提供X及Y方向的水平信号路由以及穿过盲孔216的垂直路由，以作为路由线212的电性连接。
导线217可通过各种技术沉积为单层或多层，如电镀、无电电镀、蒸镀、溅射或其组合。举例来说，首先通过将该结构浸入活化剂溶液中，使介电层215与无电镀铜产生触媒反应，接着以无电电镀方式被覆一薄铜层作为晶种层，然后以电镀方式将所需厚度的第二铜层形成于晶种层上。或者，于晶种层上沉积电镀铜层前，该晶种层可通过溅射方式形成如钛/铜的晶种层薄膜。一旦达到所需的厚度，即可使用各种技术图案化被覆层，以形成导线217，如湿蚀刻、电化学蚀刻、激光辅助蚀刻或其组合，并使用蚀刻光罩(图未示)，以定义出导线217。
此阶段已完成于牺牲载板10上形成路由电路21的工艺。于此图中，路由电路21为多层增层电路，其包括路由线212、介电层215及导线217。
图4为第一装置22电性耦接至路由电路21的剖视图。第一装置22可通过热压、回焊、或热超音波接合技术，通过第一凸块223电性耦接至路由电路21的导线217，其中第一凸块223接触第一装置22及路由电路21。于此实施方案中，该第一装置22绘示成半导体芯片。
图5为形成模封材25于路由电路21上及第一装置22周围的剖视图，其中该模封材25可通过如树脂-玻璃层压、树脂-玻璃涂布或模制(molding)方式形成。该模封材25是由上方覆盖路由电路21，且环绕、同形披覆并覆盖第一装置22的侧壁。或者，也可省略形成该模封材25的步骤。
图6为移除牺牲载板10的剖视图。牺牲载板10可通过各种方式移除，以由下方显露路由电路21，如使用酸性溶液(如氯化铁、硫酸铜溶液)或碱性溶液(如氨溶液)的湿法化学蚀刻、电化学蚀刻、或于机械方式(如钻孔或端铣)后再进行化学蚀刻。于此实施方案中，由含铁材料所制成的牺牲载板10可通过化学蚀刻溶液移除，其中化学蚀刻溶液于铜与铁间具有选择性，以避免移除牺牲载板10时导致铜路由线212遭蚀刻。
图7为第二装置27电性耦接至路由电路21的剖视图。第二装置27可通过热压、回焊、或热超音波接合技术，通过第二凸块273电性耦接至路由电路21的路由线212，其中第二凸块273接触第二装置27及路由电路21。于此实施方案中，该第二装置27绘示成半导体芯片。然而，于其他实例中，第二装置27亦可为已封装元件或无源元件。
此阶段已完成叠层式半导体次组件20的制作，其包括一路由电路21、一第一装置22、一模封材25及一第二装置27。第一装置22及第二装置27分别电性耦接至路由电路21的第一表面201及第二表面202，且该模封材25设置于第一表面201上，并环绕第一装置22。
图8为第一线路结构31的剖视图。该第一线路结构31具有一贯穿开口315，其自第一表面311延伸至第二表面312。于此附图中，该第一线路结构31包含一互连基板32、一第一增层电路33及一第二增层电路34。该互连基板32包括一核心层321、一第一路由层323、一第二路由层324及金属化贯孔327。第一路由层323及第二路由层324分别侧向延伸于核心层321的两侧，而金属化贯孔327延伸穿过该核心层321，以提供第一路由层323及第二路由层324间的电性连接。第一增层电路33及第二增层电路34分别设置于互连基板32的两侧上，且各别包括一介电层331、341及导线333、343。介电层331、341分别由下方及上方覆盖互连基板32的两侧，且可由环氧树脂、玻璃环氧树脂、聚酰亚胺、或其类似物所制成。导线333、343分别侧向延伸于介电层331、341上，并包括位于介电层331、341中的金属化盲孔334、344。金属化盲孔334、344分别接触互连基板32的第一路由层323及第二路由层324，并延伸穿过介电层331、341。
图9为散热座35设置于第一线路结构31贯穿开口315中的剖视图。散热座35可为由金属、合金、硅、陶瓷或石墨制成的导热层。于此实施方案中，该散热座35为一金属层，且其背侧表面351于向下方向上与第一线路结构31的第一表面311呈实质上共平面。
图10为第二线路结构36形成于散热座35背侧表面351及第一线路结构31第一表面311上的剖视图。于此附图中，该第二线路结构36为不具核心层的多层增层电路，其包括交替形成的多层介电层361及导线363。导线363侧向延伸于介电层361上，并包含金属化盲孔364于介电层361中。据此，第二线路结构36可通过嵌埋于介电层361中并接触第一路由层323及散热座35的金属化盲孔364，电性耦接至第一线路结构31及散热座35。
于此阶段中，已完成的线路板30包括有一第一线路结构31、一散热座35及一第二线路结构36。由于贯穿开口315深度大于散热座35厚度，故散热座35的外侧表面与第一线路结构31贯穿开口315的侧壁表面会构成位于第一线路结构31贯穿开口315中的凹穴316。因此，散热座35可对容置于凹穴316中的装置提供散热，而第一线路结构31及第二线路结构36可于线路板30两相反侧提供下一级连接用的电性接点。
图11为图7叠层式半导体次组件20贴附至图10线路板30的剖视图。该叠层式半导体次组件20会对准第一线路结构31的贯穿开口315，并设置于第一线路结构31贯穿开口315中，且第一装置22是利用导热材39贴附至线路板30的散热座35。导热材39可为焊料(如AuSn)或银/环氧黏着剂。贯穿开口315的内部侧壁侧向环绕叠层式半导体次组件20的***边缘，并与叠层式半导体次组件20的***边缘保持距离。因此，叠层式半导体次组件20***边缘与第一线路结构31内部侧壁间会留有位于贯穿开口315中的间隙317。该间隙317侧向环绕叠层式半导体次组件20，且第一线路结构31侧向环绕该间隙317。
图12为接合线41接至叠层式半导体次组件20及线路板30的剖视图，其通常可通过金或铜球形接合(ball bonding)或金或铝楔型接合(wedge bonding)方式，以接置接合线41。接合线41接触并电性耦接至路由电路21的路由线212及线路板30的导线343。因此，接合线41可将路由电路21电性耦接至第一线路结构31。
据此，如图12所示，已完成的半导体组件110包括有通过接合线41相互电性连接的叠层式半导体次组件20及线路板30。于此图中，该叠层式半导体次组件20包括一路由电路21、一第一装置22、一模封材25及一第二装置27，而线路板30包括一第一线路结构31、一散热座35及一第二线路结构36。
第一装置22是由路由电路21的一侧，以覆晶方式电性耦接至路由电路21，并被模封材25及散热座35所包围。第二装置27则由路由电路21的另一侧，以覆晶方式电性耦接至路由电路21，并通过路由电路21与第一装置22相互面朝面地连接。据此，路由电路21可提供初级扇出路由及第一装置22与第二装置27间的最短互连距离。线路板30的散热座35会与第一装置22热性导通，并由下方覆盖第一装置22。第一线路结构31侧向环绕叠层式半导体次组件20及散热座35的***边缘，并通过接合线41电性耦接至路由电路21。第二线路结构36由下方覆盖第一线路结构31及散热座35，并通过金属化盲孔364电性耦接至第一线路结构31，同时也通过金属化盲孔364与散热座35热性导通。因此，路由电路21、第一线路结构31及第二线路结构36可对第一装置22及第二装置27提供阶段式的扇出路由。
图13为图12半导体组件110还设有密封材51的剖视图。该密封材51由上方覆盖接合线41、叠层式半导体组件20及线路板30的选定部位，并进一步填满叠层式半导体组件20***边缘与线路板30内部侧壁间的间隙317。
图14为图13半导体组件110还设有第三装置61叠层于叠层式半导体组件20与线路板30第一线路结构31上方的剖视图。第三装置61可为球栅数组封装(ball grid arraypackage)或凸块化芯片(bumped chip)，且通过复数焊球71，电性耦接至第一线路结构31的导线343。
图15为图14半导体组件110还设有焊球73的剖视图。所述焊球73接置于线路板30的第二线路结构36上，用于外部连接。
图16为图13半导体组件110还设有无源元件65、焊球73及散热座81的剖视图，其中无源元件65与散热座81位于第一线路结构31处，而焊球73位于第二线路结构36处。无源元件65电性耦接至第一线路结构31的导线343。散热座81具有一凹穴811，并接置于第一线路结构31上，且通过焊球75电性耦接至第一线路结构31的导线343，以构成接地连接。第二装置27容置于散热座81的凹穴811中，并通过导热材89与散热座81热性导通，其中导热材89会接触第二装置27与散热座81。焊球73接置于第二线路结构36的导线363上，用于外部连接。
图17为颠倒的图13半导体组件110还设有第三装置61、焊球73及散热座81的剖视图，其中第三装置61与散热座81位于第二线路结构36处，而焊球73位于第一线路结构31处。第三装置61可为球栅数组封装(ball grid array package)或凸块化芯片(bumped chip)，并容置于散热座81的凹穴811内，且通过焊球71，电性耦接至第二线路结构36的导线363。散热座81通过导热材89与第三装置61热性导通，并通过焊球75电性耦接至第二线路结构36的导线363。焊球73接置于第一线路结构31的导线343上，用于外部连接。
图18为图13半导体组件110还设有额外线路板90的剖视图。该线路板90叠层于叠层式半导体次组件20与线路板30上，并包含有一第三线路结构91、一散热座95及一第四线路结构96。于此图中，第三线路结构91及第四线路结构96皆为不具核心层的多层增层电路，其分别包括交替形成的多层介电层911，961及导线913，963，以于线路板90的相反两侧提供电性接点。第三线路结构91具有从第一表面911延伸至第二表面912的贯穿开口915，并通过焊球71电性耦接至第一线路结构31的导线343。散热座95设置于第三线路结构91的贯穿开口915内，且散热座95的背侧表面952与第三线路结构91的第二表面912呈实质上共平面。第二装置27通过导热材99贴附至散热座95，以与散热座95热性导通，且第三线路结构91侧向环绕第二装置27。第四线路结构96设置于第三线路结构91第二表面912及散热座95背侧表面952上，并包括嵌埋于介电层961中并与第三线路结构91导线913及散热座95接触的金属化盲孔964。
图19为图18半导体组件110还设有第三装置61及焊球73的剖视图，其中第三装置61位于第四线路结构96处，而焊球73位于第二线路结构36处。第三装置61可为球栅数组封装(ball grid array package)或凸块化芯片(bumped chip)，并通过焊球77叠层且电性耦接至第四线路结构96的导线963。焊球73接置于第二线路结构36的导线363上，用于外部连接。
图20为图13半导体组件110还设有另一额外线路板90方案的剖视图。线路板90与图18所示结构类似，不同处在于，第三线路结构91为一互连基板，其包括一核心层921、一第一路由层923、一第二路由层924及金属化贯孔927。第一路由层923及第二路由层924设于核心层921的相反侧。金属化贯孔927延伸贯穿核心层921，并电性耦接至第一路由层923及第二路由层924。第四线路结构96包括与第三线路结构91的第二路由层924及散热座95接触的金属化盲孔964。
[实施例2]
图21-24为本发明第二实施方案中，另一种半导体组件的制作方法图，其中线路板的凹穴具有侧向环绕叠层式半导体次组件的金属化侧壁。
为了简要说明的目的，上述实施例1中任何可作相同应用的叙述皆并于此，且无须再重复相同叙述。
图21为线路板30的剖视图。该线路板30与图10所示结构类似，不同处在于，(i)该线路板30还包括一金属层37，其完全覆盖第一线路结构31的贯穿开口315侧壁，并与散热座35接触，(ii)第二线路结构35的最外层导线363包含有一导热垫366。于此图中，该散热座35的外表面与金属层37的侧表面形成一凹穴316，且该凹穴316是位于第一线路结构31的贯穿开口315中。
图22为图7叠层式半导体次组件20贴附至图21线路板30的剖视图。该叠层式半导体次组件20设置于线路板30的凹穴316中，并利用导热材39贴附至散热座35。
图23为接合线41接至叠层式半导体次组件20及线路板30的剖视图。接合线41接触并电性耦接至路由电路21的路由线212及第一线路结构31的导线343。
据此，如图23所示，完成的半导体组件210包括通过接合线41相互电性连接的叠层式半导体次组件20及线路板30。于此图中，该叠层式半导体次组件20包括一路由电路21、一第一装置22、一模封材25及一第二装置27，而该线路板30包括一第一线路结构31、一散热座35、一第二线路结构36及一金属层37。
第一装置22及第二装置27分别设置于路由电路21的相反两侧处，并通过两者间的路由电路21，面朝面地相互电性连接。据此，路由电路21可提供第一装置22与第二装置27间的最短互连距离，并对第一装置22与第二装置27提供第一级扇出路由。该散热座35覆盖第一装置22的非主动面，并与第一装置22热性导通，而金属层37则环绕叠层式半导体次组件20的***边缘，并与散热座35接触。第一线路结构31通过接合线41，电性耦接至路由电路21。第二线路结构36由下方覆盖第一线路结构31及散热座35，并通过金属化盲孔364电性耦接至第一线路结构31，以构成信号路由，同时也通过金属化盲孔364电性耦接至散热座35，以构成接地连接。据此，第一线路结构31与第二线路结构36的整体可对路由电路21提供第二级的扇出路由，并提供下一级连接用的电性接点，而电性连接至第二线路结构36的散热座35与金属层37则可共同对第一装置22提供散热及电磁屏蔽。
图24为图23半导体组件210还设有密封材51的剖视图。该密封材51由上方覆盖接合线41、叠层式半导体组件20及第一线路结构31的选定部位，并进一步填满叠层式半导体组件20***边缘与线路板30内部侧壁间的间隙317。
图25为颠倒的图24半导体组件210还设有第三装置61及无源元件65的剖视图。第三装置61是绘示成半导体芯片，并贴附于第二线路结构36的导热垫366上，且通过接合线72电性耦接至第二线路结构36的导线363。无源元件65则接置于第二线路结构36的导线363上，并与第二线路结构36的导线363电性耦接。
图26为图25半导体组件210还设有密封材85的剖视图。该密封材85由上方覆盖接合线72、第三装置61、无源元件65及第二线路结构36。
图27为图26半导体组件210还设有焊球73的剖视图。所述焊球73接置于第一线路结构31的导线343上，用于外部连接。
[实施例3]
图28-31为本发明第三实施方案中，线路板上设有垂直连接件的半导体组件制作方法图。
为了简要说明的目的，上述实施例中任何可作相同应用的叙述皆并于此，且无须再重复相同叙述。
图28为叠层式半导体次组件20容置于图10线路板30凹穴316中的剖视图。该叠层式半导体次组件20与图7所示结构相似，只是不同处在于，该叠层式半导体次组件20还包括一无源元件23及一金属柱24，该无源元件23及该金属柱24电性耦接至路由电路21，且封埋于模封材25中。该叠层式半导体次组件20是通过具导热性的导电材38贴附于散热座35上，其中具导热性的导电材38与散热座35、第一装置22、金属柱24及模封材25接触。
图29为接合线41接至叠层式半导体次组件20及线路板30的剖视图。接合线41接触并电性耦接至路由电路21的路由线212及第一线路结构31的导线343。
图30为线路板30上设置垂直连接件58的剖视图。垂直连接件58电性耦接至第一线路结构31的导线343，并与第一线路结构31的导线343接触。于此实施方案中，所述垂直连接件58是绘示成焊球581。
图31为设有密封材51的剖视图。该密封材51由上方覆盖垂直连接件58侧壁、接合线41、叠层式半导体次组件20及线路板30。据此，已完成的半导体组件310包括叠层式半导体次组件20、线路板30、接合线41、密封材51及垂直连接件58。于此图中，该叠层式半导体次组件20包括路由电路21、第一装置22、无源元件23、金属柱24、模封材25及第二装置27，而线路板30包括第一线路结构31、散热座35及第二线路结构36。
第一装置22/无源元件23及第二装置27分别设置于路由电路21的相反两侧处，并通过两者间的路由电路21，面朝面地相互电性连接。金属柱24电性连接至路由电路21，并延伸穿过模封材25。该散热座35电性连接至金属柱24，以构成接地连接，并与第一装置22热性导通，以进行散热。第一线路结构31与第二线路结构36整体通过接合线41，电性耦接至路由电路21，并通过金属化盲孔364，电性耦接至散热座35。垂直连接件58接置于第一线路结构31上，并与第一线路结构31电性耦接，且密封材51侧向环绕垂直连接件58。
图32为图31半导体组件310还设有第三装置61的剖视图。第三装置61叠层于密封材51上方，并通过焊球71电性耦接至密封材51中的垂直连接件58。
图33为图32半导体组件310还设有焊球73的剖视图。所述焊球73接置于第二线路结构36的导线363上，用于外部连接。
图34为本发明第三实施例中另一半导体组件方案的剖视图。该半导体组件320与图31所示结构相似，只是不同处在于，该密封材51的厚度大于焊球581，且密封材51具有开孔511，以由上方显露焊球581。
图35为本发明第三实施例中再一半导体组件方案的剖视图。该半导体组件330与图31所示结构相似，只是不同处在于，其包含有金属柱583作为垂直连接件58。
[实施例4]
图36-37为本发明第四实施方案中，第二装置打线至路由电路的半导体组件制作方法图。
为了简要说明的目的，上述实施例中任何可作相同应用的叙述皆并于此，且无须再重复相同叙述。
图36为叠层式半导体次组件20的剖视图。该叠层式半导体次组件20类似于图7所示的结构，不同处在于，该第二装置27是通过接合线276，电性耦接至路由电路21的路由线212。
图37为通过接合线41将图36叠层式半导体次组件20电性耦接至图10线路板30的半导体组件410剖视图。该叠层式半导体次组件20设置于线路板30的凹穴316中，并利用导热材39贴附至散热座35。接合线41接触并电性耦接至路由电路21的路由线212及第一线路结构31的导线343。
图38为图37半导体组件410还设有密封材51的剖视图。该密封材51由上方覆盖接合线41、叠层式半导体组件20及线路板30的选定部位，并进一步填满叠层式半导体组件20***边缘与线路板30内部侧壁间的间隙317。
图39为图38半导体组件410还设有第三装置61叠层于叠层式半导体次组件20与线路板30第一线路结构31上的剖视图。第三装置61通过焊球71，电性耦接至第一线路结构31的导线343。
图40为颠倒的图38半导体组件410还设有第三装置61、焊球73及散热座81的剖视图，其中第三装置61与散热座81位于第二线路结构36处，而焊球73位于第一线路结构31处。第三装置61容置于散热座81的凹穴811内，且通过焊球71，电性耦接至第二线路结构36的导线363。散热座81通过导热材89与第三装置61热性导通，并通过焊球75电性耦接至第二线路结构36的导线363。焊球73接置于第一线路结构31的导线343上，用于外部连接。
[实施例5]
图41为本发明第五实施方案的半导体组件剖视图。
该半导体组件510类似于图12所示的结构，不同处在于，(i)该叠层式半导体次组件20还包括电性耦接至路由电路21并封埋于模封材25中的无源元件23，(ii)线路板30的第一线路结构31具有较厚的厚度，以构成较深的凹穴316，并使叠层式半导体次组件20的路由电路21及第二装置27皆延伸进入线路板30的凹穴316中。
图42为图41半导体组件510还设有第三装置61于第一线路结构31处及焊球73于第二线路结构36处的剖视图。该第三装置61叠层于叠层式半导体次组件20及线路板30的上方，并通过焊球71电性耦接至第一线路结构31。焊球73接置于第二线路结构36上，并电性耦接至第二线路结构36，用于外部连接。
图43为图41半导体组件510还设有透镜88于第一线路结构31处及焊球73于第二线路结构36处的剖视图。透镜88(对至少一光波长范围呈透光)叠层于叠层式半导体次组件20上方，并通过接合材881接置于第一线路结构31。焊球73接置于第二线路结构36上，并电性耦接至第二线路结构36，用于外部连接。透镜88的材料举例包括，但不限于，多晶陶瓷(如氧化铝陶瓷、氮氧化铝、钙钛矿、多晶钇铝石榴石等)、单晶陶瓷、非晶材料(如无机玻璃及聚合物)、玻璃陶瓷(如硅酸盐类)。接合材881可为金属类材料(如焊料)、环氧类材料、聚酰亚胺、任何其他树脂或合适材料。
[实施例6]
图44为本发明第六实施方案的半导体组件剖视图。
该半导体组件610类似于图37所示的结构，不同处在于，(i)该叠层式半导体次组件20还包括电性耦接至路由电路21并封埋于模封材25中的无源元件23，(ii)线路板30的第一线路结构31具有较厚的厚度，以构成较深的凹穴316，并使叠层式半导体次组件20的路由电路21及第二装置27皆延伸进入线路板30的凹穴316中。
图45为图44半导体组件610还设有第三装置61于第一线路结构31处及焊球73于第二线路结构36处的剖视图。该第三装置61叠层于叠层式半导体次组件20及线路板30的上方，并通过焊球71电性耦接至第一线路结构31。焊球73接置于第二线路结构36上，并电性耦接至第二线路结构36，用于外部连接。
图46为图44半导体组件610还设有透镜88于第一线路结构31处及焊球73于第二线路结构36处的剖视图。透镜88(对至少一光波长范围呈透光)叠层于叠层式半导体次组件20上方，并接置于第一线路结构31。焊球73接置于第二线路结构36上，并电性耦接至第二线路结构36，用于外部连接。
上述半导体组件仅为说明范例，本发明还可通过其他多种实施例实现。此外，上述实施例可基于设计及可靠度的考虑，彼此混合搭配使用或与其他实施例混合搭配使用。举例来说，第一线路结构可包括排列成数组形状的多个贯穿开口，且每一叠层式半导体次组件容置于其对应的贯穿开口中。另外，线路板的第一线路结构可包括额外导线，以连接额外叠层式半导体次组件。
如上实施方案所示，本发明建构出一种独特的半导体组件，其包括通过接合线相互电性耦接的叠层式半导体次组件及线路板。可选择性地还包括一密封材，以覆盖接合线。为方便下文描述，在此将路由电路及第一线路结构的第一表面所面向的方向定义为第一方向，而路由电路及第一线路结构的第二表面所面向的方向定义为第二方向。
该叠层式半导体次组件包括一第一装置、一第二装置、一路由电路及一选择性的模封材，其可通过下述步骤制成：通过如凸块，将第一装置电性耦接至路由电路的第一表面，其中路由电路可拆分式地接置于一牺牲载板上；选择性提供一模封材于路由电路上；从路由电路移除牺牲载板；以及通过如凸块或接合线，将第二装置电性耦接至路由电路的第二表面。据此，分别设置于路由电路第一表面及第二表面上的第一装置及第二装置，可通过路由电路相互电性连接。
第一装置及第二装置可为半导体芯片、已封装元件或无源元件。在此，第一装置可利用现有技术的覆晶接合工艺，以主动面朝向路由电路的方式，通过凸块电性耦接至路由电路，且未有金属化盲孔接触第一装置。同样地，于移除牺牲载板后，主动面朝向路由电路的第二装置亦可利用现有技术的覆晶接合工艺，通过凸块电性耦接至路由电路，且未有金属化盲孔接触第二装置。或者，主动面背向路由电路的第二装置亦可利用打线工艺，电性耦接至路由电路。
路由电路可为不具核心层的增层电路，以提供初步扇出路由/互连，以及第一及第二装置间的最短互连距离。较佳为，该路由电路为多层增层电路，其可包括至少一介电层及导线，所述导线填满介电层中的盲孔，并侧向延伸于介电层上。介电层与导线连续轮流形成，且需要的话可重复形成。据此，路由电路于第一表面及第二表面处形成有电性接点，以供第一装置从第一表面连接，以及供第二装置及下一级连接件从第二表面连接。
该线路板包括一散热座、一第一线路结构及一第二线路结构。该第一线路结构于第二表面处包含有电性接点，以供路由电路从第二方向连接，而该第二线路结构于外表面处包含有电性接点，用于从第一方向进行下一级连接。该第一线路结构具有一贯穿开口，其从第一表面延伸至第二表面，用于容置散热座及叠层式半导体次组件于其中。该第一线路结构并不限于特定结构，其可为多层路由电路，并侧向环绕第一装置、选择性模封材及散热座的***边缘。举例说明，该第一线路结构可包括一互连基板、一第一增层电路及一第二增层电路。第一增层电路及第二增层电路分别设置于互连基板的相反两侧上。互连基板可包括一核心层、分别设于核心层相反两侧上的第一及第二路由层、及贯穿核心层的金属化贯孔，其中金属化贯孔可提供第一路由层与第二路由层间的电性连接。第一及第二增层电路通常各自包括一介电层及一或多导线。第一及第二增层电路的介电层分别设置于互连基板的相反两侧上。导线侧向延伸于介电层上，并包括导电盲孔，所述导电盲孔接触互连基板的第一及第二路由层。此外，若需要更多信号路由，第一及第二增层电路可包括额外的介电层、额外的盲孔、及额外导线。第一及第二增层电路中位于第一及第二表面的最外层导线可容置导电接点，以供路由电路从第二表面连接，以及供第二线路结构从第一表面连接。第二线路结构覆盖散热座的背侧表面及第一线路结构的第一表面，并通过嵌埋于第二线路结构介电层中的金属化盲孔，电性耦接至散热座及第一线路结构，其中所述金属化盲孔会接触散热座的背侧表面及第一线路结构的第一表面。据此，第二线路结构的介电层会从第一方向覆盖散热座，且第二线路结构可对散热座提供机械支撑，而散热座可对通过导热材贴附于散热座上的第一装置提供散热及电磁屏蔽。由于散热座的厚度小于第一线路结构的厚度，故形成于线路板中的凹穴可用来容置叠层式半导体次组件。较佳为，该散热座为一金属层，且金属层的***边缘邻接且贴附至第一线路结构贯穿开口的侧壁。此外，可选择性地还包括一额外金属层，其与散热座及第一线路结构贯穿开口的侧壁接触，并完全覆盖第一线路结构贯穿开口侧壁的剩余部位。第二线路结构可为多层路由电路，并侧向延伸至第一线路结构的***边缘。较佳为，该第二线路结构为不具核心层的多层增层电路，其包括重复交替形成的介电层及导线。导线包含有位于介电层中的金属化盲孔，并侧向延伸于介电层上。第一线路结构及第二线路结构的最外层导线可分别容置导电接点，例如焊球或接合线，以与组件、电子元件、额外散热座、额外线路板或其他元件电性传输及机械性连接。例如，可将第三装置(可为一半导体芯片)接置于第二线路结构上，并通过多条合线，将第三装置电性耦接至第二线路结构；或者，该第三装置可为球栅数组封装或凸块化芯片，并通过多个焊球，接置并电性耦接至第一线路结构或第二线路结构。于本发明另一方案中，可进一步于第一线路结构的第二表面上接置另一额外散热座，且第二装置可设置于该额外散热座的凹穴内，并通过导热材以与额外散热座热性导通。此外，该额外散热座可通过如焊球，电性耦接至第一线路结构，以构成接地连接，其中焊球可接触该额外散热座及第一线路结构的最外层导线。或者，可进一步于叠层式半导体次组件及线路板上叠层另一额外线路板，且该额外线路板可从第一线路结构的第二表面电性耦接至第一线路结构。更具体地说，该额外线路板可包括一第三线路结构、一第四线路结构及一额外散热座。该第三线路结构具有一贯穿开口，其从第一表面延伸至第二表面，用于容置该额外散热座及第二装置于其中。较佳为，第三线路结构为多层路由电路，并侧向环绕额外散热座的***边缘及次组件位于第一线路结构贯穿开口外的部份。举例说明，该第三线路结构可包括一互连基板，其具有一核心层、分别设于核心层相反两侧上的路由层、及贯穿核心层的金属化贯孔，其中金属化贯孔可提供两侧路由层间的电性连接。或者，该第三线路结构可为不具核心层的多层增层电路，其包括重复交替形成的介电层及导线。据此，第三线路结构可于其相反的第一表面及第二表面处包含有电性接点，以与第一线路结构及第四线路结构电性连接。更进一步说，第三线路结构可通过如焊球，电性耦接至第一线路结构，其中焊球位于第一线路结构的第二表面与第三线路结构的第一表面间，而第四线路结构则可通过金属化盲孔，电性耦接至第三线路结构的第二表面。此外，第四线路结构亦可通过金属化盲孔，与设于第三线路结构贯穿开口中的散热座电性耦接，以构成接地连接。因此，当次组件的第二装置设置于第三线路结构的贯穿开口中时，该额外线路板中的散热座可对第二装置(通过导热材贴附于散热座)提供散热及电磁屏蔽。较佳为，第四线路结构为多层路由电路，并侧向延伸至第三线路结构的***边缘。举例说明，该第四线路结构可为不具核心层的多层增层电路，其包括重复交替形成的介电层及导线。据此，第四线路结构可于其外表面处包含有导线，以从第二方向提供电性接点，且可选择性地将第三装置叠层于第四线路结构的外表面上，并使第三装置电性耦接至第四线路结构的外表面。另外，当该叠层式半导体次组件为光学次组件时，可将对至少一光波长范围具透光性的透镜叠层于次组件上，并接置于线路板的第一线路结构上。
接合线提供次组件中路由电路与线路板中第一线路结构间的电性连接。于一较佳实施例中，所述接合线接触并接置于路由电路的第二表面及第一线路结构的第二表面，其中路由电路的第二表面会从第一线路结构的贯穿开口显露。据此，第一及第二装置可通过路由电路及接合线，电性连接至用于外部连接的线路板。
更可选择性提供一系列垂直连接件，其电性连接至线路板，用于下一级连接。较佳为，所述垂直连接件是由第一线路结构的第二表面，接触并电性耦接至第一线路结构。所述垂直连接件可包括金属柱、焊球或其他连接件，且被密封材侧向覆盖。由于垂直连接件的一选定部位未被密封材覆盖，故可将第三装置电性耦接至垂直连接件。
“覆盖”一词意指于垂直及/或侧面方向上不完全以及完全覆盖。例如，于一较佳实施方案中，散热座于第一方向覆盖第一装置，不论另一元件例如导热材是否位于第一装置与散热座间。
“贴附于…上”及”接置于…上”一词包括与单一或多个元件间的接触与非接触。例如，于一较佳实施方案中，散热座的***边缘贴附至贯穿开口的侧壁，不论散热座的***边缘是否与贯穿开口的侧壁接触或以一黏着剂相隔。
“电性连接”、以及”电性耦接”的词意指直接或间接电性连接。例如，于一较佳实施方案中，接合线直接接触并且电性连接至第一线路结构，而路由电路与第一线路结构保持距离，并且路由电路通过接合线而电性连接至第一线路结构。
“第一方向”及”第二方向”并非取决于半导体组件的定向，本领域技术人员即可轻易了解其实际所指的方向。例如，路由电路及第一线路结构的第一表面面朝第一方向，而路由电路及第一线路结构的第二表面面朝第二方向，此与半导体组件是否倒置无关。因此，该第一及第二方向彼此相反且垂直于侧面方向。此外，当第二线路结构的外表面朝向上方向时，则第一方向为向上方向，而第二方向为向下方向，当第二线路结构的外表面朝向下方向时，第一方向则为向下方向，而第二方向为向上方向。
本发明的半导体组件具有许多优点。举例来说，将第一及第二装置接置于路由电路的相对两侧上，可于第一装置与第二装置间提供最短的互连距离。路由电路可对第一装置与第二装置提供初级的扇出路由/互连，而线路板可提供第二级的扇出路由/互连。由于次组件的路由电路是通过接合线，连接至线路板的第一线路结构，而不是直接通过增层工艺进行连接，故此简化的工艺步骤可降低制作成本。散热座可提供第一装置的散热、电磁屏蔽、以及湿气阻障。第二线路结构可提供散热座机械支撑，并将热从散热座散出。通过此方法制备成的半导体组件为可靠度高、价格低廉、且非常适合大量制造生产。
本发明的制作方法具有高度适用性，且以独特、进步的方式结合运用各种成熟的电性及机械性连接技术。此外，本发明的制作方法不需昂贵工具即可实施。因此，相较于传统技术，此制作方法可大幅提升产量、良率、效能与成本效益。
在此所述的实施例为例示之用，其中所述实施例可能会简化或省略本技术领域已熟知的元件或步骤，以免模糊本发明的特点。同样地，为使附图清晰，附图亦可能省略重复或非必要的元件及元件符号。

Claims (12)

1.一种三维整合的散热增益型半导体组件，其包括：
一叠层式半导体次组件，其包括一第一装置、一第二装置及一路由电路，其中该第一装置电性耦接至该路由电路的一第一表面，而该第二装置电性耦接至该路由电路的一相反第二表面；
一线路板，其包括一第一线路结构、一第二线路结构及一散热座，其中(i)该第一线路结构具有一第一表面、一相反第二表面、及从该第一表面延伸至该第二表面的一贯穿开口，(ii)该散热座设置于该贯穿开口中，且该散热座的一背侧表面与该第一线路结构的该第一表面呈实质上共平面，(iii)该第二线路结构设置于该散热座的该背侧表面及该第一线路结构的该第一表面上，并通过金属化盲孔电性连接至该第一线路结构且热性导通至该散热座，且(iv)该叠层式半导体次组件设置于该贯穿开口中；以及
多条接合线，其电性耦接该路由电路至该线路板。
2.如权利要求1所述的半导体组件，其中，该散热座的***边缘邻近于该贯穿开口的侧壁，且该散热座的厚度小于该贯穿开口的深度，该叠层式半导体次组件通过一导热材，使该第一装置贴附于该散热座上。
3.如权利要求1所述的半导体组件，还包括：一第三装置，其叠层于该第一线路结构或该第二线路结构上，并电性耦接至该第一线路结构或该第二线路结构。
4.如权利要求1所述的半导体组件，还包括：一密封材，其覆盖所述接合线。
5.如权利要求1所述的半导体组件，还包括：一透镜，其设置于该叠层式半导体次组件上，并接置于该第一线路结构，其中该透镜对至少一光波长范围具透光性。
6.如权利要求1所述的半导体组件，还包括：一额外线路板，其叠层于该第一线路结构上，该额外线路板包括一第三线路结构、一第四线路结构及一额外散热座，其中(i)该第三线路结构具有一第一表面、一相反第二表面、及从该第一表面延伸至该第二表面的一贯穿开口，(ii)该额外散热座设置于该贯穿开口中，且该额外散热座的一背侧表面与该第三线路结构的该第二表面呈实质上共平面，(iii)该第四线路结构设置于该额外散热座的该背侧表面及该第三线路结构的该第二表面上，并通过金属化盲孔电性连接至该第三线路结构且热性导通至该额外散热座，且(iv)该第二装置贴附至该额外散热座，并被该第三线路结构侧向环绕，而该第三线路结构则电性耦接至该第一线路结构。
7.如权利要求1所述的半导体组件，还包括：另一散热座，其电性耦接至该第一线路结构，且与该第二装置热性导通。
8.一种三维整合的散热增益型半导体组件的制作方法，其包括：
提供一叠层式半导体次组件，其包括一第一装置、一第二装置及一路由电路，其中该第一装置电性耦接至该路由电路的一第一表面，而该第二装置电性耦接至该路由电路的一相反第二表面；
提供一线路板，其包括一第一线路结构、一第二线路结构及一散热座，其中(i)该第一线路结构具有一第一表面、一相反第二表面、及从该第一表面延伸至该第二表面的一贯穿开口，(ii)该散热座设置于该贯穿开口中，且该散热座的一背侧表面与该第一线路结构的该第一表面呈实质上共平面，且(iii)该第二线路结构设置于该散热座的该背侧表面及该第一线路结构的该第一表面上，并通过金属化盲孔电性连接至该第一线路结构且热性导通至该散热座；
将该叠层式半导体次组件设置于该第一线路结构的该贯穿开口中及该散热座上；以及
提供多条接合线，以电性耦接该路由电路及该线路板。
9.如权利要求8所述的制作方法，还包括一步骤：将一第三装置叠层于该第一线路结构或该第二线路结构上，且使该第三装置电性耦接至该线路板。
10.如权利要求8所述的制作方法，还包括以下步骤：
提供一额外线路板，其包括一第三线路结构、一第四线路结构及一额外散热座，其中(i)该第三线路结构具有一第一表面、一相反第二表面、及从该第一表面延伸至该第二表面的一贯穿开口，(ii)该额外散热座设置于该贯穿开口中，且该额外散热座的一背侧表面与该第三线路结构的该第二表面呈实质上共平面，且(iii)该第四线路结构设置于该额外散热座的该背侧表面及该第三线路结构的该第二表面上，并通过金属化盲孔电性连接至该第三线路结构且热性导通至该额外散热座；以及
将该额外线路板叠层于该第一线路结构上，并使该第三线路结构电性耦接至该第一线路结构，且该第二装置贴附至该额外散热座，并被该第三线路结构侧向环绕。
11.如权利要求8所述的制作方法，还包括一步骤：叠层另一散热座于该第一线路结构上，其中该另一散热座电性耦接至该第一线路结构并贴附至该第二装置。
12.如权利要求8所述的制作方法，还包括一步骤：叠层一透镜于该叠层式半导体次组件上，其中该透镜接置于该第一线路结构上，且该透镜对至少一光波长范围具透光性。
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