WO2023092512A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

Info

Publication number
WO2023092512A1
WO2023092512A1 PCT/CN2021/133740 CN2021133740W WO2023092512A1 WO 2023092512 A1 WO2023092512 A1 WO 2023092512A1 CN 2021133740 W CN2021133740 W CN 2021133740W WO 2023092512 A1 WO2023092512 A1 WO 2023092512A1
Authority
WO
WIPO (PCT)
Prior art keywords
anode
orthographic projection
substrate
anodes
data line
Prior art date
Application number
PCT/CN2021/133740
Other languages
English (en)
French (fr)
Inventor
尚庭华
张毅
周洋
韩林宏
王予
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180003638.9A priority Critical patent/CN116530234A/zh
Priority to PCT/CN2021/133740 priority patent/WO2023092512A1/zh
Publication of WO2023092512A1 publication Critical patent/WO2023092512A1/zh

Links

Images

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • OLED display device organic light-emitting diode (Organic Light-Emitting Diode, referred to as OLED) display device is one of the hotspots of display technology research today.
  • OLED display device includes a variety of performance parameters that affect the display effect, such as OLED display device Performance parameters mainly include power consumption, image display brightness, image display color coordinates, color gamut and viewing angle deviation, etc.
  • a display substrate including: a substrate, a first conductive layer, a first planar layer, and a plurality of anodes.
  • a first conductive layer is disposed on one side of the substrate, and the first conductive layer includes a plurality of first signal lines extending along a first direction; a first planar layer is disposed on the first conductive layer away from the substrate One side; a plurality of anodes are disposed on the side of the first flat layer away from the substrate.
  • the first conductive layer is the conductive layer closest to the multiple anodes between the substrate and the multiple anodes.
  • the orthographic projection of at least one of the plurality of anodes on the substrate does not overlap with the orthographic projection of each first signal line on the substrate; and/or, the plurality of anodes
  • the orthographic projection of at least one of them on the substrate overlaps the orthographic projection of at least one first signal line on the substrate; in the overlapping anode and at least one first signal line of the orthographic projection, the At least one first signal line passes through the set position of the anode, so that taking the center line of the anode along the first direction as the axis of symmetry, the heights of the symmetrical positions in the anode are approximately equal.
  • At least A first signal line when the orthographic projection of at least one of the plurality of anodes on the substrate does not overlap with the orthographic projection of each first signal line on the substrate, at least A first signal line includes at least one straight portion and at least one bent portion; each straight portion and each bent portion are arranged alternately.
  • the straight portion extends along the first direction, and the orthographic projection of the straight portion on the substrate is located on one side of the anode's orthographic projection along the first direction.
  • the bent portion includes a first segment, a second segment and a third segment connected in sequence, the second segment extends along the first direction, and the orthographic projection of the second segment on the substrate is located at The orthographic projection of the anode is along one side in the second direction to avoid the orthographic projection of the anode, the first section connects adjacent straight sections, and the third section connects adjacent straight sections; wherein , the second direction is perpendicular to the first direction.
  • the distance between the second segment of the bent portion and the straight portion of each first signal line is 1 ⁇ m ⁇ 10 ⁇ m.
  • the orthographic projection of at least one of the plurality of anodes on the substrate overlaps with the orthographic projection of at least one first signal line on the substrate
  • the The orthographic projection of the anode overlaps with the orthographic projection of a first signal line; the orthographic projection of the first signal line coincides with the midline of the anode's orthographic projection along the first direction.
  • the orthographic projection of at least one of the plurality of anodes on the substrate overlaps with the orthographic projection of at least one first signal line on the substrate
  • the The orthographic projection of the anode overlaps with the orthographic projection of the plurality of first signal lines; the portion of the plurality of first signal lines passing through the anode is arranged symmetrically with respect to the midline of the anode along the first direction.
  • the orthographic projection of the first signal line on the substrate has no overlap with the orthographic projections of other anodes of the plurality of anodes that are adjacent to the anode on the substrate.
  • the distance between two adjacent first signal lines is 5 ⁇ m ⁇ 30 ⁇ m, wherein the second direction is perpendicular to the first direction.
  • the first conductive layer includes a plurality of data lines, and the plurality of first signal lines are the plurality of data lines.
  • the display substrate also includes a second conductive layer and a second flat layer.
  • the second flat layer is disposed on a side of the first conductive layer away from the first flat layer.
  • the second conductive layer is disposed on a side of the second planar layer away from the first conductive layer; the second conductive layer includes a plurality of voltage signal lines.
  • the first conductive layer includes a plurality of data lines and a plurality of voltage signal lines; the plurality of first signal lines are the plurality of data lines and the plurality of voltage signal lines.
  • the display substrate includes a plurality of pixel circuits, and each pixel circuit includes at least two thin film transistors and at least one capacitor.
  • the plurality of pixel circuits include a plurality of first pixel circuits, a plurality of second pixel circuits and a plurality of third pixel circuits, the plurality of pixel circuits are arranged into a plurality of pixel circuit columns, and the plurality of pixel circuit columns include A plurality of first pixel circuit columns and a plurality of second pixel circuit columns, each first pixel circuit column includes a plurality of first pixel circuits and a plurality of second pixel circuits arranged in a row along the first direction and arranged alternately Each second pixel circuit column includes a plurality of third pixel circuits arranged in a column along the first direction; along the second direction, the first pixel circuit column and the second pixel circuit column are arranged alternately.
  • the plurality of anodes include a plurality of first anodes, a plurality of second anodes and a plurality of third anodes, the plurality of anodes are arranged into a plurality of anode columns, and the plurality of anode columns include a plurality of first anode columns, A plurality of second anode columns and a plurality of third anode columns.
  • Each first anode row includes a plurality of first anodes arranged in a row along the first direction
  • each second anode row includes a plurality of second anodes arranged in a row along the first direction
  • each third The anode row includes a plurality of third anodes arranged in a row along the first direction.
  • the first anode row, the second anode row and the third anode row are arranged in a cycle.
  • each first pixel circuit is electrically connected to a first anode
  • each second pixel circuit is electrically connected to a second anode
  • each first pixel circuit corresponding to the first pixel circuit column The anode and each second anode respectively belong to the adjacent first anode column and the second anode column
  • each third pixel circuit is electrically connected to a third anode
  • the second pixel circuit The third anodes corresponding to the columns belong to the same third anode column.
  • the second direction is perpendicular to the first direction.
  • the plurality of data lines include a plurality of first data lines and a plurality of second data lines.
  • Each first data line is electrically connected to each first pixel circuit and each second pixel circuit in a first pixel circuit column, so as to be connected to each first pixel circuit included in the first anode column corresponding to the first pixel circuit column.
  • An anode is electrically connected to each second anode included in the second anode row.
  • Each second data line is electrically connected to each third pixel circuit in a second pixel circuit column, so as to be electrically connected to each third anode included in the third anode column corresponding to the second pixel circuit column.
  • each data line has a plurality of connection portions correspondingly electrically connected to a plurality of pixel circuits in the pixel circuit column.
  • a connection portion corresponding to the second pixel circuit is covered by a second anode electrically connected to the second pixel circuit.
  • two connecting portions correspondingly connecting two adjacent third pixel circuits are respectively located on two sides of the second data line.
  • the orthographic projection of at least one of the plurality of anodes on the substrate does not overlap with the orthographic projection of each first signal line on the substrate, and at least one first signal line
  • the signal line includes at least one straight portion and at least one bent portion
  • the first signal line includes the first data line
  • the first data line includes a plurality of straight portions and a plurality of bent portions, so The first data line is located between the adjacent first anode column and the second anode column.
  • the orthographic projection of each straight portion of the first data line is located on one side of the orthographic projection of a first anode in the first anode column along the second direction, and is located on one side of the second anode column
  • the orthographic projection of the second anode is along one side of the first direction
  • the orthographic projection of the second section of each bent portion of the first data line is located in one second anode in the second anode column
  • the orthographic projection of is along one side of the second direction to avoid the orthographic projection of the second anode
  • the first signal line includes the second data line
  • the second data line It includes a plurality of straight sections and a plurality of bent sections
  • the second data line is located between the adjacent third anode columns and the first anode columns.
  • the orthographic projection of each straight portion of the second data line is located on one side of the orthographic projection of a first anode in the first anode column along the second direction, and is located on one side of the third anode column
  • the orthographic projection of the third anode is along one side of the first direction;
  • the orthographic projection of the second segment of each bent portion of the second data line is a third anode located in the third anode column
  • the orthographic projection of is along one side of the second direction to avoid the orthographic projection of the third anode.
  • every two adjacent third anodes are grouped into a group, and along the first direction, two third anodes in each group
  • the distance between the third anodes is smaller than the distance between the two third anodes and other surrounding third anodes.
  • the orthographic projection of each straight portion of the second data line on the substrate is located on one side of the orthographic projection of a group of third anodes on the substrate along the first direction.
  • the orthographic projection of the second segment of each bent portion of the second data line on the substrate is located in the second direction along the orthographic projection of the group of third anodes on the substrate to avoid the orthographic projection of the group of third anodes on the substrate.
  • the first signal line is the first data line.
  • the orthographic projection of the first data line coincides with the centerline along the first direction of the orthographic projections of the second anodes included in the one second anode column.
  • the two first signal lines are adjacent to the first anode column, the The first data line and the second data line corresponding to the second anode column and the third anode column.
  • the orthographic projections of the first data line and the second data line overlap with the orthographic projections of each third anode included in a third anode column, and the first data line and the second data line
  • the portion passing through each third anode is arranged symmetrically with respect to the centerline of the third anode along the first direction.
  • the orthographic projection of the second data line does not overlap with the orthographic projection of the adjacent first anode.
  • the orthographic projection of the first data line does not overlap with the orthographic projection of its adjacent second anode; or, the orthographic projection of the first data line overlaps with each second anode in the adjacent second anode column , the overlapping portion of the orthographic projection of the first data line coincides with the centerline along the first direction of the orthographic projection of each second anode in the second anode column.
  • the display substrate further includes: a buffer layer, a semiconductor layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, a second insulating layer, a pixel defining layer, multiple A luminescent functional layer and a cathode layer.
  • the buffer layer is disposed on the substrate.
  • the semiconductor layer is disposed on a side of the buffer layer away from the substrate, the semiconductor layer includes a plurality of semiconductor patterns, and each semiconductor pattern includes active layers of a plurality of transistors in the pixel circuit.
  • the gate insulating layer is disposed on a side of the semiconductor layer away from the substrate.
  • the first gate metal layer is disposed on the side of the gate insulating layer away from the substrate; the first gate metal layer includes a plurality of first patterns, and each first pattern is a capacitor in the pixel circuit. first plate.
  • the first insulating layer is disposed on a side of the first gate metal layer away from the substrate.
  • the second gate metal layer is disposed on a side of the first insulating layer away from the substrate; the second gate metal layer includes a plurality of second patterns, and each second pattern is a capacitor in the pixel circuit. of the second plate.
  • the second insulating layer is disposed on a side of the second gate metal layer away from the substrate.
  • the pixel defining layer is disposed on a side of the plurality of anodes and the first flat layer away from the substrate; the pixel defining layer defines a plurality of openings; each opening exposes at least a part of an anode.
  • the plurality of light-emitting functional layers are disposed on the side of the plurality of anodes away from the substrate, and each light-emitting functional layer is located in an opening.
  • the cathode layer is disposed on the side of the light-emitting functional layer away from the substrate, the cathode layer extends to the side of the pixel defining layer away from the substrate, and covers the pixel defining layer.
  • each pixel circuit includes at least a compensation transistor, a driving transistor and a capacitor.
  • the active layer of the compensation transistor includes a first polar region, a second polar region, and a channel region connecting the first polar region and the second polar region.
  • the active layer of the driving transistor includes a first polar region, a second polar region, and a channel region connecting the first polar region and the second polar region.
  • the overlapping portion of the first plate of the capacitor in the first gate metal layer and the channel region of the driving transistor serves as the gate of the driving transistor.
  • the first polar region of the compensation transistor is electrically connected to the second polar region of the driving transistor, and the second polar region of the compensation transistor is electrically connected to the gate of the driving transistor through a connection structure.
  • each second anode on the substrate overlaps with the orthographic projection of the connection structure of two adjacent pixel circuits on the substrate, and one of the two adjacent pixel circuits One is a second pixel circuit electrically connected to the second anode, and the other is a third pixel circuit adjacent to the second pixel circuit.
  • the second plate of the capacitor of each pixel circuit overlaps.
  • a display device including: the display substrate as described in any one of the above aspects.
  • Fig. 1 is a cross-sectional structure diagram of a display substrate provided according to some embodiments.
  • Fig. 2 is another cross-sectional structure diagram of a display substrate provided according to some embodiments.
  • Fig. 3 is another cross-sectional structure diagram of a display substrate provided according to some embodiments.
  • Fig. 4 is another cross-sectional structure diagram of a display substrate provided according to some embodiments.
  • Fig. 5 is a structural diagram of a display device provided according to some embodiments.
  • Fig. 6 is a structural diagram of a display substrate provided according to some embodiments.
  • Fig. 7A is a partial cross-sectional view of a display substrate provided according to some embodiments.
  • Fig. 7B is a partial cross-sectional view of another display substrate according to some embodiments.
  • FIG. 7C is a circuit equivalent diagram of a pixel circuit according to some embodiments.
  • Fig. 8A is a layer structure diagram of a display substrate provided according to some embodiments.
  • Fig. 8B is a structure diagram of an anode provided according to some embodiments.
  • Figure 8C is a structural diagram of another anode provided according to some embodiments.
  • Fig. 8D is another anode structure diagram provided according to some embodiments.
  • Fig. 9A is a structural diagram of an anode and a signal line according to some embodiments.
  • Fig. 9B is a structural diagram of another anode and signal line provided according to some embodiments.
  • Fig. 9C is another structure diagram of anodes and signal lines according to some embodiments.
  • Fig. 10A is another structure diagram of anodes and signal lines according to some embodiments.
  • Fig. 10B is another structural diagram of anodes and signal lines provided according to some embodiments.
  • Fig. 10C is another structural diagram of anodes and signal lines according to some embodiments.
  • Fig. 10D is another structure diagram of anodes and signal lines according to some embodiments.
  • Fig. 11 is another film structure diagram of a display substrate provided according to some embodiments.
  • Fig. 12 is another layer structure diagram of a display substrate provided according to some embodiments.
  • Fig. 13 is another layer structure diagram of a display substrate provided according to some embodiments.
  • Fig. 14 is another layer structure diagram of a display substrate provided according to some embodiments.
  • Fig. 15 is another layer structure diagram of a display substrate provided according to some embodiments.
  • Fig. 16 is another layer structure diagram of a display substrate provided according to some embodiments.
  • Fig. 17 is another layer structure diagram of a display substrate provided according to some embodiments.
  • 18 to 24 are plan views of each film layer in the display substrate provided according to FIG. 7B;
  • FIG. 25 is another plan view of each film layer in the display substrate provided according to FIG. 24;
  • FIG. 26 is a plan view of each film layer in a single pixel circuit region of the display substrate provided according to FIG. 25 .
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • the expressions “coupled” and “electrically connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • the term “electrically connected” may be used when describing some embodiments to indicate that two or more components are in direct electrical contact.
  • the term “electrically connected” may also mean that two or more components are not in direct contact with each other, but still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the context herein.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • the performance parameters of the display device mainly include power consumption, image display brightness, image display color coordinates, color gamut, viewing angle deviation, and the like.
  • the performance parameters of the display device mainly include power consumption, image display brightness, image display color coordinates, color gamut, viewing angle deviation, and the like.
  • the flatness of the anode corresponding to each pixel has a great influence on the color shift.
  • the pattern of the metal conductive layer closest to the anode has the greatest influence on the flatness of the anode, so that the height of the anode at different positions is inconsistent.
  • anode For an anode, if there is a metal conductive pattern on the lower left side of the anode, and there is no metal conductive pattern on the lower right side of the anode, the position on the left side of the anode is higher than that on the right side, and it is located under the anode.
  • the pattern of the metal conductive layer will cause the anode to "tilt", making the thickness of the light-emitting functional layer above the anode uneven, resulting in a mismatch in the light intensity emitted by the pixel to the left and right sides. In this case, the display panel occurs.
  • the role of big vision is biased, and it appears that one side is red and the other side is blue.
  • the present disclosure improves the flatness of the plane where the anode is located by adjusting the positional relationship between the pattern of the metal conductive layer and the anode, and avoids the angle inclination of the plane where the anode is located relative to the horizontal plane, which may cause the display panel to appear. Color cast phenomenon.
  • the display device 1000 is a device or device for visually displaying electronic information.
  • the display device 1000 may be any product or component with a display function, such as a smart phone, a tablet computer, a television, a monitor, a notebook computer, and other wearable electronic devices (such as watches).
  • the display device 1000 may also be an electroluminescent display device or a photoluminescent display device.
  • the electroluminescent display device may be an organic electroluminescent diode (Organic Light-Emitting Diode, OLED for short) display device or a quantum dot electroluminescent diode (Quantum Dot Light Emitting Diode). Diodes, referred to as QLED) display device.
  • the display device 1000 is a photoluminescent display device
  • the photoluminescent display device may be a quantum dot photoluminescent diode display device.
  • the display device 1000 is an active matrix organic light emitting diode (Active-matrix organic light emitting diode, referred to as AMOLED) display device, which has faster response speed, higher contrast ratio, wider viewing angle and lower power consumption, etc. It is one of the research hotspots in the field of display technology today.
  • AMOLED active matrix organic light emitting diode
  • the above display device 1000 includes a display substrate 100 .
  • the display substrate 100 includes a display area AA (Active Area, referred to as AA area; also called an active display area) and a peripheral area BB located at least one side of the AA area.
  • AA area Active Area
  • BB peripheral area
  • each pixel P' includes at least three colors
  • the sub-pixel P of multiple colors includes at least a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3, wherein the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel
  • the light emitting colors of the pixels P3 are different, and the three colors are three primary colors (for example, red, green and blue).
  • a pixel circuit for controlling the sub-pixel P to display is disposed in the sub-pixel P, and the pixel circuit is disposed on the substrate 1 of the display substrate 100 .
  • the gate line GL connected to the sub-pixel P is used to transmit the scanning signal Gate to the pixel circuit of the sub-pixel P;
  • the data line DL connected to the sub-pixel P is used to transmit the data signal Data to the pixel circuit of the sub-pixel P, and the data signal Data comes from A source driver (Source Driver, SD for short) coupled to each data line DL.
  • the display substrate 100 includes a plurality of pixel circuits 200 .
  • the stacking sequence of the film layer diagram shown in FIG. 25 is opposite to that of the film layers in FIG.
  • the lower layer is the light emitting functional layer 13 .
  • the plurality of pixel circuits 200 includes a plurality of first pixel circuits 201 , a plurality of second pixel circuits 202 and a plurality of third pixel circuits 203 .
  • a plurality of pixel circuits 200 are arranged into a plurality of pixel circuit columns, and the plurality of pixel circuit columns include a plurality of first pixel circuit columns 210 and a plurality of second pixel circuit columns 220, and each first pixel circuit column 210 includes a plurality of pixel circuit columns along a first direction.
  • the first pixel circuit columns 210 and the second pixel circuit columns 220 are arranged alternately.
  • Each of the above pixel circuits 200 includes a plurality of thin film transistors TFT and at least one capacitor 01 .
  • the pixel circuit 200 includes a first reset transistor group T1, a compensation transistor T2, a drive transistor T3, a write transistor T4, a first light emission control transistor T5, and a second light emission control transistor T6. , the second resetting transistor T7 and the capacitor O1.
  • the control pole of the first reset transistor T1 is electrically connected to the first reset signal terminal Reset1, its first pole is electrically connected to the initialization signal terminal Vinit1, and its second pole is electrically connected to the first node N1.
  • the control electrode of the compensation transistor T2 is electrically connected to the scan signal terminal Gate, its first electrode is electrically connected to the second node N2, and its second electrode is electrically connected to the first node N1.
  • the control electrode of the driving transistor T3 is electrically connected to the first node N1, its first electrode is electrically connected to the third node N3, and its second electrode is electrically connected to the second node N2.
  • the control electrode of the writing transistor T4 is electrically connected to the scanning signal terminal Gate, the first electrode thereof is electrically connected to the data writing signal terminal VData, and the second electrode thereof is electrically connected to the third node N3.
  • the control pole of the first light emission control transistor T5 is electrically connected to the enable signal terminal EM, the first pole thereof is electrically connected to the first power supply voltage terminal VDD, and the second pole thereof is electrically connected to the third node N3.
  • the control electrode of the second light emission control transistor T6 is electrically connected to the enable signal terminal EM, its first electrode is electrically connected to the second node N2 , and its second electrode is electrically connected to the anode of the light emitting device 02 .
  • the control electrode of the second reset transistor T7 is electrically connected to the second reset signal terminal Reset2 , its first electrode is electrically connected to the initialization signal terminal Vinit1 , and its second electrode is electrically connected to the anode of the light emitting device 02 .
  • the second plate 012 of the capacitor 01 is electrically connected to the first power supply voltage terminal VDD, and the first plate 011 thereof is electrically connected to the first node N1.
  • the cathode of the light emitting device 02 is electrically connected to the second power supply voltage terminal VSS.
  • the circuit structures of the first pixel circuit 201 , the second pixel circuit 202 and the third pixel circuit 203 are the same.
  • the first pole of the above-mentioned thin film transistor TFT may be a source, and the second pole may be a drain; or, the first pole may be a drain, and the second pole may be a source, which is not limited in the embodiments of the present disclosure.
  • the above-mentioned first node N1, second node N2 and third node N3 do not represent actual components, but represent the confluence points of electrical connections of relevant sub-circuits or electronic components in the circuit diagram, that is to say, these nodes are formed by relevant sub-circuits or electronic components in the circuit diagram.
  • VDD in the above-mentioned first power supply voltage VDD is a constant high potential signal, and embodiments of the present disclosure do not limit the voltage signal to be a constant high potential signal such as VDD or VGH.
  • VSS in the second power supply voltage terminal VSS is a constant low potential signal, and embodiments of the present disclosure do not limit the voltage signal to be a constant low potential signal such as VSS, Vinit or VGL.
  • thin film transistors include P-type thin film transistors and N-type thin film transistors.
  • the thin film transistor provided in the embodiment of the present disclosure is not limited thereto, and may be a P-type thin film transistor or an N-type thin film transistor, which is selected and set according to a specific implementation manner.
  • thin film transistors include bottom gate thin film transistors and top gate thin film transistors, which are not limited to the thin film transistors provided in the embodiments of the present disclosure, and the following embodiments take top gate thin film transistors as examples.
  • the film layers included in the display substrate 100 are: a substrate 1, a buffer layer 2, and a semiconductor layer 3. , gate insulating layer 4, first gate metal layer 5, first insulating layer 6, second gate metal layer 7, second insulating layer 8, first conductive layer 9, first planar layer 10, multiple anodes 11, pixel A boundary layer 12 , a plurality of light emitting functional layers 13 and a cathode layer 14 .
  • the material used for the above-mentioned substrate 1 may include polymer resin or glass.
  • materials used for the substrate include polymer resins such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), Polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC) and cellulose acetate propionate ( CAP).
  • the substrate 1 may be flexible, comprising a glass material containing SiO2 as a main component, or rigid, comprising a resin such as reinforced plastic.
  • the substrate 1 may have a stack structure including a layer including the above polymer resin and a barrier layer on the above polymer resin layer.
  • the substrate 1 may have a stack structure including a first polymer resin layer, a first barrier layer, a second polymer resin layer, and a second barrier layer.
  • a substrate including a polymer resin can improve flexibility.
  • the first barrier layer and the second barrier layer may include silicon nitride (SiNx), silicon oxynitride (SiON), or/and silicon oxide (SiOx).
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • SiOx silicon oxide
  • the buffer layer 2 is provided on the substrate 1 .
  • the material used for the buffer layer 2 may include inorganic insulating materials such as silicon nitride (SiNx, x>0), silicon oxynitride (SiON) and silicon oxide (SiOx, x>0), and may include inorganic insulating materials containing the above-mentioned inorganic insulating materials. Single or multi-layer structure.
  • the buffer layer 2 can serve as a buffer when forming patterns on the substrate 1 .
  • the semiconductor layer 3 is disposed on the side of the buffer layer 2 away from the substrate 1 .
  • the material used for the semiconductor layer 3 may include polysilicon, amorphous silicon, oxide semiconductor or organic semiconductor.
  • the semiconductor layer 3 includes a plurality of semiconductor patterns 31 , and each semiconductor pattern 31 includes active layers of a plurality of thin film transistors TFT in the pixel circuit 200 .
  • the active layer of the compensation transistor T2 in the pixel circuit 200 includes a first polar region T21, a second polar region T22, and a channel region T23 connecting the first polar region T21 and the second polar region T22.
  • the active layer of the driving transistor T3 includes a first polar region T31, a second polar region T32, and a channel region T33 connecting the first polar region T31 and the second polar region T32.
  • the first pole region T21 and the second pole region T22 of the compensation transistor T2 are the first pole and the second pole of the compensation transistor T2 in FIG. 7C respectively
  • the first pole region T31 and the second pole region T32 of the driving transistor T3 are respectively are the first pole and the second pole of the driving transistor T3 in FIG. 7C.
  • the gate insulating layer 4 is disposed on a side of the semiconductor layer 3 away from the substrate 1 .
  • the material used for the gate insulating layer 4 may include inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide and/or hafnium oxide; layer structure.
  • the first gate metal layer 5 is disposed on a side of the gate insulating layer 4 away from the substrate 1 .
  • the material used for the first gate metal layer 5 can include low-resistance metal materials, for example, can include conductive materials molybdenum Mo, magnesium Mg, aluminum Al, copper Cu and/or titanium Ti; layer structure.
  • the first gate metal layer 5 includes a plurality of gate scan lines 50 and a plurality of first patterns 52, at least one of the plurality of gate scan lines is the first gate scan line 50, the first gate scan line 50 is the same as that shown in FIG.
  • each first pattern 52 is the first plate 011 of the capacitor 01 in the pixel circuit 200, and the first plate 011 of the capacitor 01 is the first plate 011 of the capacitor 01 in FIG. 7C. pole.
  • the overlapping portion of the first gate scanning line 50 and the channel region T23 of the compensation transistor T2 serves as the gate (control electrode) of the compensation transistor T2, for example,
  • the overlapping portion of the first plate 011 of each capacitor 01 with the channel region T33 of the driving transistor T3 serves as the gate of the driving transistor T3.
  • the first insulating layer 6 is disposed on a side of the first gate metal layer 5 away from the substrate 1 .
  • the material used for the first insulating layer 6 may include inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide and/or hafnium oxide; multi-layer structure.
  • the second gate metal layer 7 is disposed on a side of the first insulating layer 6 away from the substrate 1 .
  • the second gate metal layer 7 includes a plurality of second patterns 71 , and each second pattern 71 is the second plate 012 of the capacitor 01 in the pixel circuit 200 .
  • the second plate 71 works together with the first plates 011 of the plurality of capacitors 01 formed in the first gate metal layer 5 to serve as storage capacitors and provide storage capacitance for the pixel circuit 200 .
  • the plurality of second patterns 71 in each row can be connected as a whole.
  • the second gate metal layer 7 can be made of the same material as the first gate metal layer 5 .
  • the second insulating layer 8 is disposed on the side of the second gate metal layer 7' away from the substrate 1.
  • the material used for the second insulating layer 8 may include inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide and/or hafnium oxide; multi-layer structure.
  • the first conductive layer 9 is disposed on a side of the second insulating layer 8 away from the substrate 1 .
  • the material used for the first conductive layer 9 may include any one or more of conductive materials including molybdenum Mo, magnesium Mg, aluminum Al, copper Cu and titanium Ti.
  • the first conductive layer 9 includes a plurality of first signal lines 93, and the plurality of first signal lines 93 are a plurality of data lines and a plurality of voltage signal lines; the first conductive layer 9 also includes a source 91 and a drain of a thin film transistor TFT 92, and a plurality of first via electrodes 94, etc.
  • the source electrode 91 and the drain electrode 92 may include a single-layer or multi-layer structure including the above materials. Exemplarily, the source electrode 91 and the drain electrode 92 may include a multilayer structure of Ti/Al/Ti.
  • the first planar layer 10 is disposed on a side of the first conductive layer 9 away from the substrate 1 .
  • the material used for the first flat layer 10 may include organic insulating materials, inorganic insulating materials or both inorganic and organic insulating materials.
  • organic insulating materials include general-purpose polymers such as polymethyl methacrylate (PMMA) and polystyrene (PS), polymer derivatives with phenolic groups, acryl-based polymers, imide Any one or more of polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers and vinyl alcohol polymers.
  • the material used for the first flat layer 10 includes polyimide.
  • a plurality of anodes 11 are disposed on a side of the first planar layer 10 away from the substrate 1 .
  • the material used for the plurality of anodes 11 may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide Any one or more of (AZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • In2O3 indium oxide
  • IGO indium gallium oxide
  • AZO aluminum zinc oxide Any one or more of
  • the material used for the plurality of anodes 11 includes indium tin oxide (ITO).
  • the pixel defining layer 12 is disposed on the side of the plurality of anodes 11 and the first flat layer 10 away from the substrate 1 , and the pixel defining layer 12 defines a plurality of openings; each opening exposes at least a part of an anode 11 .
  • the material used for the pixel defining layer 12 includes at least one of an inorganic insulating material and an organic insulating material, such as silicon nitride (SiNx), silicon oxynitride (SiON), and silicon oxide (SiOx).
  • a plurality of light-emitting functional layers 13 are disposed on a side of the plurality of anodes 11 away from the substrate 1 , and each light-emitting functional layer 13 is located in an opening.
  • the plurality of light-emitting functional layers 13 may be a single-layer structure, or may be a multi-layer structure.
  • the light-emitting functional layer 13 only includes a light-emitting layer.
  • the light emitting functional layer 13 includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.
  • Materials used for the light emitting functional layer 13 include inorganic light emitting materials or organic light emitting materials. Exemplarily, different types of organic luminescent materials have different colors of emitted light.
  • the cathode layer 14 is disposed on the side of the light-emitting functional layer 13 away from the substrate 1 , the cathode layer 14 extends to the side of the pixel defining layer 12 away from the substrate 1 , and covers the pixel defining layer 12 .
  • the material used for the cathode layer 14 may include a (semi)transparent layer comprising any one of silver Ag, magnesium Mg, aluminum Al, platinum Pt, gold Au, nickel Ni, chromium Cr and lithium Li or Various.
  • the material used for the cathode layer 14 includes aluminum Al.
  • the display substrate 100 further includes a second conductive layer 9 ′ and a second flat layer 10 ′, and the second flat layer 10 ′ is disposed on the first conductive layer 9 away from the first flat layer 10 . side.
  • the first conductive layer 9 includes a plurality of first signal lines 93 , a plurality of first via electrodes 94 and a plurality of second via electrodes 95 .
  • the second conductive layer 9' is arranged on the side of the second planar layer 10' away from the first conductive layer 9, as shown in Figure 21 and Figure 22, the second conductive layer includes a plurality of second signal lines 91', a plurality of connections structure 92', and the source 91 and drain 92 of the thin film transistor TFT.
  • the multiple second signal lines 91' are multiple voltage signal lines. That is, the display substrate 100 has a structure of two metal conductive layers.
  • the second conductive layer 9' can use the same material as the first conductive layer 9.
  • the plurality of first signal lines 93 included in the first conductive layer 9 are a plurality of data lines and a plurality of The voltage signal line
  • the first conductive layer 9 also includes the source 91 and the drain 92 of the thin film transistor TFT, and a plurality of first transfer electrodes 94 and the like.
  • Multiple first via electrodes 94 are connected to the film layer where multiple anodes 11 are located and the first conductive layer 9 , for example, each first via electrode 94 is connected to one anode 11 and the drain 92 of one thin film transistor TFT.
  • the first via electrodes 94 are connected to the multiple lines after moving and bending.
  • the patterns of the first signal lines 93 do not overlap, so as to ensure the normal operation of the first via electrodes 94 and the plurality of first signal lines 93 .
  • the multiple first signal lines 93 included in the first conductive layer 9 are multiple data lines
  • the first conductive layer 9 also includes a plurality of first transfer electrodes 94 and a plurality of second transfer electrodes 95
  • the plurality of second signal lines 91' included in the second conductive layer 9' are a plurality of voltage signal lines.
  • the second conductive layer 9' also includes a source 91 and a drain 92 of the thin film transistor TFT.
  • a plurality of second via electrodes 95 are connected to the first conductive layer 9 and the second conductive layer 9', for example, each second via electrode 95 is connected to a first via electrode 94 and a drain 92 of a thin film transistor TFT, To electrically connect the thin film transistor TFT with its corresponding anode 11 .
  • the first conductive layer 9 includes a plurality of first signal lines 93 and a plurality of first via electrodes 94 and a plurality of second via electrodes 95 , regardless of the first No matter how the shape of the signal line 93 changes, it is necessary to ensure that the first via electrode 94 and the second via electrode 95 do not overlap with the patterns of the moved and bent first signal lines 93, so as to ensure that the first via electrode 94 and the plurality of first signal lines 93 work normally.
  • the display substrate 100 includes a plurality of sub-pixels P, and the plurality of sub-pixels P includes a plurality of first sub-pixels P1 , a plurality of second sub-pixels P2 and a plurality of third sub-pixels P3 .
  • the arrangement of the plurality of first sub-pixels P1, the plurality of second sub-pixels P2 and the plurality of third sub-pixels P3 is as follows:
  • a plurality of sub-pixels P are arranged into a plurality of sub-pixel columns, and the plurality of sub-pixel columns include a plurality of first sub-pixel columns, a plurality of second sub-pixel columns and a plurality of third sub-pixel columns.
  • the plurality of sub-pixel columns includes a sequential cyclic arrangement of a plurality of first sub-pixel columns, a plurality of second sub-pixel columns and a plurality of third sub-pixel columns.
  • first direction Y multiple first sub-pixels P1 are located in the same column; multiple second sub-pixels P2 are located in the same column; multiple third sub-pixels P3 are located in the same column.
  • the first direction Y is perpendicular to the second direction X.
  • multiple sub-pixels P in two adjacent columns of sub-pixels P are arranged alternately.
  • the first sub-pixel P1 is a red sub-pixel
  • the second sub-pixel P2 is a blue sub-pixel
  • the third sub-pixel P3 is a green sub-pixel.
  • the first sub-pixel P1 is a blue sub-pixel
  • the second sub-pixel P2 is a red sub-pixel
  • the third sub-pixel P3 is a green sub-pixel.
  • the first sub-pixel P1 , the second sub-pixel P2 and the third sub-pixel P3 are sub-pixels of different colors, this is not limited in the embodiment of the present disclosure.
  • the first sub-pixel P1 is a red sub-pixel
  • the second sub-pixel P2 is a blue sub-pixel
  • the third sub-pixel P3 is a green sub-pixel for illustration.
  • one pixel P' includes four sub-pixels P as shown in FIG. 8A.
  • a pixel P' includes a first sub-pixel P1, a second sub-pixel P2 and two third sub-pixels P3.
  • one pixel P' includes three sub-pixels P.
  • a pixel P' includes a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3.
  • the number of sub-pixels P of different colors included in the above-mentioned one pixel P' is related to the configuration requirements of the actual display device 1000, and those skilled in the art can select settings according to actual requirements, which is not limited in the present disclosure. As long as the plurality of sub-pixels P are coupled to the gate line GL and the data line DL, image display can be realized under the control of corresponding signals.
  • each first sub-pixel P1 includes a first anode 111 ; each second subpixel P2 includes a second anode 112 ; each third subpixel P3 includes a third anode 113 .
  • each first sub-pixel P1 of the plurality of first sub-pixels P1 further includes a light-emitting functional layer 13 and a cathode.
  • the first anode 111 , the light-emitting functional layer 13 and the cathode constitute the light-emitting device 02 .
  • each of the second sub-pixel P2 and the third sub-pixel P3 further includes a light-emitting functional layer 13 and a cathode.
  • the shapes of the first anode 111, the second anode 112 and the third anode 113 are different. As shown in FIG. 8B to FIG.
  • the shape of the anode 113 is approximately pentagonal, and the size of each anode 11 is adapted to the size of the light-emitting functional layer 13 of the sub-pixel P of different colors, so as to ensure that each sub-pixel P has an effective light-emitting area.
  • the first anode 111 includes a first anode main body portion 111 a and a first anode extension portion 111 b.
  • the shape of the first anode body part 111a is consistent with the shape of the corresponding light-emitting functional layer 13, for example, both are hexagonal, and the orthographic projection of the light-emitting functional layer 13 corresponding to the first anode 111 on the substrate 1 is located at the first anode In the orthographic projection of the main body portion 111 a on the substrate 1 , it is ensured that each sub-pixel P corresponding to the first anode 111 has an effective light emitting area.
  • the first anode extension part 111b is located in a region other than the effective light emitting region, and is configured to be electrically connected to the thin film transistor TFT.
  • the shape of the first anode body part 111a is hexagonal
  • the centerline of the hexagon along the first direction Y can be regarded as the centerline C of the first anode 111
  • the shape of the first anode extension part 111b has a significant impact on the shape of the first anode 111.
  • the influence of the position of the midline C is negligible.
  • the centerline C of the above-mentioned first anode 111 refers to the centerline C of the effective light-emitting area of the first anode 111, and the effective light-emitting area is the intersection of the anode, the light-emitting functional layer, and the cathode in the light-emitting device. overlapping area.
  • the second anode 112 includes a second anode body portion 112 a and a second anode extension portion 112 b.
  • the shape of the second anode body part 112a is consistent with the shape of the corresponding light-emitting functional layer 13, for example, both are hexagonal, and the orthographic projection of the light-emitting functional layer 13 corresponding to the second anode 112 on the substrate 1 is located at the second anode In the orthographic projection of the main body portion 112 a on the substrate 1 , it is ensured that each sub-pixel P corresponding to the second anode 112 has an effective light emitting area.
  • the second anode extension 112b is located in a region other than the effective light emitting region, and is configured to be electrically connected to the thin film transistor TFT.
  • the shape of the second anode body part 112a is hexagonal, and the centerline of the hexagon along the first direction Y can be regarded as the centerline C of the second anode 112, and the shape of the second anode extension part 112b has a significant impact on the shape of the second anode 112. The influence of the position of the midline C is negligible.
  • the third anode 113 includes a third anode body portion 113 a and a third anode extension portion 113 b.
  • the shape of the third anode body part 113a is consistent with the shape of the corresponding light-emitting functional layer 13, for example, both are pentagonal, and the orthographic projection of the light-emitting functional layer 13 corresponding to the third anode 113 on the substrate 1 is located at the third anode In the orthographic projection of the main body portion 113 a on the substrate 1 , it is ensured that each sub-pixel P corresponding to the third anode 113 has an effective light emitting area.
  • the third anode extension 113b is located in a region other than the effective light emitting region, and is configured to be electrically connected to the thin film transistor TFT.
  • the shape of the third anode main body part 113a is a pentagon, and the centerline of the pentagon along the first direction Y is approximately the centerline C of the third anode 113, and the shape of the third anode extension part 113b is opposite to that of the third anode 113.
  • the influence of the position of the midline C is negligible.
  • the arrangement of the plurality of first anodes 111, the plurality of second anodes 112 and the plurality of third anodes 113 is consistent with the arrangement of the plurality of sub-pixels P.
  • the plurality of The anodes 11 are arranged into a plurality of anode columns, and the plurality of anode columns include a plurality of first anode columns, a plurality of second anode columns and a plurality of third anode columns.
  • each first anode row includes a plurality of first anodes 111 arranged in a row along the first direction Y
  • each second anode row includes a plurality of first anodes 111 arranged in a row along the first direction Y
  • two anodes 112 each third anode row includes a plurality of third anodes 113 arranged in a row along the first direction Y.
  • the first anode column, the second anode column and the third anode column are arranged cyclically.
  • the anodes 11 included in two adjacent anode rows are arranged alternately. For example, as shown in FIG. 8A, in adjacent second anode columns and third anode columns, a part of each second anode 112 is inserted between two adjacent third anodes 113, and each third anode 113 A part of it is inserted between two adjacent second anodes 112 .
  • each first pixel circuit 201 is electrically connected to a first anode 111
  • each second pixel circuit 202 is electrically connected to a second anode 112. connect.
  • Each first anode 111 and each second anode 112 corresponding to the first pixel circuit column 210 belong to the adjacent first anode column and the second anode column respectively.
  • each third pixel circuit 203 is electrically connected to one third anode 113
  • each third anode 113 corresponding to the second pixel circuit column 220 belongs to the same third anode column.
  • the first conductive layer 9 when the display substrate 100 includes a first conductive layer 9 and a second conductive layer 9', the first conductive layer 9 includes a plurality of first signal lines 93, The multiple first signal lines 93 are multiple data lines.
  • the first conductive layer 9 further includes a plurality of first via electrodes 94 and a plurality of second via electrodes 95 .
  • the second conductive layer 9' includes a plurality of voltage signal lines 91', and the plurality of second signal lines 91' are a plurality of voltage signal lines.
  • the second conductive layer 9' also includes a source 91 and a drain 92 of the thin film transistor TFT.
  • the plurality of first signal lines 93 extend along the first direction Y, and are classified according to the connection relationship between the plurality of data lines and different sub-pixels P (or anodes 11).
  • the plurality of data lines include a plurality of first data lines 9311 and a plurality of A second data line 9312.
  • Each first data line 9311 is electrically connected to each first pixel circuit 201 and each second pixel circuit 202 in a first pixel circuit column 210, so as to be included in the first anode column corresponding to the first pixel circuit column 210.
  • Each first anode 111 of each second anode column is electrically connected to each second anode 112 included; each second data line 9312 is electrically connected to each third pixel circuit 203 in a second pixel circuit column 220, so as to It is electrically connected to each third anode 113 included in the third anode column corresponding to the second pixel circuit column 220 .
  • each data line has a plurality of connection portions correspondingly electrically connected to a plurality of pixel circuits 200 in the pixel circuit column.
  • the setting position of the connection part and the extension direction relative to the data line where it is located are related to the positions of the anodes electrically connected to the data line, and can be set according to actual needs.
  • the connecting portion 933 correspondingly connected to the second pixel circuit 202 is covered by the second anode 112 electrically connected to the second pixel circuit 202 .
  • two connecting portions 934 correspondingly connecting two adjacent third pixel circuits 203 are located on two sides of the second data line 9312 .
  • the plurality of second signal lines 91' extend along the first direction Y and are configured to transmit power supply voltage signals to pixel circuits in each sub-pixel P.
  • each data line is electrically connected to the corresponding anode 11 through the thin film transistor TFT in the pixel circuit 220 in each sub-pixel P.
  • each first data line 9311 passes through a plurality of second anodes 112 in one second anode column, and each first data line 9311 on the positive side of the substrate 1
  • the projection overlaps with the orthographic projection S of the multiple second anodes 112 in the second anode row on the substrate 1, and the first data line 9311 passes through the left side of the second anode 112, which will cause the second
  • the left side of the anode 112 is positioned higher relative to the right side thereof, and the second anode 112 is "tilted".
  • the anode 11 on the left side of FIG. 1 taking the anode 11 as the second anode 112 in FIG.
  • the position M and position N in the second anode 112 are the second anode 11 At the symmetrical position along the first direction Y (taking the center line C as the axis of symmetry), the position M on the left side of the second anode 112 is higher than the position N on the right side thereof, and the height H1 of the position M of the second anode 112 is Greater than the height H2 at its position N, the second anode 112 is "tilted".
  • the height at a certain position of the anode refers to the distance between the surface of the anode 11 at this position away from the substrate 1 and the substrate 1 along the direction perpendicular to the plane where the substrate 1 is located.
  • Each second data line 9312 passes through a plurality of third anodes 113 in an adjacent third anode column and a plurality of first anodes 111 in a first anode column, and each second data line 9312 passes through the substrate 1 and the orthographic projection S of the multiple third anodes 113 in the third anode column on the substrate 1 overlap, and the second data line 9312 passes through the position on the right side of the third anode 113, so that As a result, the position on the right side of the third anode 113 is higher than the position on the left side, and the third anode 113 is "tilted" (like the anode 11 in the middle of FIG. 1 ), and its presentation effect is similar to that of the second anode 112 above. I won't repeat them here.
  • each second data line 9312 on the substrate 1 overlaps the orthographic projection S of the plurality of first anodes 111 in the first anode column on the substrate 1, and the first data line 9311 passes through
  • the position on the left side of the first anode 111 will cause the position on the left side of the first anode 111 to be higher relative to the position on the right side thereof, and the first anode 111 "tilts" (as shown in the anode on the right side of Fig. 1 ).
  • its presenting effect is similar to that of the above-mentioned second anode 112, which will not be repeated here.
  • the display substrate 100 has a large angle of view, and when viewed visually, it appears as if one side is red and the other side is blue. Phenomenon. Wherein, please refer to FIG. 1 and FIG. 3 , and FIG. 8A and FIG.
  • the height of the symmetrical position of the anode 11 along the first direction Y refers to the height of the symmetrical position of the anode 11 along the direction perpendicular to the plane where the substrate 1 is located.
  • the symmetrical positions in the anode 11 are, for example, a position M and a position N, and the position M and the position N are symmetrically arranged with the centerline C as an axis.
  • the plurality of first signal lines 93 included in the first conductive layer 9 are a plurality of data lines and a plurality of voltage signal lines.
  • the orthographic projections of the plurality of first signal lines 93 overlap with the orthographic projections of the anode 11 , which causes the anode 11 to be “tilted” and cause color shift in the display substrate 100 .
  • the first conductive layer 9 is the conductive layer closest to the plurality of anodes 11 between the substrate 1 and the plurality of anodes 11; that is, the first conductive layer 9 and the plurality of anodes 11
  • the patterned film layer means that the film layer includes a variety of patterns, such as the first conductive layer 9, the second conductive layer 9' and the first gate metal Layer 5 is a patterned film layer, for example, the first conductive layer 9 includes a plurality of patterns to form a plurality of data lines, the second conductive layer 9' includes a plurality of patterns to form a plurality of voltage signal lines, and the first gate metal layer 5 includes various patterns to form a plurality of raster scan lines. Since the first conductive layer 9 is the pattern film layer closest to the plurality of anodes 11 , the flatness of the surfaces of the plurality of anodes is affected by
  • the present disclosure provides a display substrate 100 , which improves the above-mentioned problem of color shift by adjusting the positional relationship between the anode 11 and the first signal line 93 .
  • the orthographic projection of at least one of the plurality of anodes 11 on the substrate 1 is the same as the orthographic projection of each first signal line 93 on the substrate 1 No overlap.
  • the orthographic projection of at least one of the plurality of anodes 11 on the substrate 1 and the orthographic projection of at least one first signal line 93 on the substrate 1 There is overlap; among the overlapping anodes and at least one first signal line 93 in the orthographic projection, the at least one first signal line 93 passes through the set position of the anode 11, so that the center line of the anode 11 along the first direction Y C is the axis of symmetry, and based on the set position of the at least one first signal line 93 , the heights of the anode 11 at positions symmetrical along the axis of symmetry are approximately equal.
  • the height of the symmetrical position in the anode 11 refers to the distance between the surface of the symmetrical position of the anode 11 away from the substrate 1 and the substrate 1 along the direction perpendicular to the plane where the substrate 1 is located.
  • the anode 11 is symmetrical to positions M and N along the centerline C, and the distance between position M and the substrate 1 is H1 , the distance between position N and substrate 1 is H2.
  • the heights of the anode 11 at the symmetrical position along the axis of symmetry are approximately equal, that is, H1 and H2 are approximately equal.
  • the orthographic projection S of at least one of the plurality of anodes 11 on the substrate 1 does not overlap with the orthographic projection S of each first signal line 93 on the substrate 1, it is ensured that There is no first signal line 93 passing under at least one anode 11, so as to avoid the situation that the height of the left and right sides of the anode 11 is not consistent due to the first signal line 93 being arranged under the anode 11, and the situation of "tilting" occurs, thereby avoiding the anode 11.
  • the intensity of light emitted by the sub-pixel P where 11 is located to the left and right sides does not match.
  • the orthographic projection of at least one of the plurality of anodes 11 on the substrate 1 overlaps the orthographic projection of at least one first signal line 93 on the substrate 1, and the at least one first signal line 93
  • the center line C of the anode 11 along the first direction Y is taken as the axis of symmetry, and the heights of the anode 11 at positions symmetrical along the axis of symmetry are approximately equal, which also prevents the anode 11 from occurring. Tilting", so as to avoid the mismatch of light intensity emitted by the sub-pixel where the anode 11 is located to the left and right sides.
  • the orthographic projection S of at least one of the plurality of anodes 11 on the substrate 1 is the same as that of each first signal line 93 on the substrate 1
  • at least one first signal line 93 includes at least one straight portion 931 and at least one bent portion 932; each straight portion 931 and each bent portion 932 are arranged alternately.
  • the straight portion 931 extends along the first direction Y, and the orthographic projection of the straight portion 931 on the substrate 1 is located on one side of the anode 11 along the first direction Y.
  • the bent portion 932 includes a first segment 932a, a second segment 932b and a third segment 932c connected in sequence.
  • the second segment 932b extends along the first direction Y, and the orthographic projection of the second segment 932b on the substrate 1 is located on one side of the anode 11's orthographic projection along the second direction X, so as to avoid the anode 11's orthographic projection S.
  • the second direction X is perpendicular to the first direction Y.
  • the second anode 112 and the at least one first signal line 9 as the first data line 9311 are adjacent and electrically connected.
  • the straight portion 931 of the first data line 9311 extends along the first direction Y, and the orthographic projection of the straight portion 931 of the first data line 9311 on the substrate 1 is located at the orthographic projection of the second anode 112 along the first direction On one side of Y, this is because in the adjacent first anode column and second anode column, each first anode 111 and each second anode 112 are arranged alternately, therefore, the straight part 931 of the first data line 9311 is in the
  • the orthographic projection on the substrate 1 is located on one side of the orthographic projection S of the second anode 112 along the first direction Y, that is, the straight portion 931 of the first data line 9311 is retracted between two adjacent second anodes 112 area to avoid the first anode 111 and avoid overlapping with the first anode 111 .
  • the orthographic projection of the bent portion 932 of the first data line 9311 on the substrate 1 detours along the boundary of the orthographic projection S of the second anode 112 to avoid the orthographic projection S of the second anode 112, thus ensuring the first The two anodes 112 do not overlap with the first data line 9311 .
  • the first segment 932a of the bent portion 932 of the first data line 9311 is connected to the straight portion 931 on one side of the second anode 112 along the first direction Y; the third segment 932c is connected to the second anode 112 along the first direction Y; The straight section 931 on the other side of the direction Y is connected; the second segment 932b extends along the first direction Y and connects the first segment 932a and the third segment 932c, and the orthographic projection of the second segment 932b on the substrate is located at the second The orthographic projection of the anode 112 is along one side in the second direction X, so that the first data line 9311 avoids the orthographic projection S of the second anode 112 .
  • the first data line 9311 includes a plurality of straight sections 931 and a plurality of bent sections 932 , and each straight section 931 and each bent section 932 are arranged alternately.
  • the first data line 9311 is located between adjacent first and second anode columns.
  • the orthographic projection S of a first anode 111 located in the first anode column is located on one side of the second direction X, and is located at the first anode column in the second anode column.
  • the orthographic projection S of the two anodes 112 is along one side in the first direction Y.
  • the orthographic projection S of the second segment 932b of each bent portion 932 of the first data line 9311 is located on one side of the second anode 112 in the second anode column along the second direction X, so as to avoid Open the orthographic projection S of the second anode 112 .
  • FIG. 8A refers to the structure in which the first first signal line 93 in order from left to right is arranged at the initial setting position.
  • FIG. 12 taking the above-mentioned anode 11 as a certain second anode 112 as an example, see the first first signal line 93 in sequence from left to right.
  • the first first signal line 93 is moved to the right by an appropriate amount along the second direction X relative to the initial setting position, so as to avoid the orthographic projection S of the second anode 112 and form a straight portion 931 and a bent portion 932 structure.
  • the orthographic projection of the straight portion 931 of the first signal line 93 on the substrate 1 is located on one side of the orthographic projection S of the second anode 112 along the first direction Y; the bending of the first signal line 93
  • the orthographic projection of the portion 931 on the substrate 1 goes around along the boundary of the orthographic projection of the second anode 112 to avoid the orthographic projection of the second anode 112 .
  • the shape of the second anode 112 is hexagonal, then the extension direction of the first segment 932a, the second segment 932b and the third segment 932c of the bent portion 932 of the first signal line 93 Also fits with the left three borders of the hexagon.
  • the third anode 113 and The second data lines 9312 are adjacent and electrically connected.
  • the straight portion 931 of the second data line 9312 extends along the first direction Y, and the orthographic projection of the straight portion 931 of the second data line 9312 on the substrate 1 is located in the orthographic projection S of the third anode 113 along the first direction Y.
  • each third anode 113 and each first anode 111 are arranged alternately, so the straight part 931 of the second data line 9312 is in the
  • the orthographic projection on the substrate 1 is located on one side of the orthographic projection S of the third anode 113 along the first direction Y, that is, the straight portion 932 of the second data line 9312 is retracted between two adjacent third anodes 113 area to avoid the first anode 111 and avoid overlapping with the first anode 111 .
  • the orthographic projection of the second segment 932b of the bent portion 932 of the second data line 9312 on the substrate 1 goes around along the boundary of the orthographic projection S of the third anode 113 to avoid the orthographic projection S of the third anode 113, This ensures that the third anode 113 and the second data line 9312 do not overlap.
  • the shape of the third anode 113 is a pentagon, then the extension direction of the first segment 932a, the second segment 932b and the third segment 932c of the bent portion 932 of the first signal line 93 It also fits with the two borders on the right side of the pentagon.
  • the first signal line 93 includes the second data line 9312
  • the second data line 9312 includes a plurality of straight portions 931 and a plurality of bent portions 932, each straight The parts 931 and the bent parts 932 are arranged alternately; the second data line 9312 is located between the adjacent third anode column and the first anode column.
  • the orthographic projection S of each straight portion 931 of the second data line 9312, the orthographic projection S of the first anode 111 located in the first anode column is along one side of the second direction X, and the third anode 111 located in the third anode column
  • the orthographic projection S of the anode 113 is along one side in the first direction Y.
  • each bent portion 932 of the second data line 9312 corresponds to the position of one third anode 113 in the third anode row, so as to avoid the orthographic projection S of each third anode 11, so that the second data line 9312 There is no overlap with each third anode 113 .
  • FIG. 8A refers to the structure in which the second first signal line 93 and the fourth first signal line 93 are arranged in the initial setting position from left to right.
  • FIG. 11 taking the above-mentioned anode 11 as an example of a third anode 113, see the second first signal line 93 and the fourth first signal line 93 in order from left to right, the The second first signal line 93 is moved to the left by an appropriate amount along the second direction X relative to the initial setting position, so as to avoid the orthographic projection S of the third anode 113 and form a structure with a straight portion 931 and a bent portion 932 .
  • the conversion process of the fourth first signal line 93 is the same as that of the second first signal line 93 , and will not be repeated here.
  • the second first signal line 93 and the fourth first signal line 93 are the second data lines 9312 .
  • the orthographic projection S of the first anode 111 in the first anode column is located on one side of the second direction X, and is located at the first anode column.
  • the orthographic projection S of the third anode 113 in the three anode columns is along one side in the first direction Y.
  • the orthographic projection S of the second segment 932b of each bent portion 932 of the second data line 9312, the orthographic projection S of at least one third anode 113 located in the third anode row is along one side of the second direction X, so as to avoid Open the orthographic projection S of the third anode 113 .
  • the shape of the third anode 113 is a pentagon, then the extension direction of the first segment 932a, the second segment 932b and the third segment 932c of the bent portion 932 of the first signal line 93 It also fits with the three borders on the right side of the pentagon to avoid the orthographic projection S of the third anode 113 .
  • every two adjacent third anodes 113 are divided into one group, and along the first direction Y, each group of third anodes
  • the distance between two third anodes 113 in 113 is smaller than the distance between these two third anodes 113 and other third anodes 113 around them.
  • the shape of the third anode 113 is a pentagon, and in every two adjacent third anodes 113, one side of the two third anodes 113 is opposite and parallel to each other.
  • the third anode 113 serves as a group of third anodes 113 .
  • third anodes 113 are convenient for explaining the positional relationship between the orthographic projection S of the third anode 113 on the substrate and the orthographic projection S of the first signal line 93 on the substrate 1, and does not limit one Groups of third anodes 113 are located in the same pixel P'.
  • the shape of the third anodes 113 is a pentagon, and two parallel sides of the two third anodes 113 face each other.
  • the orthographic projection of each straight portion 931 of the second data line 9312 on the substrate 1 is located in a group of third anodes 113 on the substrate 1
  • the orthographic projection is along the first direction Y on one side.
  • the orthographic projection of the second segment 932b of each bent portion 932 of the second data line 9312 on the substrate 1 is located at one of the orthographic projections S of a group of third anodes 113 on the substrate 1 along the second direction X. side to avoid the orthographic projection S of a group of third anodes 113 on the substrate 1 .
  • the third anode 113 is an anode corresponding to the green sub-pixel
  • two third anodes 113 with smaller areas are used.
  • the first anode 111 is the anode corresponding to the red sub-pixel
  • the second anode 112 is the anode corresponding to the blue sub-pixel
  • the area of the third anode 113 is smaller than the area of the first anode 111
  • the area of the first anode 111 The area is smaller than that of the second anode 112 .
  • the area of the third anode 113 is the smallest. This is because the light-emitting functional layer of the green sub-pixel has the highest luminous efficiency, and such a design can eliminate the color shift problem caused by the different luminous efficiencies of the red, green, and blue sub-pixels.
  • the first anode 111 and the second The data lines 9312 are adjacent.
  • the straight portion 931 of the second data line 9312 extends along the first direction Y, and the orthographic projection of the straight portion 931 of the second data line 9312 on the substrate 1 is located along the first direction S of the first anode 111. side in direction Y.
  • the orthographic projection of the bent portion 932 of the second data line 9312 on the substrate 1 detours along the boundary of the orthographic projection S of the first anode 111, and the bent portion 932 of the second data line 9312 includes sequentially connected first Segment 932a, second segment 932b and third segment 932c, the second segment 932b extends along the first direction Y, the orthographic projection of the second segment 932b on the substrate 1 is located on the orthographic projection of the first anode 111 along the second direction X to avoid the orthographic projection S of the first anode 111 .
  • the orthographic projection of the second data line 9312 on the substrate simultaneously avoids the The third anode 113 and the first anode 111, the second segment 932b of the second data line 9312 in FIG. 9B relative to the bent portion 932 of the first anode 111 can also be used as the straight portion 931 of the third anode 113 in FIG. 9C.
  • the second data line 9312 is located between the adjacent third anode column and the first anode column, although the final shape of the second data line 9312 is the same, but the second data line 9312 is located in a different position based on the initial state. and direction bends.
  • each first signal line 93 includes a plurality of straight portions 931 and a plurality of bent portions 932 .
  • the structure of the first signal line 93 is also periodic.
  • the at least one first signal line 93 includes a first data line 9311 and a second data line 9312 .
  • the first data line 9311 is located between adjacent first and second anode columns.
  • the second data line 9312 is located between the adjacent third anode column and the first anode column.
  • the first data line 9311 includes a plurality of straight portions 931 and a plurality of bent portions 932, the orthographic projection of each straight portion 931 of the first data line 9311, and the orthographic projection of a first anode 111 located in the first anode column
  • the projection S is along one side in the second direction X
  • the orthographic projection S of the second anode 112 located in the second anode column is along one side in the first direction Y.
  • the orthographic projection S of the second section of each bent portion 932 of the first data line 9311, the orthographic projection S of a second anode 112 located in the second anode column is along one side of the second direction X to avoid Orthographic projection of the second anode 112 .
  • the second data line 9312 includes a plurality of straight portions and a plurality of bent portions, the orthographic projection of each straight portion 931 of the second data line 9312, and the orthographic projection S of the first anode 111 located in the first anode column
  • One side in the second direction X, and the orthographic projection of the third anode 113 located in the third anode column is along one side in the first direction Y.
  • the orthographic projection of the second section of each bent portion 932 of the second data line 9312, the orthographic projection of at least one third anode 113 located in the third anode row is along one side of the second direction X, so as to avoid the first Orthographic projection S of the three anodes 113 .
  • FIG. 8A refers to the structure in which the first first signal line 93 and the second first signal line 93 are arranged in the initial setting position from left to right.
  • FIG. 12 the setting positions of the first first signal line 93 and the second first signal line 93 in order from left to right, compared with the transformation process of their respective initial setting positions, refer to the above two for details. example, which will not be repeated here.
  • the light emitted by the light-emitting functional layer 13 is irradiated on the anode 11, and the light is reflected by the anode 11. Because the anode 11 is not flat or has a pre-tilt angle, the path length of the reflected light is different, resulting in different display brightness of the outgoing light. Uniform reflection, the problem of color cast of the displayed image appears.
  • the above-mentioned first signal line 93 will not affect the horizontal effect of the plane where the third anode 113 corresponding to the third sub-pixel P3 is located, and the above-mentioned first signal line 93 will not affect the second sub-pixel P2 either.
  • the horizontal effect of the plane where the corresponding second anode 112 is located can prevent the second anode 112 and the third anode 113 from being inclined, thereby affecting the luminous effect.
  • the vertical distance L1 between the bent portion 932 and the straight portion 931 is 1 ⁇ m ⁇ 10 ⁇ m, wherein the second direction X is perpendicular to the first direction Y.
  • the vertical distance L1 between the bent portion 932 and the straight portion 931 is 1 ⁇ m, 6 ⁇ m or 10 ⁇ m.
  • the degree of bending of the first signal line 93 is set to ensure that each first signal line 93 can be connected to the corresponding The anode 11 of the pixel P is coupled to reduce the manufacturing process difficulty.
  • the orthographic projection S of at least one of the plurality of anodes 11 on the substrate 1 intersects with the orthographic projection S of at least one first signal line 93 on the substrate 1 stack, wherein the orthographic projection S of at least one anode 11 on the substrate 1 overlaps the orthographic projection S of a first signal line 93 on the substrate 1, or, the orthographic projection S of at least one anode 11 on the substrate 1 S overlaps with the orthographic projections of the plurality of first signal lines 93 on the substrate 1 .
  • the orthographic projection S of at least one anode 11 overlaps with the orthographic projection of a first signal line 93; the orthographic projection of the first signal line 93 overlaps with the The orthographic projections S of the anode 11 coincide along the centerline C of the first direction Y.
  • the at least one first signal line 93 on the substrate 1 is located at the anode 11
  • the parts other than the orthographic projection of the anode 11 do not overlap with the orthographic projections of other anodes 11 adjacent to the anode 11 on the substrate 1 .
  • the orthographic projection of the first data line 9311 and the orthographic projection S of the second anode 112 along the midline of the first direction Y C overlap, so that the centerline C of the second anode 112 along the first direction Y is the axis of symmetry, and the heights of the symmetrical positions of the second anode 112 relative to the axis of symmetry are approximately equal.
  • other anodes 11 adjacent to the second anode 112 among the plurality of anodes 11 are other anodes around the second anode 112 , including the anodes located along the second direction of the second anode 112
  • Other types of anodes on both sides, and other types of anodes located on both sides of the second anode 112 along the first direction for example, the first anode in the first anode column on the left side and the first anode on the right side
  • the third anode in the third anode column for example, the first anode in the first anode column on the left side and the first anode on the right side.
  • the orthographic projection of the at least one first signal line 93 on the substrate 1 overlaps the orthographic projections of the plurality of second anodes 112 on the substrate 1, then these The first signal line 93 does not overlap with the orthographic projections of the first anode 111 and the third anode 113 on the substrate 1 .
  • the orthographic projection of the first signal line 93 on the left side on the substrate 1 overlaps the orthographic projection of the plurality of second anodes 112 along the first direction Y on the substrate 1, and the first signal line
  • the orthographic projection of the line 93 coincides with the centerline C of the orthographic projection S of the multiple second anodes 112 along the first direction Y.
  • the orthographic projection of the first signal line 93 coincides with the multiple The orthographic projections of the first anodes 111 do not overlap, and at the same time, the orthographic projections of the first signal line 93 and the orthographic projections of the plurality of third anodes 113 on the right side of the plurality of second anodes 112 do not overlap.
  • the orthographic projection of the first data line 9311 coincides with the midline C of the orthographic projection S of each second anode 112 included in the second anode column along the first direction Y, so that the The centerline C of the second anode row along the first direction Y is a symmetry axis, and the heights of the symmetrical positions of the second anodes 112 included in the second anode row are approximately equal to the symmetry axis.
  • the height H1 of the position M on the left side of the second anode row is approximately equal to the height H2 of the position N on the right side, and the plane where the second anode row is located is horizontal.
  • the flatness of the surface of the part of the first flat layer 10 corresponding to the orthographic projection S of the second anode 112 is symmetrical with respect to the central axis of the anode orthographic projection S, and the surface of this part of the first flat layer 10 is close to the level. A large tilt will be generated to avoid the problem of color cast of the displayed image.
  • the orthographic projection of at least one anode 11 overlaps with the orthographic projections of the plurality of first signal lines 93 , and the plurality of first signal lines 93 pass through the anode 11
  • the part is arranged symmetrically with respect to the central line C of the anode 11 along the first direction Y.
  • the number of the plurality of first signal lines 93 is two.
  • the orthographic projection S of at least one anode 11 overlaps the orthographic projections of the two first signal lines 93 on the substrate 1, and the two first signal lines 93 are adjacent to each other.
  • the first data line 9311 and the second data line 9312 corresponding to the first anode column, the second anode column and the third anode column.
  • the part of the first data line 9311 and the second data line 9312 passing through the first anode 111 is along the first direction Y relative to the first anode 111
  • the midline C is set symmetrically. Therefore, taking the centerline C of the first anode 111 along the first direction Y as the axis of symmetry, the heights of the symmetrical positions in the first anode 111 are approximately equal.
  • the part of the first data line 9311 and the second data line 9312 passing through the second anode 112 is along the first direction Y relative to the second anode 112
  • the midline C is set symmetrically. Therefore, taking the centerline C of the second anode 112 along the first direction Y as the axis of symmetry, the heights of the symmetrical positions in the second anode 112 are approximately equal.
  • the part of the first data line 9311 and the second data line 9312 passing through the third anode 113 is along the first direction Y relative to the third anode 113
  • the midline C is set symmetrically. Therefore, taking the centerline C of the third anode 113 along the first direction Y as the axis of symmetry, the heights of the symmetrical positions of the third anode 113 are approximately equal.
  • the orthographic projections of the first data line 9311 and the second data line 9312 overlap with the orthographic projections of each third anode 113 included in a third anode column, and the first data line
  • the part 9311 and the second data line 9312 passing through each third anode 113 is arranged symmetrically with respect to the centerline C of the third anode 113 along the first direction Y. Therefore, taking the centerline C of the third anode row along the first direction Y as the axis of symmetry, the heights of the symmetrical positions of the third anodes 113 included in the second anode row are approximately equal.
  • the two first signal lines 93 are the first first data line 9311 and the second data line 9311 in order from left to right.
  • the second data line 9312, the orthographic projection of the first data line 9311 and the orthographic projection of the second second data line 9312 and the orthographic projection of the third anode 113 are arranged symmetrically along the center line C in the first direction Y.
  • the orthographic projection S of the second data line 9312 does not overlap with the orthographic projection S of the adjacent first anode 111 .
  • the orthographic projection S of the first data line 9311 does not overlap with the orthographic projection S of the adjacent second anode 112 .
  • the above-mentioned two first signal lines 93 are the first first data line 9311 and the second first data line 9311 in order from left to right.
  • the two data lines 9312, the orthographic projection of the first data line 9311, the orthographic projection of the second second data line 9312 and the orthographic projection of the third anode 113 are arranged symmetrically along the center line C in the first direction Y.
  • the orthographic projection of the first first data line 9311 does not overlap with the orthographic projection of the adjacent second anode 112 .
  • the shape of the second anode 112 is hexagonal, then the first segment 932a, the second segment 932b and the third segment 932c of the bent portion 932 of the first data line 9311
  • the extension direction of the line also coincides with the two borders on the right side of the hexagon to avoid the orthographic projection S of the second anode 112, thus ensuring that the second anode 112 does not overlap with the first data line 9311.
  • the orthographic projection S of the second second data line 9312 does not overlap with the orthographic projection S of the adjacent first anode 111 .
  • the orthographic projection S of the second data line 9312 does not overlap with the orthographic projection S of the adjacent first anode 111 .
  • the orthographic projection of the first data line 9311 overlaps with its adjacent second anode 112, and the overlapping portion of the orthographic projection of the first data line 9311 and the orthographic projection of the second anode 112 are along the centerline C of the first direction Y coincide.
  • the above-mentioned two first signal lines 93 are the first first data line 9311 and the second first data line 9311 in sequence from left to right.
  • the two data lines 9312, the orthographic projection of the first data line 9311, the orthographic projection of the second second data line 9312 and the orthographic projection of the third anode 113 are arranged symmetrically along the center line C in the first direction Y.
  • the orthographic projection of the first data line 9311 overlaps with its adjacent second anode 112, and the overlapping portion of the orthographic projection of the first data line 9311 and the orthographic projection of the second anode 112 are along the centerline C of the first direction Y. coincide.
  • the orthographic projection S of the second data line 9312 does not overlap with the orthographic projection S of the adjacent first anode 111 .
  • the plane of the surface of the part of the first flat layer 10 corresponding to the anode orthographic projection S is horizontal, preventing the multiple anodes 11 on the first flat layer 10 from having a pre-tilt angle or being uneven, resulting in color shift in the displayed image.
  • one of the plurality of first signal lines 93 may also extend along the first direction Y, and the orthographic projection of the first signal line 93 on the substrate 1 does not overlap with the anode orthographic projection S.
  • the extension of each of the above-mentioned multiple first signal lines 93 may be any one or a combination of the above-mentioned embodiments. It only needs to ensure that the planes where the multiple anodes 11 are located are horizontal.
  • the distance L2 between two adjacent first signal lines 93 ranges from 5 ⁇ m to 30 ⁇ m.
  • the distance between two adjacent signal lines 93 is 5 ⁇ m, 15 ⁇ m or 30 ⁇ m, so as to ensure the effective operation of the signal transmission of the first signal line 93 and avoid signal interference.
  • each pixel circuit 200 includes at least a compensation transistor T2 , a driving transistor T3 and a capacitor O1 .
  • the first polar region T21 of the compensation transistor T2 is electrically connected to the second polar region T32 of the driving transistor T3 .
  • the second polar region T22 of the compensation transistor T2 is electrically connected to the gate of the driving transistor T3 (where the channel region T33 of T3 overlaps the first plate 011 of the capacitor 01 ) through the connection structure 92'.
  • connection structure 92' is located on the second conductive layer 9', one end of the connection structure 92' is electrically connected to the second pole region T22 of the compensation transistor T2 through a first via hole, and the first via hole penetrates to the semiconductor layer 3,
  • the other end of the connection structure 92' is electrically connected to the gate of the drive transistor T3 (the overlapping part of the channel region T33 of T3 and the first plate 011 of the capacitor 01) through the second via hole, and the second via hole penetrates to the first electrode plate 011 of the capacitor 01.
  • Gate metal layer 5 is provided on the second conductive layer 9', one end of the connection structure 92' is electrically connected to the second pole region T22 of the compensation transistor T2 through a first via hole, and the first via hole penetrates to the semiconductor layer 3.
  • the other end of the connection structure 92' is electrically connected to the gate of the drive transistor T3 (the overlapping part of the channel region T33 of T3 and the first plate 011 of the capacitor 01) through the second via hole,
  • the orthographic projection of each second anode 112 on the substrate 1 is the same as the orthographic projection of the connecting structures 92 ′ of two adjacent pixel circuits 200 on the substrate 1 overlapping (please refer to the position of the dotted ellipse circle in FIG. 24 ), and one of the two adjacent pixel circuits 200 is the second pixel circuit 202 electrically connected to the second anode 112, and the other is A third pixel circuit 203 adjacent to the second pixel circuit.
  • the connection structure 92' corresponds to the first node N1 in the equivalent circuit diagram.
  • each data line overlaps the second plate 012 of the capacitor 01 of each pixel circuit 200 in the pixel circuit column to which each data line is electrically connected.
  • the first data line 9311 is electrically connected to the first pixel circuit column 210, and the first pixel circuit column 210 includes a plurality of first pixel circuits 201 and a plurality of second pixel circuits 202 , the first data line 9311 overlaps with the second plate 012 of the capacitor 01 in the first pixel circuit 201; and overlaps with the second plate 012 of the capacitor 01 in the second pixel circuit 202 (see FIG. 24 and the dotted triangle area in Fig. 26).
  • the second data line 9312 is electrically connected to the second pixel circuit column 220, and the second data line 9312 overlaps with the second plate 012 of the capacitor 01 in the second pixel circuit 202 (see the dotted triangle in Fig. 24 and Fig. 26 area).
  • the second plate 012 of the capacitor 01 is electrically connected to multiple voltage signal lines and signal lines to receive a constant voltage signal, the second plate 012 of the capacitor 01 of the data line is overlapped to stabilize the data transmitted by the data line signal to avoid data signal fluctuations caused by interference from other factors.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)

Abstract

一种显示基板，包括衬底，第一导电层，第一平坦层和多个阳极。第一导电层设置于衬底的一侧。第一导电层包括多条沿第一方向延伸的第一信号线。第一平坦层设置于第一导电层远离衬底的一侧。多个阳极设置于第一平坦层远离衬底的一侧。其中，第一导电层为衬底和多个阳极之间最靠近多个阳极的导电层；且多个阳极中的至少一个在衬底上的正投影，与每条第一信号线在衬底上的正投影无交叠；和/或，多个阳极中的至少一个在衬底上的正投影与至少一条第一信号线在衬底上的正投影有交叠；正投影相交叠的阳极和至少一条第一信号线中，至少一条第一信号线经过阳极的设定位置，使得以阳极沿第一方向的中线为对称轴，阳极中对称位置处的高度大致相等。

Description

显示基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
随着显示技术的进步，有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置是当今显示技术研究的热点之一，OLED显示装置包括多种影响显示效果的性能参数，例如OLED显示装置的性能参数主要有功耗、图像显示亮度、图像显示色坐标、色域和视角色偏等等。
发明内容
一方面，提供一种显示基板，包括：衬底、第一导电层、第一平坦层和多个阳极。第一导电层设置于所述衬底一侧，所述第一导电层包括多条沿第一方向延伸的第一信号线；第一平坦层设置于所述第一导电层远离所述衬底一侧；多个阳极设置于所述第一平坦层远离所述衬底一侧。所述第一导电层为所述衬底和所述多个阳极之间最靠近所述多个阳极的导电层。
其中，所述多个阳极中的至少一个在所述衬底上的正投影，与每条第一信号线在所述衬底上的正投影无交叠；和/或，所述多个阳极中的至少一个在所述衬底上的正投影与至少一条第一信号线在所述衬底上的正投影有交叠；正投影相交叠的阳极和至少一条第一信号线中，所述至少一条第一信号线经过所述阳极的设定位置，使得以所述阳极沿第一方向的中线为对称轴，所述阳极中对称位置处的高度大致相等。
在一些实施例中，在所述多个阳极中的至少一个在所述衬底上的正投影，与每条第一信号线在所述衬底上的正投影无交叠的情况下，至少一条第一信号线包括至少一个直行部分和至少一个弯折部分；各直行部分和各弯折部分交替设置。所述直行部分沿所述第一方向延伸，且所述直行部分在所述衬底上的正投影位于所述阳极的正投影沿所述第一方向上的一侧。所述弯折部分包括依次连接的第一段、第二段和第三段，所述第二段沿所述第一方向延伸，且所述第二段在所述衬底上的正投影位于所述阳极的正投影沿第二方向上的一侧，以避开所述阳极的正投影，所述第一段连接相邻的直行部分，所述第三段连接相邻的直行部分；其中，所述第二方向与所述第一方向垂直。
在一些实施例中，沿第二方向，每条第一信号线的所述弯折部分的第二段与所述直行部分之间的距离为1μm～10μm。
在一些实施例中，在所述多个阳极中的至少一个在所述衬底上的正投影 与至少一条第一信号线在所述衬底上的正投影有交叠的情况下，所述阳极的正投影与一条第一信号线的正投影有交叠；所述第一信号线的正投影与所述阳极的正投影沿第一方向的中线重合。
在一些实施例中，在所述多个阳极中的至少一个在所述衬底上的正投影与至少一条第一信号线在所述衬底上的正投影有交叠的情况下，所述阳极的正投影与多条第一信号线的正投影有交叠；所述多条第一信号线经过所述阳极的部分相对于所述阳极沿所述第一方向的中线对称设置。
在一些实施例中，在所述衬底上的正投影与所述阳极的正投影有交叠的至少一条第一信号线中，所述第一信号线在所述衬底上的正投影的位于所述阳极的正投影之外的部分，与所述多个阳极中的与所述阳极相邻的其他阳极在所述衬底上的正投影无交叠。
在一些实施例中，沿第二方向，相邻两条第一信号线之间的距离为5μm～30μm，其中，所述第二方向与所述第一方向垂直。
在一些实施例中，所述第一导电层包括多条数据线，所述多条第一信号线为所述多条数据线。所述显示基板还包括第二导电层和第二平坦层。所述第二平坦层设置于所述第一导电层远离所述第一平坦层的一侧。所述第二导电层设置于所述第二平坦层远离所述第一导电层的一侧；所述第二导电层包括多条电压信号线。
在一些实施例中，所述第一导电层包括多条数据线和多条电压信号线；所述多条第一信号线为所述多条数据线和所述多条电压信号线。
在一些实施例中，所述显示基板包括多个像素电路，每个像素电路包括至少两个薄膜晶体管以及至少一个电容器。所述多个像素电路包括多个第一像素电路、多个第二像素电路和多个第三像素电路，所述多个像素电路排列成多个像素电路列，所述多个像素电路列包括多个第一像素电路列和多个第二像素电路列，每个第一像素电路列包括沿所述第一方向排成一列且交替设置的多个第一像素电路和多个第二像素电路，每个第二像素电路列包括沿所述第一方向排成一列的多个第三像素电路；沿第二方向，所述第一像素电路列和所述第二像素电路列交替设置。
所述多个阳极包括多个第一阳极、多个第二阳极和多个第三阳极，所述多个阳极排列成多个阳极列，所述多个阳极列包括多个第一阳极列、多个第二阳极列和多个第三阳极列。每个第一阳极列包括沿所述第一方向排成一列的多个第一阳极，每个第二阳极列包括沿所述第一方向排成一列的多个第二阳极，每个第三阳极列包括沿所述第一方向排成一列的多个第三阳极。沿第 二方向，按照所述第一阳极列、所述第二阳极列和所述第三阳极列的次序循环设置。
所述第一像素电路列中，每个第一像素电路与一个第一阳极电连接，每个第二像素电路与一个第二阳极电连接；所述第一像素电路列所对应的各第一阳极和各第二阳极分别属于相邻的第一阳极列和第二阳极列；所述第二像素电路列中，每个第三像素电路与一个第三阳极电连接；所述第二像素电路列所对应的各第三阳极属于同一第三阳极列。所述第二方向与所述第一方向垂直。
在一些实施例中，在所述多条第一信号线为所述多条数据线的情况下，所述多条数据线包括多条第一数据线和多条第二数据线。每条第一数据线与一个第一像素电路列中的各第一像素电路和各第二像素电路电连接，以与所述第一像素电路列所对应的第一阳极列所包括的各第一阳极和第二阳极列所包括的各第二阳极电连接。每条第二数据线与一个第二像素电路列中的各第三像素电路电连接，以与所述第二像素电路列所对应的第三阳极列所包括的各第三阳极电连接。
在一些实施例中，每条数据线具有与像素电路列中多个像素电路对应电连接的多个连接部。所述第一数据线上，对应连接所述第二像素电路的连接部，被所述第二像素电路所电连接的第二阳极覆盖。所述第二数据线上，对应连接相邻两个第三像素电路的两个连接部分别位于所述第二数据线的两侧。
在一些实施例中，在所述多个阳极中的至少一个在所述衬底上的正投影，与每条第一信号线在所述衬底上的正投影无交叠，至少一条第一信号线包括至少一个直行部分和至少一个弯折部分的情况下，所述第一信号线包括所述第一数据线，所述第一数据线包括多个直行部分和多个弯折部分，所述第一数据线位于相邻的所述第一阳极列和所述第二阳极列之间。所述第一数据线的每个直行部分的正投影，位于所述第一阳极列中的一个第一阳极的正投影沿第二方向上的一侧，且位于所述第二阳极列中的第二阳极的正投影沿所述第一方向上的一侧；所述第一数据线的每个弯折部分的第二段的正投影，位于所述第二阳极列中的一个第二阳极的正投影沿所述第二方向上的一侧，以避开所述第二阳极的正投影；和/或，所述第一信号线包括所述第二数据线，所述第二数据线包括多个直行部分和多个弯折部分，所述第二数据线位于相邻的所述第三阳极列和所述第一阳极列之间。所述第二数据线的每个直行部分的正投影，位于所述第一阳极列中的一个第一阳极的正投影沿第二方向上的一侧，且位于所述第三阳极列中的第三阳极的正投影沿所述第一方向上的 一侧；所述第二数据线的每个弯折部分的第二段的正投影，位于所述第三阳极列中的一个第三阳极的正投影沿所述第二方向上的一侧，以避开所述第三阳极的正投影。
在一些实施例中，所述第三阳极列中的多个第三阳极中，每两个相邻的第三阳极分为一组，且沿第一方向，每组第三阳极中的两个第三阳极之间的间距，小于所述两个第三阳极与周围的其他第三阳极之间的间距。
所述第二数据线的每个直行部分在所述衬底上的正投影，位于一组第三阳极在所述衬底上的正投影沿所述第一方向上的一侧。所述第二数据线的每个弯折部分的第二段在所述衬底上的正投影，位于所述一组第三阳极在所述衬底上的正投影沿所述第二方向上的一侧，以避开所述一组第三阳极在所述衬底上的正投影。
在一些实施例中，在所述阳极的正投影与一条第一信号线的正投影有交叠的情况下，所述第一信号线为所述第一数据线。所述第一数据线的正投影与所述一个第二阳极列所包括的各第二阳极的正投影沿第一方向的中线重合。
在一些实施例中，在所述阳极的正投影与两条第一信号线的正投影有交叠的情况下，所述两条第一信号线为相邻的所述第一阳极列、所述第二阳极列和所述第三阳极列所对应的第一数据线和第二数据线。所述第一数据线和所述第二数据线的正投影与一个第三阳极列所包括的各第三阳极的正投影有交叠，且所述第一数据线和所述第二数据线经过每个第三阳极的部分相对于所述第三阳极沿所述第一方向的中线对称设置。
在一些实施例中，所述第二数据线的正投影与其相邻的第一阳极的正投影无交叠。所述第一数据线的正投影与其相邻的第二阳极的正投影无交叠；或者，所述第一数据线的正投影与其相邻的第二阳极列中各第二阳极有交叠，所述第一数据线的正投影的交叠部分与所述第二阳极列中各第二阳极的正投影沿第一方向的中线重合。
在一些实施例中，所述显示基板还包括：缓冲层、半导体层、栅绝缘层、第一栅金属层、第一绝缘层、第二栅金属层、第二绝缘层、像素界定层、多个发光功能层和阴极层。所述缓冲层设置在所述衬底上。所述半导体层设置在所述缓冲层远离所述衬底的一侧，所述半导体层包括多个半导体图案，每个半导体图案包括所述像素电路中多个晶体管的有源层。所述栅绝缘层设置在所述半导体层远离所述衬底的一侧。所述第一栅金属层设置在所述栅绝缘层远离所述衬底的一侧；所述第一栅金属层包括多个第一图案，每个第一图案为所述像素电路中电容器的第一极板。所述第一绝缘层设置在所述第一栅 金属层远离所述衬底的一侧。所述第二栅金属层设置在所述第一绝缘层远离所述衬底的一侧；所述第二栅金属层包括多个第二图案，每个第二图案为所述像素电路中电容器的第二极板。所述第二绝缘层设置在所述第二栅金属层远离所述衬底的一侧。所述像素界定层设置于所述多个阳极和所述第一平坦层远离所述衬底的一侧；所述像素界定层限定出多个开口；每个开口暴露一个阳极的至少一部分。所述多个发光功能层设置在所述多个阳极远离所述衬底一侧的多个发光功能层，每个发光功能层位于一个开口内。所述阴极层设置在所述发光功能层远离所述衬底的一侧，所述阴极层延伸至所述像素界定层远离所述衬底的一侧，且覆盖所述像素界定层。
在一些实施例中，每个像素电路至少包括补偿晶体管、驱动晶体管以及电容器。所述补偿晶体管的有源层包括第一极区、第二极区以及连接所述第一极区和所述第二极区的沟道区。所述驱动晶体管的有源层包括第一极区、第二极区以及连接所述第一极区和所述第二极区的沟道区。所述第一栅金属层中所述电容器的第一极板中与所述驱动晶体管的沟道区的交叠部分作为所述驱动晶体管的栅极。所述补偿晶体管的第一极区与所述驱动晶体管的第二极区电连接，所述补偿晶体管的第二极区与所述驱动晶体管的栅极通过连接结构电连接。每个第二阳极在所述衬底上的正投影，与相邻两个像素电路的连接结构在所述衬底上的正投影有重叠，且所述相邻两个像素电路中的其中一者为与所述第二阳极电连接的第二像素电路，另一者为与所述第二像素电路相邻的第三像素电路。
在一些实施例中，每条数据线与其所电连接的像素电路列中，各像素电路的电容器的第二极板有交叠。
另一方面，提供一种显示装置，包括：如上一方面中任一项所述的显示基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例提供的一种显示基板剖面结构图；
图2为根据一些实施例提供的另一种显示基板剖面结构图；
图3为根据一些实施例提供的又一种显示基板剖面结构图；
图4为根据一些实施例提供的又一种显示基板剖面结构图；
图5为根据一些实施例提供的显示装置的结构图；
图6为根据一些实施例提供的显示基板的结构图；
图7A为根据一些实施例提供的一种显示基板的局部剖视图；
图7B为根据一些实施例提供的另一种显示基板的局部剖视图；
图7C为根据一些实施例的像素电路一种电路等效图；
图8A为根据一些实施例提供的一种显示基板的一种膜层结构图；
图8B为根据一些实施例提供的一种阳极结构图；
图8C为根据一些实施例提供的另一种阳极的结构图；
图8D为根据一些实施例提供的又一种阳极结构图；
图9A为根据一些实施例提供的一种阳极与信号线的结构图；
图9B为根据一些实施例提供的另一种阳极与信号线的结构图；
图9C为根据一些实施例提供的又一种阳极与信号线的结构图；
图10A为根据一些实施例提供的又一种阳极与信号线的结构图；
图10B为根据一些实施例提供的又一种阳极与信号线的结构图；
图10C为根据一些实施例提供的又一种阳极与信号线的结构图；
图10D为根据一些实施例提供的又一种阳极与信号线的结构图；
图11为根据一些实施例提供的一种显示基板的另一种膜层结构图；
图12为根据一些实施例提供的一种显示基板的又一种膜层结构图；
图13为根据一些实施例提供的一种显示基板的又一种膜层结构图；
图14为根据一些实施例提供的一种显示基板的又一种膜层结构图；
图15为根据一些实施例提供的一种显示基板的又一种膜层结构图；
图16为根据一些实施例提供的一种显示基板的又一种膜层结构图；
图17为根据一些实施例提供的一种显示基板的又一种膜层结构图；
图18～图24为根据图7B所提供的显示基板中各膜层的平面图；
图25为根据图24所提供的显示基板中各膜层的另一种平面图；
图26为根据图25所提供的显示基板中单个像素电路区域中各膜层的一种平面图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他 实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“电连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“电连接”以表明两个或两个以上部件有直接电接触。然而，术语“电连接”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量 ***的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
目前，随着显示技术的发展，需要对显示装置的各项性能进行优化研究。显示装置的性能参数主要有功耗、图像显示亮度、图像显示色坐标、色域和视角色偏等等。其中，视角色偏问题的影响因素很多，例如，用于图像显示的多个像素中，每个像素对应的阳极的平坦度对色偏有很大影响。示例的，如图1所示，从显示基板上的电路结构设计角度考虑，靠近阳极最近的金属导电层的图案对阳极的平坦度影响最大，使得阳极不同位置处的高度不一致。例如，对于某一阳极来说，若该阳极的左侧下方设置有金属导电图案，其右侧下方没有金属导电图案，则阳极的左侧的位置相对于右侧的位置较高，位于阳极下方的金属导电层的图案会导致阳极发生“倾斜”，使得设置于阳极上方的发光功能层的厚度不均一，从而导致像素向左右两侧发出的光强度不匹配，这种情况下，显示面板发生大视角色偏，目视时呈现类似一侧发红，另一侧发青的现象。
为此，如图2～图4所示，本公开通过调节金属导电层的图案与阳极的位置关系，改善阳极所在平面的平整度，避免阳极所在平面相对于水平面存在角度倾斜，导致显示面板出现色偏现象。
本公开一些实施例提供了一种显示装置1000。如图5所示，显示装置1000是用于可视化的显示电子信息的装置或者设备。示例性的，显示装置1000可以是智能手机、平板电脑、电视机、显示器、笔记本电脑以及其他可穿戴电子设备(例如手表)等任何具有显示功能的产品或部件。
示例性地，显示装置1000也可以为电致发光显示装置或光致发光显示装置。在显示装置1000为电致发光显示装置的情况下，电致发光显示装置可以为有机电致发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置或量子点电致发光二极管(Quantum Dot Light Emitting Diodes，简称QLED) 显示装置。在显示装置1000为光致发光显示装置的情况下，光致发光显示装置可以为量子点光致发光二极管显示装置。
在一些实施例中，显示装置1000为有源矩阵有机发光二极管(Active-matrix organic light emitting diode，简称AMOLED)显示装置，具有反应速度较快、对比度更高、视角更广且功耗更低等特点，是当今显示技术领域研究的热点之一。
如图6所示，上述显示装置1000包括显示基板100。该显示基板100包括显示区AA(Active Area，简称AA区；也可称为有效显示区)和位于AA区至少一侧的周边区BB。
上述显示基板100中，显示区AA中设置有多个像素P’和多条信号线，多条信号线与多个像素P’电连接，示例性地，每个像素P’包括至少三种颜色的子像素P，该多种颜色的子像素P至少包括第一子像素P1、第二子像素P2和第三子像素P3，其中，第一子像素P1、第二子像素P2和第三子像素P3的发光颜色各不相同，三种颜色为三基色(例如红色、绿色和蓝色)。
子像素P内设置有用于控制子像素P进行显示的像素电路，像素电路设置在显示基板100的衬底1上。与子像素P连接的栅线GL用于向子像素P的像素电路传输扫描信号Gate；与子像素P连接的数据线DL用于向子像素P的像素电路传输数据信号Data，数据信号Data来自与各条数据线DL耦接的源极驱动器(Source Driver，简称SD)。
在一些实施例中，如图25所示，显示基板100包括多个像素电路200。需要说明的是，为清楚表示显示基板100中各膜层结构，图25所示意的膜层图的层叠顺序与图24中的各膜层的层叠顺序相反，即最上层为半导体层3，最下层为发光功能层13。示例性地，多个像素电路200包括多个第一像素电路201、多个第二像素电路202和多个第三像素电路203。多个像素电路200排列成多个像素电路列，多个像素电路列包括多个第一像素电路列210和多个第二像素电路列220，每个第一像素电路列210包括沿第一方向Y排成一列且交替设置的多个第一像素电路201和多个第二像素电路202，每个第二像素电路列220包括沿第一方向Y排成一列的多个第三像素电路203。沿第二方向X，第一像素电路列210和第二像素电路列220交替设置。
上述每个像素电路200包括多个薄膜晶体管TFT以及至少一个电容器01。示例性地，如图7C和图26所示，像素电路200包括第一复位晶体管组T1，补偿晶体管T2、驱动晶体管T3、写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、第二复位化晶体管T7和电容器01。第一复位晶体 管T1的控制极与第一复位信号端Reset1电连接，其第一极与初始化信号端Vinit1电连接，其第二极与第一节点N1电连接。补偿晶体管T2的控制极与扫描信号端Gate电连接，其第一极与第二节点N2电连接，其第二极与第一节点N1电连接。驱动晶体管T3的控制极与第一节点N1电连接，其第一极与第三节点N3电连接，其第二极与第二节点N2电连接。写入晶体管T4的控制极与扫描信号端Gate电连接，其第一极与数据写入信号端VData电连接，其第二极与第三节点N3电连接。第一发光控制晶体管T5的控制极与使能信号端EM电连接，其第一极与第一电源电压端VDD电连接，其第二极与第三节点N3电连接。第二发光控制晶体管T6的控制极与使能信号端EM电连接，其第一极与第二节点N2电连接，其第二极与发光器件02的阳极电连接。第二复位晶体管T7的控制极与第二复位信号端Reset2电连接，其第一极与初始化信号端Vinit1电连接，其第二极与发光器件02的阳极电连接。电容器01的第二极板012与第一电源电压端VDD电连接，其第一极板011与第一节点N1电连接。发光器件02的阴极与第二电源电压端VSS电连接。
可以理解的是，第一像素电路201、第二像素电路202和第三像素电路203的电路结构相同。
上述薄膜晶体管TFT的第一极可以为源极，第二极可以为漏极；或者，第一极可以为漏极，第二极可以为源极，本公开的实施例对此不做限制。上述第一节点N1、第二节点N2和第三节点N3并非表示实际存在的部件，而是表示电路图中相关子电路或电子元件电连接的汇合点，也就是说，这些节点是由电路图中相关子电路或电子元件电连接的汇合点等效而成的节点。以及，上述第一电源电压VDD中的“VDD”为恒定高电位信号，本公开的实施例并不限制电压信号为VDD或VGH等恒定高电位信号。类似的，第二电源电压端VSS中的“VSS”为恒定低电位信号，本公开的实施例并不限制电压信号为VSS、Vinit或VGL等恒定低电位信号。
需要说明的是，按照导通关断类型划分，薄膜晶体管包括P型薄膜晶体管和N型薄膜晶体管。本公开实施例提供的薄膜晶体管对此不做限定，可以为P型薄膜晶体管，也可以为N型薄膜晶体管，根据具体实施方式选择设置。按照膜层结构类型划分，薄膜晶体管包括底栅型薄膜晶体管和顶栅型薄膜晶体管，本公开实施例提供的薄膜晶体管对此不做限定，以下实施例以顶栅型薄膜晶体管为例。
在一些实施例中，如图7A、图7B、图17～图24所示，按照从下至上的顺序，显示基板100所包括的膜层分别为：衬底1、缓冲层2、半导体层3、 栅绝缘层4、第一栅金属层5、第一绝缘层6、第二栅金属层7、第二绝缘层8、第一导电层9、第一平坦层10、多个阳极11、像素界定层12、多个发光功能层13和阴极层14。
上述衬底1采用的材料可以包括聚合物树脂或玻璃。示例性地，衬底采用的材料包括聚合物树脂，诸如聚醚砜(PES)、聚芳酯(PAR)、聚醚酰亚胺(PEI)、聚萘二甲酸乙二醇酯(PEN)、聚对苯二甲酸乙二醇酯(PET)、聚苯硫醚(PPS)、聚酰亚胺(PI)、聚碳酸酯(PC)、三乙酸纤维素(TAC)和乙酸丙酸纤维素(CAP)中的一种。示例的，衬底1可以是柔性的，包括包含SiO2作为主要成分的玻璃材料；或者也可以是刚性的，包括诸如增强塑料的树脂。衬底1可以具有包括包含上述聚合物树脂的层以及位于上述聚合物树脂层上的阻挡层的堆叠结构。例如，衬底1可以具有包括第一聚合物树脂层、第一阻挡层、第二聚合物树脂层和第二阻挡层的堆叠结构。其中，包括聚合物树脂的衬底可以改善柔性。第一阻挡层和第二阻挡层可以包括氮化硅(SiNx)、氮氧化硅(SiON)或/和氧化硅(SiOx)。本公开实施例不限于此。
缓冲层2设置在衬底1上。缓冲层2采用的材料可以包括诸如氮化硅(SiNx，x>0)、氮氧化硅(SiON)和氧化硅(SiOx，x>0)的无机绝缘材料，并且可以包括包含上述无机绝缘材料的单层或多层结构。缓冲层2能够起到在衬底1上制作图案时提供缓冲作用。
半导体层3设置在缓冲层2远离衬底1的一侧。半导体层3采用的材料可以包括多晶硅、非晶硅、氧化物半导体或有机半导体。如图18所示，半导体层3包括多个半导体图案31，每个半导体图案31包括像素电路200中多个薄膜晶体管TFT的有源层。示例性地，像素电路200中补偿晶体管T2的有源层包括第一极区T21、第二极区T22以及连接第一极区T21和第二极区T22的沟道区T23。驱动晶体管T3的有源层包括第一极区T31、第二极区T32以及连接第一极区T31和第二极区T32的沟道区T33。其中，补偿晶体管T2的第一极区T21、第二极区T22分别为图7C中补偿晶体管T2的第一极和第二极，驱动晶体管T3的第一极区T31、第二极区T32分别为图7C中驱动晶体管T3的第一极和第二极。
栅绝缘层4设置在半导体层3远离衬底1的一侧。栅绝缘层4采用的材料可以包括无机绝缘材料，诸如氧化硅、氮化硅、氮氧化硅、氧化铝、氧化钛、氧化钽和/或氧化铪；也可以包括包含以上材料的单层或多层结构。
第一栅金属层5设置在栅绝缘层4远离所述衬底1的一侧。第一栅金属层5采用的材料可以包括低电阻金属材料，例如，可以包括导电材料钼Mo、 镁Mg、铝Al、铜Cu和/或钛Ti；也可以包括包含以上材料的单层或多层结构。第一栅金属层5包括多条栅扫描线50以及多个第一图案52，多条栅扫描线中的至少一条栅扫描线为第一栅扫描线50，第一栅扫描线50与图7C所示的像素电路中扫描信号端Gate电连接，每个第一图案52为像素电路200中电容器01的第一极板011，电容器01的第一极板011为图7C中电容器01的第一极。示例性地，如图18、图19和图26所示，第一栅扫描线50与补偿晶体管T2的沟道区T23有交叠的部分作为补偿晶体管T2的栅极(控制极)，例如，第一栅扫描线50上具有多个突出部51，每个突出部51与一个补偿晶体管T2的沟道区T23衬底1上的正投影有交叠，该突出部51作为补偿晶体管T2的栅极51。每个电容器01的第一极板011中与驱动晶体管T3的沟道区T33的交叠部分作为驱动晶体管T3的栅极。
第一绝缘层6设置在第一栅金属层5远离衬底1的一侧。第一绝缘层6采用的材料可以包括无机绝缘材料，诸如氧化硅、氮化硅、氮氧化硅、氧化铝、氧化钛、氧化钽和/或氧化铪；也可以包括包含以上材料的单层或多层结构。
第二栅金属层7设置在第一绝缘层6远离衬底1的一侧。如图20所示，第二栅金属层7包括多个第二图案71，每个第二图案71为像素电路200中电容器01的第二极板012。如图26所示，该第二极板71与第一栅金属层5中形成的多个电容器01的第一极板011共同作用，作为存储电容器，为像素电路200提供存储电容。示例性地，由于多个像素电路的电容器01的第二极板012接收恒定的电压信号，因此每行的多个第二图案71可以连为一体。第二栅金属层7可以采用与第一栅金属层5相同的材料。
第二绝缘层8设置在第二栅金属层7’远离衬底1的一侧。第二绝缘层8采用的材料可以包括无机绝缘材料，诸如氧化硅、氮化硅、氮氧化硅、氧化铝、氧化钛、氧化钽和/或氧化铪；也可以包括包含以上材料的单层或多层结构。
第一导电层9设置在第二绝缘层8远离衬底1的一侧。第一导电层9采用的材料可以包括包含钼Mo、镁Mg、铝Al、铜Cu和钛Ti的导电材料中的任意一种或多种。第一导电层9包括多条第一信号线93，多条第一信号线93为多条数据线和多条电压信号线；第一导电层9还包括薄膜晶体管TFT的源极91和漏极92，以及多个第一转接电极94等。源极91和漏极92可以包括包含以上材料的单层或多层结构。示例的，源极91和漏极92可以包括Ti/Al/Ti的多层结构。
第一平坦层10设置在第一导电层9远离衬底1的一侧。第一平坦层10采用的材料可以包括有机绝缘材料，无机绝缘材料或者无机和有机绝缘材料。示例性的，有机绝缘材料包括诸如聚甲基丙烯酸甲酯(PMMA)和聚苯乙烯(PS)的通用聚合物、具有苯酚类基团的聚合物衍生物、丙烯酰基类聚合物、酰亚胺类聚合物、芳基醚类聚合物、酰胺类聚合物、氟类聚合物、对二甲苯类聚合物和乙烯醇类聚合物中的任意一种或多种。例如，第一平坦层10采用的材料包括聚酰亚胺。
多个阳极11设置在第一平坦层10远离衬底1的一侧。多个阳极11采用的材料可以包括导电氧化物，诸如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铟镓(IGO)和氧化铝锌(AZO)中的任意一种或多种。例如，多个阳极11采用的材料包括氧化铟锡(ITO)。
像素界定层12设置在多个阳极11和第一平坦层10远离衬底1的一侧，像素界定层12限定出多个开口；每个开口暴露一个阳极11的至少一部分。像素界定层12采用的材料包括无机绝缘材料和有机绝缘材料中的至少一种，诸如氮化硅(SiNx)、氮氧化硅(SiON)和氧化硅(SiOx)。
多个发光功能层13设置在多个阳极11远离衬底1的一侧，每个发光功能层13位于一个开口内。多个发光功能层13具体可以为单层结构，也可以为多层结构。示例性地，发光功能层13仅包括发光层。或者，发光功能层13包括空穴注入层、空穴传输层、发光层、电子传输层、电子注入层。发光功能层13采用的材料包括无机发光材料或有机发光材料。示例性地，有机发光材料的类型不同，发出光线的颜色也不同。
阴极层14设置在发光功能层13远离衬底1的一侧，阴极层14延伸至像素界定层12远离衬底1的一侧，且覆盖像素界定层12。阴极层14采用的材料可以包括(半)透明层，该(半)透明层包括银Ag、镁Mg、铝Al、铂Pt、金Au、镍Ni、铬Cr和锂Li中的任意一种或多种。例如，阴极层14采用的材料包括铝Al。
在一些实施例中，如图7B所示，显示基板100还包括第二导电层9’和第二平坦层10’，第二平坦层10’设置于第一导电层9远离第一平坦层10的一侧。此时，第一导电层9包括多条第一信号线93，多个第一转接电极94和多个第二转接电极95。
第二导电层9’设置于第二平坦层10’远离第一导电层9的一侧，如图21和图22所示，第二导电层包括多条第二信号线91’，多个连接结构92’，以及薄膜晶体管TFT的源极91和漏极92。多条第二信号线91’为多条电压 信号线。即显示基板100具有双层金属导电层的结构。第二导电层9’可以采用与第一导电层9相同的材料。
如图7A所示，在显示基板100仅包括第一导电层9和第一平坦层10的情况下，第一导电层9所包括的多条第一信号线93为多条数据线和多条电压信号线，第一导电层9还包括薄膜晶体管TFT的源极91和漏极92，以及多个第一转接电极94等。多个第一转接电极94连接多个阳极11所在膜层和第一导电层9，例如，每个第一转接电极94连接一个阳极11和一个薄膜晶体管TFT的漏极92。
需要说明的是，如图15所示，第一导电层9包括多条第一信号线93和第一转接电极94的情况下，第一转接电极94与移动和弯折后的多条第一信号线93的图案不重叠，以保证第一转接电极94和多条第一信号线93各自的正常工作。
如图7B所示，在显示基板100还包括第二导电层9’和第二平坦层10’的情况下，第一导电层9所包括的多条第一信号线93为多条数据线，第一导电层9还包括多个第一转接电极94和多个第二转接电极95，第二导电层9’所包括的多条第二信号线91’为多条电压信号线，第二导电层9’还包括薄膜晶体管TFT的源极91和漏极92等。多个第二转接电极95连接第一导电层9和第二导电层9’，例如，每个第二转接电极95连接一个第一转接电极94和一个薄膜晶体管TFT的漏极92，以将薄膜晶体管TFT与其对应的阳极11电连接。
需要说明的是，如图7B所示，在第一导电层9包括多条第一信号线93和多个第一转接电极94和多个第二转接电极95的情况下，无论第一信号线93的形状如何变化，都要保证第一转接电极94和第二转接电极95与移动和弯折后的多条第一信号线93的图案不重叠，以保证第一转接电极94和多条第一信号线93各自的正常工作。
在一些实施例中，如图6所示，显示基板100包括多个子像素P，多个子像素P包括多个第一子像素P1、多个第二子像素P2和多个第三子像素P3。在一些示例中，多个第一子像素P1、多个第二子像素P2和多个第三子像素P3的排布如下：
如图8A所示，多个子像素P排列成多个子像素列，所述多个子像素列包括多个第一子像素列、多个第二子像素列和多个第三子像素列。沿第二方向X多个子像素列包括多个第一子像素列、多个第二子像素列和多个第三子像素列的次序循环设置。沿第一方向Y，多个第一子像素P1位于同一列；多个第 二子像素P2位于同一列；多个第三子像素P3位于同一列。其中，第一方向Y与第二方向X垂直。在一些实施例中，沿所述第一方向Y，相邻的两列子像素P中的多个子像素P相互交错设置。
示例性地，第一子像素P1为红色子像素，第二子像素P2为蓝色子像素，第三子像素P3为绿色子像素。或者，第一子像素P1为蓝色子像素，第二子像素P2为红色子像素，第三子像素P3为绿色子像素。在此，只要第一子像素P1、第二子像素P2和第三子像素P3为不同颜色的子像素即可，本公开实施例对此不做限定。以下实施例以第一子像素P1为红色子像素，第二子像素P2为蓝色子像素，第三子像素P3为绿色子像素为例进行说明。
在一些示例中，如图8A所示，一个像素P’包括四个子像素P。示例的，一个像素P’包括一个第一子像素P1、一个第二子像素P2和两个第三子像素P3。
在另一些示例中，一个像素P’包括三个子像素P。示例的，一个像素P’包括一个第一子像素P1、一个第二子像素P2和一个第三子像素P3。
可以理解的是，上述一个像素P’中包含不同颜色的子像素P的个数与实际显示装置1000的配置需求有关，本领域技术人员可以根据实际需求选择设置，本公开对此不做限制。只要多个子像素P与栅线GL和数据线DL耦接，在相应的信号控制下实现图像显示即可。
在一些实施例中，如图8A所示，多个子像素P包括多个第一子像素P1、多个第二子像素P2和多个第三子像素P3的情况下，每个第一子像素P1包括第一阳极111；每个第二子像素P2包括第二阳极112；每个第三子像素P3包括第三阳极113。
可以理解的是，多个第一子像素P1中的每个第一子像素P1还包括发光功能层13和阴极。第一阳极111、发光功能层13和阴极构成发光器件02。类似的，每个第二子像素P2和第三子像素P3还包括发光功能层13和阴极。其中，第一阳极111、第二阳极112和第三阳极113的形状各不相同，如图8B～图8D所示，第一阳极111、第二阳极112的形状近似为六边形，第三阳极113的形状近似为五边形，各阳极11的大小与不同颜色的子像素P的发光功能层13的大小相适应，保证每个子像素P具有有效发光区域。
示例性地，如图8B所示，第一阳极111包括第一阳极主体部111a和第一阳极延伸部111b。该第一阳极主体部111a的形状与其对应的发光功能层13的形状一致，例如均为六边形，且第一阳极111对应的发光功能层13在衬底1上的正投影位于第一阳极主体部111a在衬底1上的正投影内，保证第一 阳极111对应的每个子像素P具有有效发光区域。第一阳极延伸部111b位于有效发光区域以外的区域，被配置为与薄膜晶体管TFT电连接。其中，第一阳极主体部111a的形状为六边形，该六边形沿第一方向Y的中线可以认为第一阳极111的中线C，第一阳极延伸部111b的形状对第一阳极111的中线C的位置影响忽略不计。需要注意的是，上述第一阳极111的中线C，指的是第一阳极111的有效发光区域的中线C，所述有效发光区域为发光器件中阳极、发光功能层和阴极等膜层的交叠区域。
示例性地，如图8C所示，第二阳极112包括第二阳极主体部112a和第二阳极延伸部112b。该第二阳极主体部112a的形状与其对应的发光功能层13的形状一致，例如均为六边形，且第二阳极112对应的发光功能层13在衬底1上的正投影位于第二阳极主体部112a在衬底1上的正投影内，保证第二阳极112对应的每个子像素P具有有效发光区域。第二阳极延伸部112b位于有效发光区域以外的区域，被配置为与薄膜晶体管TFT电连接。其中，第二阳极主体部112a的形状为六边形，该六边形沿第一方向Y的中线可以认为第二阳极112的中线C，第二阳极延伸部112b的形状对第二阳极112的中线C的位置影响忽略不计。
示例性地，如图8D所示，第三阳极113包括第三阳极主体部113a和第三阳极延伸部113b。该第三阳极主体部113a的形状与其对应的发光功能层13的形状一致，例如均为五边形，且第三阳极113对应的发光功能层13在衬底1上的正投影位于第三阳极主体部113a在衬底1上的正投影内，保证第三阳极113对应的每个子像素P具有有效发光区域。第三阳极延伸部113b位于有效发光区域以外的区域，被配置为与薄膜晶体管TFT电连接。其中，第三阳极主体部113a的形状为五边形，该五边形沿第一方向Y的中线近似为第三阳极113的中线C，第三阳极延伸部113b的形状对第三阳极113的中线C的位置影响忽略不计。
上述多个第一阳极111、多个第二阳极112和多个第三阳极113的排布方式与多个子像素P的排布方式一致，示例性地，如图8A所示，所述多个阳极11排列成多个阳极列，所述多个阳极列包括多个第一阳极列、多个第二阳极列和多个第三阳极列。
示例性地，每个第一阳极列包括沿所述第一方向Y排成一列的多个第一阳极111，每个第二阳极列包括沿所述第一方向Y排成一列的多个第二阳极112，每个第三阳极列包括沿所述第一方向Y排成一列的多个第三阳极113。
沿第二方向X，按照第一阳极列、第二阳极列和第三阳极列的次序循环 设置。沿第一方向Y，相邻的两个阳极列所包括的阳极11相互交错设置。例如，如图8A所示，相邻的第二阳极列和第三阳极列中，每个第二阳极112的一部分穿***相邻的两个第三阳极113之间，每个第三阳极113的一部分穿***相邻的两个第二阳极112之间。
在一些实施例中，如图24所示，第一像素电路列210中，每个第一像素电路201与一个第一阳极111电连接，每个第二像素电路202与一个第二阳极112电连接。第一像素电路列210所对应的各第一阳极111和各第二阳极112分别属于相邻的第一阳极列和第二阳极列。第二像素电路列220中，每个第三像素电路203与一个第三阳极113电连接，第二像素电路列220所对应的各第三阳极113属于同一第三阳极列。
在一些实施例中，如图7B和图8A所示，在显示基板100包括第一导电层9和第二导电层9’的情况下，第一导电层9包括多条第一信号线93，多条第一信号线93为多条数据线。第一导电层9还包括多个第一转接电极94和多个第二转接电极95。第二导电层9’包括多条电压信号线91’，多条第二信号线91’为多条电压信号线。第二导电层9’还包括薄膜晶体管TFT的源极91和漏极92。
上述多条第一信号线93沿第一方向Y延伸，按照多条数据线与不同的子像素P(或者阳极11)的连接关系分类，多条数据线包括多条第一数据线9311和多条第二数据线9312。每条第一数据线9311与一个第一像素电路列210中的各第一像素电路201和各第二像素电路202电连接，以与第一像素电路列210所对应的第一阳极列所包括的各第一阳极111和一个第二阳极列所包括的各第二阳极112电连接；每条第二数据线9312与一个第二像素电路列220中的各第三像素电路203电连接，以与第二像素电路列220所对应的第三阳极列所包括的各第三阳极113电连接。
在一些实施例中，如图23和图24所示，每条数据线具有与像素电路列中多个像素电路200对应电连接的多个连接部。连接部的设置位置和相对于其所在的数据线的延伸方向，与该数据线所电连接的各阳极的位置有关，可根据实际需求设置。
示例性地，如图23和图24所示，第一数据线9311上，对应连接第二像素电路202的连接部933，被第二像素电路202所电连接的第二阳极112覆盖。第二数据线9312上，对应连接相邻两个第三像素电路203的两个连接部934分别位于第二数据线9312的两侧。
多条第二信号线91’沿第一方向Y延伸，被配置为将电源电压信号传 递至各子像素P中的像素电路。
需要说明的是，每条数据线通过各子像素P中的像素电路220中的薄膜晶体管TFT与对应的阳极11电连接。
在一些示例中，如图7A和图8A所示，每条第一数据线9311经过一个第二阳极列中的多个第二阳极112，每条第一数据线9311在衬底1上的正投影与第二阳极列中的多个第二阳极112在衬底1上的正投影S有交叠，且第一数据线9311经过第二阳极112的靠左侧位置，这样就会导致第二阳极112的左侧的位置相对于其右侧的位置较高，第二阳极112发生“倾斜”。示例的，如图1的左侧的阳极11所示，以该阳极11为图8A和图8C中的第二阳极112为例，在第二阳极112中的位置M和位置N为第二阳极11沿第一方向Y的对称位置处(以中线C为对称轴)，第二阳极112的左侧的位置M相对于其右侧的位置N较高，第二阳极112的位置M的高度H1大于其位置N处的高度H2，使得第二阳极112发生“倾斜”。如图1所示，阳极的某一位置处的高度是指，沿垂直于衬底1所在平面的方向上，阳极11中该位置处远离衬底1的表面与衬底1之间的距离。
每条第二数据线9312经过相邻的一个第三阳极列中的多个第三阳极113和一个第一阳极列中的多个第一阳极111，每条第二数据线9312在衬底1上的正投影与第三阳极列中的多个第三阳极113在衬底1上的正投影S有交叠，且第二数据线9312经过第三阳极113的靠右侧位置，这样就会导致第三阳极113的右侧的位置相对于其左侧的位置较高，第三阳极113发生“倾斜”(如图1的中间的阳极11)，其呈现效果与上述第二阳极112类似，在此不再赘述。
同时，每条第二数据线9312在衬底1上的正投影与第一阳极列中的多个第一阳极111在衬底1上的正投影S有交叠，且第一数据线9311经过第一阳极111的靠左侧位置，这样就会导致第一阳极111的左侧的位置相对于其右侧的位置较高，第一阳极111发生“倾斜”(如图1的右侧的阳极11)，其呈现效果与上述第二阳极112类似，在此不再赘述。
由于阳极11的表面不平坦，以所述阳极11沿第一方向Y的中线为对称轴，阳极11沿第一方向Y的对称位置处的高度不相等，使得设置于阳极11上方的发光功能层13的厚度不均一，从而导致像素向左右两侧发出的光强度不匹配，这种情况下，显示基板100发生大视角色偏，目视时呈现类似一侧发红，另一侧发青的现象。其中，请参见图1和图3、图8A和图8C，阳极11沿第一方向Y的对称位置处的高度是指，沿垂直于衬底1所在平面的方向上，阳极11中对称位置处远离衬底1的表面与衬底1之间的距离。阳极11 中对称位置处例如为位置M和位置N，该位置M和位置N以中线C为轴对称设置。
需要解释的是，如图7B所示，沿垂直于衬底1的方向，第二导电层9’与多个阳极11之间的距离，相较于第一导电层9与多个阳极11之间的距离更远。并且，第二导电层9’与多个阳极11之间有第一平坦层10和第二平坦层10’，因此，经过两层平坦层的平坦化作用，第二导电层9’的各个图案对第一平坦层10远离衬底1的一侧的表面的平坦度的影响可以忽略不计。类似的，半导体层3，第一栅金属层5，第二栅金属层7的各个图案，对第一平坦层10远离衬底1的一侧的表面的平坦度的影响也可以忽略不计。
在显示基板100仅包括第一导电层9不包括第二导电层9’的情况下，第一导电层9包括的多条第一信号线93为多条数据线和多条电压信号线，也会出现多条第一信号线93的正投影与阳极11的正投影有交叠，从而导致阳极11发生“倾斜”，使得显示基板100出现色偏的现象。
需要说明的是，如图7A和7B所示，第一导电层9为衬底1和多个阳极11之间最靠近所述多个阳极11的导电层；即，第一导电层9和所述多个阳极11之间无其他可导电的图案膜层，其中，图案膜层是指该膜层中包括多种图案，例如第一导电层9、第二导电层9’和第一栅金属层5均为图案膜层，例如第一导电层9包括多个图案，以形成多条数据线，第二导电层9’包括多个图案，以形成多条电压信号线，第一栅金属层5包括多种图案，以形成多条栅扫描线。由于第一导电层9为最靠近多个阳极11的图案膜层，多个阳极的表面的平坦性受到第一导电层中的多条第一信号线的排布位置影响。
基于此，如图9A～图17所示，本公开提供了一种显示基板100，通过调整阳极11与第一信号线93之间的位置关系，改善上述出现色偏的问题。
如图11和图12所示，在一些实施例中，所述多个阳极11中的至少一个在衬底1上的正投影，与每条第一信号线93在衬底1上的正投影无交叠。
如图13～图17所示，在另一些实施例中，所述多个阳极11中的至少一个在衬底1上的正投影与至少一条第一信号线93在衬底1上的正投影有交叠；正投影相交叠的阳极和至少一条第一信号线93中，所述至少一条第一信号线93经过所述阳极11的设定位置，使得以阳极11沿第一方向Y的中线C为对称轴，在该至少一条第一信号线93的设定位置基础上，该阳极11沿对称轴对称的位置处的高度大致相等。
其中，阳极11中对称位置处的高度是指，沿垂直于衬底1所在平面的方向上，阳极11中对称位置处远离衬底1的表面与衬底1之间的距离。示例的， 如图3和图10D所示，以阳极11沿第一方向Y的中线C为对称轴，阳极11沿中线C对称位置M和N，位置M与衬底1之间的距离为H1，位置N与衬底1之间的距离为H2。这样，阳极11沿对称轴对称的位置处的高度大致相等，即为H1与H2大致相等。
在上述实施例中，由于所述多个阳极11中的至少一个在衬底1上的正投影S，与每条第一信号线93在衬底1上的正投影无交叠，这样就保证了至少一个阳极11的下方没有第一信号线93经过，避免出现由于该阳极11下方设置有第一信号线93而导致阳极11左右两侧高度不一致，发生“倾斜”的情况，从而避免该阳极11所在子像素P向左右两侧发出的光强度不匹配。再者，在多个阳极11中的至少一个在衬底1上的正投影与至少一条第一信号线93在衬底1上的正投影有交叠，且所述至少一条第一信号线93经过所述阳极11的设定位置，使得以阳极11沿第一方向Y的中线C为对称轴，该阳极11沿对称轴对称的位置处的高度大致相等，同样也避免了该阳极11发生“倾斜”的情况，从而避免该阳极11所在子像素向左右两侧发出的光强度不匹配。以上两种设计均能改善阳极11表面的平坦度和高度的一致性，进而改善显示基板100发生大视角色偏的现象，下面做具体介绍。
如图9A～图9C所示，在一些实施例中，在多个阳极11中的至少一个在所述衬底1上的正投影S，与每条第一信号线93在衬底1上的正投影无交叠的情况下，至少一条第一信号线93包括至少一个直行部分931和至少一个弯折部分932；各直行部分931和各弯折部分932交替设置。所述直行部分931沿第一方向Y延伸，且所述直行部分931在所述衬底1上的正投影位于阳极11的正投影沿第一方向Y上的一侧。所述弯折部分932包括依次连接的第一段932a、第二段932b和第三段932c。第二段932b沿第一方向Y延伸，且第二段932b在衬底1上的正投影位于阳极11的正投影沿第二方向X上的一侧，以避开所述阳极11的正投影S。其中，第二方向X与第一方向Y垂直。
在一些实施例中，如图9A和图12所示，以该至少一个阳极11为第二阳极112，该至少一条第一信号线9为第一数据线9311为例，该第二阳极112与该第一数据线9311相邻且电连接。所述第一数据线9311的直行部分931沿第一方向Y延伸，且第一数据线9311的直行部分931在衬底1上的正投影位于所述第二阳极112的正投影沿第一方向Y上的一侧，这是由于相邻的第一阳极列和第二阳极列中，各第一阳极111和各第二阳极112相互交错设置，因此，第一数据线9311的直行部分931在衬底1上的正投影位于所述第二阳极112的正投影S沿第一方向Y上的一侧，即第一数据线9311的直行部分 931收进相邻两个第二阳极112之间的区域，以避开第一阳极111，避免与第一阳极111发生交叠。该第一数据线9311的弯折部分932在衬底1上的正投影沿第二阳极112的正投影S的边界绕行，以避开第二阳极112的正投影S，这样就保证了第二阳极112与第一数据线9311不会发生交叠。
例如，第一数据线9311的弯折部分932的第一段932a与位于第二阳极112沿第一方向Y的一侧的直行部分931连接；第三段932c与位于第二阳极112沿第一方向Y的另一侧的直行部分931连接；第二段932b沿第一方向Y延伸且连接第一段932a和第三段932c，第二段932b在所述衬底上的正投影位于第二阳极112的正投影沿第二方向X上的一侧，以使第一数据线9311避开第二阳极112的正投影S。
作为一种可能的设计，请继续参见图12，所述第一数据线9311包括多个直行部分931和多个弯折部分932，各直行部分931和各弯折部分932交替设置。第一数据线9311位于相邻的第一阳极列和第二阳极列之间。第一数据线9311的每个直行部分931的正投影，位于第一阳极列中的一个第一阳极111的正投影S沿第二方向X上的一侧，且位于第二阳极列中的第二阳极112的正投影S沿第一方向Y上的一侧。第一数据线9311的每个弯折部分932的第二段932b的正投影S，位于第二阳极列中的一个第二阳极112的正投影S沿第二方向X上的一侧，以避开第二阳极112的正投影S。
示例性地，如图8A所示，参见从左至右顺序的第一条第一信号线93设置在初始设置位置的结构。在一些示例中，请继续参阅图12，以上述阳极11为某一第二阳极112为例，参见从左至右顺序的第一条第一信号线93。该第一条第一信号线93相对于初始设置位置，沿第二方向X向右移动适量位置，以避开该第二阳极112的正投影S，形成具有直行部分931和弯折部分932的结构。其中，第一信号线93的直行部分931在所述衬底1上的正投影位于第二阳极112的正投影S沿所述第一方向Y上的一侧；第一信号线93的弯折部分931在所述衬底1上的正投影沿该第二阳极112的正投影的边界绕行，以避开该第二阳极112的正投影。示例性地，如图9A所示，第二阳极112的形状为六边形，则第一信号线93的弯折部分932的第一段932a、第二段932b和第三段932c的延伸方向也与六边形的左侧三条边界契合。
在另一些示例中，如图9C和图11所示，以该至少一个阳极11为第三阳极113，该至少一条第一信号线93为第二数据线9312为例，该第三阳极113与该第二数据线9312相邻且电连接。所述第二数据线9312的直行部分931沿第一方向Y延伸，且第二数据线9312的直行部分931在衬底1上的正投影 位于所述第三阳极113的正投影S沿第一方向Y上的一侧，这是由于相邻的第三阳极列和第一阳极列中，各第三阳极113和各第一阳极111相互交错设置，因此第二数据线9312的直行部分931在衬底1上的正投影位于所述第三阳极113的正投影S沿第一方向Y上的一侧，即第二数据线9312的直行部分932收进相邻两个第三阳极113之间的区域，以避开第一阳极111，避免与第一阳极111发生交叠。该第二数据线9312的弯折部分932的第二段932b在衬底1上的正投影沿第三阳极113的正投影S的边界绕行，以避开第三阳极113的正投影S，这样就保证了第三阳极113与第二数据线9312不会发生交叠。示例性地，如图9C所示，第三阳极113的形状为五边形，则第一信号线93的弯折部分932的第一段932a、第二段932b和第三段932c的延伸方向也与五边形边形的右侧两条边界契合。
作为一种可能的设计，请继续参见图11，第一信号线93包括所述第二数据线9312，所述第二数据线9312包括多个直行部分931和多个弯折部分932，各直行部分931和各弯折部分932交替设置；第二数据线9312位于相邻的第三阳极列和第一阳极列之间。第二数据线9312的每个直行部分931的正投影，位于第一阳极列中的第一阳极111的正投影S沿第二方向X上的一侧，且位于第三阳极列中的第三阳极113的正投影S沿第一方向Y上的一侧。第二数据线9312的每个弯折部分932的第二段932b的正投影，位于第三阳极列中的一个第三阳极113的正投影S沿第二方向X上的一侧，以避开第三阳极113的正投影S。示例性地，第二数据线9312的每个弯折部分932与第三阳极列中的一个第三阳极113位置对应，以避开各第三阳极11的正投影S，从而第二数据线9312与各第三阳极113均无交叠。
如图8A所示，参见从左至右顺序的第二条第一信号线93和第四条第一信号线93设置在初始设置位置的结构。示例性地，请继续参阅图11，以上述阳极11为某一第三阳极113为例，参见从左至右顺序的第二条第一信号线93和第四条第一信号线93，该第二条第一信号线93相对于初始设置位置，沿第二方向X向左移动适量位置，以避开第三阳极113的正投影S，形成具有直行部分931和弯折部分932的结构。该第四条第一信号线93与第二条第一信号线93的变换过程相同，在次不再赘述。第二条第一信号线93和第四条第一信号线93为第二数据线9312。其中，第二数据线9312的每个直行部分931在衬底1上的正投影，位于第一阳极列中的第一阳极111的正投影S沿第二方向X上的一侧，且位于第三阳极列中的第三阳极113的正投影S沿第一方向Y上的一侧。第二数据线9312的每个弯折部分932的第二段932b的正投 影，位于第三阳极列中的至少一个第三阳极113的正投影S沿第二方向X上的一侧，以避开第三阳极113的正投影S。示例性地，如图11所示，第三阳极113的形状为五边形，则第一信号线93的弯折部分932的第一段932a、第二段932b和第三段932c的延伸方向也与五边形的右侧三条边界契合，以避开第三阳极113的正投影S。
示例的，请继续参阅图11，第三阳极列中的多个第三阳极113中，每两个相邻的第三阳极113分为一组，且沿第一方向Y，每组第三阳极113中的两个第三阳极113之间的间距，小于这两个第三阳极113与周围的其他第三阳极113之间的间距。示例性地，如图11所示，第三阳极113的形状为五边形，每相邻的两个第三阳极113中，两个第三阳极113的一条边相对且相互平行，这两个第三阳极113作为一组第三阳极113。
需要说明的是，上述一组第三阳极113的划分，便于说明第三阳极113在衬底上的正投影S与第一信号线93在衬底1上的正投影的位置关系，不限制一组第三阳极113位于同一个像素P’内。
示例性地，以一组第三阳极113为例，第三阳极113的形状为五边形，两个第三阳极113的相互平行的两条边相对。在第一信号线93包括所述第二数据线9312的情况下，第二数据线9312的每个直行部分931在衬底1上的正投影，位于一组第三阳极113在衬底1上的正投影沿第一方向Y上的一侧。第二数据线9312的每个弯折部分932的第二段932b在衬底1上的正投影，位于一组第三阳极113在衬底1上的正投影S沿第二方向X上的一侧，以避开一组第三阳极113在衬底1上的正投影S。
可以理解的是，在第三阳极113为绿色子像素对应的阳极的情况下，采用两个较小面积的第三阳极113。示例的，第一阳极111为红色子像素对应的阳极，第二阳极112为蓝色子像素对应的阳极，则第三阳极113的面积小于第一阳极111的面积，且，第一阳极111的面积小于第二阳极112的面积。这样，第三阳极113的面积最小。这是因为绿色子像素的发光功能层的发光效率最高，通过这样的设计可以消除红色、绿色、蓝色子像素各发光效率不同而产生的色偏问题。
在另一些示例中，如图9B所示，以该至少一个阳极11为第一阳极111，该至少一条第一信号线93为第二数据线9312为例，该第一阳极111与该第二数据线9312相邻。所述第二数据线9312的直行部分931沿第一方向Y延伸，且第二数据线9312的直行部分931在衬底1上的正投影位于所述第一阳极111的正投影S沿第一方向Y上的一侧。该第二数据线9312的弯折部分 932在衬底1上的正投影沿第一阳极111的正投影S的边界绕行，该第二数据线9312的弯折部分932包括依次连接的第一段932a、第二段932b和第三段932c，第二段932b沿第一方向Y延伸，第二段932b在衬底1上的正投影位于第一阳极111的正投影沿第二方向X上的一侧，以避开第一阳极111的正投影S。
可以理解的是，请继续参阅图9C和图9B，考虑到不同的布线结构，对于同一条第二数据线9312，第二数据线9312在衬底上的正投影同时避开位于其两侧的第三阳极113和第一阳极111，图9B中第二数据线9312相对于第一阳极111的弯折部分932的第二段932b，也可以作为图9C中第三阳极113的直行部分931。这样，第二数据线9312位于相邻的第三阳极列和第一阳极列之间，虽然第二数据线9312最后呈现的形状相同，但是，基于初始状态的第二数据线9312进行了不同位置和方向的弯折。
在一些实施例中，如图12所示，每条第一信号线93包括多个直行部分931和多个弯折部分932。根据多个阳极呈周期性的排布，第一信号线93的结构也呈周期性规律。至少一条第一信号线93包括第一数据线9311和第二数据线9312。第一数据线9311位于相邻的第一阳极列和第二阳极列之间。第二数据线9312位于相邻的第三阳极列和第一阳极列之间。
所述第一数据线9311包括多个直行部分931和多个弯折部分932，第一数据线9311的每个直行部分931的正投影，位于第一阳极列中的一个第一阳极111的正投影S沿第二方向X上的一侧，且位于第二阳极列中的第二阳极112的正投影S沿第一方向Y上的一侧。第一数据线9311的每个弯折部分932的第二段的正投影S，位于第二阳极列中的一个第二阳极112的正投影S沿第二方向X上的一侧，以避开所述第二阳极112的正投影。
所述第二数据线9312包括多个直行部分和多个弯折部分，第二数据线9312的每个直行部分931的正投影，位于第一阳极列中的第一阳极111的正投影S沿第二方向X上的一侧，且位于第三阳极列中的第三阳极113的正投影沿第一方向Y上的一侧。第二数据线9312的每个弯折部分932的第二段的正投影，位于第三阳极列中的至少一个第三阳极113的正投影沿第二方向X上的一侧，以避开第三阳极113的正投影S。
如图8A所示，参见从左至右顺序的第一条第一信号线93和第二条第一信号线93设置在初始设置位置的结构。请继续参阅图12，从左至右顺序的第一条第一信号线93和第二条第一信号线93的设置位置，相较于其各自的初始设置位置的变换过程，具体参见上述两个示例，在此不再赘述。
这样，在阳极11的正投影S对应区域的第一导电层9上无信号线图案，保证阳极正投影S对应的第一平坦层10的区域所在平面是水平的，位于该区域上的阳极11所在平面也是水平的，从而，避免因阳极11的不平坦或具有的预倾角，导致阳极11、发光功能层13和阴极层14共同作用下的发光器件02发出的光线至显示位置的距离不同，导致出射光线的显示亮度不均匀，出现显示图像的色偏问题。以及，在发光功能层13发出的光线照射到阳极11上，由阳极11将该光线反射，由于阳极11不平坦或具有的预倾角，反射的光线的路径长度不同，导致出射光线的显示亮度不均匀反射，出现显示图像的色偏问题。如图9A～图12所示，上述第一信号线93不会影响第三子像素P3对应的第三阳极113所在平面的水平效果，上述第一信号线93也不会影响第二子像素P2对应的第二阳极112所在平面的水平效果，从而避免第二阳极112和第三阳极113发生倾斜，从而影响发光效果。
如图11和图12所示，沿第二方向X，弯折部分932与直行部分931之间的垂直距离L1为1μm～10μm，其中，第二方向X与第一方向Y垂直。例如：弯折部分932与直行部分931之间的垂直距离L1为1μm、6μm或10μm。根据相邻两条第一信号线93之间的距离，以及，阳极正投影S的位置和面积，设置第一信号线93的弯折程度，保证每条第一信号线93能够与相应的子像素P的阳极11耦接，且降低制作工艺难度。
如图13～图17所示，在一些实施例中，多个阳极11中的至少一个在衬底1上的正投影S与至少一条第一信号线93在衬底1上的正投影有交叠，其中，至少一个阳极11在衬底1上的正投影S与一条第一信号线93在衬底1上的正投影有交叠，或者，至少一个阳极11在衬底1上的正投影S与多条第一信号线93在衬底1上的正投影有交叠。
如图13和图14所示，在一些实施例中，至少一个阳极11的正投影S与一条第一信号线93的正投影有交叠；所述第一信号线93的正投影与所述阳极11的正投影S沿第一方向Y的中线C重合。
示例的，在衬底1上的正投影与阳极11的正投影有交叠的至少一条第一信号线93中，该至少一条第一信号线93在衬底1上的正投影的位于阳极11的正投影之外的部分，与多个阳极11中与该阳极11相邻的其他阳极11在衬底1上的正投影无交叠。
示例性地，如图10D、图13和图14所示，以上述阳极11为第二阳极112，第一信号线93为第一数据线9311为例，上述至少一条第一数据线9311图13中为从左至右顺序的第一条第一数据线9311或者第三条第一数据线9311，第 一数据线9311的正投影与第二阳极112的正投影S沿第一方向Y的中线C重合，从而使得以该第二阳极112沿第一方向Y的中线C为对称轴，且该第二阳极112中相对于对称轴的对称位置处的高度大致相等。
如图13和图14所示，多个阳极11中与该第二阳极112相邻的其他阳极11为该第二阳极112周围的其他阳极，包括位于该第二阳极112沿第二方向上的两侧的其他类型的阳极，和位于该第二阳极112沿第一方向上的两侧的其他类型的阳极，例如位于其左侧的第一阳极列中的第一阳极和位于其右侧的第三阳极列中的第三阳极。
以至少一个阳极11为第二阳极12为例，至少一条第一信号线93在衬底1上的正投影与多个第二阳极112在衬底1上的正投影有交叠，则，这些第一信号线93与第一阳极111和第三阳极113在衬底1上的正投影均无交叠。例如，左侧第一条第一信号线93在衬底1上的正投影，与沿第一方向Y的多个第二阳极112在衬底1上的正投影交叠，且该第一信号线93的正投影与多个第二阳极112的正投影S沿第一方向Y的中线C重合，此时，该第一信号线93的正投影与多个第二阳极112左侧的多个第一阳极111的正投影无交叠，同时，该第一信号线93的正投影与多个第二阳极112右侧的多个第三阳极113的正投影无交叠。
在一些实施例中，所述第一数据线9311的正投影与所述一个第二阳极列所包括的各第二阳极112的正投影S沿第一方向Y的中线C重合，从而使得以该第二阳极列沿第一方向Y的中线C为对称轴，该第二阳极列所包括的各第二阳极112中相对于对称轴的对称位置处的高度大致相等。如图3中的左侧的阳极11所示，第二阳极列的左侧的位置M的高度H1与其右侧的位置N的高度H2大致相等，第二阳极列所在平面是水平的。由此，对应第二阳极112的正投影S的部分第一平坦层10的表面的平整度是关于阳极正投影S的中轴线对称的，该部分第一平坦层10的表面趋近水平，不会产生较大的倾斜，避免产生显示图像色偏的问题。
如图13～图17所示，在又一些实施例中，至少一个阳极11的正投影与多条第一信号线93的正投影有交叠，所述多条第一信号线93经过阳极11的部分相对于所述阳极11沿第一方向Y的中线C对称设置。例如，该多条第一信号线93的数量为两条。
在一些示例中，如图15所示，至少一个阳极11的正投影S与两条第一信号线93在衬底1上的正投影有交叠，两条第一信号线93为相邻的第一阳极列、第二阳极列和第三阳极列所对应的第一数据线9311和第二数据线9312。
如图10A所示，以上述阳极11为第一阳极111为例，该第一数据线9311和第二数据线9312经过第一阳极111的部分相对于所述第一阳极111沿第一方向Y的中线C对称设置。从而使得以该第一阳极111沿第一方向Y的中线C为对称轴，该第一阳极111中对称位置处的高度大致相等。
如图10B所示，以上述阳极11为第二阳极112为例，该第一数据线9311和第二数据线9312经过第二阳极112的部分相对于所述第二阳极112沿第一方向Y的中线C对称设置。从而使得以该第二阳极112沿第一方向Y的中线C为对称轴，该第二阳极112中对称位置处的高度大致相等。
如图10C所示，以上述阳极11为第三阳极113为例，该第一数据线9311和第二数据线9312经过第三阳极113的部分相对于所述第三阳极113沿第一方向Y的中线C对称设置。从而使得以该第三阳极113沿第一方向Y的中线C为对称轴，该第三阳极113中对称位置处的高度大致相等。
示例性地，请继续参阅图15，第一数据线9311和第二数据线9312的正投影与一个第三阳极列所包括的各第三阳极113的正投影有交叠，且第一数据线9311和第二数据线9312经过每个第三阳极113的部分相对于第三阳极113沿第一方向Y的中线C对称设置。从而使得以该第三阳极列沿第一方向Y的中线C为对称轴，该第二阳极列所包括的各第三阳极113中对称位置处的高度大致相等。
在又一些示例中，如图16所示，以上述阳极11为第三阳极113为例，上述两条第一信号线93为从左至右顺序的第一条第一数据线9311和第二条第二数据线9312，第一数据线9311的正投影和第二条第二数据线9312的正投影与第三阳极113的正投影沿第一方向Y的中线C对称设置。并且，第二数据线9312的正投影与其相邻的第一阳极111的正投影S无交叠。且，第一数据线9311的正投影与其相邻的第二阳极112的正投影S无交叠。
示例性地，请继续参阅图16，以上述阳极11为第三阳极113为例，上述两条第一信号线93为从左至右顺序的第一条第一数据线9311和第二条第二数据线9312，第一数据线9311的正投影和第二条第二数据线9312的正投影与第三阳极113的正投影沿第一方向Y的中线C对称设置。并且，第一条第一数据线9311的正投影与其相邻的第二阳极112的正投影无交叠。示例性地，如图10C和图16所示，第二阳极112的形状为六边形，则第一数据线9311的弯折部分932的第一段932a、第二段932b和第三段932c的延伸方向也与六边形边形的右侧两条边界契合，以避开第二阳极112的正投影S，这样就保证了第二阳极112与第一数据线9311不会发生交叠。第二条第二数据线9312 的正投影与其相邻的第一阳极111的正投影S无交叠。
在又一些实施例中，如图17所示，第二数据线9312的正投影与其相邻的第一阳极111的正投影S无交叠。且，第一数据线9311的正投影与其相邻的第二阳极112有交叠，第一数据线9311的正投影的交叠部分与第二阳极112的正投影沿第一方向Y的中线C重合。
示例性地，请继续参阅图17，以上述阳极11为第三阳极113为例，上述两条第一信号线93为从左至右顺序的第一条第一数据线9311和第二条第二数据线9312，第一数据线9311的正投影和第二条第二数据线9312的正投影与第三阳极113的正投影沿第一方向Y的中线C对称设置。并且，第一数据线9311的正投影与其相邻的第二阳极112有交叠，第一数据线9311的正投影的交叠部分与第二阳极112的正投影沿第一方向Y的中线C重合。第二数据线9312的正投影与其相邻的第一阳极111的正投影S无交叠。
从而，对应阳极正投影S的部分第一平坦层10的表面所在平面是水平的，避免位于第一平坦层10上的多个阳极11有预倾角或者不平坦，导致显示图像出现色偏问题。
可以理解的是，多条第一信号线93中的一条也可以沿第一方向Y延伸，且第一信号线93在衬底1上的正投影与阳极正投影S无交叠。上述多条第一信号线93中的每条的延伸情况可以为上述实施例中的任意一种或组合。只要保证多个阳极11所在平面是水平的即可。
上述实施例中，如图11～图17所示，沿第二方向X，相邻两条第一信号线93之间的距离L2的取值范围为5μm～30μm。例如，无论第一信号线93的直行部分931或弯折部分932，相邻两条信号线93之间的距离为5μm、15μm或30μm，以保证第一信号线93信号传输的有效工作，避免信号干扰。
在一些实施例中，如图7C和图26所示，每个像素电路200至少包括补偿晶体管T2、驱动晶体管T3以及电容器01。
如图18和图26所示，补偿晶体管T2的第一极区T21与驱动晶体管T3的第二极区T32电连接。如图21所示，补偿晶体管T2的第二极区T22与驱动晶体管T3的栅极(T3的沟道区T33与电容器01的第一极板011交叠部分)通过连接结构92’电连接。示例性地，连接结构92’位于第二导电层9’，连接结构92’的一端通过第一过孔与补偿晶体管T2的第二极区T22电连接，第一过孔贯穿至半导体层3，连接结构92’的另一端通过第二过孔与驱动晶体管T3的栅极(T3的沟道区T33与电容器01的第一极板011交叠部分)电连接，第二过孔贯穿至第一栅金属层5。
示例性地，如图24和图25所示，每个第二阳极112在衬底1上的正投影，与相邻两个像素电路200的连接结构92’在衬底1上的正投影有重叠(请参见图24中虚线椭圆圈的位置)，且所述相邻两个像素电路200中的其中一者为与所述第二阳极112电连接的第二像素电路202，另一者为与所述第二像素电路相邻的第三像素电路203。如图7C所示，连接结构92’对应等效电路图中的第一节点N1，通过将第二阳极112的形状做外扩设置，使其遮挡相邻两个像素电路200的连接结构92’，能够稳定第一节点N1的电压。
在一些实施例中，如图24～图26所示，每条数据线与其所电连接的像素电路列中各像素电路200的电容器01的第二极板012有交叠。示例性地，如图25和图26所示，第一数据线9311与第一像素电路列210电连接，第一像素电路列210包括多个第一像素电路201和多个第二像素电路202，第一数据线9311与第一像素电路201中的电容器01的第二极板012有交叠；且，与第二像素电路202中的电容器01的第二极板012有交叠(参见图24和图26中的虚线三角形区域)。第二数据线9312与第二像素电路列220电连接，第二数据线9312与第二像素电路202中的电容器01的第二极板012有交叠(参见图24和图26中的虚线三角形区域)。
由于电容器01的第二极板012与多条电压信号线信号线电连接，接收恒定的电压信号，将数据线的电容器01的第二极板012交叠设置，能够稳定数据线所传输的数据信号，避免数据信号受到其他因素干扰造成波动。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板，包括：
    衬底；
    设置于所述衬底一侧的第一导电层；所述第一导电层包括多条沿第一方向延伸的第一信号线；
    设置于所述第一导电层远离所述衬底一侧的第一平坦层；
    设置于所述第一平坦层远离所述衬底一侧的多个阳极；
    其中，所述第一导电层为所述衬底和所述多个阳极之间最靠近所述多个阳极的导电层；且，
    所述多个阳极中的至少一个在所述衬底上的正投影，与每条第一信号线在所述衬底上的正投影无交叠；和/或，
    所述多个阳极中的至少一个在所述衬底上的正投影与至少一条第一信号线在所述衬底上的正投影有交叠；正投影相交叠的阳极和至少一条第一信号线中，所述至少一条第一信号线经过所述阳极的设定位置，使得以所述阳极沿第一方向的中线为对称轴，所述阳极中对称位置处的高度大致相等。
  2. 根据权利要求1所述的显示基板，其中，在所述多个阳极中的至少一个在所述衬底上的正投影，与每条第一信号线在所述衬底上的正投影无交叠的情况下，至少一条第一信号线包括至少一个直行部分和至少一个弯折部分；各直行部分和各弯折部分交替设置；
    所述直行部分沿所述第一方向延伸，且所述直行部分在所述衬底上的正投影位于所述阳极的正投影沿所述第一方向上的一侧；
    所述弯折部分包括依次连接的第一段、第二段和第三段，所述第二段沿所述第一方向延伸，且所述第二段在所述衬底上的正投影位于所述阳极的正投影沿第二方向上的一侧，以避开所述阳极的正投影，所述第一段连接相邻的直行部分，所述第三段连接相邻的直行部分；
    其中，所述第二方向与所述第一方向垂直。
  3. 根据权利要求2中所述的显示基板，其中，沿第二方向，每条第一信号线的所述弯折部分的第二段与所述直行部分之间的距离为1μm～10μm。
  4. 根据权利要求1所述的显示基板，其中，在所述多个阳极中的至少一个在所述衬底上的正投影与至少一条第一信号线在所述衬底上的正投影有交叠的情况下，
    所述阳极的正投影与一条第一信号线的正投影有交叠；所述第一信号线的正投影与所述阳极的正投影沿第一方向的中线重合；或者，
    所述阳极的正投影与多条第一信号线的正投影有交叠；所述多条第一信号线经过所述阳极的部分相对于所述阳极沿所述第一方向的中线对称设置。
  5. 根据权利要求4所述的显示基板，其中，在所述衬底上的正投影与所述阳极的正投影有交叠的至少一条第一信号线中，
    所述第一信号线在所述衬底上的正投影的位于所述阳极的正投影之外的部分，与所述多个阳极中的与所述阳极相邻的其他阳极在所述衬底上的正投影无交叠。
  6. 根据权利要求1～5中任一项所述的显示基板，其中，沿第二方向，相邻两条第一信号线之间的距离为5μm～30μm，其中，所述第二方向与所述第一方向垂直。
  7. 根据权利要求1～6中任一项所述的显示基板，其中，所述第一导电层包括多条数据线，所述多条第一信号线为所述多条数据线；
    所述显示基板还包括第二导电层和第二平坦层；
    所述第二平坦层设置于所述第一导电层远离所述第一平坦层的一侧；
    所述第二导电层设置于所述第二平坦层远离所述第一导电层的一侧；
    所述第二导电层包括多条电压信号线。
  8. 根据权利要求1～6中任一项所述的显示基板，其中，所述第一导电层包括多条数据线和多条电压信号线；
    所述多条第一信号线为所述多条数据线和所述多条电压信号线。
  9. 根据权利要求7所述的显示基板，其中，所述显示基板包括多个像素电路，每个像素电路包括至少两个薄膜晶体管以及至少一个电容器；所述多个像素电路包括多个第一像素电路、多个第二像素电路和多个第三像素电路，所述多个像素电路排列成多个像素电路列，所述多个像素电路列包括多个第一像素电路列和多个第二像素电路列，每个第一像素电路列包括沿所述第一方向排成一列且交替设置的多个第一像素电路和多个第二像素电路，每个第二像素电路列包括沿所述第一方向排成一列的多个第三像素电路；沿第二方向，所述第一像素电路列和所述第二像素电路列交替设置；
    所述多个阳极包括多个第一阳极、多个第二阳极和多个第三阳极，所述多个阳极排列成多个阳极列，所述多个阳极列包括多个第一阳极列、多个第二阳极列和多个第三阳极列；
    每个第一阳极列包括沿所述第一方向排成一列的多个第一阳极，每个第二阳极列包括沿所述第一方向排成一列的多个第二阳极，每个第三阳极列包括沿所述第一方向排成一列的多个第三阳极；
    沿所述第二方向，按照所述第一阳极列、所述第二阳极列和所述第三阳极列的次序循环设置；
    所述第一像素电路列中，每个第一像素电路与一个第一阳极电连接，每个第二像素电路与一个第二阳极电连接；所述第一像素电路列所对应的各第一阳极和各第二阳极分别属于相邻的第一阳极列和第二阳极列；所述第二像素电路列中，每个第三像素电路与一个第三阳极电连接；所述第二像素电路列所对应的各第三阳极属于同一第三阳极列；
    所述第二方向与所述第一方向垂直。
  10. 根据权利要求9所示的显示基板，其中，在所述多条第一信号线为所述多条数据线的情况下，所述多条数据线包括多条第一数据线和多条第二数据线；
    每条第一数据线与一个第一像素电路列中的各第一像素电路和各第二像素电路电连接，以与所述第一像素电路列所对应的第一阳极列所包括的各第一阳极和第二阳极列所包括的各第二阳极电连接；
    每条第二数据线与一个第二像素电路列中的各第三像素电路电连接，以与所述第二像素电路列所对应的第三阳极列所包括的各第三阳极电连接。
  11. 根据权利要求10所示的显示基板，其中，每条数据线具有与像素电路列中多个像素电路对应电连接的多个连接部；
    所述第一数据线上，对应连接所述第二像素电路的连接部，被所述第二像素电路所电连接的第二阳极覆盖；
    所述第二数据线上，对应连接相邻两个第三像素电路的两个连接部分别位于所述第二数据线的两侧。
  12. 根据权利要求10所示的显示基板，其中，在所述多个阳极中的至少一个在所述衬底上的正投影，与每条第一信号线在所述衬底上的正投影无交叠，至少一条第一信号线包括至少一个直行部分和至少一个弯折部分的情况下，
    所述第一信号线包括所述第一数据线，所述第一数据线包括多个直行部分和多个弯折部分，所述第一数据线位于相邻的所述第一阳极列和所述第二阳极列之间；所述第一数据线的每个直行部分的正投影，位于所述第一阳极列中的一个第一阳极的正投影沿第二方向上的一侧，且位于所述第二阳极列中的第二阳极的正投影沿所述第一方向上的一侧；所述第一数据线的每个弯折部分的第二段的正投影，位于所述第二阳极列中的一个第二阳极的正投影沿所述第二方向上的一侧，以避开所述第二阳极的正投影；
    和/或，
    所述第一信号线包括所述第二数据线，所述第二数据线包括多个直行部分和多个弯折部分，所述第二数据线位于相邻的所述第三阳极列和所述第一阳极列之间；所述第二数据线的每个直行部分的正投影，位于所述第一阳极列中的一个第一阳极的正投影沿第二方向上的一侧，且位于所述第三阳极列中的第三阳极的正投影沿所述第一方向上的一侧；所述第二数据线的每个弯折部分的第二段的正投影，位于所述第三阳极列中的一个第三阳极的正投影沿所述第二方向上的一侧，以避开所述第三阳极的正投影。
  13. 根据权利要求12所述的显示基板，其中，所述第三阳极列中的多个第三阳极中，每两个相邻的第三阳极分为一组，且沿第一方向，每组第三阳极中的两个第三阳极之间的间距，小于所述两个第三阳极与周围的其他第三阳极之间的间距；
    所述第二数据线的每个直行部分在所述衬底上的正投影，位于所述第三阳极列中的一组第三阳极在所述衬底上的正投影沿所述第一方向上的一侧；
    所述第二数据线的每个弯折部分的第二段在所述衬底上的正投影，位于所述一组第三阳极在所述衬底上的正投影沿所述第二方向上的一侧，以避开所述一组第三阳极在所述衬底上的正投影。
  14. 根据权利要求10所示的显示基板，其中，在所述阳极的正投影与一条第一信号线的正投影有交叠的情况下，所述第一信号线为所述第一数据线；
    所述第一数据线的正投影与所述一个第二阳极列所包括的各第二阳极的正投影沿第一方向的中线重合。
  15. 根据权利要求10所示的显示基板，其中，在所述阳极的正投影与两条第一信号线的正投影有交叠的情况下，所述两条第一信号线为相邻的所述第一阳极列、所述第二阳极列和所述第三阳极列所对应的第一数据线和第二数据线；
    所述第一数据线和所述第二数据线的正投影与一个第三阳极列所包括的各第三阳极的正投影有交叠，且所述第一数据线和所述第二数据线经过每个第三阳极的部分相对于所述第三阳极沿所述第一方向的中线对称设置。
  16. 根据权利要求15所述的显示基板，其中，所述第二数据线的正投影与其相邻的第一阳极的正投影无交叠；
    所述第一数据线的正投影与其相邻的第二阳极的正投影无交叠；或者，所述第一数据线的正投影与其相邻的第二阳极列中各第二阳极有交叠，所述第一数据线的正投影的交叠部分与所述第二阳极列中各第二阳极的正投影沿 第一方向的中线重合。
  17. 根据权利要求10所述的显示基板，其中，所述显示基板还包括：
    设置在所述衬底上的缓冲层；
    设置在所述缓冲层远离所述衬底一侧的半导体层，所述半导体层包括多个半导体图案，每个半导体图案包括所述像素电路中多个晶体管的有源层；
    设置在所述半导体层远离所述衬底一侧的栅绝缘层；
    设置在所述栅绝缘层远离所述衬底一侧的第一栅金属层；所述第一栅金属层包括多个第一图案，每个第一图案为所述像素电路中电容器的第一极板；
    设置在所述第一栅金属层远离所述衬底一侧的第一绝缘层；
    设置在所述第一绝缘层远离所述衬底一侧的第二栅金属层；所述第二栅金属层包括多个第二图案，每个第二图案为所述像素电路中电容器的第二极板；
    设置在所述第二栅金属层远离所述衬底一侧的第二绝缘层；
    设置在所述多个阳极和所述第一平坦层远离所述衬底一侧的像素界定层，所述像素界定层限定出多个开口；每个开口暴露一个阳极的至少一部分；
    设置在所述多个阳极远离所述衬底一侧的多个发光功能层，每个发光功能层位于一个开口内；
    设置在所述发光功能层远离所述衬底一侧的阴极层，所述阴极层延伸至所述像素界定层远离所述衬底的一侧，且覆盖所述像素界定层。
  18. 根据权利要求10所述的显示基板，其中，每个像素电路至少包括补偿晶体管、驱动晶体管以及电容器；
    所述补偿晶体管的有源层包括第一极区、第二极区以及连接所述第一极区和所述第二极区的沟道区；
    所述驱动晶体管的有源层包括第一极区、第二极区以及连接所述第一极区和所述第二极区的沟道区；
    所述第一栅金属层中所述电容器的第一极板中与所述驱动晶体管的沟道区的交叠部分作为所述驱动晶体管的栅极；
    所述补偿晶体管的第一极区与所述驱动晶体管的第二极区电连接，所述补偿晶体管的第二极区与所述驱动晶体管的栅极通过连接结构电连接；
    每个第二阳极在所述衬底上的正投影，与相邻两个像素电路的连接结构在所述衬底上的正投影有重叠，且所述相邻两个像素电路中的其中一者为与所述第二阳极电连接的第二像素电路，另一者为与所述第二像素电路相邻的第三像素电路。
  19. 根据权利要求18所述的显示基板，其中，每条数据线与其所电连接的像素电路列中各像素电路的电容器的第二极板有交叠。
  20. 一种显示装置，包括：如权利要求1～19中任一项所述的显示基板。
PCT/CN2021/133740 2021-11-26 2021-11-26 显示基板及显示装置 WO2023092512A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180003638.9A CN116530234A (zh) 2021-11-26 2021-11-26 显示基板及显示装置
PCT/CN2021/133740 WO2023092512A1 (zh) 2021-11-26 2021-11-26 显示基板及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/133740 WO2023092512A1 (zh) 2021-11-26 2021-11-26 显示基板及显示装置

Publications (1)

Publication Number Publication Date
WO2023092512A1 true WO2023092512A1 (zh) 2023-06-01

Family

ID=86538721

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/133740 WO2023092512A1 (zh) 2021-11-26 2021-11-26 显示基板及显示装置

Country Status (2)

Country Link
CN (1) CN116530234A (zh)
WO (1) WO2023092512A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109037194A (zh) * 2018-08-03 2018-12-18 上海天马有机发光显示技术有限公司 一种显示面板及其显示装置
CN112670325A (zh) * 2020-12-23 2021-04-16 湖北长江新型显示产业创新中心有限公司 显示面板及显示装置
CN112750872A (zh) * 2019-10-29 2021-05-04 三星显示有限公司 有机发光显示设备
CN113078196A (zh) * 2021-03-26 2021-07-06 昆山国显光电有限公司 显示面板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109037194A (zh) * 2018-08-03 2018-12-18 上海天马有机发光显示技术有限公司 一种显示面板及其显示装置
CN112750872A (zh) * 2019-10-29 2021-05-04 三星显示有限公司 有机发光显示设备
CN112670325A (zh) * 2020-12-23 2021-04-16 湖北长江新型显示产业创新中心有限公司 显示面板及显示装置
CN113078196A (zh) * 2021-03-26 2021-07-06 昆山国显光电有限公司 显示面板

Also Published As

Publication number Publication date
CN116530234A (zh) 2023-08-01

Similar Documents

Publication Publication Date Title
US11069302B2 (en) Display apparatus having extended connecting lines
JP2022518075A (ja) ディスプレイパネル及びその製造方法、表示装置
KR20210015929A (ko) 디스플레이 기판 및 디스플레이 디바이스
EP4068260A1 (en) Display substrate and display device
EP4068374A1 (en) Display substrate and display device
WO2022001435A1 (zh) 显示基板和显示装置
EP4095937A1 (en) Display substrate and display device
US10868103B2 (en) Wiring structure and manufacture method thereof, OLED array substrate and display device
WO2022001434A1 (zh) 显示面板和显示装置
CN113196494B (zh) 显示基板及其制备方法、显示装置
US20240179989A1 (en) Display substrate and display device
CN215266306U (zh) 显示面板及显示装置
US20230354660A1 (en) Display panel and display device
WO2021227186A1 (zh) 柔性显示屏
CN218160381U (zh) 显示基板和显示装置
WO2023092512A1 (zh) 显示基板及显示装置
CN113964138A (zh) 一种显示基板、显示面板及显示装置
US11972727B2 (en) Display substrate and display device
CN115424570A (zh) 像素电路及其驱动方法、显示基板和显示装置
US11997897B2 (en) Display substrate including connection line and power line surrounding display area, preparation method thereof, and display device
US20240237396A1 (en) Display substrate and display apparatus
KR20220030451A (ko) 표시 장치
WO2023060520A1 (zh) 显示面板及显示装置
WO2022232987A1 (zh) 显示基板及显示装置
WO2023000215A1 (zh) 显示基板及显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202180003638.9

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 17922263

Country of ref document: US