WO2023000215A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023000215A1
WO2023000215A1 PCT/CN2021/107671 CN2021107671W WO2023000215A1 WO 2023000215 A1 WO2023000215 A1 WO 2023000215A1 CN 2021107671 W CN2021107671 W CN 2021107671W WO 2023000215 A1 WO2023000215 A1 WO 2023000215A1
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WO
WIPO (PCT)
Prior art keywords
sub
pixel
transistor
electrically connected
line
Prior art date
Application number
PCT/CN2021/107671
Other languages
English (en)
French (fr)
Inventor
袁志东
李永谦
张大成
许静波
袁粲
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21950473.5A priority Critical patent/EP4300473A1/en
Priority to CN202180001936.4A priority patent/CN116157856A/zh
Priority to PCT/CN2021/107671 priority patent/WO2023000215A1/zh
Priority to US17/779,576 priority patent/US20240161691A1/en
Publication of WO2023000215A1 publication Critical patent/WO2023000215A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels

Definitions

  • This article relates to but not limited to the field of display technology, especially a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • At least one embodiment of the present disclosure provides a display substrate, including: a base substrate and a plurality of pixel unit groups.
  • the base substrate includes a display area.
  • a plurality of pixel unit groups are located in the display area.
  • At least one pixel unit group includes a plurality of sub-pixel groups, and at least one sub-pixel group includes a pixel circuit.
  • the pixel circuit includes: a first sub-pixel circuit, a second sub-pixel circuit and a light emission control sub-circuit, both of the first sub-pixel circuit and the second sub-pixel circuit are electrically connected to the light emission control sub-circuit.
  • the light emission control sub-circuit is configured to control a first light emitting element electrically connected to the first sub-pixel circuit to emit light, and to control a second light emitting element electrically connected to the second sub-pixel circuit to emit light.
  • the first sub-pixel circuit and the second sub-pixel circuit are substantially symmetrical about a center line of the pixel circuits of the sub-pixel group in the first direction.
  • the light emission control subcircuit of the pixel circuit is located between the first subpixel circuit and the second subpixel circuit.
  • the light emission control sub-circuit is electrically connected to a light emission control line, and the light emission control line extends along the second direction and is located between the first sub-pixel circuit and the second sub-pixel circuit; The second direction intersects the first direction.
  • the light emission control sub-circuit includes: a light emission control transistor; the control electrode of the light emission control transistor is electrically connected to the light emission control line, and the first electrode of the light emission control transistor is electrically connected to the first power line connected, the second pole of the light emission control transistor is electrically connected to the first sub-pixel circuit and the second sub-pixel circuit.
  • At least one sub-pixel group further includes: a first light-emitting element electrically connected to the first sub-pixel circuit, and a second light-emitting element electrically connected to the second sub-pixel circuit.
  • the first pole of the first light-emitting element is electrically connected to the first sub-pixel circuit
  • the first pole of the second light-emitting element is electrically connected to the second sub-pixel circuit. Both the second poles of the first light emitting element and the second light emitting element are electrically connected to the second power line.
  • the base substrate further includes: a frame area located around the display area.
  • the display area is provided with a plurality of first auxiliary power lines extending along the first direction, and at least one first auxiliary power line is connected to the second poles of the first light-emitting element and the second light-emitting element in the frame area. electrical connection.
  • At least one first auxiliary power supply line is located between adjacent sub-pixel groups within at least one pixel unit group.
  • the display area of the base substrate is further provided with a plurality of first power lines extending along the first direction. At least one first power supply line is located between adjacent pixel unit groups.
  • adjacent pixel unit groups share one first power supply line.
  • each sub-pixel group of at least one pixel unit group includes the pixel circuit, and the at least one pixel unit group is about a center line of a plurality of pixel circuits of the pixel unit group in the second direction Substantially symmetrically, the second direction intersects the first direction.
  • the display area of the base substrate is further provided with a plurality of sensing lines extending along the first direction. At least one sensing line is located between adjacent sub-pixel groups within the at least one pixel unit group.
  • a sensing line and a first auxiliary power supply line are arranged between adjacent sub-pixel groups in at least one pixel unit group;
  • the projection is located on one side of the orthographic projection of the first auxiliary power line on the base substrate.
  • one sensing line and two first auxiliary power supply lines are arranged between adjacent sub-pixel groups in at least one pixel unit group.
  • the orthographic projections of the two first auxiliary power lines on the base substrate are respectively located on two sides of the orthographic projection of the sensing line on the base substrate.
  • the auxiliary power line and the sensing line are of the same layer structure.
  • a first auxiliary power line, a sensing line, and a second auxiliary power line are arranged between adjacent sub-pixel groups in at least one pixel unit group; the second auxiliary power line extending along the first direction and electrically connected to the first power line.
  • the orthographic projection of the first auxiliary power line on the base substrate overlaps with the orthographic projection of the sensing line on the base substrate, and the second auxiliary power line is on the substrate
  • the orthographic projection on the substrate is on one side of the orthographic projection of the sensing line on the base substrate.
  • the first auxiliary power line in a plane perpendicular to the display substrate, is located on a side of the sensing line close to the base substrate.
  • the at least one pixel unit group includes: six sub-pixel groups sequentially arranged along the second direction, and the pixel circuits of the first sub-pixel group and the second sub-pixel group are related to the first The pixel circuits of the first and second sub-pixel groups are approximately symmetrical to the center line in the second direction, and the second direction intersects with the first direction.
  • the display area of the base substrate is further provided with a plurality of data lines extending along the first direction. Two data lines are arranged between the pixel circuits of the first sub-pixel group and the second sub-pixel group, and a data line is arranged between the pixel circuits of the second sub-pixel group and the third sub-pixel group Wire.
  • the first sub-pixel circuit includes: a first transistor, a second transistor, a third transistor, and a first storage capacitor.
  • the control electrode of the first transistor is electrically connected to the ith first scanning line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the third transistor.
  • the control pole is electrically connected.
  • the control electrode of the second transistor is electrically connected to the i-th second scanning line, the first electrode of the second transistor is electrically connected to the sensing line, and the second electrode of the second transistor is electrically connected to the third transistor.
  • the second pole is electrically connected.
  • the first pole of the third transistor is electrically connected to the light emission control sub-circuit.
  • the first electrode of the first storage capacitor is electrically connected to the control electrode of the third transistor, and the second electrode of the first storage capacitor is electrically connected to the second electrode of the third transistor.
  • the second pole of the third transistor is electrically connected to the first pole of the first light emitting element.
  • the second sub-pixel circuit includes: a fourth transistor, a fifth transistor, a sixth transistor and a second storage capacitor.
  • the control electrode of the fourth transistor is electrically connected to the (i+1)th first scanning line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the The control electrode of the sixth transistor is electrically connected.
  • the control electrode of the fifth transistor is electrically connected to the (i+1)th second scanning line, the first electrode of the fifth transistor is electrically connected to the sensing line, and the second electrode of the fifth transistor is electrically connected to the second scanning line.
  • the second pole of the sixth transistor is electrically connected.
  • the first pole of the sixth transistor is electrically connected to the light emission control sub-circuit.
  • the first electrode of the second storage capacitor is electrically connected to the control electrode of the sixth transistor, and the second electrode of the second storage capacitor is electrically connected to the second electrode of the sixth transistor.
  • the second pole of the sixth transistor is electrically connected to the first pole of the second light emitting element.
  • i is a natural number.
  • the display substrate in a plane perpendicular to the display substrate, includes: a first conductive layer, a semiconductor layer, a second conductive layer and a third conductive layer disposed on the base substrate. layer.
  • the first conductive layer at least includes: a second pole of the first storage capacitor and a second pole of the second storage capacitor of the pixel circuit.
  • the semiconductor layer at least includes: an active layer of a plurality of transistors of the pixel circuit, a first pole of the first storage capacitor, and a second pole of the second storage capacitor.
  • the second conductive layer at least includes: control electrodes of a plurality of transistors of the pixel circuit, the first scanning line, the second scanning line, and the light emission control line.
  • the third conductive layer at least includes: the data lines and the sensing lines.
  • the first auxiliary power line electrically connected to the second electrodes of the first light-emitting element and the second light-emitting element is located on the first conductive layer or the third conductive layer.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned display substrate.
  • FIG. 1 is a schematic structural view of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of a display substrate of at least one embodiment of the present disclosure
  • FIG. 3 is an equivalent circuit diagram of a pixel circuit of a sub-pixel group in at least one embodiment of the present disclosure
  • FIG. 4 is a working timing diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 5 is a top view of a pixel circuit of a sub-pixel group according to at least one embodiment of the present disclosure
  • Fig. 6 is a partial cross-sectional schematic diagram along the Q-Q' direction in Fig. 5;
  • FIG. 7 is a top view of a pixel circuit of a pixel unit group according to at least one embodiment of the present disclosure.
  • FIG. 8 is a top view of a pixel circuit of a pixel unit group after forming a first conductive layer according to at least one embodiment of the present disclosure
  • FIG. 9 is a top view of a pixel circuit of a pixel unit group after forming a semiconductor layer according to at least one embodiment of the present disclosure.
  • FIG. 10 is a top view of a pixel circuit of a pixel unit group after forming a second conductive layer according to at least one embodiment of the present disclosure
  • FIG. 11 is a top view of a pixel circuit of a pixel unit group after forming a third insulating layer according to at least one embodiment of the present disclosure
  • FIG. 12 is a top view of a pixel circuit of a pixel unit group after forming a third conductive layer according to at least one embodiment of the present disclosure
  • FIG. 13 is a top view of pixel circuits of multiple pixel unit groups according to at least one embodiment of the present disclosure
  • Fig. 14 is a schematic diagram of the arrangement of the first auxiliary power line according to at least one embodiment of the present disclosure.
  • FIG. 15 is another top view of a pixel circuit of a pixel unit group according to at least one embodiment of the present disclosure.
  • 16 is another top view of a pixel circuit of a pixel unit group according to at least one embodiment of the present disclosure
  • 17 is another top view of a pixel circuit of a pixel unit group according to at least one embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate (gate electrode), a drain, and a source.
  • a transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain and the second electrode may be the source, or the first electrode may be the source and the second electrode may be the drain.
  • the gate may also be referred to as a control electrode. In cases where transistors with opposite polarities are used, or when the direction of current changes during circuit operation, the functions of "source” and “drain” may be interchanged. Therefore, in this specification, “source” and “drain” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° to 10°, and therefore includes a state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • An embodiment of the present disclosure provides a display substrate, including: a base substrate and a plurality of pixel unit groups.
  • the base substrate includes a display area, and a plurality of pixel unit groups are located in the display area.
  • At least one pixel unit group includes a plurality of sub-pixel groups, and at least one sub-pixel group includes a pixel circuit.
  • the pixel circuit of at least one sub-pixel group includes: a first sub-pixel circuit, a second sub-pixel circuit and a light emission control sub-circuit. Both the first sub-pixel circuit and the second sub-pixel circuit are electrically connected to the light emission control sub-circuit.
  • the light emission control subcircuit is configured to control the first light emitting element electrically connected to the first subpixel circuit, and to control the second light emitting element electrically connected to the second subpixel circuit to emit light.
  • the first sub-pixel circuit and the second sub-pixel circuit are substantially symmetrical about a center line of the pixel circuits of the sub-pixel group in the first direction.
  • the display substrate provided in this embodiment can realize high gray scale and improve the display effect by arranging the light emission control sub-circuit in the pixel circuit; moreover, by arranging the first sub-pixel circuit and the second sub-pixel circuit
  • the center line in one direction is roughly symmetrical, which can optimize the space and increase the resolution without affecting the normal display.
  • the light emission control subcircuit of the pixel circuit in the first direction, is located between the first subpixel circuit and the second subpixel circuit.
  • the first sub-pixel circuit, the light emission control sub-circuit and the second sub-pixel circuit of the pixel circuit may be sequentially arranged along the first direction.
  • the first direction and the second direction intersect, eg, are perpendicular to each other.
  • the first direction is parallel to the sub-pixel column direction
  • the second direction is parallel to the sub-pixel row direction.
  • this embodiment does not limit it.
  • the lighting control sub-circuit is electrically connected to the lighting control line.
  • the light emission control line extends along a second direction crossing the first direction, and is located between the first sub-pixel circuit and the second sub-pixel circuit.
  • the light emission control subcircuit includes: a light emission control transistor.
  • the control pole of the light emission control transistor is electrically connected to the light emission control line
  • the first pole of the light emission control transistor is electrically connected to the first power supply line
  • the second pole of the light emission control transistor is electrically connected to the first sub-pixel circuit and the second sub-pixel circuit.
  • this embodiment does not limit it.
  • At least one sub-pixel group further includes: a first light-emitting element electrically connected to the first sub-pixel circuit, and a second light-emitting element electrically connected to the second sub-pixel circuit.
  • the first electrode of the first light-emitting element is electrically connected to the first sub-pixel circuit
  • the first electrode of the second light-emitting element is electrically connected to the second sub-pixel circuit. Both the second poles of the first light-emitting element and the second light-emitting element are electrically connected to the second power line.
  • the base substrate also includes: a frame area located around the display area.
  • the display area is provided with a plurality of first auxiliary power lines extending along the first direction, and at least one first auxiliary power line is electrically connected to the second poles of the first light-emitting element and the second light-emitting element in the frame area.
  • first auxiliary power line by disposing the first auxiliary power line on the display substrate, the IR drop of the second power line can be reduced.
  • At least one first auxiliary power supply line is located between adjacent sub-pixel groups within at least one pixel unit group.
  • at least one pixel unit group includes six sub-pixel groups arranged along the second direction, and at least one first auxiliary power line may be located between the third sub-pixel group and the fourth sub-pixel group.
  • this embodiment does not limit it.
  • the display area of the base substrate is further provided with a plurality of first power lines extending along the first direction. At least one first power supply line is located between adjacent pixel unit groups.
  • this embodiment does not limit it.
  • adjacent pixel unit groups share one first power supply line.
  • a first power supply line may be provided between adjacent pixel unit groups, and the adjacent pixel unit groups are all electrically connected to the first power supply line.
  • this embodiment does not limit it.
  • two first power lines may be arranged between adjacent pixel unit groups, and one first power line is electrically connected to one pixel unit group.
  • each sub-pixel group of at least one pixel unit group includes the pixel circuit, and at least one pixel unit group is substantially symmetrical about the center line of the plurality of pixel circuits of the pixel unit group in the second direction. . Wherein, the second direction intersects with the first direction. However, this embodiment does not limit it.
  • the display area of the base substrate is further provided with a plurality of sensing lines extending along the first direction. At least one sensing line is located between adjacent sub-pixel groups within at least one pixel unit group.
  • the pixel unit group includes six sub-pixel groups arranged along the second direction, one sensing line may be located between the third sub-pixel group and the fourth sub-pixel group, and the pixels of the six sub-pixel groups
  • the circuits are all electrically connected with the sensing line. However, this embodiment does not limit it.
  • two sensing lines may be provided between the third sub-pixel group and the fourth sub-pixel group included in the pixel unit group, and the pixel circuits of the first to third sub-pixel groups may be electrically connected to one of the sensing lines.
  • the pixel circuits of the fourth to sixth sub-pixel groups may be electrically connected to another sensing line.
  • a sensing line and a first auxiliary power supply line are disposed between adjacent sub-pixel groups in at least one pixel unit group.
  • the orthographic projection of the sensing line on the base substrate is located at one side of the orthographic projection of the first auxiliary power line on the base substrate.
  • the orthographic projection of the sensing line on the base substrate may not overlap with the orthographic projection of the first auxiliary power line on the base substrate.
  • the first auxiliary power line and the sensing line may have the same layer structure. However, this embodiment does not limit it.
  • one sensing line and two first auxiliary power supply lines are arranged between adjacent sub-pixel groups in at least one pixel unit group.
  • Orthographic projections of the two first auxiliary power lines on the base substrate are respectively located on two sides of the orthographic projection of the sensing line on the base substrate.
  • the orthographic projections of the sensing lines on the base substrate may not overlap with the orthographic projections of the two first auxiliary power lines on the base substrate.
  • the first auxiliary power line and the sensing line may have the same layer structure. However, this embodiment does not limit it.
  • a first auxiliary power line, a sensing line and a second auxiliary power line may be disposed between adjacent sub-pixel groups in at least one pixel unit group.
  • the second auxiliary power line extends along the first direction and is electrically connected with the first power line.
  • the orthographic projection of the first auxiliary power line on the substrate overlaps with the orthographic projection of the sensing line on the substrate, and the orthographic projection of the second auxiliary power line on the substrate is located at the position of the sensing line on the substrate.
  • the orthographic projection of the second auxiliary power line on the base substrate may not overlap with the orthographic projections of the sensing line and the first auxiliary power line on the base substrate.
  • the second auxiliary power line and the sensing line may have the same layer structure. However, this embodiment does not limit it.
  • the first auxiliary power line in a plane perpendicular to the display substrate, may be located on a side of the sensing line close to the base substrate.
  • At least one pixel unit group includes: six sub-pixel groups sequentially arranged along the second direction, and the pixel circuits of the first sub-pixel group and the second sub-pixel group are related to the first and second sub-pixel groups.
  • the pixel circuits of the second sub-pixel group are approximately symmetrical to the center line in the second direction, and the second direction intersects with the first direction.
  • this embodiment does not limit it.
  • the display area of the base substrate is further provided with a plurality of data lines extending along the first direction. Two data lines may be arranged between the pixel circuits of the first sub-pixel group and the second sub-pixel group, and one data line may be arranged between the pixel circuits of the second sub-pixel group and the third sub-pixel group.
  • this embodiment does not limit it.
  • the first sub-pixel circuit may include: a first transistor, a second transistor, a third transistor, and a first storage capacitor.
  • the control electrode of the first transistor is electrically connected to the ith first scanning line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor.
  • the control electrode of the second transistor is electrically connected to the i-th second scanning line, the first electrode of the second transistor is electrically connected to the sensing line, and the second electrode of the second transistor is electrically connected to the second electrode of the third transistor.
  • the first pole of the third transistor is electrically connected with the light emission control sub-circuit.
  • the first electrode of the first storage capacitor is electrically connected to the control electrode of the third transistor, and the second electrode of the first storage capacitor is electrically connected to the second electrode of the third transistor.
  • the second pole of the third transistor is electrically connected with the first pole of the first light emitting element.
  • the second sub-pixel circuit includes: a fourth transistor, a fifth transistor, a sixth transistor and a second storage capacitor.
  • the control electrode of the fourth transistor is electrically connected to the i+1 first scanning line, the first electrode of the fourth transistor is electrically connected to the data line, and the second electrode of the fourth transistor is electrically connected to the control electrode of the sixth transistor. .
  • the control electrode of the fifth transistor is electrically connected to the i+1th second scanning line, the first electrode of the fifth transistor is electrically connected to the sensing line, and the second electrode of the fifth transistor is electrically connected to the second electrode of the sixth transistor. electrical connection.
  • the first pole of the sixth transistor is electrically connected with the light emission control sub-circuit.
  • the first electrode of the second storage capacitor is electrically connected to the control electrode of the sixth transistor, and the second electrode of the second storage capacitor is electrically connected to the second electrode of the sixth transistor.
  • the second pole of the sixth transistor is electrically connected to the first pole of the second light emitting element.
  • i is a natural number.
  • the display substrate in a plane perpendicular to the display substrate, includes: a first conductive layer, a semiconductor layer, a second conductive layer and a third conductive layer disposed on the base substrate.
  • the first conductive layer at least includes: a second pole of the first storage capacitor and a second pole of the second storage capacitor of the pixel circuit.
  • the semiconductor layer at least includes: an active layer of multiple transistors of the pixel circuit, a first pole of the first storage capacitor, and a second pole of the second storage capacitor.
  • the second conductive layer at least includes: control electrodes of a plurality of transistors of the pixel circuit, a first scanning line, a second scanning line, and an emission control line.
  • the third conductive layer at least includes: data lines and sensing lines.
  • the first auxiliary power line electrically connected to the first light emitting element and the second electrode of the second light emitting element may be located on the first conductive layer or the third conductive layer.
  • this embodiment does not limit it.
  • the display substrate of this embodiment will be described below through some examples.
  • FIG. 1 is a schematic structural diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include: a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array.
  • the pixel array may include: a plurality of scan lines (eg, G(1) to G(m)), a plurality of data lines (eg, D(1) to D(n)), a plurality of emission control lines (eg, EM (1) to EM(m)) and multiple sub-pixel groups.
  • m and n are both natural numbers.
  • the timing controller may provide grayscale values and control signals suitable for the specification of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the
  • the scan driver can supply a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be supplied to the data lines D(1) to D(n) using gray values and control signals received from the timing controller, n may be a natural number.
  • the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data lines D(1) to D(n) in units of pixel rows.
  • the scan driver may generate scan signals to be supplied to the scan lines G(1) to G(m) by receiving a clock signal, a scan start signal, etc. from the timing controller, and m may be a natural number.
  • the scan driver may sequentially supply scan signals having turn-on level pulses to the scan lines G(1) to G(m).
  • the scan driver can be configured in the form of a shift register, and can generate scan signals in such a manner as to sequentially transmit scan start signals supplied in the form of on-level pulses to the next-stage circuit under the control of a clock signal .
  • the light emission driver may generate emission signals to be supplied to the light emission control lines EM( 1 ) to EM(m) by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission driver may sequentially supply emission signals having off-level pulses to the light emission control lines EM( 1 ) to EM(m).
  • the light emitting driver may be configured in the form of a shift register, and may generate light emitting signals in such a manner as to sequentially transmit light emitting stop signals provided in the form of off-level pulses to a next-stage circuit under the control of a clock signal.
  • the pixel array may include a plurality of pixel unit groups, and at least one pixel unit group may include a plurality of sub-pixel groups.
  • FIG. 2 is a schematic plan view of a display substrate according to at least one embodiment of the present disclosure.
  • the display substrate may include a plurality of pixel unit groups P arranged in a matrix, and at least one of the plurality of pixel unit groups P may include a plurality of sub-pixel groups.
  • At least one pixel unit group P includes six sub-pixel groups (for example, two first sub-pixel groups P1 , two second sub-pixel groups P2 and two third sub-pixel groups P3 ) arranged in sequence along the second direction.
  • At least one sub-pixel group includes: a pixel circuit, a first light emitting element and a second light emitting element.
  • the pixel circuit of at least one sub-pixel group includes: a first sub-pixel circuit, a light emission control sub-circuit and a second sub-pixel circuit sequentially arranged along the first direction; the first light-emitting element is electrically connected to the first sub-pixel circuit, The second light emitting element is electrically connected with the second sub-pixel circuit.
  • the first direction intersects with the second direction, for example, the first direction and the second direction are perpendicular to each other.
  • the first sub-pixel group P1 can emit light of the first color
  • the second sub-pixel group P2 can emit light of the second color
  • the third sub-pixel group P3 can emit light of the third color.
  • the first color light may be red light
  • the second color light may be green light
  • the third color light may be blue light.
  • this embodiment does not limit it.
  • two light emitting elements in the same sub-pixel group can emit light of the same or different colors.
  • the first subpixel circuit and the light emission control subcircuit are configured to receive the data voltage transmitted by the data line and output a corresponding current to the first light emitting element under the control of the scan line and the light emission control line.
  • the second sub-pixel circuit and the light-emitting control sub-circuit are configured to receive the data voltage transmitted by the data line and output a corresponding current to the second light-emitting element under the control of the scan line and the light-emitting control line.
  • the light emission control subcircuit is configured to control the first light emitting element electrically connected to the first subpixel circuit to emit light, and to control the second light emitting element electrically connected to the second subpixel circuit to emit light.
  • the first light-emitting element is configured to emit light with corresponding brightness in response to the current output by the first sub-pixel circuit
  • the second light-emitting element is configured to emit light with corresponding brightness in response to the current output by the second sub-pixel circuit.
  • at least one sub-pixel group may include two sub-pixels that share a light emission control sub-circuit, for example, one of the sub-pixels may include a first sub-pixel circuit and a first light-emitting element, and the other sub-pixel may include a second sub-pixel A pixel circuit and a second light emitting element.
  • this embodiment does not limit it.
  • one pixel unit in at least one pixel unit group P may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, or may include red sub-pixels,
  • the green sub-pixel, the blue sub-pixel and the white sub-pixel are not limited in this disclosure.
  • the shape of a sub-pixel in a pixel unit may be a rectangle, a rhombus, a pentagon or a hexagon.
  • the pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically or squarely.
  • the pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely. Disclosure is not limited here.
  • FIG. 3 is an equivalent circuit diagram of a pixel circuit of a sub-pixel group according to at least one embodiment of the present disclosure.
  • the pixel circuits of the sub-pixel group include: a first sub-pixel circuit 71 , a second sub-pixel circuit 72 and a light emission control sub-circuit 73 . Both the first sub-pixel circuit 71 and the second sub-pixel circuit 72 are electrically connected to the light emission control sub-circuit 73 .
  • the first sub-pixel circuit of the sub-pixel group is electrically connected to the scanning line in the i-th row
  • the second sub-pixel circuit is electrically connected to the scanning line in the i+1-th row as an example for illustration.
  • i is a natural number.
  • the first sub-pixel circuit 71 of the sub-pixel group includes: a first transistor T1 , a second transistor T2 , a third transistor T3 and a first storage capacitor Cst1 .
  • the first transistor T1 may be called a switching transistor
  • the second transistor T2 may be called a sensing compensation transistor
  • the third transistor T3 may be called a driving transistor.
  • the control electrode of the first transistor T1 is electrically connected to the first scanning line G1(i), the first electrode of the first transistor T1 is electrically connected to the data line D, and the first The second pole of the transistor T1 is electrically connected to the control pole of the third transistor T3.
  • the control electrode of the second transistor T2 is electrically connected to the second scan line G2(i), the first electrode of the second transistor T2 is electrically connected to the sensing line SE, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3. Diode electrical connection.
  • the first pole of the third transistor T3 is electrically connected to the light emission control sub-circuit 73 .
  • the first electrode of the first storage capacitor Cst1 is electrically connected to the control electrode of the third transistor T3, and the second electrode of the first storage capacitor Cst1 is electrically connected to the second electrode of the third transistor T3.
  • the first storage capacitor Cst1 is configured to store the potential of the gate electrode of the third transistor T3.
  • the first electrode of the first light emitting element EL is electrically connected to the second electrode of the third transistor T3, and the second electrode of the first light emitting element EL is electrically connected to the second power line PL2.
  • the first transistor T1 is configured to receive the data signal transmitted by the data line D under the control of the first scan line G1(i), and make the control electrode of the third transistor T3 receive the data signal .
  • the third transistor T3 is configured to generate a corresponding current at the second electrode by using the first power signal provided by the light emission control sub-circuit 73 under the control of the data signal received by the control electrode.
  • the first light emitting element EL is configured to emit light of corresponding brightness in response to the current generated by the second electrode of the third transistor T3.
  • the second transistor T2 is configured to extract the threshold voltage Vth and the mobility of the third transistor T3 in response to the compensation timing, so as to compensate the threshold voltage Vth.
  • the second sub-pixel circuit 72 of the sub-pixel group includes: a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 and a second storage capacitor Cst2 .
  • the fourth transistor T4 may be called a switching transistor
  • the fifth transistor T5 may be called a sensing compensation transistor
  • the sixth transistor T6 may be called a driving transistor.
  • the control electrode of the fourth transistor T4 is electrically connected to the first scanning line G1(i+1), and the first electrode of the fourth transistor T4 is electrically connected to the data line D,
  • the second pole of the fourth transistor T4 is electrically connected to the control pole of the sixth transistor T6.
  • the control electrode of the fifth transistor T5 is electrically connected to the second scanning line G2 (i+1), the first electrode of the fifth transistor T5 is electrically connected to the sensing line SE, and the second electrode of the fifth transistor T5 is electrically connected to the sixth transistor T6.
  • the second pole is electrically connected.
  • the first pole of the sixth transistor T6 is electrically connected to the light emission control sub-circuit 73 .
  • the first electrode of the second storage capacitor Cst2 is electrically connected to the control electrode of the sixth transistor T6, and the second electrode of the second storage capacitor Cst2 is electrically connected to the second electrode of the sixth transistor T6.
  • the first pole of the second light emitting element EL' is electrically connected to the second pole of the sixth transistor T6, and the second pole of the second light emitting element EL' is electrically connected to the second power line PL2.
  • the light emission control subcircuit 73 of the sub-pixel group may include: a light emission control transistor T7.
  • the control pole of the light emission control transistor T7 is electrically connected to the light emission control line EM(i)
  • the first pole of the light emission control transistor T7 is electrically connected to the first power supply line PL1
  • the second pole of the light emission control transistor T7 is connected to the first pole of the third transistor T3
  • One pole is electrically connected to the first pole of the sixth transistor T6.
  • the light emitting control transistor T7 is configured to transmit the first power signal provided by the first power line PL1 to the first pole of the third transistor T3 and the first pole of the sixth transistor T6 under the control of the light emitting control line EM(i).
  • both the first sub-pixel circuit and the second sub-pixel circuit in the sub-pixel group are electrically connected to the same light emission control sub-circuit. That is, adjacent subpixels in a subpixel group share one light emission control subcircuit.
  • the pixel circuit of this exemplary embodiment can realize high-gray-scale display by setting the light-emitting control sub-circuit, thereby improving the display effect.
  • the first power line PL1 may continuously provide a high-level signal
  • the second power line PL2 may continuously provide a low-level signal.
  • the first to sixth transistors T1 to T6 and the light emission control transistor T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield rate of the product.
  • the first transistor T1 to the sixth transistor T6 and the light emission control transistor T7 may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide thin film transistor is made of oxide (Oxide).
  • the low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current.
  • a low temperature polysilicon thin film transistor and an oxide thin film transistor can be integrated on a display substrate to form a low temperature polycrystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display substrate, and the advantages of both can be utilized, It can achieve high resolution (PPI, Pixel Per Inch), low frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • the first light emitting element EL and the second light emitting element EL' may be organic electroluminescent diodes (OLEDs).
  • the first light emitting element EL and the second light emitting element EL' may each include a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode).
  • FIG. 4 is a working timing diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • the working process of the pixel circuit of this embodiment will be described below by taking an example in which multiple transistors of the pixel circuit are all N-type transistors.
  • the working process of the pixel circuit in this embodiment includes: a display phase S1 and an idle phase S2.
  • the compensation operation for one row of sub-pixels can be completed, for example, the detection of the threshold voltage Vth and the mobility of the driving transistors of one row of sub-pixels can be completed, so that the detection can be used in the display phase
  • the received data is compensated by the data signal to complete the display.
  • the display phase may include a data writing phase and a light emitting phase.
  • the first scan line G1(i) and the second scan line G2(i) provide high-level signals, and the first transistor T1 and the second transistor T2 of the first sub-pixel circuit are turned on.
  • the first transistor T1 is turned on, and writes the data signal provided by the data line D into the control electrode of the third transistor T3, and charges the first storage capacitor Cst1.
  • the second transistor T2 is turned on, and provides the reset voltage provided by the sensing line SE to the first pole of the first light emitting element EL, and resets the first pole of the first light emitting element EL.
  • the light emission control line EM(i) provides a low level signal, and the light emission control transistor T7 is turned off. In this stage, the first light emitting element EL does not emit light.
  • the first scan line G1(i) and the second scan line G2(i) provide low-level signals, and the first transistor T1 and the second transistor T2 of the first sub-pixel circuit are turned off.
  • the light emission control line EM(i) provides a high level signal, and the light emission control transistor T7 is turned on.
  • the high level signal provided by the first power line PL1 is transmitted to the first electrode of the third transistor T3, and the third transistor T3 provides a driving current to the first light emitting element EL to drive the first light emitting element EL to emit light.
  • the control of the second sub-pixel circuit on the first scan line G1(i+1) and the second scan line G2(i+1) Write data below.
  • the emission control transistor T7 Under the control of the high-level signal of the emission control line EM(i), the emission control transistor T7 is turned on, so that the sixth transistor T6 of the second sub-pixel circuit provides a driving current to the second light emitting element EL' to drive the second The light emitting element EL' emits light.
  • the completion of the compensation operation of the first sub-pixel circuit in the idle phase S2 is taken as an example for illustration.
  • the first scan line G1(i) and the second scan line G2(i) provide a high-level signal
  • the first transistor T1 and the second transistor T2 of the first sub-pixel circuit are turned on
  • the data line D The provided test data voltage is written into the control electrode of the third transistor T3, the electrical signal at the second electrode of the third transistor T3 is read through the second transistor T2, and output through the sensing line SE, so that the external compensation circuit can output through the
  • the electric signal compensates the mobility of the third transistor T3.
  • the light emission control line EM(i) can continuously provide a high level signal
  • the light emission control transistor T7 is turned on, so that the third transistor T3 can generate a driving current.
  • a luminescence control transistor is electrically connected to the first sub-pixel circuit and the second sub-pixel circuit of the 3T1C structure, and the luminescence control transistor is controlled to be turned off during the data writing phase, so as to avoid the generation of the driving transistor during the data writing process.
  • Current to ensure that the driving current is provided to the light-emitting element during the light-emitting stage, which can achieve high gray scale and improve the display effect.
  • FIG. 5 is a top view of a pixel circuit of a sub-pixel group according to at least one embodiment of the present disclosure.
  • Fig. 6 is a schematic partial cross-sectional view along the Q-Q' direction in Fig. 5 .
  • the light emission control subcircuits of the subpixel groups are located in the first subpixel circuit and the second subpixel circuit. between.
  • the first sub-pixel circuit and the second sub-pixel circuit of the sub-pixel group are symmetrical about the center line OY in the first direction Y of the pixel circuits of the sub-pixel group.
  • the centerlines of the first scan lines G1(i) and G1(i+1) in the first direction Y coincide with the centerline OY.
  • the first direction Y crosses the second direction X, for example, the first direction Y is perpendicular to the second direction X.
  • the first direction Y is parallel to the sub-pixel row direction
  • the second direction X is parallel to the sub-pixel row direction.
  • this embodiment does not limit it.
  • the length of the pixel circuit of the sub-pixel group in the first direction Y may be less than 200 micrometers.
  • the above-mentioned length can be from the active layer 20 of the second transistor T2 of the first sub-pixel circuit of the sub-pixel group far away from the boundary of the second sub-pixel circuit to the active layer of the fifth transistor T5 of the second sub-pixel circuit far away from the first sub-pixel circuit The distance between the borders of the pixel circuits.
  • the present exemplary embodiment can optimize the space of the pixel circuit.
  • the second transistor T2 in the plane parallel to the display substrate, in the first direction Y, the second transistor T2, the third transistor T3 and the first sub-pixel circuit of the sub-pixel group
  • the first transistors T1 are arranged in sequence, and the first storage capacitor Cst1 is located between the second transistor T2 and the third transistor T3.
  • the fourth transistor T4, the sixth transistor T6, the second storage capacitor Cst2 and the fifth transistor T5 of the second sub-pixel circuit are sequentially arranged along the side away from the light emission control transistor T7.
  • the light emission control transistor T7 is located between the first transistor T1 and the fourth transistor T4 in the first direction Y.
  • the display substrate in a plane perpendicular to the display substrate, includes: a base substrate 60 , a first conductive layer disposed on the base substrate 60 , a semiconductor layer , the second conductive layer and the third conductive layer.
  • a first insulating layer 61 is arranged between the first conductive layer and the semiconductor layer
  • a second insulating layer 62 is arranged between the semiconductor layer and the second conductive layer
  • a third insulating layer is arranged between the second conductive layer and the third conductive layer.
  • Layer 63 In some examples, the first insulating layer 61 , the second insulating layer 62 and the third insulating layer 63 may be inorganic insulating layers.
  • a fourth insulating layer, a fifth insulating layer, an anode layer and a pixel definition layer may be sequentially disposed on the side of the second conductive layer away from the base substrate 60 .
  • the fourth insulating layer may be an inorganic insulating layer
  • the fifth insulating layer may be an organic insulating layer.
  • this embodiment does not limit it.
  • the first conductive layer at least includes: a second pole of the storage capacitor (eg, the second pole 52 of the first storage capacitor Cst1 ).
  • the semiconductor layer includes at least: active layers of a plurality of transistors (for example, the active layer 10 of the first transistor T1, the active layer 20 of the second transistor T2, the active layer 30 of the third transistor T3, and the active layer of the light emission control transistor T7 active layer 40), and the first pole of the storage capacitor (for example, the first pole 51 of the first storage capacitor Cst1).
  • the first conductive layer at least includes: control electrodes of a plurality of transistors (for example, the control electrode 13 of the first transistor T1, the control electrode 23 of the second transistor T2, the control electrode 33 of the third transistor T3 and the control electrode of the light emission control transistor T7 43), the first scan line (for example, the first scan line G1(i) and G1(i+1)), the second scan line (for example, the second scan line G2(i) and G2(i+1)) , and an emission control line (for example, an emission control line EM(i)).
  • the second conductive layer may include: a data line D, a first power line, a sensing line, and first and second poles of a plurality of transistors (for example, the first pole 11 and the second pole 12 of the first transistor T1, the second pole The second pole 22 of the second transistor T2, the first pole 31 and the second pole 32 of the third transistor T3, the second pole 42 of the light emission control transistor T7).
  • the active layer includes a channel region and first and second doped regions located on both sides of the channel region.
  • the channel region of the active layer has semiconductor characteristics, and the first doped region and the second doped region have conductivity.
  • the first doped region or the second doped region of the active layer may be interpreted as a source electrode or a drain electrode of a transistor.
  • the portion of the active layer between the transistors can be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors.
  • the material of the semiconductor layer may include metal oxides, such as IGZO. However, this embodiment does not limit it.
  • the material of the semiconductor layer may include polysilicon, for example.
  • the control electrode 13 of the first transistor T1 and the first scan line G1(i) may have an integral structure.
  • the first pole 11 of the first transistor T1 and the data line D may be integrally structured.
  • the first electrode 11 of the first transistor T1 is electrically connected to the first doped region of the active layer 10 of the first transistor T1 through the fifth via hole K5.
  • the second electrode 12 of the first transistor T1 is electrically connected to the second doped region of the active layer 10 of the first transistor T1 through the sixth via hole K6, and is also connected to the control electrode 33 of the third transistor T3 through the sixth via hole K6 electrical connection.
  • the third insulating layer 63 and the second insulating layer 62 in the fifth via hole K5 are etched away, exposing the surface of the semiconductor layer.
  • the third insulating layer 63 and the second insulating layer 62 in the half area of the sixth via hole K6 are etched away, exposing the surface of the semiconductor layer, and the third insulating layer 63 in the other half area is etched away, exposing the the surface of the second conductive layer.
  • the control electrode 23 of the second transistor T2 and the second scan line G2(i) may have an integrated structure.
  • the second pole 22 of the second transistor T2 is electrically connected to the second doped region of the active layer 20 of the second transistor T2 through the first via hole K1.
  • the control electrode 33 of the third transistor T3 is located between the first scanning line G1(i) and the second scanning line G2(i).
  • the first electrode 31 of the third transistor T3 is electrically connected to the first doped region of the active layer 30 of the third transistor T3 through the third via hole K3.
  • the second pole 32 of the third transistor and the second pole 22 of the second transistor T2 are integrally formed.
  • the second electrode 32 of the third transistor T3 is electrically connected to the second doped region of the active layer 30 of the third transistor T3 through the second via hole K2, and is also connected to the second electrode of the first storage capacitor Cst1 through the seventh via hole K7.
  • Pole 52 is electrically connected.
  • the third insulating layer 63 and the second insulating layer 62 in the first via hole K1 , the second via hole K2 and the third via hole K3 are etched away, exposing the surface of the semiconductor layer.
  • the third insulating layer 63 , the second insulating layer 62 and the first insulating layer 61 in the seventh via hole K7 are etched away, exposing the surface of the first conductive layer.
  • the control electrode 43 of the light emission control transistor T7 and the light emission control line EM(i) may have an integrated structure.
  • the second pole 42 of the light emission control transistor T7 is electrically connected to the second doped region of the active layer 40 of the light emission control transistor T7 through the fourth via hole K4.
  • the second pole 42 of the light emission control transistor T7, the first pole 31 of the third transistor T3, and the first pole of the sixth transistor T6 may have an integral structure.
  • the third insulating layer 63 and the second insulating layer 62 in the fourth via hole K4 are etched away, exposing the surface of the semiconductor layer.
  • the first electrode 51 of the first storage capacitor Cst1 and the active layer 10 of the first transistor T1 may have an integrated structure, and have an integrated structure with the active layer of the first transistor T1.
  • the second doped region of the source layer 10 is electrically connected.
  • the second pole 52 of the first storage capacitor Cst1 is electrically connected to the second pole 22 of the second transistor T2 and the second pole 32 of the third transistor T3.
  • the orthographic projection of the second pole 52 of the first storage capacitor Cst1 on the substrate 60 overlaps with the orthographic projection of the channel region of the active layer 30 of the third transistor T3 on the substrate 60 .
  • the second pole 52 of the first storage capacitor Cst1 can also be used as a light-shielding electrode to prevent the ambient light on the side of the base substrate 60 from affecting the driving transistor (ie, the third transistor T3 ).
  • this embodiment does not limit it.
  • the structure of the fourth transistor T4 is substantially symmetrical to that of the first transistor T1 about the center line OY
  • the structure of the fifth transistor T5 is substantially symmetrical to that of the second transistor T2 about the center line OY
  • the structure of the sixth transistor T2 is substantially symmetrical about the center line OY.
  • the structure of the transistor T6 and the structure of the third transistor T3 are approximately symmetrical about the central line OY
  • the structure of the second storage capacitor Cst2 and the structure of the first storage capacitor Cst1 are approximately symmetrical about the central line OY.
  • the structure of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the second storage capacitor Cst2 can refer to the structure of the first transistor T1, the second transistor T2, the third transistor T3 and the first storage capacitor Cst1, in This will not be repeated here.
  • FIG. 7 is a top view of a pixel circuit of a pixel unit group according to at least one embodiment of the present disclosure.
  • one pixel unit group includes: six sub-pixel groups (for example, the sub-pixel group of the jth column to the j+5th column of the sub-pixel group, wherein j is a positive integer).
  • Each sub-pixel group includes a first sub-pixel circuit, a light emission control sub-circuit and a second sub-pixel circuit sequentially arranged along the first direction Y.
  • FIG. 8 is a top view of a pixel circuit of a pixel unit group after forming a first conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 9 is a top view of a pixel circuit of a pixel unit group after forming a semiconductor layer according to at least one embodiment of the present disclosure.
  • FIG. 10 is a top view of a pixel circuit of a pixel unit group after forming a second conductive layer according to at least one embodiment of the present disclosure.
  • FIG. 11 is a top view of a pixel circuit of a pixel unit group after forming a third insulating layer according to at least one embodiment of the present disclosure.
  • FIG. 12 is a top view of a pixel circuit of a pixel unit group after forming a third conductive layer according to at least one embodiment of the present disclosure.
  • the first scan lines G1(i) and G1(i+1), the second scan lines G2(i) and G2( i+1) and the light emission control line EM(i) both extend along the second direction X.
  • the emission control line EM(i) is located between the first scan line G1(i) and the first scan line G1(i+1).
  • the plurality of data lines, the two first power lines PL1a and PL1b, the sensing line SE, and the first auxiliary power line FL all extend in the first direction Y.
  • the first power line PL1a In the second direction X, according to the first power line PL1a, three data lines (for example, data lines D(j), D(j+1), D(j+2)), the sensing line SE, the first auxiliary The power line FL, three data lines (for example, data lines D(j+3), D(j+4), D(j+5)) and the first power line PL1b are arranged in sequence.
  • this embodiment does not limit it.
  • the first pixel circuits and the second pixel circuits of the plurality of sub-pixel groups in the pixel unit group are on the same plane as the pixel circuits of the sub-pixel groups.
  • the center lines OY in the first direction Y are symmetrical to each other.
  • the pixel circuits of the pixel unit group are symmetrical to each other with respect to the center line OX of the pixel circuits of the pixel unit group in the second direction X.
  • this embodiment does not limit it.
  • a first power line is arranged on both sides of the pixel unit group, for example, the first power line PL1a is arranged on the left side, and the first power line PL1a is arranged on the right side.
  • Power line PL1b is located between adjacent pixel unit groups.
  • the first power lines PL1a and PL1b extend along the first direction Y and are sequentially arranged along the second direction X.
  • this embodiment does not limit it.
  • one sensing line SE and one first auxiliary power supply line FL are disposed between adjacent sub-pixel groups within a pixel unit group.
  • the sensing line SE and the first auxiliary power supply line FL are located between the third sub-pixel group and the fourth sub-pixel group of the pixel unit group.
  • Both the sensing line SE and the first auxiliary power line FL extend along the first direction Y and are arranged along the second direction X.
  • the orthographic projection of the first auxiliary power line FL on the base substrate 60 does not overlap with the orthographic projection of the sensing line SE on the base substrate 60 .
  • the orthographic projection of the first auxiliary power line FL on the base substrate 60 is located on one side of the orthographic projection of the sensing line SE on the base substrate 60 , for example, on the side close to the j+3th column sub-pixel group.
  • this embodiment does not limit it.
  • the first power supply lines and the sensing lines are arranged at intervals, and three sub-pixel groups are arranged between the adjacent first power supply lines and the sensing lines.
  • the first conductive layer of the display area may include: a first auxiliary power line FL, a second pole 52 of the first storage capacitor Cst1, a second storage capacitor Cst2 the second pole.
  • the second poles of the first storage capacitor and the second storage capacitor may serve as light-shielding electrodes.
  • the orthographic projection of the second pole 52 of the first storage capacitor on the substrate can cover the orthographic projection of the channel region of the active layer of the third transistor on the substrate, and the second pole of the second storage capacitor is on the substrate.
  • the orthographic projection on the substrate may cover the orthographic projection of the channel region of the active layer of the sixth transistor on the base substrate, so as to prevent ambient light from affecting the channel region.
  • the semiconductor layer in the display area may include: an active layer of a plurality of transistors in the pixel circuit, a first electrode of the first storage capacitor, a first electrode of the second storage capacitor first pole.
  • the active layer 20 of the second transistor of the pixel circuits of the plurality of sub-pixel groups of the pixel unit group may have an integral structure.
  • the first doped regions of the active layer 20 of the second transistors of the pixel circuits of the multiple sub-pixel groups of the pixel unit group are electrically connected to each other.
  • the active layer 10 of the first transistor and the active layer 30 of the third transistor of the pixel circuit of the sub-pixel group are adjacent in the second direction X.
  • the active layer 40 of the light emission control transistors of the pixel circuits of the multiple sub-pixel groups of the pixel unit group may have an integrated structure.
  • the first doped regions of the active layer 40 of the light emission control transistors of the pixel circuits of the multiple sub-pixel groups may be electrically connected to each other.
  • the first pole of the first storage capacitor and the active layer of the first transistor may be integrally structured, and the first pole of the second storage capacitor may be integrally structured with the active layer of the fourth transistor.
  • the second conductive layer of the display area may include: control electrodes of multiple transistors of the pixel circuit, multiple first scan lines, multiple second scan lines and multiple luminous control lines.
  • the control electrodes of the first transistors of the pixel circuits of multiple sub-pixel groups in the same row of pixel unit groups and a first scanning line can be integrated, and the control electrodes of the second transistors of the pixel circuits of multiple sub-pixel groups in the same row of pixel unit groups
  • the electrode and a second scanning line can have an integrated structure, and the control electrode of the fourth transistor of the pixel circuit of multiple sub-pixel groups in the same row of pixel units can be in an integrated structure with a first scanning line.
  • the control electrode of the fifth transistor of the pixel circuit of the sub-pixel group and a second scanning line may be integrally structured.
  • the control electrodes of the light emission control transistors of the multiple sub-pixel groups of the same row of pixel unit groups and one light emission control line may have an integrated structure.
  • the control electrode of the first transistor of the first sub-pixel circuit of the sub-pixel group and the first scan line G1(i) may be integrally structured, and the control electrode of the fourth transistor of the second sub-pixel circuit of the sub-pixel group is connected with the first scanning line G1(i).
  • a scan line G1(i+1) may have an integral structure; the control electrode of the second transistor of the first sub-pixel circuit and the second scan line G2(i) may have an integral structure, and the fifth transistor of the second sub-pixel circuit
  • this embodiment does not limit it.
  • the third conductive layer may include: a plurality of first power supply lines, a plurality of data lines, a sensing line SE, and a plurality of transistors of the pixel circuit the first pole and the second pole.
  • the sensing line SE is electrically connected to the first doped region of the active layer 20 of the second transistor of the first sub-pixel circuit through the eighth via hole K8, and connected to the second transistor of the second sub-pixel circuit through the ninth via hole K9.
  • the first doped region of the active layer is electrically connected.
  • one sensing line SE is electrically connected to pixel circuits of a plurality of sub-pixel groups of one pixel unit group.
  • the first power line PL1a is electrically connected to the first doped region of the active layer of the light emission control transistor T7 of the light emission control subcircuit through the tenth via hole K10, and the first power line PL1b is connected to the light emission control subcircuit through the eleventh via hole K11.
  • the first doped region of the active layer of the light emission control transistor T7 of the circuit is electrically connected.
  • a pixel unit group includes six sub-pixel groups arranged in sequence along the second direction X, between the first sub-pixel group and the second sub-pixel group There are two data lines (ie, data lines D(j) and D(j+1)), and one data line (ie, data line D(j+2) is set between the second sub-pixel group and the third sub-pixel group )).
  • the pixel circuits of the first sub-pixel group and the pixel circuits of the second sub-pixel group are approximately symmetrical about their center line in the second direction X.
  • the center lines of the pixel circuits of the first sub-pixel group and the pixel circuits of the second sub-pixel group in the second direction X may be aligned with the data lines D(j) and D(j+1) in the second direction X centerlines coincide.
  • this embodiment does not limit it.
  • the structures of the pixel circuits of the second sub-pixel group and the pixel circuits of the third sub-pixel group may be substantially the same, so details will not be repeated here.
  • the pixel circuits of the pixel unit group are approximately symmetrical with respect to the center line OX of the pixel circuits of the pixel unit group in the second direction X.
  • the display substrate provided in this exemplary embodiment can reduce the number of light-emitting control lines by arranging sub-pixel groups that share the light-emitting control sub-circuit, thereby optimizing the spatial arrangement and effectively increasing the resolution.
  • FIG. 13 is a top view of pixel circuits of a plurality of pixel unit groups according to at least one embodiment of the present disclosure.
  • Figure 13 illustrates four pixel unit groups arranged in two rows and two columns (for example, the pixel unit group in the bth row and k column, the bth row and k+1 column pixel unit group, the b+1th row and k column pixel unit group, b+1th row k+1th column pixel unit group, b and k are both integers).
  • two adjacent pixel unit groups share a first power supply line.
  • the pixel unit group at row b, column k and the pixel unit group at row b, column k+1 share the first power line PL1b.
  • this embodiment does not limit it.
  • Fig. 14 is a schematic diagram of the arrangement of the first auxiliary power lines according to at least one embodiment of the present disclosure.
  • the display substrate includes: a display area AA and a frame area BB located around the display area AA.
  • the frame area BB has a first connection area DD and a second connection area EE.
  • the display area AA is provided with a plurality of first auxiliary power lines FL.
  • the plurality of first auxiliary power lines FL extend along the first direction Y and are arranged along the second direction X.
  • At least one first auxiliary power line FL is located between adjacent sub-pixel groups in the pixel unit group, for example, in the second direction X, three sub-pixel groups may be arranged between two adjacent first auxiliary power lines FL .
  • the first auxiliary power line FL may extend from the display area AA to the first connection area DD and the second connection area EE along the first direction Y.
  • the first auxiliary power line FL may be electrically connected to the second electrodes of the first light emitting element and the second light emitting element through the connection electrodes.
  • the first auxiliary power line FL is located on the first conductive layer, and can be electrically connected to the second electrodes of the first light-emitting element and the second light-emitting element through the connecting electrodes located on the third conductive layer and the anode layer.
  • the first auxiliary power line in this embodiment can reduce the resistance of the second poles of the first light-emitting element and the second light-emitting element, thereby reducing the IR drop of the second power line.
  • the structure of the display substrate will be described below by way of an example of the manufacturing process of the display substrate.
  • the “patterning process” mentioned in this disclosure includes deposition of film layer, coating of photoresist, mask exposure, development, etching and stripping of photoresist. Any one or more of sputtering, evaporation and chemical vapor deposition can be used for deposition, any one or more of spray coating and spin coating can be used for coating, and any of dry etching and wet etching can be used for etching. one or more.
  • “Film” refers to a layer of film produced by depositing or coating a certain material on a substrate.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • a and B are arranged in the same layer in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the projection of A includes the projection of B means that the boundary of the projection of B falls within the boundary range of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.
  • the manufacturing process of the display substrate may include the following operations, as shown in FIGS. 5 to 12 .
  • the display substrate is a top emission display substrate, and a pixel unit group is taken as an example for illustration.
  • a first conductive film is deposited on the base substrate 60, and the first conductive film is patterned by a patterning process to form a first conductive layer pattern.
  • the first conductive layer may include: a first auxiliary power line FL, a second pole 52 of the first storage capacitor, and a second pole of the second storage capacitor.
  • the second pole 52 of the first storage capacitor and the second pole of the second storage capacitor can also serve as light-shielding electrodes to protect the channel region of the active layer of the driving transistor of the pixel circuit.
  • the substrate substrate 60 may be a rigid substrate or a flexible substrate.
  • the rigid substrate may comprise one or more of glass, metal foil.
  • Flexible substrates may include polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide One or more of amine, polyvinyl chloride, polyethylene, textile fiber. However, this embodiment does not limit it.
  • the first insulating film and the semiconductor film are deposited sequentially on the base substrate 60 formed with the aforementioned pattern, and the semiconductor film is patterned by a patterning process to form the first insulating layer 61 and the first insulating layer 61 formed on the first insulating film.
  • the semiconductor layer may include: an active layer of a plurality of transistors of the pixel circuit, a first pole of the first storage capacitor, and a first pole of the second storage capacitor.
  • the active layer of the first transistor of the first sub-pixel circuit and the first electrode of the first storage capacitor may be integrated, and the active layer of the fourth transistor of the second sub-pixel circuit and the second storage capacitor
  • the first pole of can be a one-piece structure.
  • a second insulating film and a second conductive film are sequentially deposited on the base substrate 60 formed with the aforementioned pattern, and the second conductive film is patterned by a patterning process to form the second insulating layer 62 and the A second conductive layer on the second insulating layer 62 .
  • the second conductive layer may include: control electrodes of multiple transistors of the pixel circuit, multiple first scan lines, multiple second scan lines, and multiple light emission control lines.
  • a third insulating film is deposited on the base substrate 60 formed with the foregoing pattern, and the third insulating film is patterned by a patterning process to form a pattern of the third insulating layer 63 .
  • a plurality of via hole patterns are opened on the third insulating layer 63 .
  • the third insulating layer in the first via hole K1, the second via hole K2, the third via hole K3, the fourth via hole K4, the fifth via hole K5, the eighth via hole K8 to the eleventh via hole K11 63 and the second insulating layer 62 are etched away, exposing the surface of the semiconductor layer; the third insulating layer 63 and the second insulating layer 62 in the half region of the sixth via hole K6 are etched away, exposing the surface of the semiconductor layer surface, the third insulating layer 63 in the other half area is etched away, exposing the surface of the second conductive layer; the third insulating layer 63, the second insulating layer 62 and the first insulating layer 61 in the seventh via hole K7 are etched away, exposing the surface of the first conductive layer.
  • the orthographic projection of the plurality of via holes on the base substrate 60 may be rectangular or circular. However, this embodiment does not limit it.
  • a third conductive film is deposited on the base substrate 60 formed with the foregoing pattern, and the third conductive film is patterned by a patterning process to form a third conductive layer pattern on the third insulating layer 63 .
  • the third conductive layer may include: a plurality of first power lines, a plurality of data lines, a sensing line SE, and first electrodes and second electrodes of a plurality of transistors of the pixel circuit.
  • a fourth insulating film is deposited on the base substrate 60 formed with the foregoing pattern to form a fourth insulating layer. Then, a fifth insulating film is coated, and a fifth insulating layer pattern is formed by masking, exposing and developing the fifth insulating film. A plurality of via holes exposing the fourth insulating layer are opened on the fifth insulating layer. Then, the exposed fourth insulating layer is etched, and a plurality of via holes are formed on the fourth insulating layer to expose the surface of the third conductive layer.
  • a fourth conductive film is deposited on the base substrate 60 formed with the foregoing pattern, and the fourth conductive film is patterned by a patterning process to form an anode layer pattern on the fifth insulating layer.
  • the anode layer at least includes: a first pole of the first light-emitting element of the sub-pixel group, and a first pole of the second light-emitting element.
  • the first electrode of the first light-emitting element may be electrically connected to the second electrode of the third transistor of the first sub-pixel circuit through the via hole on the fourth insulating layer and the fifth insulating layer.
  • the first electrode of the second light-emitting element may be electrically connected to the second electrode of the sixth transistor of the second sub-pixel circuit through the via hole on the fourth insulating layer and the fifth insulating layer.
  • the anode layer may use any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or any of the above metals Alloys made of one or more types.
  • a pixel definition film is coated on the base substrate 60 formed with the foregoing pattern, and a pixel definition layer pattern is formed through masking, exposure and development processes.
  • the pixel definition layer of each sub-pixel group is formed with a first pixel opening exposing the first pole of the first light emitting element and a second pixel opening exposing the second pole of the second light emitting element.
  • the first organic light-emitting layer of the first light-emitting element can be formed in the formed first pixel opening, and the first organic light-emitting layer is electrically connected to the first electrode of the first light-emitting element;
  • the second organic light emitting layer of the second light emitting element is formed in the opening of the second pixel, and the second organic light emitting layer is electrically connected with the first electrode of the second light emitting element.
  • a transparent conductive film is deposited, and the transparent film is patterned by a patterning process to form the second pole pattern of the first light-emitting element and the second pole pattern of the second light-emitting element.
  • transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO) can be used for the second electrodes of the first light emitting element and the second light emitting element.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • an encapsulation layer may be formed on the first light emitting element and the second electrodes of the second light emitting element.
  • the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material. However, this embodiment does not limit it.
  • the first conductive layer, the second conductive layer, and the third conductive layer can use metal materials, such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • One or more, or alloy materials of the above metals such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the light-shielding performance of the metal material used in the first conductive layer may be stronger than that of the metal materials used in the second conductive layer and the third conductive layer.
  • the first insulating layer 61, the second insulating layer 62, the third insulating layer 63, and the fourth insulating layer can be any one of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON) or More kinds, can be single layer, multilayer or composite layer.
  • Organic materials such as polyimide, acrylic or polyethylene terephthalate can be used for the fifth insulating layer and the pixel definition layer.
  • the semiconductor layer can be metal oxide or polysilicon. However, this embodiment does not limit it.
  • the pixel circuit may be electrically connected to the first electrode of the first light-emitting element and the first electrode of the second light-emitting element through a connecting electrode.
  • the present disclosure is not limited here.
  • the preparation process of the present disclosure can be realized by using mature preparation equipment at present, can be well compatible with the existing preparation process, the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.
  • FIG. 15 is another schematic top view of the pixel circuit of the pixel unit group according to at least one embodiment of the present disclosure.
  • two first auxiliary power lines FLa and FLb and one sensing line SE are arranged between adjacent sub-pixel groups in a pixel unit group.
  • the pixel unit group includes six sub-pixel groups arranged in sequence along the second direction X, two first auxiliary power supply lines FLa and FLb and one sensing line SE may be located in the third sub-pixel group and the fourth sub-pixel group of the pixel unit group. between sub-pixel groups.
  • the two first auxiliary power lines FLa and FLb are located on the first conductive layer, and the sensing line SE is located on the third conductive layer.
  • the orthographic projections of the two first auxiliary power lines FLa and FLb on the base substrate may be located on opposite sides of the orthographic projection of the sensing line SE on the base substrate in the second direction X.
  • the orthographic projections of the two first auxiliary power lines FLa and FLb on the base substrate and the orthographic projection of the sensing line SE on the base substrate may not overlap.
  • the IR drop of the second power supply line can be further reduced.
  • FIG. 16 is another schematic top view of the pixel circuit of the pixel unit group according to at least one embodiment of the present disclosure.
  • one sensing line SE, one first auxiliary power line FL and one second auxiliary power line HL are disposed between adjacent sub-pixel groups within a pixel unit group.
  • the pixel unit group includes six sub-pixel groups arranged in sequence along the second direction X, and a first auxiliary power line FL, a second auxiliary power line HL, and a sensing line SE may be located in the third sub-pixel group of the pixel unit group. between the pixel group and the fourth sub-pixel group.
  • the sensing line SE and the second auxiliary power line HL may be located on the third conductive layer, and the first auxiliary power line FL may be located on the first conductive layer.
  • the orthographic projection of the first auxiliary power line FL on the base substrate overlaps with the orthographic projection of the sensing line SE on the base substrate.
  • the orthographic projection of the second auxiliary power line HL on the base substrate and the orthographic projection of the sensing line SE on the base substrate may not overlap.
  • the second auxiliary power line HL may be located on one side of the sensing line SE, for example, on a side close to the j+3th column sub-pixel group.
  • the second auxiliary power line HL may be electrically connected to the first doped region of the active layer of the light emission control transistor through the twelfth via hole K12.
  • the second auxiliary power line HL and the first power lines PL1a and PL1b may be electrically connected through the active layer of the light emission control transistor.
  • the width (ie, the length along the second direction X) of the second auxiliary power line HL may be smaller than the width of the first power line PL1a or PL1b.
  • the width means a characteristic dimension in a direction perpendicular to the extending direction.
  • the IR voltage drop of the first power supply line can be reduced.
  • the pixel unit group includes six sub-pixel groups arranged in sequence along the second direction X, and a first auxiliary power supply line, a second auxiliary power supply line and a sensing line may be located in the pixel unit group between the third sub-pixel group and the fourth sub-pixel group.
  • the second auxiliary power line and the first auxiliary power line may have the same layer structure, for example, both are located on the first conductive layer.
  • the sensing line may be located on the third conductive layer.
  • the second auxiliary power line may be electrically connected to the first doped region of the active layer of the light emission control transistor through the via hole on the first insulating layer.
  • the orthographic projection of the sensing line on the base substrate may be located in the middle of the orthographic projections of the first auxiliary power line and the second auxiliary power line on the base substrate.
  • the orthographic projections of the sensing line, the first auxiliary power line and the second auxiliary power line on the base substrate may not overlap.
  • this embodiment does not limit it.
  • the sensing line, the first auxiliary power line and the second auxiliary power line may be located between the second sub-pixel group and the third sub-pixel group, or between the fourth sub-pixel group and the fifth sub-pixel group.
  • FIG. 17 is another schematic top view of the pixel circuit of the pixel unit group according to at least one embodiment of the present disclosure.
  • one sensing line SE and one first auxiliary power supply line FL are provided between adjacent sub-pixel groups within a pixel unit group.
  • the pixel unit group includes six sub-pixel groups arranged in sequence along the second direction X, a first auxiliary power line FL and a sensing line SE may be located in the third sub-pixel group and the fourth sub-pixel group of the pixel unit group between. Both the sensing line SE and the first auxiliary power line FL are located on the third conductive layer.
  • the first auxiliary power line FL may be located at one side of the sensing line SE, for example, a side close to the j+3th column sub-pixel group. However, this embodiment does not limit it.
  • the first auxiliary power line FL may be located on a side of the sensing line SE close to the j+2th column of sub-pixel groups.
  • one sensing line and two first auxiliary pixel groups may be arranged between adjacent sub-pixel groups in a pixel unit group (for example, between the third sub-pixel group and the fourth sub-pixel group).
  • power cable Both the sensing line and the two first auxiliary power lines may be located on the third conductive layer, and the two first auxiliary power lines may be located on opposite sides of the sensing line in the second direction X.
  • a sensing line, a first auxiliary power supply and cord and a second auxiliary power cord may all be located on the third conductive layer, and the first auxiliary power line and the second auxiliary power line may be located on opposite sides of the sensing line in the second direction.
  • the second auxiliary power line may be electrically connected to the first doped region of the active layer of the light emission control transistor.
  • the display substrate provided in this exemplary embodiment can reduce the IR drop of the second power supply line by arranging a plurality of first auxiliary power supply lines. Moreover, by providing the second auxiliary power line, the IR drop of the first power line can be reduced.
  • FIG. 18 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 18 , this embodiment provides a display device 91 including the display substrate 910 of the foregoing embodiments.
  • the display substrate 910 may be an OLED display substrate or a QLED display substrate.
  • the display device 91 may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator. However, this embodiment does not limit it.

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Abstract

一种显示基板(910)，包括：衬底基板(60)和多个像素单元组(P)。多个像素单元组(P)位于衬底基板(60)的显示区域(AA)。至少一个像素单元组(P)包括多个子像素组，至少一个子像素组包括像素电路。像素电路包括：第一子像素电路(71)、第二子像素电路(72)以及发光控制子电路(73)。第一子像素电路(71)和第二子像素电路(72)均与发光控制子电路(73)电连接。发光控制子电路(73)被配置为控制与第一子像素电路(71)电连接的第一发光元件(EL)发光，以及控制与第二子像素电路(72)电连接的第二发光元件(EL')发光。第一子像素电路(71)和第二子像素电路(72)关于子像素组在第一方向(Y)上的中心线(OY)大致对称。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开至少一实施例提供一种显示基板及显示装置。
一方面，本公开至少一实施例提供一种显示基板，包括：衬底基板和多个像素单元组。衬底基板包括显示区域。多个像素单元组位于显示区域。至少一个像素单元组包括多个子像素组，至少一个子像素组包括像素电路。所述像素电路包括：第一子像素电路、第二子像素电路以及发光控制子电路，所述第一子像素电路和第二子像素电路均与所述发光控制子电路电连接。所述发光控制子电路被配置为控制与所述第一子像素电路电连接的第一发光元件发光，以及控制与所述第二子像素电路电连接的第二发光元件发光。所述第一子像素电路和第二子像素电路关于所述子像素组的像素电路在第一方向上的中心线大致对称。
在一些示例性实施方式中，在所述第一方向上，所述像素电路的发光控制子电路位于所述第一子像素电路和第二子像素电路之间。
在一些示例性实施方式中，所述发光控制子电路与发光控制线电连接，所述发光控制线沿第二方向延伸，且位于所述第一子像素电路和第二子像素电路之间；所述第二方向与所述第一方向交叉。
在一些示例性实施方式中，所述发光控制子电路包括：发光控制晶体管；所述发光控制晶体管的控制极与发光控制线电连接，所述发光控制晶体管的第一极与第一电源线电连接，所述发光控制晶体管的第二极与所述第一子像素电路和第二子像素电路电连接。
在一些示例性实施方式中，至少一个子像素组还包括：与所述第一子像素电路电连接的第一发光元件、与所述第二子像素电路电连接的第二发光元件。所述第一发光元件的第一极与所述第一子像素电路电连接，所述第二发光元件的第一极与所述第二子像素电路电连接。所述第一发光元件和所述第二发光元件的第二极均与第二电源线电连接。所述衬底基板还包括：位于所述显示区域周边的边框区域。所述显示区域设置有多条沿第一方向延伸的第一辅助电源线，至少一条第一辅助电源线在所述边框区域与所述第一发光元件和所述第二发光元件的第二极电连接。
在一些示例性实施方式中，在与所述第一方向交叉的第二方向上，至少一条第一辅助电源线位于至少一个像素单元组内的相邻子像素组之间。
在一些示例性实施方式中，所述衬底基板的显示区域还设置有多条沿所述第一方向延伸的第一电源线。至少一条第一电源线位于相邻像素单元组之间。
在一些示例性实施方式中，相邻像素单元组共用一条第一电源线。
在一些示例性实施方式中，至少一个像素单元组的每个子像素组包括所述像素电路，所述至少一个像素单元组关于所述像素单元组的多个像素电路在第二方向上的中心线大致对称，所述第二方向与所述第一方向交叉。
在一些示例性实施方式中，所述衬底基板的显示区域还设置有多条沿所述第一方向延伸的感测线。至少一条感测线位于所述至少一个像素单元组内的相邻子像素组之间。
在一些示例性实施方式中，至少一个像素单元组内的相邻子像素组之间 设置有一条感测线和一条第一辅助电源线；所述感测线在所述衬底基板上的正投影位于所述第一辅助电源线在所述衬底基板上的正投影的一侧。
在一些示例性实施方式中，至少一个像素单元组内的相邻子像素组之间设置有一条感测线和两条第一辅助电源线。所述两条第一辅助电源线在所述衬底基板上的正投影分别位于所述感测线在所述衬底基板上的正投影的两侧。
在一些示例性实施方式中，所述辅助电源线与感测线为同层结构。
在一些示例性实施方式中，至少一个像素单元组内的相邻子像素组之间设置有一条第一辅助电源线、一条感测线和一条第二辅助电源线；所述第二辅助电源线沿所述第一方向延伸并与第一电源线电连接。所述第一辅助电源线在所述衬底基板上的正投影与所述感测线在所述衬底基板上的正投影存在交叠，且所述第二辅助电源线在所述衬底基板上的正投影位于所述感测线在所述衬底基板上的正投影的一侧。
在一些示例性实施方式中，在垂直于所述显示基板的平面内，所述第一辅助电源线位于所述感测线靠近所述衬底基板的一侧。
在一些示例性实施方式中，所述至少一个像素单元组包括：沿第二方向依次排布的六个子像素组，第一个子像素组和第二个子像素组的像素电路关于所述第一个和第二个子像素组的像素电路在所述第二方向上的中心线大致对称，所述第二方向与所述第一方向交叉。
在一些示例性实施方式中，所述衬底基板的显示区域还设置有沿所述第一方向延伸的多条数据线。所述第一个子像素组和第二个子像素组的像素电路之间排布有两条数据线，所述第二个子像素组和第三个子像素组的像素电路之间排布有一条数据线。
在一些示例性实施方式中，第一子像素电路包括：第一晶体管、第二晶体管、第三晶体管、以及第一存储电容。所述第一晶体管的控制极与第i条第一扫描线电连接，所述第一晶体管的第一极与数据线电连接，所述第一晶体管的第二极与所述第三晶体管的控制极电连接。所述第二晶体管的控制极与第i条第二扫描线电连接，所述第二晶体管的第一极与感测线电连接，所述第二晶体管的第二极与所述第三晶体管的第二极电连接。所述第三晶体管的第一极与所述发光控制子电路电连接。所述第一存储电容的第一极与所述 第三晶体管的控制极电连接，所述第一存储电容的第二极与所述第三晶体管的第二极电连接。所述第三晶体管的第二极与第一发光元件的第一极电连接。所述第二子像素电路包括：第四晶体管、第五晶体管、第六晶体管以及第二存储电容。所述第四晶体管的控制极与第i+1条第一扫描线电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第六晶体管的控制极电连接。所述第五晶体管的控制极与第i+1条第二扫描线电连接，所述第五晶体管的第一极与所述感测线电连接，所述第五晶体管的第二极与所述第六晶体管的第二极电连接。所述第六晶体管的第一极与所述发光控制子电路电连接。所述第二存储电容的第一极与所述第六晶体管的控制极电连接，所述第二存储电容的第二极与所述第六晶体管的第二极电连接。所述第六晶体管的第二极与所述第二发光元件的第一极电连接。其中，i为自然数。
在一些示例性实施方式中，在垂直于所述显示基板的平面内，所述显示基板包括：设置在所述衬底基板上的第一导电层、半导体层、第二导电层和第三导电层。所述第一导电层至少包括：所述像素电路的第一存储电容的第二极和第二存储电容的第二极。所述半导体层至少包括：所述像素电路的多个晶体管的有源层、所述第一存储电容的第一极和第二存储电容的第二极。所述第二导电层至少包括：所述像素电路的多个晶体管的控制极、所述第一扫描线、所述第二扫描线、以及所述发光控制线。所述第三导电层至少包括：所述数据线以及所述感测线。
在一些示例性实施方式中，与所述第一发光元件和第二发光元件的第二极电连接的第一辅助电源线位于所述第一导电层或者所述第三导电层。
另一方面，本公开实施例还提供一种显示装置，包括如上所述的显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开 的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的显示基板的结构示意图；
图2为本公开至少一实施例的显示基板的平面示意图；
图3为本公开至少一实施例的子像素组的像素电路的等效电路图；
图4为本公开至少一实施例的像素电路的工作时序图；
图5为本公开至少一实施例的子像素组的像素电路的俯视图；
图6为图5中沿Q-Q’方向的局部剖面示意图；
图7为本公开至少一实施例的一个像素单元组的像素电路的俯视图；
图8为本公开至少一实施例的形成第一导电层后的像素单元组的像素电路的俯视图；
图9为本公开至少一实施例的形成半导体层后的像素单元组的像素电路的俯视图；
图10为本公开至少一实施例的形成第二导电层后的像素单元组的像素电路的俯视图；
图11为本公开至少一实施例的形成第三绝缘层后的像素单元组的像素电路的俯视图；
图12为本公开至少一实施例的形成第三导电层后的像素单元组的像素电路的俯视图；
图13为本公开至少一实施例的多个像素单元组的像素电路的俯视图；
图14为本公开至少一实施例的第一辅助电源线的排布示意图；
图15为本公开至少一实施例的像素单元组的像素电路的另一俯视图；
图16为本公开至少一实施例的像素单元组的像素电路的另一俯视图；
图17为本公开至少一实施例的像素单元组的像素电路的另一俯视图；
图18为本公开至少一实施例的显示装置的示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，晶体管是指至少包括栅极(栅电极)、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、 沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。另外，栅极还可以称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。
本公开实施例提供一种显示基板，包括：衬底基板和多个像素单元组。衬底基板包括显示区域，多个像素单元组位于显示区域。至少一个像素单元组包括多个子像素组，至少一个子像素组包括像素电路。至少一个子像素组的像素电路包括：第一子像素电路、第二子像素电路以及发光控制子电路。第一子像素电路和第二子像素电路均与发光控制子电路电连接。发光控制子电路被配置为控制与第一子像素电路电连接的第一发光元件元件，以及控制与第二子像素电路电连接的第二发光元件发光。第一子像素电路和第二子像素电路关于所述子像素组的像素电路在第一方向上的中心线大致对称。
本实施例提供的显示基板，通过在像素电路设置发光控制子电路，可以实现高灰阶等级，提高显示效果；而且，通过设置第一子像素电路和第二子像素电路关于子像素组在第一方向上的中心线大致对称，可以优化空间，在不影响正常显示的基础上，可以增加分辨率。
在一些示例性实施方式中，在第一方向上，像素电路的发光控制子电路位于第一子像素电路和第二子像素电路之间。在本示例中，像素电路的第一子像素电路、发光控制子电路和第二子像素电路可以沿着第一方向依次排布。在一些示例中，第一方向与第二方向交叉，例如，相互垂直。例如，第一方向平行于子像素列方向，第二方向平行于子像素行方向。然而，本实施例对此并不限定。
在一些示例性实施方式中，发光控制子电路与发光控制线电连接。发光控制线沿与第一方向交叉的第二方向延伸，且位于第一子像素电路和第二子像素电路之间。
在一些示例性实施方式中，发光控制子电路包括：发光控制晶体管。发光控制晶体管的控制极与发光控制线电连接，发光控制晶体管的第一极与第一电源线电连接，发光控制晶体管的第二极与第一子像素电路和第二子像素电路电连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，至少一个子像素组还包括：与第一子像素电路电连接的第一发光元件、与第二子像素电路电连接的第二发光元件。第一发光元件的第一极与第一子像素电路电连接，第二发光元件的第一极与第二子像素电路电连接。第一发光元件和第二发光元件的第二极均与第二电源线电连接。衬底基板还包括：位于显示区域周边的边框区域。显示区域设置有多条沿第一方向延伸的第一辅助电源线，至少一条第一辅助电源线在边框区域与第一发光元件和第二发光元件的第二极电连接。本示例性实施方式通过在显示基板设置第一辅助电源线，可以降低第二电源线的IR压降。
在一些示例性实施方式中，在与第一方向交叉的第二方向上，至少一条第一辅助电源线位于至少一个像素单元组内的相邻子像素组之间。例如，至少一个像素单元组包括沿第二方向排布的六个子像素组，至少一条第一辅助电源线可以位于第三个子像素组和第四个子像素组之间。然而，本实施例对此并不限定。
在一些示例性实施方式中，衬底基板的显示区域还设置有多条沿第一方向延伸的第一电源线。至少一条第一电源线位于相邻像素单元组之间。然而，本实施例对此并不限定。
在一些示例性实施方式中，相邻像素单元组共用一条第一电源线。在本示例中，相邻像素单元组之间可以设置一条第一电源线，且相邻像素单元组均与该第一电源线电连接。然而，本实施例对此并不限定。例如，相邻像素单元组之间可以排布两条第一电源线，且一条第一电源线与一个像素单元组电连接。
在一些示例性实施方式中，至少一个像素单元组的每个子像素组包括所述像素电路，至少一个像素单元组关于所述像素单元组的多个像素电路在第二方向上的中心线大致对称。其中，第二方向与第一方向交叉。然而，本实施例对此并不限定。
在一些示例性实施方式中，衬底基板的显示区域还设置有多条沿第一方向延伸的感测线。至少一条感测线位于至少一个像素单元组内的相邻子像素组之间。在一些示例中，像素单元组包括沿第二方向排布的六个子像素组，一条感测线可以位于第三个子像素组和第四个子像素组之间，且所述六个子像素组的像素电路均与该条感测线电连接。然而，本实施例对此并不限定。例如，像素单元组包括的第三个子像素组和第四个子像素组之间可以设置两条感测线，且所述第一至第三个子像素组的像素电路可以与其中一条感测线电连接，第四至第六个子像素组的像素电路可以与另一条感测线电连接。
在一些示例性实施方式中，至少一个像素单元组内的相邻子像素组之间设置有一条感测线和一条第一辅助电源线。感测线在衬底基板上的正投影位于第一辅助电源线在衬底基板上的正投影的一侧。在本示例中，感测线在衬底基板上的正投影与第一辅助电源线在衬底基板上的正投影可以没有交叠。在一些示例中，第一辅助电源线与感测线可以为同层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，至少一个像素单元组内的相邻子像素组之间设置有一条感测线和两条第一辅助电源线。所述两条第一辅助电源线在衬底基板上的正投影分别位于感测线在衬底基板上的正投影的两侧。在本示例中，感测线在衬底基板上的正投影与两条第一辅助电源线在衬底基板上的正投影可以没有交叠。在一些示例中，第一辅助电源线与感测线可以为同层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，至少一个像素单元组内的相邻子像素组之间可以设置有一条第一辅助电源线、一条感测线和一条第二辅助电源线。第二辅助电源线沿第一方向延伸并与第一电源线电连接。第一辅助电源线在衬底基板上的正投影与感测线在衬底基板上的正投影存在交叠，且第二辅助电源线在衬底基板上的正投影位于感测线在衬底基板上的正投影的一侧。在一些示例中，第二辅助电源线在衬底基板上的正投影与感测线和第一辅助电源线在衬底基板上的正投影可以没有交叠。在一些示例中，第二辅助电源线与感测线可以为同层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，在垂直于显示基板的平面内，第一辅助电源线可以位于感测线靠近衬底基板的一侧。
在一些示例性实施方式中，至少一个像素单元组包括：沿第二方向依次排布的六个子像素组，第一个子像素组和第二个子像素组的像素电路关于所述第一个和第二个子像素组的像素电路在第二方向上的中心线大致对称，第二方向与第一方向交叉。然而，本实施例对此并不限定。
在一些示例性实施方式中，衬底基板的显示区域还设置有沿第一方向延伸的多条数据线。第一个子像素组和第二个子像素组的像素电路之间可以排布两条数据线，第二个子像素组和第三个子像素组的像素电路之间可以排布一条数据线。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一子像素电路可以包括：第一晶体管、第二晶体管、第三晶体管以及第一存储电容。第一晶体管的控制极与第i条第一扫描线电连接，第一晶体管的第一极与数据线电连接，第一晶体管的第二极与第三晶体管的控制极电连接。第二晶体管的控制极与第i条第二扫描线电连接，第二晶体管的第一极与感测线电连接，第二晶体管的第二极与第三晶体管的第二极电连接。第三晶体管的第一极与发光控制子电路电连接。第一存储电容的第一极与第三晶体管的控制极电连接，第一存储电容的第二极与第三晶体管的第二极电连接。第三晶体管的第二极与第一发光元件的第一极电连接。第二子像素电路包括：第四晶体管、第五晶体管、第六晶体管以及第二存储电容。第四晶体管的控制极与第i+1条第一扫描线电连接，第四晶体管的第一极与所述数据线电连接，第四晶体管的第二极与第六晶体管的 控制极电连接。第五晶体管的控制极与第i+1条第二扫描线电连接，第五晶体管的第一极与所述感测线电连接，第五晶体管的第二极与第六晶体管的第二极电连接。第六晶体管的第一极与发光控制子电路电连接。第二存储电容的第一极与第六晶体管的控制极电连接，第二存储电容的第二极与第六晶体管的第二极电连接。第六晶体管的第二极与第二发光元件的第一极电连接。其中，i为自然数。
在一些示例性实施方式中，在垂直于显示基板的平面内，显示基板包括：设置在衬底基板上的第一导电层、半导体层、第二导电层和第三导电层。第一导电层至少包括：像素电路的第一存储电容的第二极和第二存储电容的第二极。半导体层至少包括：像素电路的多个晶体管的有源层、第一存储电容的第一极和第二存储电容的第二极。第二导电层至少包括：像素电路的多个晶体管的控制极、第一扫描线、第二扫描线、以及发光控制线。第三导电层至少包括：数据线以及感测线。
在一些示例性实施方式中，与第一发光元件和第二发光元件的第二极电连接的第一辅助电源线可以位于第一导电层或者第三导电层。然而，本实施例对此并不限定。
下面通过一些示例对本实施例的显示基板进行举例说明。
图1为本公开至少一实施例的显示基板的结构示意图。如图1所示，显示基板可以包括：时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列。像素阵列可以包括：多个扫描线(例如，G(1)到G(m))、多个数据线(例如，D(1)到D(n))、多个发光控制线(例如，EM(1)到EM(m))和多个子像素组。其中，m和n均为自然数。
在一些示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据线D(1)至D(n)的数据电压，n可以为自然数。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据线 D(1)至D(n)。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描线G(1)至G(m)的扫描信号，m可以为自然数。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线G(1)至G(m)。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光控制线EM(1)至EM(m)的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光控制线EM(1)至EM(m)。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号。像素阵列可以包括多个像素单元组，至少一个像素单元组可以包括多个子像素组。
图2为本公开至少一实施例的显示基板的平面示意图。在一些示例性实施方式中，如图2所示，显示基板可以包括以矩阵方式排布的多个像素单元组P，多个像素单元组P的至少一个可以包括多个子像素组。至少一个像素单元组P包括沿第二方向依次排布的六个子像素组(例如，两个第一子像素组P1、两个第二子像素组P2以及两个第三子像素组P3)。至少一个子像素组包括：像素电路、第一发光元件和第二发光元件。例如，至少一个子像素组的像素电路包括：沿第一方向依次排布的第一子像素电路、发光控制子电路和第二子像素电路；第一发光元件与第一子像素电路电连接，第二发光元件与第二子像素电路电连接。其中，第一方向与第二方向交叉，例如，第一方向和第二方向相互垂直。在一些示例中，第一子像素组P1可以出射第一颜色光线，第二子像素组P2可以出射第二颜色光线，第三子像素组P3可以出射第三颜色光线。例如，第一颜色光线可以为红光，第二颜色光线可以为绿光，第三颜色光线可以为蓝光。然而，本实施例对此并不限定。例如，同一子像素组中的两个发光元件可以出射相同或不同颜色光线。
在一些示例性实施方式中，第一子像素电路和发光控制子电路被配置为在扫描线和发光控制线的控制下，接收数据线传输的数据电压，向第一发光元件输出相应的电流。第二子像素电路和发光控制子电路被配置为在扫描线 和发光控制线的控制下，接收数据线传输的数据电压，向第二发光元件输出相应的电流。发光控制子电路被配置为控制与第一子像素电路电连接的第一发光元件发光，以及控制与第二子像素电路电连接的第二发光元件发光。第一发光元件配置为响应第一子像素电路输出的电流发出相应亮度的光，第二发光元件配置为响应第二子像素电路输出的电流发出相应亮度的光。在本示例中，至少一个子像素组可以包括共用发光控制子电路的两个子像素，例如，其中一个子像素可以包括第一子像素电路和第一发光元件，另一个子像素可以包括第二子像素电路和第二发光元件。然而，本实施例对此并不限定。
在一些示例性实施方式中，至少一个像素单元组P中的一个像素单元可以包括红色(R)子像素、绿色(G)子像素和蓝色(B)子像素，或者可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素，本公开在此不做限定。在一些示例性实施方式中，像素单元中子像素的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列，本公开在此不做限定。
图3为本公开至少一实施例的子像素组的像素电路的等效电路图。在一些示例性实施方式中，如图3所示，子像素组的像素电路包括：第一子像素电路71、第二子像素电路72以及发光控制子电路73。第一子像素电路71和第二子像素电路72均与发光控制子电路73电连接。在图3中，以子像素组的第一子像素电路与第i行扫描线电连接，第二子像素电路与第i+1行扫描线电连接为例进行说明。i为自然数。
在一些示例性实施方式中，如图3所示，子像素组的第一子像素电路71包括：第一晶体管T1、第二晶体管T2、第三晶体管T3以及第一存储电容Cst1。在一些示例中，第一晶体管T1可以称为开关晶体管，第二晶体管T2可以称为感测补偿晶体管，第三晶体管T3可以称为驱动晶体管。
在一些示例性实施方式中，如图3所示，第一晶体管T1的控制极与第一扫描线G1(i)电连接，第一晶体管T1的第一极与数据线D电连接，第一晶体管T1的第二极与第三晶体管T3的控制极电连接。第二晶体管T2的控制极与第二扫描线G2(i)电连接，第二晶体管T2的第一极与感测线SE电连接， 第二晶体管T2的第二极与第三晶体管T3的第二极电连接。第三晶体管T3的第一极与发光控制子电路73电连接。第一存储电容Cst1的第一极与第三晶体管T3的控制极电连接，第一存储电容Cst1的第二极与第三晶体管T3的第二极电连接。第一存储电容Cst1配置为存储第三晶体管T3的控制极的电位。第一发光元件EL的第一极与第三晶体管T3的第二极电连接，第一发光元件EL的第二极与第二电源线PL2电连接。
在一些示例性实施方式中，第一晶体管T1配置为在第一扫描线G1(i)的控制下，接收数据线D传输的数据信号，并使第三晶体管T3的控制极接收所述数据信号。第三晶体管T3配置为在其控制极所接收的数据信号的控制下，利用发光控制子电路73提供的第一电源信号在第二极产生相应的电流。第一发光元件EL配置为响应第三晶体管T3的第二极产生的电流而发出相应亮度的光。第二晶体管T2配置为响应补偿时序提取第三晶体管T3的阈值电压Vth以及迁移率，以对阈值电压Vth进行补偿。
在一些示例性实施方式中，如图3所示，子像素组的第二子像素电路72包括：第四晶体管T4、第五晶体管T5、第六晶体管T6以及第二存储电容Cst2。在一些示例中，第四晶体管T4可以称为开关晶体管，第五晶体管T5可以称为感测补偿晶体管，第六晶体管T6可以称为驱动晶体管。
在一些示例性实施方式中，如图3所示，第四晶体管T4的控制极与第一扫描线G1(i+1)电连接，第四晶体管T4的第一极与数据线D电连接，第四晶体管T4的第二极与第六晶体管T6的控制极电连接。第五晶体管T5的控制极与第二扫描线G2(i+1)电连接，第五晶体管T5的第一极与感测线SE电连接，第五晶体管T5的第二极与第六晶体管T6的第二极电连接。第六晶体管T6的第一极与发光控制子电路73电连接。第二存储电容Cst2的第一极与第六晶体管T6的控制极电连接，第二存储电容Cst2的第二极与第六晶体管T6的第二极电连接。第二发光元件EL’的第一极与第六晶体管T6的第二极电连接，第二发光元件EL’的第二极与第二电源线PL2电连接。
在一些示例性实施方式中，如图3所示，子像素组的发光控制子电路73可以包括：发光控制晶体管T7。发光控制晶体管T7的控制极与发光控制线EM(i)电连接，发光控制晶体管T7的第一极与第一电源线PL1电连接，发光 控制晶体管T7的第二极与第三晶体管T3的第一极和第六晶体管T6的第一极电连接。发光控制晶体管T7配置为在发光控制线EM(i)的控制下，向第三晶体管T3的第一极和第六晶体管T6的第一极传输第一电源线PL1提供的第一电源信号。
在本示例性实施方式中，子像素组内的第一子像素电路和第二子像素电路均与同一个发光控制子电路电连接。即，子像素组内的相邻子像素共用一个发光控制子电路。本示例性实施例的像素电路通过设置发光控制子电路，可以实现高灰阶等级显示，从而提高显示效果。
在一些示例性实施方式中，第一电源线PL1可以持续提供高电平信号，第二电源线PL2可以持续提供低电平信号。第一晶体管T1到第六晶体管T6以及发光控制晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。
在一些示例性实施方式中，第一晶体管T1到第六晶体管T6以及发光控制晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点。在一些示例性实施方式中，可以将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现高分辨率(PPI，Pixel Per Inch)，低频驱动，可以降低功耗，可以提高显示品质。
在一些示例性实施方式中，第一发光元件EL和第二发光元件EL’可以是有机电致发光二极管(OLED)。第一发光元件EL和第二发光元件EL’可以各自包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图4为本公开至少一实施例的像素电路的工作时序图。下面以像素电路的多个晶体管均为N型晶体管为例，对本实施例的像素电路的工作过程进行 说明。
在一些示例性实施方式中，本实施例的像素电路的工作过程包括：显示阶段S1和空闲阶段S2。在每两帧显示阶段之间的空闲阶段，可以完成对一行子像素的补偿操作，例如，完成对一行子像素的驱动晶体管的阈值电压Vth以及迁移率的侦测，以在显示阶段使用侦测到的数据得到补偿数据信号完成显示。
在一些示例性实施方式中，如图3和图4所示，以子像素组的第一子像素电路的工作过程为例，显示阶段可以包括数据写入阶段和发光阶段。
在数据写入阶段，第一扫描线G1(i)和第二扫描线G2(i)提供高电平信号，第一子像素电路的第一晶体管T1和第二晶体管T2导通。第一晶体管T1导通，将数据线D提供的数据信号写入第三晶体管T3的控制极，并给第一存储电容Cst1充电。第二晶体管T2导通，将感测线SE提供的复位电压提供至第一发光元件EL的第一极，对第一发光元件EL的第一极进行复位。发光控制线EM(i)提供低电平信号，发光控制晶体管T7断开。在本阶段，第一发光元件EL不发光。
在发光阶段，第一扫描线G1(i)和第二扫描线G2(i)提供低电平信号，第一子像素电路的第一晶体管T1和第二晶体管T2断开。发光控制线EM(i)提供高电平信号，发光控制晶体管T7导通。第一电源线PL1提供的高电平信号传输至第三晶体管T3的第一极，第三晶体管T3向第一发光元件EL提供驱动电流，以驱动第一发光元件EL发光。
如图4所示，子像素组的第一子像素电路完成数据写入之后，第二子像素电路在第一扫描线G1(i+1)和第二扫描线G2(i+1)的控制下进行数据写入。在发光控制线EM(i)的高电平信号的控制下，发光控制晶体管T7导通，使得第二子像素电路的第六晶体管T6向第二发光元件EL’提供驱动电流，以驱动第二发光元件EL’发光。
在一些示例性实施方式中，以空闲阶段S2完成第一子像素电路的补偿操作为例进行说明。在空闲阶段S2，第一扫描线G1(i)和第二扫描线G2(i)提供高电平信号，第一子像素电路的第一晶体管T1和第二晶体管T2导通，将数据线D提供的测试数据电压写入第三晶体管T3的控制极，通过第二晶体 管T2读取第三晶体管T3的第二极处的电信号，并通过感测线SE输出，以使外界补偿电路通过输出的电信号对第三晶体管T3的迁移率进行补偿。在空闲阶段S2，发光控制线EM(i)可以持续提供高电平信号，发光控制晶体管T7导通，以使第三晶体管T3可以产生驱动电流。
在本示例性实施方式中，给3T1C架构的第一子像素电路和第二子像素电路电连接一个发光控制晶体管，在数据写入阶段控制发光控制晶体管断开，避免数据写入过程驱动晶体管产生电流，保证在发光阶段向发光元件提供驱动电流，可以实现高灰阶等级，提高显示效果。
图5为本公开至少一实施例的子像素组的像素电路的俯视图。图6为图5中沿Q-Q’方向的局部剖面示意图。
在一些示例性实施方式中，如图5所示，在平行于显示基板的平面内，在第一方向Y上，子像素组的发光控制子电路位于第一子像素电路和第二子像素电路之间。子像素组的第一子像素电路和第二子像素电路关于所述子像素组的像素电路在第一方向Y上的中心线OY对称。在一些示例中，第一扫描线G1(i)和G1(i+1)在第一方向Y上的中心线与中心线OY重合。本示例中，第一方向Y与第二方向X交叉，例如，第一方向Y垂直于第二方向X。例如，第一方向Y平行于子像素列方向，第二方向X平行于子像素行方向。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图5所示，在平行于显示基板的平面内，子像素组的像素电路在第一方向Y上的长度可以小于200微米。上述长度可以为子像素组的第一子像素电路的第二晶体管T2的有源层20远离第二子像素电路的边界至第二子像素电路的第五晶体管T5的有源层远离第一子像素电路的边界之间的距离。本示例性实施方式可以优化像素电路的空间。
在一些示例性实施方式中，如图5所示，在平行于显示基板的平面内，在第一方向Y上，子像素组的第一子像素电路的第二晶体管T2、第三晶体管T3以及第一晶体管T1依次排布，第一存储电容Cst1位于第二晶体管T2和第三晶体管T3之间。在第一方向Y上，第二子像素电路的第四晶体管T4、第六晶体管T6、第二存储电容Cst2和第五晶体管T5沿着远离发光控制晶体管T7的一侧依次排布。发光控制晶体管T7在第一方向Y上位于第一晶体管 T1和第四晶体管T4之间。
在一些示例性实施方式中，如图5和图6所示，在垂直于显示基板的平面内，显示基板包括：衬底基板60、设置在衬底基板60上的第一导电层、半导体层、第二导电层和第三导电层。第一导电层和半导体层之间设置有第一绝缘层61，半导体层和第二导电层之间设置有第二绝缘层62，第二导电层和第三导电层之间设置有第三绝缘层63。在一些示例中，第一绝缘层61、第二绝缘层62和第三绝缘层63可以为无机绝缘层。在一些示例中，在第二导电层远离衬底基板60的一侧可以依次设置第四绝缘层、第五绝缘层、阳极层和像素定义层。例如，第四绝缘层可以为无机绝缘层，第五绝缘层可以为有机绝缘层。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图5和图6所示，第一导电层至少包括：存储电容的第二极(例如，第一存储电容Cst1的第二极52)。半导体层至少包括：多个晶体管的有源层(例如，第一晶体管T1的有源层10、第二晶体管T2的有源层20、第三晶体管T3的有源层30和发光控制晶体管T7的有源层40)、以及存储电容的第一极(例如，第一存储电容Cst1的第一极51)。第一导电层至少包括：多个晶体管的控制极(例如，第一晶体管T1的控制极13、第二晶体管T2的控制极23、第三晶体管T3的控制极33和发光控制晶体管T7的控制极43)、第一扫描线(例如，第一扫描线G1(i)和G1(i+1))、第二扫描线(例如，第二扫描线G2(i)和G2(i+1))、以及发光控制线(例如，发光控制线EM(i))。第二导电层可以包括：数据线D、第一电源线、感测线以及多个晶体管的第一极和第二极(例如，第一晶体管T1的第一极11和第二极12、第二晶体管T2的第二极22、第三晶体管T3的第一极31和第二极32、发光控制晶体管T7的第二极42)。
在一些示例性实施方式中，有源层包括沟道区和位于沟道区两侧的第一掺杂区和第二掺杂区。有源层的沟道区具有半导体特性，第一掺杂区和第二掺杂区具有导电性。有源层的第一掺杂区或第二掺杂区可以被解释为晶体管的源电极或漏电极。晶体管之间的有源层的部分可以被解释为掺杂有杂质的布线，可以用于电连接晶体管。在一些示例中，半导体层的材料可以包括金属氧化物，例如IGZO。然而，本实施例对此并不限定。例如，半导体层的 材料例如可以包括多晶硅。
在一些示例性实施方式中，如图5和图6所示，第一晶体管T1的控制极13与第一扫描线G1(i)可以为一体结构。第一晶体管T1的第一极11与数据线D可以为一体结构。第一晶体管T1的第一极11通过第五过孔K5与第一晶体管T1的有源层10的第一掺杂区电连接。第一晶体管T1的第二极12通过第六过孔K6与第一晶体管T1的有源层10的第二掺杂区电连接，还通过第六过孔K6与第三晶体管T3的控制极33电连接。在本示例中，第五过孔K5内的第三绝缘层63和第二绝缘层62被刻蚀掉，暴露出半导体层的表面。第六过孔K6的一半区域内的第三绝缘层63和第二绝缘层62被刻蚀掉，暴露出半导体层的表面，另一半区域内的第三绝缘层63被刻蚀掉，暴露出第二导电层的表面。
在一些示例性实施方式中，如图5和图6所示，第二晶体管T2的控制极23与第二扫描线G2(i)可以为一体结构。第二晶体管T2的第二极22通过第一过孔K1与第二晶体管T2的有源层20的第二掺杂区电连接。第三晶体管T3的控制极33位于第一扫描线G1(i)和第二扫描线G2(i)之间。第三晶体管T3的第一极31通过第三过孔K3与第三晶体管T3的有源层30的第一掺杂区电连接。第三晶体管的第二极32和第二晶体管T2的第二极22为一体结构。第三晶体管T3的第二极32通过第二过孔K2与第三晶体管T3的有源层30的第二掺杂区电连接，还通过第七过孔K7与第一存储电容Cst1的第二极52电连接。在本示例中，第一过孔K1、第二过孔K2和第三过孔K3内的第三绝缘层63和第二绝缘层62被刻蚀掉，暴露出半导体层的表面。第七过孔K7内的第三绝缘层63、第二绝缘层62和第一绝缘层61被刻蚀掉，暴露出第一导电层的表面。
在一些示例性实施方式中，如图5和图6所示，发光控制晶体管T7的控制极43与发光控制线EM(i)可以为一体结构。发光控制晶体管T7的第二极42通过第四过孔K4与发光控制晶体管T7的有源层40的第二掺杂区电连接。发光控制晶体管T7的第二极42与第三晶体管T3的第一极31、以及第六晶体管T6的第一极可以为一体结构。在本示例中，第四过孔K4内的第三绝缘层63和第二绝缘层62被刻蚀掉，暴露出半导体层的表面。
在一些示例性实施方式中，如图5和图6所示，第一存储电容Cst1的第一极51与第一晶体管T1的有源层10可以为一体结构，且与第一晶体管T1的有源层10的第二掺杂区电连接。第一存储电容Cst1的第二极52与第二晶体管T2的第二极22和第三晶体管T3的第二极32电连接。在本示例中，第一存储电容Cst1的第二极52在衬底基板60上的正投影与第三晶体管T3的有源层30的沟道区在衬底基板60上的正投影存在交叠。第一存储电容Cst1的第二极52还可以作为遮光电极，防止衬底基板60一侧的环境光对驱动晶体管(即第三晶体管T3)造成影响。然而，本实施例对此并不限定。
在一些示例性实施方式中，第四晶体管T4的结构与第一晶体管T1的结构关于中心线OY大致对称，第五晶体管T5的结构与第二晶体管T2的结构关于中心线OY大致对称，第六晶体管T6的结构与第三晶体管T3的结构关于中心线OY大致对称，第二存储电容Cst2的结构与第一存储电容Cst1的结构关于中心线OY大致对称。故关于第四晶体管T4、第五晶体管T5、第六晶体管T6和第二存储电容Cst2的结构可以参照第一晶体管T1、第二晶体管T2、第三晶体管T3和第一存储电容Cst1的结构，于此不再赘述。
图7为本公开至少一实施例的像素单元组的像素电路的俯视图。在一些示例中，一个像素单元组包括：六个子像素组(例如，第j列子像素组至第j+5列子像素组，其中，j为正整数)。每一子像素组包括沿第一方向Y依次排布的第一子像素电路、发光控制子电路和第二子像素电路。
图8为本公开至少一实施例的形成第一导电层后的像素单元组的像素电路的俯视图。图9为本公开至少一实施例的形成半导体层后的像素单元组的像素电路的俯视图。图10为本公开至少一实施例的形成第二导电层后的像素单元组的像素电路的俯视图。图11为本公开至少一实施例的形成第三绝缘层后的像素单元组的像素电路的俯视图。图12为本公开至少一实施例的形成第三导电层后的像素单元组的像素电路的俯视图。
在一些示例性实施方式中，如图7所示，在平行于显示基板的平面内，第一扫描线G1(i)和G1(i+1)、第二扫描线G2(i)和G2(i+1)、发光控制线EM(i)均沿第二方向X延伸。在第一方向Y上，发光控制线EM(i)位于第一扫描线G1(i)和第一扫描线G1(i+1)之间。多条数据线、两条第一电源线PL1a和PL1b、 感测线SE和第一辅助电源线FL均沿第一方向Y延伸。在第二方向X上，按照第一电源线PL1a、三条数据线(例如，数据线D(j)、D(j+1)、D(j+2))、感测线SE、第一辅助电源线FL、三条数据线(例如，数据线D(j+3)、D(j+4)、D(j+5))以及第一电源线PL1b依次排布。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图7所示，在平行于显示基板的平面内，像素单元组内的多个子像素组的第一像素电路和第二像素电路关于子像素组的像素电路在第一方向Y上的中心线OY相互对称。像素单元组的像素电路，关于像素单元组的像素电路在第二方向X上的中心线OX相互对称。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图7所示，在第二方向X上，像素单元组的两侧分别设置一条第一电源线，例如左侧设置第一电源线PL1a，右侧设置第一电源线PL1b。换言之，第一电源线位于相邻像素单元组之间。第一电源线PL1a和PL1b沿第一方向Y延伸，且沿第二方向X依次排布。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图7所示，像素单元组内的相邻子像素组之间设置有一条感测线SE和一条第一辅助电源线FL。例如，感测线SE和第一辅助电源线FL位于像素单元组的第三个子像素组和第四个子像素组之间。感测线SE和第一辅助电源线FL均沿第一方向Y延伸，且沿第二方向X排布。第一辅助电源线FL在衬底基板60上的正投影与感测线SE在衬底基板60上的正投影没有交叠。第一辅助电源线FL在衬底基板60上的正投影位于感测线SE在衬底基板60上的正投影的一侧，例如，位于靠近第j+3列子像素组的一侧。然而，本实施例对此并不限定。在本示例性实施方式中，在第二方向X上，第一电源线和感测线间隔排布，且相邻第一电源线和感测线之间设置有三个子像素组。
在一些示例性实施方式中，如图7和图8所示，显示区域的第一导电层可以包括：第一辅助电源线FL、第一存储电容Cst1的第二极52、第二存储电容Cst2的第二极。在本示例中，第一存储电容和第二存储电容的第二极可以作为遮光电极。第一存储电容的第二极52在衬底基板上的正投影可以覆盖第三晶体管的有源层的沟道区在衬底基板上的正投影，第二存储电容的第二 极在衬底基板上的正投影可以覆盖第六晶体管的有源层的沟道区在衬底基板上的正投影，以避免环境光对沟道区产生影响。
在一些示例性实施方式中，如图7和图9所示，显示区域的半导体层可以包括：像素电路的多个晶体管的有源层、第一存储电容的第一极、第二存储电容的第一极。在本示例中，像素单元组的多个子像素组的像素电路的第二晶体管的有源层20可以为一体结构。像素单元组的多个子像素组的像素电路的第二晶体管的有源层20的第一掺杂区相互电连接。子像素组的像素电路的第一晶体管的有源层10和第三晶体管的有源层30在第二方向X上相邻。像素单元组的多个子像素组的像素电路的发光控制晶体管的有源层40可以为一体结构。多个子像素组的像素电路的发光控制晶体管的有源层40的第一掺杂区可以相互电连接。第一存储电容的第一极与第一晶体管的有源层可以为一体结构，第二存储电容的第一极与第四晶体管的有源层可以为一体结构。
在一些示例性实施方式中，如图7和图10所示，显示区域的第二导电层可以包括：像素电路的多个晶体管的控制极、多条第一扫描线、多条第二扫描线和多条发光控制线。同一行像素单元组的多个子像素组的像素电路的第一晶体管的控制极与一条第一扫描线可以为一体结构，同一行像素单元组的多个子像素组的像素电路的第二晶体管的控制极与一条第二扫描线可以为一体结构，同一行像素单元组的多个子像素组的像素电路的第四晶体管的控制极与一条第一扫描线可以为一体结构，同一行像素单元组的多个子像素组的像素电路的第五晶体管的控制极与一条第二扫描线可以为一体结构。同一行像素单元组的多个子像素组的发光控制晶体管的控制极与一条发光控制线可以为一体结构。例如，子像素组的第一子像素电路的第一晶体管的控制极与第一扫描线G1(i)可以为一体结构，子像素组的第二子像素电路的第四晶体管的控制极与第一扫描线G1(i+1)可以为一体结构；第一子像素电路的第二晶体管的控制极与第二扫描线G2(i)可以为一体结构，第二子像素电路的第五晶体管的控制极与第一扫描线G2(i+1)可以为一体结构；发光控制子电路的发光控制晶体管的控制极与发光控制线EM(i)可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图7、图11和图12所示，第三导电层可 以包括：多条第一电源线、多条数据线、感测线SE以及像素电路的多个晶体管的第一极和第二极。感测线SE通过第八过孔K8与第一子像素电路的第二晶体管的有源层20的第一掺杂区电连接，通过第九过孔K9与第二子像素电路的第二晶体管的有源层的第一掺杂区电连接。在本示例中，一条感测线SE与一个像素单元组的多个子像素组的像素电路电连接。第一电源线PL1a通过第十过孔K10与发光控制子电路的发光控制晶体管T7的有源层的第一掺杂区电连接，第一电源线PL1b通过第十一过孔K11与发光控制子电路的发光控制晶体管T7的有源层的第一掺杂区电连接。
在一些示例性实施方式中，如图7至图12所示，一个像素单元组包括沿第二方向X依次排布的六个子像素组，第一个子像素组和第二个子像素组之间设置有两条数据线(即数据线D(j)和D(j+1))，第二个子像素组和第三个子像素组之间设置有一条数据线(即数据线D(j+2))。第一个子像素组的像素电路与第二个子像素组的像素电路，关于两者在第二方向X的中心线大致对称。例如，第一个子像素组的像素电路和第二个子像素组的像素电路在第二方向X上的中心线可以与数据线D(j)和D(j+1)在第二方向X上的中心线重合。然而，本实施例对此并不限定。在本示例中，第二个子像素组的像素电路和第三个子像素组的像素电路的结构可以大致相同，故于此不再赘述。像素单元组的像素电路关于像素单元组的像素电路在第二方向X上的中心线OX大致对称。
本示例性实施方式提供的显示基板，通过设置共用发光控制子电路的子像素组，可以减少发光控制线的数量，从而优化空间排布，有效增加分辨率。
图13为本公开至少一实施例的多个像素单元组的像素电路的俯视图。图13示意了排布为两行两列的四个像素单元组(例如，第b行第k列像素单元组、第b行第k+1列像素单元组、第b+1行第k列像素单元组、第b+1行第k+1列像素单元组，b和k均为整数)。如图13所示，在第二方向X上，相邻两个像素单元组共用一条第一电源线。例如，第b行第k列像素单元组和第b行第k+1列像素单元组共用第一电源线PL1b。然而，本实施例对此并不限定。
图14为本公开至少一实施例的第一辅助电源线的排布示意图。在一些示 例性实施方式中，如图14所示，显示基板包括：显示区域AA和位于显示区域AA周边的边框区域BB。边框区域BB具有第一连接区DD和第二连接区EE。显示区域AA设置有多条第一辅助电源线FL。多条第一辅助电源线FL沿第一方向Y延伸，且沿第二方向X排布。例如，至少一条第一辅助电源线FL位于像素单元组内的相邻子像素组之间，例如在第二方向X上，相邻两条第一辅助电源线FL之间可以设置有三个子像素组。第一辅助电源线FL沿第一方向Y可以从显示区域AA延伸至第一连接区DD和第二连接区EE。在第一连接区DD和第二连接区EE，第一辅助电源线FL可以通过连接电极与第一发光元件和第二发光元件的第二极电连接。在一些示例中，第一辅助电源线FL位于第一导电层，可以通过位于第三导电层和阳极层的连接电极与第一发光元件和第二发光元件的第二极电连接。本实施例的第一辅助电源线可以起到降低第一发光元件和第二发光元件的第二极的电阻的作用，进而降低第二电源线的IR压降(IR drop)。
下面通过显示基板的制备过程的示例说明显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
本公开所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的投影包含B的投影”，是指B的投影的边界落入A的投影的边界范围内，或者A的投影的边界与B的投影的边界重叠。
在一些示例性实施方式中，显示基板的制备过程可以包括如下操作，如图5至图12所示。本示例性实施方式中以显示基板为顶发射型显示基板，并以一个像素单元组为例进行说明。
(1)、形成第一导电层图案。
在一些示例性实施方式中，在衬底基板60上沉积第一导电薄膜，通过构图工艺对第一导电薄膜进行构图，形成第一导电层图案。如图8所示，第一导电层可以包括：第一辅助电源线FL、第一存储电容的第二极52以及第二存储电容的第二极。在本示例中，第一存储电容的第二极52和第二存储电容的第二极还可以作为遮光电极，保护像素电路的驱动晶体管的有源层的沟道区域。
在一些示例性实施方式中，衬底基板60可以为刚性衬底或柔性衬底。刚性衬底可以包括玻璃、金属箔片中的一种或多种。柔性衬底可以包括聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。然而，本实施例对此并不限定。
(2)、形成半导体层图案。
在一些示例性实施方式中，在形成前述图案的衬底基板60上，依次沉积第一绝缘薄膜和半导体薄膜，通过构图工艺对半导体薄膜进行构图，形成第一绝缘层61以及形成在第一绝缘层61上的半导体层图案。如图9所示，半导体层可以具有弯曲或弯折形状。半导体层可以包括：像素电路的多个晶体管的有源层、第一存储电容的第一极以及第二存储电容的第一极。在本示例中，第一子像素电路的第一晶体管的有源层与第一存储电容的第一极可以为一体结构，第二子像素电路的第四晶体管的有源层与第二存储电容的第一极可以为一体结构。
(3)、形成第二导电层图案。
在一些示例性实施方式中，在形成前述图案的衬底基板60上，依次沉积第二绝缘薄膜和第二导电薄膜，通过构图工艺对第二导电薄膜进行构图，形成第二绝缘层62以及形成在第二绝缘层62上的第二导电层。如图10所示，第二导电层可以包括：像素电路的多个晶体管的控制极、多条第一扫描线、多条第二扫描线和多条发光控制线。
(4)、形成第三导电层图案。
在一些示例性实施方式中，在形成前述图案的衬底基板60上，沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成第三绝缘层63图案。第三绝缘层63上开设有多个过孔图案。例如，第一过孔K1、第二过孔K2、第三过孔K3、第四过孔K4、第五过孔K5、第八过孔K8至第十一过孔K11内的第三绝缘层63和第二绝缘层62被刻蚀掉，暴露出半导体层的表面；第六过孔K6的一半区域内的第三绝缘层63和第二绝缘层62被刻蚀掉，暴露出半导体层的表面，另一半区域内的第三绝缘层63被刻蚀掉，暴露出第二导电层的表面；第七过孔K7内的第三绝缘层63、第二绝缘层62和第一绝缘层61被刻蚀掉，暴露出第一导电层的表面。多个过孔在衬底基板60上的正投影可以呈矩形或圆形。然而，本实施例对此并不限定。
在一些示例性实施方式中，在形成前述图案的衬底基板60上，沉积第三导电薄膜，通过构图工艺对第三导电薄膜进行构图，在第三绝缘层63上形成第三导电层图案。如图12所示，第三导电层可以包括：多条第一电源线、多条数据线、感测线SE以及像素电路的多个晶体管的第一极和第二极。
在一些示例性实施方式中，在形成前述图案的衬底基板60上，沉积第四绝缘薄膜，形成第四绝缘层。然后，涂覆第五绝缘薄膜，通过对第五绝缘薄膜的掩模、曝光和显影，形成第五绝缘层图案。第五绝缘层上开设有多个暴露出第四绝缘层的过孔。然后，对暴露出的第四绝缘层进行刻蚀，在第四绝缘层上形成多个过孔，以暴露出第三导电层的表面。
在一些示例性实施方式中，在形成有前述图案的衬底基板60上沉积第四导电薄膜，通过构图工艺对第四导电薄膜进行构图，在第五绝缘层上形成阳极层图案。阳极层至少包括：子像素组的第一发光元件的第一极、第二发光元件的第一极。第一发光元件的第一极可以通过第四绝缘层和第五绝缘层上的过孔与第一子像素电路的第三晶体管的第二极电连接。第二发光元件的第一极可以通过第四绝缘层和第五绝缘层上的过孔与第二子像素电路的第六晶体管的第二极电连接。在一些示例中，阳极层可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或采用上述金属中任意一种或多种制成的合金。
在一些示例性实施方式中，在形成前述图案的衬底基板60上涂覆像素定 义薄膜，通过掩模、曝光和显影工艺形成像素定义层图案。每个子像素组的像素定义层形成有暴露出第一发光元件的第一极的第一像素开口和暴露出第二发光元件的第二极的第二像素开口。
在一些示例性实施方式中，可以在形成的第一像素开口内形成第一发光元件的第一有机发光层，第一有机发光层与第一发光元件的第一极电连接；在形成的第二像素开口内形成第二发光元件的第二有机发光层，第二有机发光层与第二发光元件的第一极电连接。随后，沉积透明导电薄膜，通过构图工艺对透明薄膜进行构图，形成第一发光元件的第二极和第二发光元件的第二极图案。例如，第一发光元件和第二发光元件的第二极可以用氧化铟锡(ITO)或氧化铟锌(IZO)等透明导电材料。随后，可以在第一发光元件和第二发光元件的第二极上形成封装层。封装层可以包括无机材料/有机材料/无机材料的叠层结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一导电层、第二导电层和第三导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。在一些示例中，第一导电层所采用的金属材料的遮光性能可以强于第二导电层和第三导电层所采用的金属材料。第一绝缘层61、第二绝缘层62、第三绝缘层63、第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第五绝缘层和像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。半导体层可以采用金属氧化物或多晶硅。然而，本实施例对此并不限定。
本公开所示结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，像素电路和第一发光元件的第一极以及第二发光元件的第一极之间可以通过连接电极电连接。然而，本公开在此不做限定。
本公开的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
图15为本公开至少一实施例的像素单元组的像素电路的另一俯视示意图。在一些示例性实施方式中，如图15所示，像素单元组内的相邻子像素组之间设置有两条第一辅助电源线FLa和FLb、以及一条感测线SE。例如，像素单元组包括沿第二方向X依次排布的六个子像素组，两条第一辅助电源线FLa和FLb以及一条感测线SE可以位于像素单元组的第三个子像素组和第四个子像素组之间。两条第一辅助电源线FLa和FLb位于第一导电层，感测线SE位于第三导电层。两条第一辅助电源线FLa和FLb在衬底基板上的正投影在第二方向X上可以位于感测线SE在衬底基板上的正投影的相对两侧。两条第一辅助电源线FLa和FLb在衬底基板上的正投影与感测线SE在衬底基板上的正投影可以没有交叠。
在本示例性实施方式中，通过在像素单元组内的相邻子像素组之间设置两条第一辅助电源线，可以进一步降低第二电源线的IR压降。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图16为本公开至少一实施例的像素单元组的像素电路的另一俯视示意图。在一些示例性实施方式中，如图16所示，像素单元组内的相邻子像素组之间设置有一条感测线SE、一条第一辅助电源线FL和一条第二辅助电源线HL。例如，像素单元组包括沿第二方向X依次排布的六个子像素组，一条第一辅助电源线FL、一条第二辅助电源线HL以及一条感测线SE可以位于像素单元组的第三个子像素组和第四个子像素组之间。感测线SE和第二辅助电源线HL可以位于第三导电层，第一辅助电源线FL可以位于第一导电层。第一辅助电源线FL在衬底基板上的正投影与感测线SE在衬底基板上的正投影存在交叠。第二辅助电源线HL在衬底基板上的正投影与感测线SE在衬底基板上的正投影可以没有交叠。在第二方向X上，第二辅助电源线HL可以位于感测线SE的一侧，例如，靠近第j+3列子像素组的一侧。第二辅助电源线HL可以通过第十二过孔K12与发光控制晶体管的有源层的第一掺杂区电连接。第二辅助电源线HL与第一电源线PL1a和PL1b可以通过发光控制晶体管的有源层实现电连接。在一些示例中，第二辅助电源线HL的宽度(即沿第二方向X的长度)可以小于第一电源线PL1a或PL1b的宽度。在本公开 中，宽度表示在延伸方向的垂直方向的特征尺寸。
本示例性实施方式中，通过在像素单元组内的相邻子像素组之间设置第二辅助电源线，可以降低第一电源线的IR压降。
在另一些示例性实施方式中，像素单元组包括沿第二方向X依次排布的六个子像素组，一条第一辅助电源线、一条第二辅助电源线以及一条感测线可以位于像素单元组的第三个子像素组和第四个子像素组之间。第二辅助电源线可以与第一辅助电源线为同层结构，例如均位于第一导电层。感测线可以位于第三导电层。第二辅助电源线可以通过第一绝缘层上的过孔与发光控制晶体管的有源层的第一掺杂区电连接。在一些示例中，感测线在衬底基板上的正投影可以位于第一辅助电源线和第二辅助电源线在衬底基板上的正投影的中间。感测线、第一辅助电源线和第二辅助电源线在衬底基板上的正投影可以没有交叠。然而，本实施例对此并不限定。例如，感测线、第一辅助电源线和第二辅助电源线可以位于第二个子像素组和第三个子像素组之间，或者，第四个子像素组和第五个子像素组之间。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
图17为本公开至少一实施例的像素单元组的像素电路的另一俯视示意图。在一些示例性实施方式中，如图17所示，像素单元组内的相邻子像素组之间设置有一条感测线SE和一条第一辅助电源线FL。例如，像素单元组包括沿第二方向X依次排布的六个子像素组，一条第一辅助电源线FL以及一条感测线SE可以位于像素单元组的第三个子像素组和第四个子像素组之间。感测线SE和第一辅助电源线FL均位于第三导电层。第一辅助电源线FL可以位于感测线SE的一侧，例如，靠近第j+3列子像素组的一侧。然而，本实施例对此并不限定。例如，第一辅助电源线FL可以位于感测线SE靠近第j+2列子像素组的一侧。
在另一些示例性实施方式中，像素单元组内的相邻子像素组之间(例如，第三个子像素组和第四个子像素组之间)可以设置一条感测线和两条第一辅助电源线。感测线和两条第一辅助电源线可以均位于第三导电层，且在第二方向X上两条第一辅助电源线可以位于感测线的相对两侧。
在另一些示例性实施方式中，像素单元组内的相邻子像素组之间(例如，第三个子像素组和第四个子像素组之间)可以设置一条感测线、一条第一辅助电源线和一条第二辅助电源线。感测线、第一辅助电源线和第二辅助电源线可以均位于第三导电层，且在第二方向上第一辅助电源线和第二辅助电源线可以位于感测线的相对两侧。第二辅助电源线可以与发光控制晶体管的有源层的第一掺杂区电连接。
关于本实施例的显示基板的其余结构可以参照前述实施例的说明，故于此不再赘述。
本示例性实施例提供的显示基板，通过设置多条第一辅助电源线，可以降低第二电源线的IR压降。而且，通过设置第二辅助电源线，可以降低第一电源线的IR压降。
图18为本公开至少一实施例的显示装置的示意图。如图18所示，本实施例提供一种显示装置91，包括前述实施例的显示基板910。在一些示例中，显示基板910可以为OLED显示基板或者QLED显示基板。显示装置91可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (21)

  1. 一种显示基板，包括：
    衬底基板，包括显示区域；
    多个像素单元组，位于所述显示区域；
    至少一个像素单元组包括多个子像素组，至少一个子像素组包括像素电路；所述像素电路包括：第一子像素电路、第二子像素电路以及发光控制子电路，所述第一子像素电路和第二子像素电路均与所述发光控制子电路电连接，所述发光控制子电路被配置为控制与所述第一子像素电路电连接的第一发光元件发光，以及控制与所述第二子像素电路电连接的第二发光元件发光；
    所述第一子像素电路和第二子像素电路关于所述子像素组的像素电路在第一方向上的中心线大致对称。
  2. 根据权利要求1所述的显示基板，其中，在所述第一方向上，所述像素电路的发光控制子电路位于所述第一子像素电路和第二子像素电路之间。
  3. 根据权利要求1或2所述的显示基板，其中，所述发光控制子电路与发光控制线电连接，所述发光控制线沿第二方向延伸，且位于所述第一子像素电路和第二子像素电路之间；所述第二方向与所述第一方向交叉。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述发光控制子电路包括：发光控制晶体管；所述发光控制晶体管的控制极与发光控制线电连接，所述发光控制晶体管的第一极与第一电源线电连接，所述发光控制晶体管的第二极与所述第一子像素电路和第二子像素电路电连接。
  5. 根据权利要求1至4中任一项所述的显示基板，其中，所述至少一个子像素组还包括：与所述第一子像素电路电连接的所述第一发光元件、与所述第二子像素电路电连接的所述第二发光元件；所述第一发光元件的第一极与所述第一子像素电路电连接，所述第二发光元件的第一极与所述第二子像素电路电连接，所述第一发光元件和所述第二发光元件的第二极均与第二电源线电连接；
    所述衬底基板还包括：位于所述显示区域周边的边框区域；
    所述显示区域设置有多条沿所述第一方向延伸的第一辅助电源线，至少 一条第一辅助电源线在所述边框区域与所述第一发光元件和所述第二发光元件的第二极电连接。
  6. 根据权利要求5所述的显示基板，其中，在与所述第一方向交叉的第二方向上，至少一条第一辅助电源线位于至少一个像素单元组内的相邻子像素组之间。
  7. 根据权利要求1至6中任一项所述的显示基板，其中，所述衬底基板的显示区域还设置有多条沿所述第一方向延伸的第一电源线；至少一条第一电源线位于相邻像素单元组之间。
  8. 根据权利要求7所述的显示基板，其中，相邻像素单元组共用一条所述第一电源线。
  9. 根据权利要求1至8中任一项所述的显示基板，其中，至少一个像素单元组的每个子像素组包括所述像素电路，所述至少一个像素单元组关于所述像素单元组的多个像素电路在第二方向上的中心线大致对称，所述第二方向与所述第一方向交叉。
  10. 根据权利要求1至9中任一项所述的显示基板，其中，所述衬底基板的显示区域还设置有多条沿所述第一方向延伸的感测线；至少一条感测线位于所述至少一个像素单元组内的相邻子像素组之间。
  11. 根据权利要求10所述的显示基板，其中，至少一个像素单元组内的相邻子像素组之间设置有一条感测线和一条第一辅助电源线；所述感测线在所述衬底基板上的正投影位于所述第一辅助电源线在所述衬底基板上的正投影的一侧。
  12. 根据权利要求10所述的显示基板，其中，至少一个像素单元组内的相邻像子像素组之间设置有一条感测线和两条第一辅助电源线；
    所述两条第一辅助电源线在所述衬底基板上的正投影分别位于所述感测线在所述衬底基板上的正投影的两侧。
  13. 根据权利要求11或12所述的显示基板，其中，所述第一辅助电源线与感测线为同层结构。
  14. 根据权利要求10所述的显示基板，其中，至少一个像素单元组内的 相邻子像素组之间设置有一条第一辅助电源线、一条感测线和一条第二辅助电源线；所述第二辅助电源线沿所述第一方向延伸并与第一电源线电连接；
    所述第一辅助电源线在所述衬底基板上的正投影与所述感测线在所述衬底基板上的正投影存在交叠，且所述第二辅助电源线在所述衬底基板上的正投影位于所述感测线在所述衬底基板上的正投影的一侧。
  15. 根据权利要求11、12或14所述的显示基板，其中，在垂直于所述显示基板的平面内，所述第一辅助电源线位于所述感测线靠近所述衬底基板的一侧。
  16. 根据权利要求1至15中任一项所述的显示基板，其中，所述至少一个像素单元组包括：沿第二方向依次排布的六个子像素组，第一个子像素组和第二个子像素组的像素电路关于所述第一个和第二个子像素组的像素电路在所述第二方向上的中心线大致对称，所述第二方向与所述第一方向交叉。
  17. 根据权利要求16中任一项所述的显示基板，其中，所述衬底基板的显示区域还设置有沿所述第一方向延伸的多条数据线；所述第一个子像素组和第二个子像素组的像素电路之间排布有两条数据线，所述第二个子像素组和第三个子像素组的像素电路之间排布有一条数据线。
  18. 根据权利要求1至17中任一项所述的显示基板，其中，所述第一子像素电路包括：第一晶体管、第二晶体管、第三晶体管以及第一存储电容；
    所述第一晶体管的控制极与第i条第一扫描线电连接，所述第一晶体管的第一极与数据线电连接，所述第一晶体管的第二极与所述第三晶体管的控制极电连接；所述第二晶体管的控制极与第i条第二扫描线电连接，所述第二晶体管的第一极与感测线电连接，所述第二晶体管的第二极与所述第三晶体管的第二极电连接；所述第三晶体管的第一极与所述发光控制子电路电连接；所述第一存储电容的第一极与所述第三晶体管的控制极电连接，所述第一存储电容的第二极与所述第三晶体管的第二极电连接；所述第三晶体管的第二极与所述第一发光元件的第一极电连接；
    所述第二子像素电路包括：第四晶体管、第五晶体管、第六晶体管以及第二存储电容；
    所述第四晶体管的控制极与第i+1条第一扫描线电连接，所述第四晶体管的第一极与所述数据线电连接，所述第四晶体管的第二极与所述第六晶体管的控制极电连接；所述第五晶体管的控制极与第i+1条第二扫描线电连接，所述第五晶体管的第一极与所述感测线电连接，所述第五晶体管的第二极与所述第六晶体管的第二极电连接；所述第六晶体管的第一极与所述发光控制子电路电连接；所述第二存储电容的第一极与所述第六晶体管的控制极电连接，所述第二存储电容的第二极与所述第六晶体管的第二极电连接；所述第六晶体管的第二极与所述第二发光元件的第一极电连接；其中，i为自然数。
  19. 根据权利要求18所述的显示基板，其中，在垂直于所述显示基板的平面内，所述显示基板包括：设置在所述衬底基板上的第一导电层、半导体层、第二导电层和第三导电层；
    所述第一导电层至少包括：所述像素电路的第一存储电容的第二极和第二存储电容的第二极；
    所述半导体层至少包括：所述像素电路的多个晶体管的有源层、所述第一存储电容的第一极和第二存储电容的第二极；
    所述第二导电层至少包括：所述像素电路的多个晶体管的控制极、所述第一扫描线、所述第二扫描线、以及所述发光控制线；
    所述第三导电层至少包括：所述数据线以及所述感测线。
  20. 根据权利要求19所述的显示基板，其中，与所述第一发光元件和第二发光元件的第二极电连接的第一辅助电源线位于所述第一导电层或者所述第三导电层。
  21. 一种显示装置，包括如权利要求1至20中任一项所述的显示基板。
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CN111028774A (zh) * 2019-12-16 2020-04-17 深圳市华星光电半导体显示技术有限公司 显示面板及显示终端
CN111564140A (zh) * 2020-06-12 2020-08-21 京东方科技集团股份有限公司 显示基板及显示装置

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