WO2022006846A1 - 基于数字信号处理的脉冲宽度调制端口复用电路和装置 - Google Patents

基于数字信号处理的脉冲宽度调制端口复用电路和装置 Download PDF

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WO2022006846A1
WO2022006846A1 PCT/CN2020/101313 CN2020101313W WO2022006846A1 WO 2022006846 A1 WO2022006846 A1 WO 2022006846A1 CN 2020101313 W CN2020101313 W CN 2020101313W WO 2022006846 A1 WO2022006846 A1 WO 2022006846A1
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Prior art keywords
logic gate
port
pulse width
width modulation
power supply
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PCT/CN2020/101313
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English (en)
French (fr)
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唐建军
赵德琦
吴壬华
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深圳欣锐科技股份有限公司
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Priority to PCT/CN2020/101313 priority Critical patent/WO2022006846A1/zh
Priority to CN202080005563.3A priority patent/CN114175506B/zh
Publication of WO2022006846A1 publication Critical patent/WO2022006846A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries

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  • the present application relates to the technical field of electronic circuits, in particular to a pulse width port multiplexing circuit and device based on digital signal processing.
  • PWM Pulse Width Modulation
  • DSP Digital Signal Processing
  • the embodiments of the present application provide a pulse width modulation port multiplexing circuit and device based on digital signal processing, which can realize the pulse width modulation port in the forward working state of the circuit as the pulse width modulation port required in the reverse working state of the circuit. It can effectively solve the problem that the pulse width modulation port of the digital signal processing of the two-way operation of the power supply is not enough, and the discrete components are reduced, the circuit is simplified, and the promotion is easy.
  • a first aspect of the embodiments of the present application provides a digital signal processing-based pulse width modulation port multiplexing circuit, including a control unit and a pulse width modulation port multiplexing circuit, wherein:
  • the power supply end of the control unit is connected to the power supply, the ground end of the control unit is connected to the ground wire, the first output port of the control unit is connected to the first input port of the pulse width modulation port multiplexing circuit, the control unit the second output port is connected to the second input port of the pulse width modulation port multiplexing circuit;
  • the control unit receives the control signal and transmits the control signal to the pulse width modulation port multiplexing circuit, and the pulse width modulation port multiplexing circuit realizes the forward working state of the bidirectional power supply after receiving the control signal
  • the pulse width modulation port in the lower state is used as the pulse width modulation port required in the reverse working state of the bidirectional power supply.
  • control unit includes a digital signal processing control chip, wherein:
  • the power supply terminal of the digital signal processing control chip is connected to the power supply, the ground terminal of the digital signal processing control chip is connected to the ground wire, and the first pulse width modulation port of the digital signal processing control chip is connected to the pulse width modulation port multiplexing the first input port of the circuit, the second pulse width modulation port of the digital signal processing control chip is connected to the second input port of the pulse width modulation port multiplexing circuit;
  • the digital signal processing control chip receives a control signal and transmits the control signal to the pulse width modulation port multiplexing circuit, where the control signal is used to control the working state of the pulse width modulation port multiplexing circuit.
  • the PWM port multiplexing circuit includes a first AND logic gate, a second AND logic gate, a third AND logic gate, and a fourth AND logic gate, wherein:
  • the power supply is respectively connected to the power supply end of the first AND logic gate, the power supply end of the second AND logic gate, the power supply end of the third AND logic gate and the power supply end of the fourth AND logic gate;
  • the ground terminal of the first AND logic gate, the ground terminal of the second AND logic gate, the ground terminal of the third AND logic gate, and the ground terminal of the fourth AND logic gate are respectively connected to ground lines;
  • the first input port of an AND logic gate and the first input port of the second AND logic gate are connected to the first pulse width modulation port of the digital signal processing control chip, and the first input port of the third AND logic gate and the first input port of the fourth AND logic gate is connected to the second pulse width modulation port of the digital signal processing control chip, the second input port of the first AND logic gate, the second AND logic gate
  • the second input port, the second input port of the third AND logic gate, and the second input port of the fourth AND logic gate are connected to the digital signal processing control chip through an I/O interface, and the first AND logic gate
  • the first AND logic gate, the second AND logic gate, the third AND logic gate, and the fourth AND logic gate are used for transmitting and processing control signals.
  • the forward working state includes that the bidirectional power supply is charged by the grid;
  • the pulse width modulation port multiplexing circuit is in a forward working state.
  • the reverse working state includes that the bidirectional power supply supplies power to the grid or to electrical appliances;
  • the pulse width modulation port multiplexing circuit is in a reverse working state.
  • the bidirectional power supply includes an on-board power supply or a photovoltaic inverter.
  • the first AND logic gate, the second AND logic gate, the third AND logic gate and the fourth AND logic gate are all complementary metal oxide semiconductor AND logic gates .
  • the ground terminal of the first AND logic gate, the ground terminal of the second AND logic gate, the ground terminal of the third AND logic gate, and the ground terminal of the fourth AND logic gate are connected to the same ground terminal.
  • a second aspect of the embodiments of the present application provides an apparatus for pulse width modulation port multiplexing based on digital signal processing, including a power supply and the digital signal processing-based pulse pulse described in any one of the first aspect of the embodiments of the present application. Width modulation port multiplexing circuit.
  • the power supply includes a first auxiliary power supply and a second auxiliary power supply
  • the first auxiliary power supply supplies power to the digital signal processing control chip
  • the second auxiliary power supply is the first auxiliary power supply
  • the AND logic gate, the second AND logic gate, the third AND logic gate, and the fourth AND logic gate are powered.
  • a pulse width modulation port multiplexing circuit based on digital signal processing includes a control unit and a pulse width modulation port multiplexing circuit, wherein:
  • the power supply end of the control unit is connected to the power supply, the ground end of the control unit is connected to the ground wire, the first output port of the control unit is connected to the first input port of the pulse width modulation port multiplexing circuit, the control unit the second output port is connected to the second input port of the pulse width modulation port multiplexing circuit;
  • the control unit receives the control signal and transmits the control signal to the pulse width modulation port multiplexing circuit, and the pulse width modulation port multiplexing circuit realizes the forward working state of the bidirectional power supply after receiving the control signal
  • the pulse width modulation port in the lower state is used as the pulse width modulation port required in the reverse working state of the bidirectional power supply.
  • the PWM port in the forward working state of the circuit can be used as the PWM port required in the reverse working state of the circuit, so as to effectively solve the PWM port for digital signal processing in the bidirectional operation of the power supply. Not enough problems, and reduce discrete components, simplify the circuit, easy to promote.
  • FIG. 1 is a schematic structural diagram of a pulse width modulation port multiplexing circuit based on digital signal processing disclosed in an embodiment of the present application;
  • FIG. 2 is a schematic structural diagram of another pulse width modulation port multiplexing circuit based on digital signal processing disclosed in an embodiment of the application;
  • 3a is a schematic structural diagram of another pulse width modulation port multiplexing circuit based on digital signal processing disclosed in an embodiment of the present application;
  • 3b is a schematic diagram of a control signal of a pulse width modulation port multiplexing circuit based on digital signal processing disclosed in an embodiment of the present application;
  • FIG. 4 is a schematic structural diagram of an apparatus for multiplexing of pulse width modulation ports based on digital signal processing disclosed in an embodiment of the present application.
  • Embodiments of the present application provide a pulse width modulation port multiplexing circuit and device based on digital signal processing, which will be described in detail below.
  • FIG. 1 is a schematic structural diagram of a pulse width modulation port multiplexing circuit based on digital signal processing disclosed in an embodiment of the present application.
  • the pulse width modulation port multiplexing circuit based on digital signal processing described in this embodiment includes a control unit 10 and a PWM port multiplexing circuit 20, wherein:
  • the power supply terminal 11 of the control unit 10 is connected to the power supply, the ground terminal 14 of the control unit 10 is connected to the ground wire, the first output port 12 of the control unit 10 is connected to the first input port 21 of the PWM port multiplexing circuit 20, and the second The output port 13 is connected to the second input port 22 of the PWM port multiplexing circuit 20;
  • the control signal is output from the first output port 12 of the control unit 10 and the second output port 13 of the control unit 10 through the first input port 21 of the PWM port multiplexing circuit 20 and the second input port of the PWM port multiplexing circuit 20 respectively.
  • 22 flows into the PWM port multiplexing circuit 20, and the PWM port multiplexing circuit 20 is used to realize the PWM port in the forward working state of the bidirectional power supply as the PWM port required in the reverse working state of the bidirectional power supply.
  • control unit 10 is an integration of at least one DSP control chip
  • the PWM port multiplexing circuit 20 is an integration of at least four AND logic gates and lines connected between the AND logic gates, and the control unit 10 generates control The signal is transmitted to the PWM port multiplexing circuit 20 through the connection line, and is used to control the working state of the PWM port multiplexing circuit 20.
  • the bidirectional power supply is the application scenario of the embodiment of the present application, and the above-mentioned bidirectional power supply is specifically a bidirectional power supply that requires PWM port multiplexing.
  • the forward working state of the bidirectional power supply includes the bidirectional power supply being charged by the grid, and the reverse working state of the bidirectional power supply is that the bidirectional power supply supplies power to the grid or to electrical appliances.
  • the forward work will not be performed at the same time, so the working state of the PWM port multiplexing circuit 20 is controlled by the control signal generated by the control unit 10, so as to realize that the PWM port in forward operation can also be used as the PWM port required in reverse operation. .
  • FIG. 2 is a schematic structural diagram of a pulse width modulation port multiplexing circuit based on digital signal processing disclosed in an embodiment of the present application.
  • the control unit 10 described in this embodiment includes a DSP control chip 101, wherein:
  • the power supply terminal 111 of the DSP control chip 101 is connected to the power supply, the ground terminal 114 of the DSP control chip 101 is connected to the ground wire, the first PWM port 112 of the DSP control chip 101 is connected to the first input port 21 of the PWM port multiplexing circuit 20, and the DSP control chip
  • the second PWM port 113 of 101 is connected to the second input port 22 of the PWM port multiplexing circuit 20;
  • the control signal is output from the first PWM port 112 of the DSP control chip 101 and the second PWM port 113 of the DSP control chip 101, respectively, through the first input port 21 of the PWM port multiplexing circuit 20 and the second input port of the PWM port multiplexing circuit 20.
  • the input port 22 flows into the PWM port multiplexing circuit 20 , and the control signal is used to control the working state of the PWM port multiplexing circuit 20 .
  • the DSP control chip 101 is a TMS320F28004X series control chip, which is a powerful 32-bit floating-point microcontroller unit (MCU), which allows designers to integrate key components on a single device control peripherals, differential analog and non-volatile memory; at the same time, high-performance analog blocks are integrated on this series of chips to further support system integration, three independent 12-bit analog-to-digital converters (Analog to Digital Converter, ADC ) to accurately and efficiently manage multiple analog signals, ultimately increasing system throughput, seven programmable gain amplifiers (PGAs) on the analog front end enable on-chip voltage regulation before conversion, seven analog comparators
  • ADC analog to Digital Converter
  • PGAs programmable gain amplifiers
  • the module provides continuous monitoring of input voltage levels for trip conditions; in addition, the family of chips includes industry-leading control peripherals that allow for best-in-class control of the system, supports connectivity through a variety of industry-standard communication ports, and provides multiple Multiplexing for optimal signal placement in various applications.
  • FIG. 3a is a schematic structural diagram of a pulse width modulation port multiplexing circuit based on digital signal processing disclosed in an embodiment of the present application.
  • the PWM port multiplexing circuit 20 described in this embodiment includes a first AND logic gate 201, a second AND logic gate 301, a third AND logic gate 401 and a fourth AND logic gate 501, wherein:
  • the power supply terminal 211 of the first AND logic gate 201, the power supply terminal 311 of the second AND logic gate 301, the power supply terminal 411 of the third AND logic gate 401, and the power supply terminal 511 of the fourth AND logic gate 501 are connected to the power supply.
  • the ground terminal 213 of the gate 201, the ground terminal 313 of the second AND logic gate 301, the ground terminal 413 of the third AND logic gate 401 and the ground terminal 513 of the fourth AND logic gate 501 are connected to the ground wire;
  • the first input port 215 and the first input port 315 of the second AND logic gate 301 are connected to the first PWM port 112 of the DSP control chip 101 , the first input port 414 of the third AND logic gate 401 and the fourth AND logic gate 501 .
  • the first input port 514 is connected to the second PWM port 113 of the DSP control chip 101 , the second input port 214 of the first AND logic gate 201 , the second input port 314 of the second AND logic gate 301 , and the third AND logic gate 401 .
  • the second input port 415 and the second input port 515 of the fourth AND logic gate 501 are connected to the DSP control chip 101 through the I/O interface, the output port 212 of the first AND logic gate 201 and the output port 312 of the second AND logic gate 301 , the output port 412 of the third AND logic gate 401 and the output port 512 of the fourth AND logic gate 501 are respectively connected to different driver chips;
  • the first AND logic gate 201, the second AND logic gate 301, the third AND logic gate 401 and the fourth AND logic gate 501 are used for transmitting and processing control signals;
  • the control signal is output from the first PWM port 112 of the DSP control chip 101 and transmitted to the first input port 215 of the first AND logic gate 201 and the first input port 315 of the second AND logic gate 301, and the control signal is also sent from the DSP control chip.
  • the second PWM port 113 of the The control signals received by the second input port 314 of the second AND logic gate 301 , the second input port 415 of the third AND logic gate 401 and the second input port 515 of the fourth AND logic gate 501 are controlled by the DSP control chip 101 according to the PWM The working state of the port multiplexing circuit 20 is controlled;
  • the ports 415 are all high level, the second input port 314 of the second AND logic gate 301 and the second input port 515 of the fourth AND logic gate 501 are both low level, then the output port 212 of the first AND logic gate 201 and the output port 412 of the third AND logic gate 401 are both high level, the output port 312 of the second AND logic gate 301 and the output port 512 of the fourth AND logic gate 501 are both low level, then the first AND logic gate
  • the output port 212 of the 201 and the output port 412 of the third AND logic gate 401 output a drive signal, and the drive signal makes the connected drive chip enter the working state by controlling the rear switch.
  • the above process is the process of the PWM port multiplexing circuit 20. Forward working state; when the first input port 315 of the second AND logic gate 301, the second input port 314 of the second AND logic gate 301, the first input port 514 of the fourth AND logic gate 501 and the fourth AND logic gate
  • the second input port 515 of 501 is both high level
  • the second input port 214 of the first AND logic gate 201 and the second input port 415 of the third AND logic gate 401 are both low level
  • the output port 312 of 301 and the output port 512 of the fourth AND logic gate 501 are both high level
  • the output port 212 of the first AND logic gate 201 and the output port 412 of the third AND logic gate 401 are both low level
  • the output port 312 of the second AND logic gate 301 and the output port 512 of the fourth AND logic gate 501 output a driving signal, and the driving signal causes the connected driving chip to enter the working state by controlling the back-pole switch.
  • the above process is the P
  • the first AND logic gate 201, the second AND logic gate 301, the third AND logic gate 401, and the fourth AND logic gate 501 are all complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) and Logic gates, CMOS and logic gates allow a wide range of power supply voltages, which is convenient for the design of power supply circuits.
  • CMOS complementary Metal Oxide Semiconductor
  • the logic swing is large, which makes the circuit strong anti-interference ability and low static power consumption.
  • the isolation gate structure makes the input resistance of CMOS devices extremely large, thereby The ability to drive similar logic gates during CMOS is much stronger than other families.
  • FIG. 3b is a schematic diagram of a control signal of a pulse width modulation port multiplexing circuit based on digital signal processing disclosed in an embodiment of the present application.
  • the control signal described in this embodiment is a square wave signal with alternating high level and low level, the control signal may include a transmission control command, and may also include a data segment or a data block, In the control signal, "0" corresponds to a low level, and "1" corresponds to a high level.
  • the above control signal takes the control command as an example.
  • the control signal is low level "0" in the first time period, high level "1" in the second time period, and low level in the third time period.
  • the sum of the durations of these five time periods can be regarded as a cycle, and in the next cycle
  • the levels corresponding to these five time periods will appear repeatedly, which can be used to transmit the same control command periodically. It should be noted that the high level and the low level in the control signal do not correspond to voltages of two specific values, but correspond to two voltage ranges.
  • FIG. 4 is a schematic structural diagram of an apparatus for PWM port multiplexing based on digital signal processing disclosed in an embodiment of the present application.
  • the device for PWM port multiplexing based on digital signal processing described in this embodiment includes a power supply and a digital signal as shown in any one of FIG. 1 or FIG. 2 or FIG. 3a Processing DSP's pulse width modulation PWM port multiplexing circuit, where:
  • the power supply includes a first auxiliary power supply 601 and a second auxiliary power supply 701.
  • the output port 611 of the first auxiliary power supply 601 is connected to the power supply terminal 111 of the DSP control chip 101, and the output port 711 of the second auxiliary power supply 701 is connected to the first AND logic gate 201.
  • the PWM port in the forward working state of the circuit can be used as the PWM port required in the reverse working state of the circuit, so as to effectively solve the PWM port for digital signal processing in the bidirectional operation of the power supply Not enough problems, and reduce discrete components and simplify the circuit.

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Abstract

本申请实施例公开了一种基于数字信号处理的脉冲宽度调制端口复用电路和装置，该电路包括：控制单元和脉冲宽度调制端口复用电路；所述控制单元的供电端连接电源，所述控制单元的接地端连接地线，所述控制单元的第一输出端口连接所述脉冲宽度调制端口复用电路的第一输入端口，所述控制单元的第二输出端口连接所述脉冲宽度调制端口复用电路的第二输入端口。实施本申请实施例，可以实现电路正向工作状态下的脉冲宽度调制端口作为电路反向工作状态下所需的脉冲宽度调制端口来使用，从而有效解决电源双向工作数字信号处理的脉冲宽度调制端口不够用的问题，并减少了分立元器件，简化电路，易于推广。

Description

基于数字信号处理的脉冲宽度调制端口复用电路和装置 技术领域
本申请涉及电子电路技术领域，具体涉及一种基于数字信号处理的脉冲宽度端口复用电路和装置。
背景技术
随着电源以及数字控制技术的发展，越来越多的场合需要电源具有双向工作的功能，在一些需要电源双向工作的电路拓扑中，需要使用较多的脉冲宽度调制(Pulse Width Modulation，PWM)端口，而当前的数字信号处理(Digital Signal Processing，DSP)控制芯片大多都是8对PWM端口，当电路反向工作时，这些PWM端口是不够的。
当前，解决PWM端口不够用的最常见方法是在电路中增加一颗DSP控制芯片，这样做虽然解决了实际问题，但是会导致电路中的分立元器件过多，电路复杂，不利于推广。
申请内容
本申请实施例提供一种基于数字信号处理的脉冲宽度调制端口复用电路和装置，可以实现电路正向工作状态下的脉冲宽度调制端口作为电路反向工作状态下所需的脉冲宽度调制端口来使用，从而有效解决电源双向工作数字信号处理的脉冲宽度调制端口不够用的问题，并减少了分立元器件，简化电路，易于推广。
本申请实施例第一方面，提供了一种基于数字信号处理的脉冲宽度调制端口复用电路，包括控制单元和脉冲宽度调制端口复用电路，其中：
所述控制单元的供电端连接电源，所述控制单元的接地端连接地线，所述控制单元的第一输出端口连接所述脉冲宽度调制端口复用电路的第一输入端口，所述控制单元的第二输出端口连接所述脉冲宽度调制端口复用电路的第二输入端口；
所述控制单元接收控制信号并将所述控制信号传输至所述脉冲宽度调制 端口复用电路，所述脉冲宽度调制端口复用电路在接收到所述控制信号后，实现双向电源正向工作状态下的脉冲宽度调制端口作为所述双向电源反向工作状态下所需的脉冲宽度调制端口来使用。
在一种可能的实现方式中，所述控制单元包括数字信号处理控制芯片，其中：
所述数字信号处理控制芯片的供电端连接电源，所述数字信号处理控制芯片的接地端连接地线，所述数字信号处理控制芯片的第一脉冲宽度调制端口连接所述脉冲宽度调制端口复用电路的第一输入端口，所述数字信号处理控制芯片的第二脉冲宽度调制端口连接所述脉冲宽度调制端口复用电路的第二输入端口；
所述数字信号处理控制芯片接收控制信号并将所述控制信号传输至所述脉冲宽度调制端口复用电路，所述控制信号用于控制所述脉冲宽度调制端口复用电路的工作状态。
在一种可能的实现方式中，所述脉冲宽度调制端口复用电路包括第一与逻辑门，第二与逻辑门，第三与逻辑门，第四与逻辑门，其中：
所述电源分别连接所述第一与逻辑门的供电端、所述第二与逻辑门的供电端、所述第三与逻辑门的供电端和所述第四与逻辑门的供电端；所述第一与逻辑门的接地端、所述第二与逻辑门的接地端、所述第三与逻辑门的接地端和所述第四与逻辑门的接地端分别连接地线；所述第一与逻辑门的第一输入端口和所述第二与逻辑门的第一输入端口连接所述数字信号处理控制芯片的第一脉冲宽度调制端口，所述第三与逻辑门的第一输入端口和所述第四与逻辑门的第一输入端口连接所述数字信号处理控制芯片的第二脉冲宽度调制端口，所述第一与逻辑门的第二输入端口、所述第二与逻辑门的第二输入端口、所述第三与逻辑门的第二输入端口和所述第四与逻辑门的第二输入端口通过I/O接口连接所述数字信号处理控制芯片，所述第一与逻辑门的输出端口、所述第二与逻辑门的输出端口、所述第三与逻辑门的输出端口和所述第四与逻辑门的输出端口分别连接不同的驱动芯片；
所述第一与逻辑门、所述第二与逻辑门、所述第三与逻辑门和所述第四与逻辑门用于传输和处理控制信号。
在一种可能的实现方式中，所述正向工作状态包括所述双向电源由电网充电；
当所述第一与逻辑门的第一输入端口、所述第一与逻辑门的第二输入端口、所述第三与逻辑门的第一输入端口和所述第三与逻辑门的第二输入端口均为高电平时，所述脉冲宽度调制端口复用电路为正向工作状态。
在一种可能的实现方式中，所述反向工作状态包括所述双向电源给电网供电或给电器供电；
当所述第二与逻辑门的第一输入端口、所述第二与逻辑门的第二输入端口、所述第四与逻辑门的第一输入端口和所述第四与逻辑门的第二输入端口均为高电平时，所述脉冲宽度调制端口复用电路为反向工作状态。
在一种可能的实现方式中，所述双向电源包括车载电源或光伏逆变器。
在一种可能的实现方式中，所述第一与逻辑门、所述第二与逻辑门、所述第三与逻辑门和所述第四与逻辑门均为互补金属氧化物半导体与逻辑门。
在一种可能的实现方式中，所述第一与逻辑门的接地端、所述第二与逻辑门的接地端、所述第三与逻辑门的接地端和所述第四与逻辑门的接地端连接同一个地端。
本申请实施例第二方面，提供了一种基于数字信号处理的脉冲宽度调制端口复用的装置，包括电源和本申请实施例第一方面中的任一项所述的基于数字信号处理的脉冲宽度调制端口复用电路。
在一种可能的实现方式中，所述电源包括第一辅助电源和第二辅助电源，所述第一辅助电源为所述数字信号处理控制芯片供电，所述第二辅助电源为所述第一与逻辑门、所述第二与逻辑门、所述第三与逻辑门和所述第四与逻辑门供电。
本申请实施例提供的一种基于数字信号处理的脉冲宽度调制端口复用电路，包括控制单元和脉冲宽度调制端口复用电路，其中：
所述控制单元的供电端连接电源，所述控制单元的接地端连接地线，所述控制单元的第一输出端口连接所述脉冲宽度调制端口复用电路的第一输入端口，所述控制单元的第二输出端口连接所述脉冲宽度调制端口复用电路的第二输入端口；
所述控制单元接收控制信号并将所述控制信号传输至所述脉冲宽度调制端口复用电路，所述脉冲宽度调制端口复用电路在接收到所述控制信号后，实现双向电源正向工作状态下的脉冲宽度调制端口作为所述双向电源反向工作状态下所需的脉冲宽度调制端口来使用。
实施本申请实施例，可以实现电路正向工作状态下的脉冲宽度调制端口作为电路反向工作状态下所需的脉冲宽度调制端口来使用，从而有效解决电源双向工作数字信号处理的脉冲宽度调制端口不够用的问题，并减少了分立元器件，简化电路，易于推广。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例公开的一种基于数字信号处理的脉冲宽度调制端口复用电路的结构示意图；
图2为本申请实施例公开的另一种基于数字信号处理的脉冲宽度调制端口复用电路的结构示意图；
图3a为本申请实施例公开的又一种基于数字信号处理的脉冲宽度调制端口复用电路的结构示意图；
图3b为本申请实施例公开的一种基于数字信号处理的脉冲宽度调制端口复用电路的控制信号示意图；
图4为本申请实施例公开的一种基于数字信号处理的脉冲宽度调制端口复用的装置的结构示意图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整地描述。显然，所描述的实施方式是本申请的一部分实施方式， 而不是全部实施方式。
本申请实施例提供一种基于数字信号处理的脉冲宽度调制端口复用电路和装置，以下进行详细说明。
本申请实施例所涉及的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序，此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。
请参阅图1，图1是本申请实施例公开的一种基于数字信号处理的脉冲宽度调制端口复用电路的结构示意图。如图1所示，本实施例中所描述的基于数字信号处理的脉冲宽度调制端口复用电路，包括控制单元10和PWM端口复用电路20，其中：
控制单元10的供电端11连接电源，控制单元10的接地端14连接地线，控制单元10的第一输出端口12连接PWM端口复用电路20的第一输入端口21，控制单元10的第二输出端口13连接PWM端口复用电路20的第二输入端口22；
控制信号从控制单元10的第一输出端口12和控制单元10的第二输出端口13输出，分别通过PWM端口复用电路20的第一输入端口21和PWM端口复用电路20的第二输入端口22流入PWM端口复用电路20，PWM端口复用电路20用于实现双向电源正向工作状态下的PWM端口作为双向电源反向工作状态下所需的PWM端口来使用。
在本申请实施例中，控制单元10为至少一个DSP控制芯片的集成，PWM端口复用电路20为至少四个与逻辑门和连接在与逻辑门之间的线路的集成，控制单元10生成控制信号，通过连接线路传输至PWM端口复用电路20，用于控制PWM端口复用电路20的工作状态，双向电源为本申请实施例的应用场景，上述双向电源具体为需要PWM端口复用的双向电源，包括车载电源或光伏逆变器，双向电源正向工作状态包括双向电源由电网充电，双向电源反向工作状态为双向电源给电网供电或给电器供电，因双向电源的正向工作和反向工作不会同时进行，故通过控制单元10生成的控制信号来控制PWM端口复用电路20的工作状态，从而实现作为正向工作时的PWM端口也可以作为反 向工作时需要的PWM端口使用。
请参阅图2，图2是本申请实施例公开的一种基于数字信号处理的脉冲宽度调制端口复用电路的结构示意图。如图2所示，本实施例中所描述的控制单元10包括DSP控制芯片101，其中：
DSP控制芯片101的供电端111连接电源，DSP控制芯片101的接地端114连接地线，DSP控制芯片101的第一PWM端口112连接PWM端口复用电路20的第一输入端口21，DSP控制芯片101的第二PWM端口113连接PWM端口复用电路20的第二输入端口22；
控制信号从DSP控制芯片101的第一PWM端口112和DSP控制芯片101的第二PWM端口113输出，分别通过PWM端口复用电路20的第一输入端口21和PWM端口复用电路20的第二输入端口22流入PWM端口复用电路20，控制信号用于控制PWM端口复用电路20的工作状态。
在本申请实施例中，DSP控制芯片101为TMS320F28004X系列控制芯片，该系列芯片是一个功能强大的32位浮点微控制器单元(Microcontroller Unit，MCU)，可让设计人员在单个器件上集成关键的控制外设、差分模拟和非易失性存储器；同时，该系列芯片上集成了高性能模拟块，以进一步支持***整合，三个独立的12位模数转换器(Analog to Digital Converter，ADC)可准确、高效地管理多个模拟信号，从而最终提高***吞吐量，模拟前端上的七个可编程增益放大器(Pmgrammable Gain Amplifier，PGA)可以在转换之前实现片上电压调节，七个模拟比较器模块可以针对跳闸情况对输入电压电平进行持续监控；此外，该系列芯片包含行业领先的控制外设，允许对***进行一流的控制，通过各种行业标准通信端口支持连接，并且提供了多个多路复用，可在各种应用中实现最佳信号布置。
请参阅图3a，图3a是本申请实施例公开的一种基于数字信号处理的脉冲宽度调制端口复用电路的结构示意图。如图3a所示，本实施例中所描述的PWM端口复用电路20包括第一与逻辑门201，第二与逻辑门301，第三与逻辑门401和第四与逻辑门501，其中：
第一与逻辑门201的供电端211、第二与逻辑门301的供电端311、第三 与逻辑门401的供电端411和第四与逻辑门501的供电端511连接电源，第一与逻辑门201的接地端213、第二与逻辑门301的接地端313、第三与逻辑门401的接地端413和第四与逻辑门501的接地端513连接地线；第一与逻辑门201的第一输入端口215和第二与逻辑门301的第一输入端口315连接DSP控制芯片101的第一PWM端口112，第三与逻辑门401的第一输入端口414和第四与逻辑门501的第一输入端口514连接DSP控制芯片101的第二PWM端口113，第一与逻辑门201的第二输入端口214、第二与逻辑门301的第二输入端口314、第三与逻辑门401的第二输入端口415和第四与逻辑门501的第二输入端口515通过I/O接口连接DSP控制芯片101，第一与逻辑门201的输出端口212、第二与逻辑门301的输出端口312、第三与逻辑门401的输出端口412和第四与逻辑门501的输出端口512分别连接不同的驱动芯片；
第一与逻辑门201、第二与逻辑门301、第三与逻辑门401和第四与逻辑门501用于传输和处理控制信号；
控制信号从DSP控制芯片101的第一PWM端口112输出并传输至第一与逻辑门201的第一输入端口215和第二与逻辑门301的第一输入端口315，控制信号还从DSP控制芯片101的第二PWM端口113输出并传输至第三与逻辑门401的第一输入端口414和第四与逻辑门501的第一输入端口514，第一与逻辑门201的第二输入端口214、第二与逻辑门301的第二输入端口314、第三与逻辑门401的第二输入端口415和第四与逻辑门501的第二输入端口515接收到的控制信号由DSP控制芯片101根据PWM端口复用电路20的工作状态来控制；
当第一与逻辑门201的第一输入端口215、第一与逻辑门201的第二输入端口214、第三与逻辑门401的第一输入端口414和第三与逻辑门401的第二输入端口415均为高电平，第二与逻辑门301的第二输入端口314和第四与逻辑门501的第二输入端口515均为低电平，则第一与逻辑门201的输出端口212和第三与逻辑门401的输出端口412均为高电平，第二与逻辑门301的输出端口312和第四与逻辑门501的输出端口512均为低电平，则第一与逻辑门201的输出端口212和第三与逻辑门401的输出端口412输出驱动信号，该驱 动信号通过控制后极开关管来使连接的驱动芯片进入工作状态，上述过程即为PWM端口复用电路20的正向工作状态；当第二与逻辑门301的第一输入端口315、第二与逻辑门301的第二输入端口314、第四与逻辑门501的第一输入端口514和第四与逻辑门501的第二输入端口515均为高电平，第一与逻辑门201的第二输入端口214和第三与逻辑门401的第二输入端口415均为低电平，则第二与逻辑门301的输出端口312和第四与逻辑门501的输出端口512均为高电平，第一与逻辑门201的输出端口212和第三与逻辑门401的输出端口412均为低电平，则第二与逻辑门301的输出端口312和第四与逻辑门501的输出端口512输出驱动信号，该驱动信号通过控制后极开关管来使连接的驱动芯片进入工作状态，上述过程即为PWM端口复用电路20的反向工作状态，具体情况如下表一、表二所示：
表一
Figure PCTCN2020101313-appb-000001
表二
Figure PCTCN2020101313-appb-000002
在本申请实施例中，第一与逻辑门201、第二与逻辑门301、第三与逻辑门401和第四与逻辑门501均为互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)与逻辑门，CMOS与逻辑门允许的电源电压范 围宽，方便电源电路的设计，逻辑摆幅大，使电路抗干扰能力强，静态功耗低，隔离栅结构使CMOS器件的输入电阻极大，从而使CMOS期间驱动同类逻辑门的能力比其他系列强得多。
请参阅图3b，图3b是本申请实施例公开的一种基于数字信号处理的脉冲宽度调制端口复用电路的控制信号示意图。如图3b所示，本实施例中所描述的控制信号是一种以高电平和低电平交替出现的方波信号，该控制信号可以包括传输控制命令，也可以包括数据段或数据块，控制信号中，以“0”对应低电平，以“1”对应高电平。上述控制信号以控制命令为例，控制信号在第一个时间段内为低电平“0”、第二个时间段内为高电平“1”、第三个时间段内为低电平“0”、第四个时间段内为低电平“0”、第五个时间段内为高电平“1”，可以将这五个时间段的时长之和作为一个周期，在下一周期又会重复出现这五个时间段对应的电平，可以用于周期性的传输同一控制命令。需要注意的是，控制信号中的高电平和低电平不是对应两个具体数值的电压，而是对应为两个电压范围。
请参阅图4，图4是本申请实施例公开的一种基于数字信号处理的脉冲宽度调制端口复用的装置的结构示意图。如图4所示，本实施例中所描述的基于数字信号处理的脉冲宽度调制端口复用的装置，包括电源和如图1或如图2或如图3a中任意一项所示的数字信号处理DSP的脉宽调制PWM端口复用电路，其中：
电源包括第一辅助电源601和第二辅助电源701，第一辅助电源601的输出端口611连接DSP控制芯片101的供电端111，第二辅助电源701的输出端口711连接第一与逻辑门201的供电端211、第二与逻辑门301的供电端311、第三与逻辑门401的供电端411和第四与逻辑门501的供电端511；第一辅助电源601为DSP控制芯片101供电，第二辅助电源701为第一与逻辑门201、第二与逻辑门301、第三与逻辑门401和第四与逻辑门501供电。
通过以上申请实施例，可以实现电路正向工作状态下的脉冲宽度调制端口作为电路反向工作状态下所需的脉冲宽度调制端口来使用，从而有效解决电源双向工作数字信号处理的脉冲宽度调制端口不够用的问题，并减少了分立元器 件，简化电路。
以上对本申请实施例所提供的一种基于数字信号处理的脉冲宽度调制端口复用电路和装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种基于数字信号处理的脉冲宽度调制端口复用电路，其特征在于，所述电路包括：控制单元和脉冲宽度调制端口复用电路；所述控制单元的供电端连接电源，所述控制单元的接地端连接地线，所述控制单元的第一输出端口连接所述脉冲宽度调制端口复用电路的第一输入端口，所述控制单元的第二输出端口连接所述脉冲宽度调制端口复用电路的第二输入端口；
    所述控制单元接收控制信号并将所述控制信号传输至所述脉冲宽度调制端口复用电路，所述脉冲宽度调制端口复用电路在接收到所述控制信号后，实现双向电源正向工作状态下的脉冲宽度调制端口作为所述双向电源反向工作状态下所需的脉冲宽度调制端口来使用。
  2. 根据权利要求1所述的基于数字信号处理的脉冲宽度调制端口复用电路，其特征在于，所述控制单元包括：数字信号处理控制芯片；所述数字信号处理控制芯片的供电端连接电源，所述数字信号处理控制芯片的接地端连接地线，所述数字信号处理控制芯片的第一脉冲宽度调制端口连接所述脉冲宽度调制端口复用电路的第一输入端口，所述数字信号处理控制芯片的第二脉冲宽度调制端口连接所述脉冲宽度调制端口复用电路的第二输入端口；
    所述数字信号处理控制芯片接收控制信号并将所述控制信号传输至所述脉冲宽度调制端口复用电路，所述控制信号用于控制所述脉冲宽度调制端口复用电路的工作状态。
  3. 根据权利要求2所述的基于数字信号处理的脉冲宽度调制端口复用电路，其特征在于，所述脉冲宽度调制端口复用电路包括：第一与逻辑门，第二与逻辑门，第三与逻辑门和第四与逻辑门；所述电源分别连接所述第一与逻辑门的供电端、所述第二与逻辑门的供电端、所述第三与逻辑门的供电端和所述第四与逻辑门的供电端；所述第一与逻辑门的接地端、所述第二与逻辑门的接地端、所述第三与逻辑门的接地端和所述第四与逻辑门的接地端分别连接地线；所述第一与逻辑门的第一输入端口和所述第二与逻辑门的第一输入端口连接所述数字信号处理控制芯片的第一脉冲宽度调制端口，所述第三与逻辑门的第 一输入端口和所述第四与逻辑门的第一输入端口连接所述数字信号处理控制芯片的第二脉冲宽度调制端口，所述第一与逻辑门的第二输入端口、所述第二与逻辑门的第二输入端口、所述第三与逻辑门的第二输入端口和所述第四与逻辑门的第二输入端口通过I/O接口连接所述数字信号处理控制芯片，所述第一与逻辑门的输出端口、所述第二与逻辑门的输出端口、所述第三与逻辑门的输出端口和所述第四与逻辑门的输出端口分别连接不同的驱动芯片；
    所述第一与逻辑门、所述第二与逻辑门、所述第三与逻辑门和所述第四与逻辑门用于传输和处理控制信号。
  4. 根据权利要求3所述的基于数字信号处理的脉冲宽度调制端口复用电路，其特征在于，所述正向工作状态包括：所述双向电源由电网充电；当所述第一与逻辑门的第一输入端口、所述第一与逻辑门的第二输入端口、所述第三与逻辑门的第一输入端口和所述第三与逻辑门的第二输入端口均为高电平时，所述脉冲宽度调制端口复用电路为正向工作状态。
  5. 根据权利要求3所述的基于数字信号处理的脉冲宽度调制端口复用电路，其特征在于，所述反向工作状态包括：所述双向电源给电网供电或给电器供电；当所述第二与逻辑门的第一输入端口、所述第二与逻辑门的第二输入端口、所述第四与逻辑门的第一输入端口和所述第四与逻辑门的第二输入端口均为高电平时，所述脉冲宽度调制端口复用电路为反向工作状态。
  6. 根据权利要求5所述的基于数字信号处理的脉冲宽度调制端口复用电路，其特征在于，所述双向电源包括：车载电源或光伏逆变器。
  7. 根据权利要求5所述的基于数字信号处理的脉冲宽度调制端口复用电路，其特征在于，所述第一与逻辑门、所述第二与逻辑门、所述第三与逻辑门和所述第四与逻辑门均为互补金属氧化物半导体与逻辑门。
  8. 根据权利要求3所述的基于数字信号处理的脉冲宽度调制端口复用电 路，其特征在于，所述第一与逻辑门的接地端、所述第二与逻辑门的接地端、所述第三与逻辑门的接地端和所述第四与逻辑门的接地端连接同一个地端。
  9. 一种基于数字信号处理的脉冲宽度调制端口复用的装置，其特征在于，包括电源和权利要求1～8的任一项所述的基于数字信号处理的脉冲宽度调制端口复用电路。
  10. 根据权利要求9所述的基于数字信号处理的脉冲宽度调制端口复用的装置，其特征在于，所述电源包括第一辅助电源和第二辅助电源，所述第一辅助电源为所述数字信号处理控制芯片供电，所述第二辅助电源为所述第一与逻辑门、所述第二与逻辑门、所述第三与逻辑门和所述第四与逻辑门供电。
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