WO2021179370A1 - 一种阵列基板、显示面板 - Google Patents

一种阵列基板、显示面板 Download PDF

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Publication number
WO2021179370A1
WO2021179370A1 PCT/CN2020/083008 CN2020083008W WO2021179370A1 WO 2021179370 A1 WO2021179370 A1 WO 2021179370A1 CN 2020083008 W CN2020083008 W CN 2020083008W WO 2021179370 A1 WO2021179370 A1 WO 2021179370A1
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Prior art keywords
electrically connected
thin film
film transistor
sub
main
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PCT/CN2020/083008
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English (en)
French (fr)
Inventor
陈亚妮
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Tcl华星光电技术有限公司
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Priority to US16/758,422 priority Critical patent/US11537017B2/en
Publication of WO2021179370A1 publication Critical patent/WO2021179370A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/028—Improving the quality of display appearance by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and a display panel.
  • the birefringence of the liquid crystal molecules at different viewing angles has a large difference, resulting in a large visual role deviation.
  • a multi-domain display mode is often used in some wide viewing angle liquid crystal displays to increase the viewing angle of the display.
  • the multi-domain display mode refers to the division of multiple regions in a sub-pixel.
  • the deflection angles of the liquid crystals in different regions are different.
  • the multi-domain display mode can reduce the loss of all liquid crystals in the pixel.
  • the difference in contrast between different viewing angles caused by the same deflection angle increases the viewing angle.
  • the current wide viewing angle liquid crystal displays have limited improvement in viewing angle and cannot meet the increasing demand for wide viewing angles, such as e-sports and virtual reality (VR) screens.
  • VR virtual reality
  • the embodiments of the present application provide an array substrate and a display panel, which can solve the technical problem that the viewing angle of the existing display panel is narrow and cannot meet the increasing demand for wide viewing angle.
  • the present application provides an array substrate, including sub-pixels arranged in an array on the substrate, each of the sub-pixels including a main area, a first sub-area, and a second sub-area;
  • One gate line is provided for each row of the sub-pixels, the gate line is located between the main area and the second sub-region, and one data line and one voltage dividing line are provided for each column of the sub-pixels, Two adjacent data lines define a pixel boundary, and the voltage dividing line is located between two adjacent data lines;
  • the pixel electrode includes a main pixel electrode corresponding to the main area, a first sub-pixel electrode corresponding to the first sub-area, and a second sub-pixel electrode corresponding to the second sub-area;
  • the sub-pixel also includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a fourth thin film transistor.
  • the first thin film transistor is electrically connected to the first pixel electrode, and the second thin film transistor is connected to the The main pixel electrode is electrically connected, the third thin film transistor is electrically connected to the second sub-pixel electrode, and the fourth thin film transistor is electrically connected to the voltage dividing line;
  • the channel aspect ratio of the second thin film transistor is greater than the channel aspect ratio of the first thin film transistor and the channel aspect ratio of the third thin film transistor.
  • the channel aspect ratio of the first thin film transistor is the same as the channel aspect ratio of the third thin film transistor.
  • the array substrate further includes a common electrode, the common electrode and the gate line are arranged in the same layer, and the common electrode corresponds to the main region, the first region, and the The second zone setting.
  • a first potential difference is formed between the main pixel electrode and the common electrode of the sub-pixel, and a second potential difference is formed between the first pixel electrode and the common electrode
  • a third potential difference is formed between the second sub-pixel electrode and the common electrode, and the first potential difference is greater than the third potential difference, and the third potential difference is greater than the second potential difference.
  • the gate of the first thin film transistor is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is respectively connected to the first pixel electrode and the The common electrode and the source of the third thin film transistor are electrically connected;
  • the gate of the second thin film transistor is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is electrically connected to the main pixel electrode and the common electrode, respectively;
  • the gate of the third thin film transistor is electrically connected to the gate line, and the drain is respectively electrically connected to the second sub-pixel electrode, the common electrode, and the source of the fourth thin film transistor;
  • the gate of the fourth thin film transistor is electrically connected to the gate line, and the drain is electrically connected to the voltage dividing line.
  • the sub-pixel further includes a main storage capacitor and a main liquid crystal capacitor corresponding to the main area, and a first storage capacitor and a first liquid crystal capacitor corresponding to the first area, corresponding to all The second storage capacitor and the second liquid crystal capacitor in the second area are described.
  • the gate electrode of the first thin film transistor is electrically connected to the gate line
  • the source electrode is electrically connected to the data line
  • the drain electrode is respectively connected to the first pixel electrode and the Common electrode electrical connection
  • the gate of the second thin film transistor is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is electrically connected to the main pixel electrode and the common electrode, respectively;
  • the gate of the third thin film transistor is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is respectively connected to the second sub-pixel electrode, the common electrode and the fourth thin film The source of the transistor is electrically connected;
  • the gate of the fourth thin film transistor is electrically connected to the gate line, and the drain is electrically connected to the voltage dividing line.
  • the sub-pixel further includes a main storage capacitor and a main liquid crystal capacitor corresponding to the main area, and a first storage capacitor and a first liquid crystal capacitor corresponding to the first area, corresponding to all The second storage capacitor and the second liquid crystal capacitor in the second area are described.
  • the first plate of the first storage capacitor and the first plate of the first liquid crystal capacitor are both electrically connected to the drain of the first thin film transistor, and the first The second plate of the primary storage capacitor is electrically connected to the first-time pixel electrode, and the second plate of the first-time liquid crystal capacitor is electrically connected to the common electrode;
  • the first plate of the main storage capacitor and the first plate of the main liquid crystal capacitor are electrically connected to the drain of the second thin film transistor, and the second plate of the main storage capacitor is connected to the main pixel.
  • the electrodes are electrically connected, and the second plate of the main liquid crystal capacitor is electrically connected to the common electrode;
  • Both the first plate of the second storage capacitor and the first plate of the second liquid crystal capacitor are electrically connected to the drain of the third thin film transistor, and the second electrode of the second storage capacitor The plate is electrically connected to the second sub-pixel electrode, and the second electrode plate of the second sub-liquid crystal capacitor is electrically connected to the common electrode.
  • the potentials of the common electrodes corresponding to the main region, the first secondary region, and the second secondary region are the same.
  • the present application also provides a display panel, including the array substrate and the color filter substrate as described above, and a liquid crystal layer located between the array substrate and the color filter substrate, the display panel including sub-pixels distributed in an array, The main region, the first sub-region and the second sub-region of each of the sub-pixels respectively correspond to four domains of liquid crystal molecules.
  • the present application also provides an array substrate, including sub-pixels arranged in an array on the substrate, each of the sub-pixels including a main area, a first sub-area, and a second sub-area;
  • One gate line is provided for each row of the sub-pixels, the gate line is located between the main area and the second sub-region, and one data line and one voltage dividing line are provided for each column of the sub-pixels, Two adjacent data lines define a pixel boundary, and the voltage dividing line is located between two adjacent data lines;
  • the pixel electrode includes a main pixel electrode corresponding to the main area, a first sub-pixel electrode corresponding to the first sub-area, and a second sub-pixel electrode corresponding to the second sub-area;
  • a common electrode, the common electrode and the gate line are arranged in the same layer, and the common electrode is arranged corresponding to the main region, the first primary region, and the second secondary region;
  • the sub-pixel also includes a first thin film transistor, a second thin film transistor, a third thin film transistor, and a fourth thin film transistor.
  • the first thin film transistor is electrically connected to the first pixel electrode, and the second thin film transistor is connected to the The main pixel electrode is electrically connected, the third thin film transistor is electrically connected to the second sub-pixel electrode, and the fourth thin film transistor is electrically connected to the voltage dividing line;
  • the channel aspect ratio of the second thin film transistor is greater than the channel aspect ratio of the first thin film transistor and the channel aspect ratio of the third thin film transistor, and the channel aspect ratio of the first thin film transistor The channel aspect ratio is the same as the channel aspect ratio of the third thin film transistor.
  • a first potential difference is formed between the main pixel electrode and the common electrode of the sub-pixel, and a second potential difference is formed between the first pixel electrode and the common electrode
  • a third potential difference is formed between the second sub-pixel electrode and the common electrode, and the first potential difference is greater than the third potential difference, and the third potential difference is greater than the second potential difference.
  • the gate of the first thin film transistor is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is respectively connected to the first pixel electrode and the The common electrode and the source of the third thin film transistor are electrically connected;
  • the gate of the second thin film transistor is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is electrically connected to the main pixel electrode and the common electrode, respectively;
  • the gate of the third thin film transistor is electrically connected to the gate line, and the drain is respectively electrically connected to the second sub-pixel electrode, the common electrode, and the source of the fourth thin film transistor;
  • the gate of the fourth thin film transistor is electrically connected to the gate line, and the drain is electrically connected to the voltage dividing line.
  • the sub-pixel further includes a main storage capacitor and a main liquid crystal capacitor corresponding to the main area, and a first storage capacitor and a first liquid crystal capacitor corresponding to the first area, corresponding to all The second storage capacitor and the second liquid crystal capacitor in the second area are described.
  • the gate electrode of the first thin film transistor is electrically connected to the gate line
  • the source electrode is electrically connected to the data line
  • the drain electrode is respectively connected to the first pixel electrode and the Common electrode electrical connection
  • the gate of the second thin film transistor is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is electrically connected to the main pixel electrode and the common electrode, respectively;
  • the gate of the third thin film transistor is electrically connected to the gate line, the source is electrically connected to the data line, and the drain is respectively connected to the second sub-pixel electrode, the common electrode and the fourth thin film The source of the transistor is electrically connected;
  • the gate of the fourth thin film transistor is electrically connected to the gate line, and the drain is electrically connected to the voltage dividing line.
  • the sub-pixel further includes a main storage capacitor and a main liquid crystal capacitor corresponding to the main area, and a first storage capacitor and a first liquid crystal capacitor corresponding to the first area, corresponding to all The second storage capacitor and the second liquid crystal capacitor in the second area are described.
  • the first plate of the first storage capacitor and the first plate of the first liquid crystal capacitor are both electrically connected to the drain of the first thin film transistor, and the first The second plate of the primary storage capacitor is electrically connected to the first-time pixel electrode, and the second plate of the first-time liquid crystal capacitor is electrically connected to the common electrode;
  • the first plate of the main storage capacitor and the first plate of the main liquid crystal capacitor are electrically connected to the drain of the second thin film transistor, and the second plate of the main storage capacitor is connected to the main pixel.
  • the electrodes are electrically connected, and the second plate of the main liquid crystal capacitor is electrically connected to the common electrode;
  • Both the first plate of the second storage capacitor and the first plate of the second liquid crystal capacitor are electrically connected to the drain of the third thin film transistor, and the second electrode of the second storage capacitor The plate is electrically connected to the second sub-pixel electrode, and the second electrode plate of the second sub-liquid crystal capacitor is electrically connected to the common electrode.
  • the potentials of the common electrodes corresponding to the main region, the first secondary region, and the second secondary region are the same.
  • the array substrate and the display panel provided by the embodiments of the application are designed with a twelve-domain pixel structure, and each sub-pixel includes a main area, a first sub-area, a second sub-area, and four thin film transistors; the main area, The three display areas of the first time area and the second time area are respectively driven by a thin film transistor.
  • the channel aspect ratio of the thin film transistor in the driving main region is increased, and the drain of the fourth thin film transistor is electrically connected to the voltage dividing line to divide the voltage of the second sub-region, so that the sub-pixels are in the main region.
  • the potential difference between the first zone, the first zone, and the second zone are different, so that the liquid crystal molecules in each domain have a different deflection angle, thereby allowing the display panel to obtain a wider viewing angle.
  • FIG. 1 is a schematic diagram of a pixel structure of an array substrate provided by an embodiment of the application.
  • FIG. 2 is an equivalent circuit diagram of a pixel structure provided by an embodiment of the application.
  • FIG. 3 is an equivalent circuit diagram of a pixel structure provided by another embodiment of the application.
  • first and second are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • FIG. 1 is a schematic diagram of the pixel structure of the array substrate provided by the embodiment of the present application.
  • the array substrate of the present application includes sub-pixels arranged in an array on the substrate.
  • only one sub-pixel is used as an example for description. It can be understood that other sub-pixels have the same structure as this sub-pixel.
  • the array substrate includes a plurality of gate lines 1 and a plurality of data lines 2 and a plurality of voltage dividing lines 3, wherein one gate line 1 is provided corresponding to each row of the sub-pixels, corresponding to each column of the sub-pixels.
  • the pixel is provided with one data line 2 and one voltage dividing line 3, two adjacent data lines 2 define a pixel boundary, and the dividing voltage line 3 is located between two adjacent data lines 2.
  • the sub-pixels include a main area (that is, a main display area) 4, a first time area (that is, a first time display area) 5, and a second time area (that is, a second time display area) 6, and the gate line 1 is located Between the main zone 4 and the second secondary zone 6.
  • the array substrate further includes a common electrode 7 provided on the same layer as the gate line 1, and the common electrode 7 includes a main common electrode 71 corresponding to the main area 4, and a main common electrode 71 corresponding to the first area 5 and the first area.
  • the secondary common electrode 72 provided in the second secondary region 6 is described.
  • the common electrode 7 may be a transparent electrode, such as indium tin oxide, indium gallium tin oxide, etc., which is not limited here.
  • the common electrode 7 is provided with a first common electrode and a second common electrode corresponding to the first primary region 5 and the second secondary region 6, respectively.
  • the array substrate further includes a pixel electrode 8.
  • the pixel electrode 8 includes a main pixel electrode 81 corresponding to the main region 4, a first pixel electrode 82 corresponding to the first region 5, and a first pixel electrode 82 corresponding to the first region 5.
  • the second sub-pixel electrode 83 is provided in the secondary region 6.
  • the pixel electrode 8 may be a transparent electrode, such as indium tin oxide, indium gallium tin oxide, etc., which is not limited here.
  • the pixel electrode 8 has a fishbone shape or a “m” shape structure.
  • a first potential difference is formed between the main pixel electrode 81 and the main common electrode 71 of the sub-pixel, and a second potential difference is formed between the first primary pixel electrode 82 and the secondary common electrode 72, so A third potential difference is formed between the second sub-pixel electrode 83 and the sub-common electrode 72.
  • the electric potential of the common electrode 7 corresponding to the main region 4, the first secondary region 5 and the second secondary region 6 are the same.
  • the sub-pixel also includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a fourth thin film transistor T4 located between the main region 4 and the second subregion 6.
  • the drain of a thin film transistor T1 is electrically connected to the first pixel electrode 82 through a via hole
  • the drain of the second thin film transistor T2 is electrically connected to the main pixel electrode 81 through a via hole
  • the drain of the transistor T3 is electrically connected to the second sub-pixel electrode 83 through a via hole
  • the drain of the fourth thin film transistor T4 is electrically connected to the voltage dividing line 3.
  • the data line 2 charges the three display areas of the sub-pixel through the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3, respectively.
  • the channel aspect ratio (W/L) of the second thin film transistor T2 is greater than the channel aspect ratio of the first thin film transistor T1 and the channel aspect ratio of the third thin film transistor T3. That is, the channel aspect ratio of the second thin film transistor T2 is the largest, so its charging ability is the strongest. Therefore, the pixel voltage of the main region 4 is the largest.
  • the channel aspect ratio of the first thin film transistor T1 is the same as the channel aspect ratio of the third thin film transistor T3.
  • the potential of the second sub-pixel electrode 83 corresponding to the second sub-region 6 is divided by the fourth thin film transistor T4 to the voltage dividing line 3, resulting in pixels in the second sub-region 6
  • the voltage is lower than the pixel voltage of the first primary region 5.
  • the pixel voltages of the main region 4, the first primary region 5, and the second secondary region 6 of the sub-pixel are different from each other, and the first potential difference is greater than the third potential difference,
  • the third potential difference is greater than the second potential difference, so that the deflection angles of the liquid crystal molecules corresponding to the main region 4, the first primary region 5, and the second secondary region 6 are different;
  • the main region 4, the first primary region 5, and the second secondary region 6 each correspond to four domains, so the deflection angle of the liquid crystal molecules in each domain is different, so that the display panel can obtain a wider viewing angle.
  • the sub-pixel includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a fourth thin film transistor T4.
  • the gate of the first thin film transistor T1 is electrically connected to the gate line 1
  • the source is electrically connected to the data line 2
  • the drain is respectively connected to the first secondary pixel electrode 82 and the secondary common
  • the electrode 72 is electrically connected to the source of the third thin film transistor T3.
  • the gate of the second thin film transistor T2 is electrically connected to the gate line 1, the source is electrically connected to the data line 2, and the drain is electrically connected to the main pixel electrode 81 and the main common electrode 71, respectively .
  • the gate of the third thin film transistor T3 is electrically connected to the gate line 1, and the drain is respectively connected to the second sub-pixel electrode 83, the sub-common electrode 72, and the source of the fourth thin film transistor T4. Electric connection.
  • the gate of the fourth thin film transistor T4 is electrically connected to the gate line 1, and the drain is electrically connected to the voltage dividing line 3.
  • the sub-pixel also includes a main storage capacitor Cst1 and a main liquid crystal capacitor Clc1 corresponding to the main area 4, a first storage capacitor Cst2 and a first liquid crystal capacitor Clc2 corresponding to the first area 5, corresponding to the first The second storage capacitor Cst3 and the second liquid crystal capacitor Clc3 of the secondary area 6.
  • the first plate of the main storage capacitor Cst1 and the first plate of the main liquid crystal capacitor Clc1 are electrically connected to the drain of the second thin film transistor T2, and the second plate of the main storage capacitor Cst1 is electrically connected to the drain of the second thin film transistor T2.
  • the main pixel electrode 81 is electrically connected, and the second plate of the main liquid crystal capacitor Clc1 is electrically connected to the main common electrode 71.
  • the first plate of the first storage capacitor Cst2 and the first plate of the first liquid crystal capacitor Clc2 are electrically connected to the drain of the first thin film transistor T1, and the first storage capacitor Cst2
  • the second electrode plate of the first time pixel electrode 82 is electrically connected, and the second electrode plate of the first time liquid crystal capacitor Clc2 is electrically connected to the secondary common electrode 72.
  • the first plate of the second storage capacitor Cst3 and the first plate of the second liquid crystal capacitor Clc3 are electrically connected to the drain of the third thin film transistor T3, and the second storage capacitor Cst3
  • the second plate of the second sub-pixel electrode 83 is electrically connected to the second sub-pixel electrode 83
  • the second plate of the second sub-liquid crystal capacitor Clc3 is electrically connected to the sub-common electrode 72.
  • FIG. 3 it is an equivalent circuit diagram of a pixel structure provided by another embodiment of this application.
  • only one sub-pixel is taken as an example for description.
  • the gate of the first thin film transistor T1 is electrically connected to the gate line 1, the source is electrically connected to the data line 2, and the drain is respectively connected to the first secondary pixel electrode 82 and the secondary common
  • the electrode 72 is electrically connected.
  • the gate of the second thin film transistor T2 is electrically connected to the gate line 1, the source is electrically connected to the data line 2, and the drain is electrically connected to the main pixel electrode 81 and the main common electrode 71, respectively .
  • the gate of the third thin film transistor T3 is electrically connected to the gate line 1, the source is electrically connected to the data line 2, and the drain is respectively connected to the second sub-pixel electrode 83 and the sub-common electrode 72. And the source of the fourth thin film transistor T4 is electrically connected.
  • the gate of the fourth thin film transistor T4 is electrically connected to the gate line 1, and the drain is electrically connected to the voltage dividing line 3.
  • the sub-pixel also includes a main storage capacitor Cst1 and a main liquid crystal capacitor Clc1 corresponding to the main area 4, a first storage capacitor Cst2 and a first liquid crystal capacitor Clc2 corresponding to the first area 5, corresponding to the first The second storage capacitor Cst3 and the second liquid crystal capacitor Clc3 of the secondary area 6.
  • the first plate of the main storage capacitor Cst1 and the first plate of the main liquid crystal capacitor Clc1 are electrically connected to the drain of the second thin film transistor T2, and the second plate of the main storage capacitor Cst1 is electrically connected to the drain of the second thin film transistor T2.
  • the main pixel electrode 81 is electrically connected, and the second plate of the main liquid crystal capacitor Clc1 is electrically connected to the main common electrode 71.
  • the first plate of the first storage capacitor Cst2 and the first plate of the first liquid crystal capacitor Clc2 are electrically connected to the drain of the first thin film transistor T1, and the first storage capacitor Cst2
  • the second electrode plate of the first time pixel electrode 82 is electrically connected, and the second electrode plate of the first time liquid crystal capacitor Clc2 is electrically connected to the secondary common electrode 72.
  • the first plate of the second storage capacitor Cst3 and the first plate of the second liquid crystal capacitor Clc3 are electrically connected to the drain of the third thin film transistor T3, and the second storage capacitor Cst3
  • the second plate of the second sub-pixel electrode 83 is electrically connected to the second sub-pixel electrode 83
  • the second plate of the second sub-liquid crystal capacitor Clc3 is electrically connected to the sub-common electrode 72.
  • the data line 2 charges the three display areas of the sub-pixel through the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3, respectively.
  • the channel aspect ratio of the second thin film transistor T2 is the largest, so its charging ability is the strongest. Therefore, the pixel voltage of the main region 4 is the largest.
  • the channel aspect ratio of the first thin film transistor T1 is the same as the channel aspect ratio of the third thin film transistor T3.
  • the potential of the second sub-pixel electrode 83 corresponding to the second sub-region 6 is divided by the fourth thin film transistor T4 to the voltage dividing line 3, resulting in pixels in the second sub-region 6 The voltage is lower than the pixel voltage of the first primary region 5.
  • the pixel voltages of the main region 4, the first primary region 5, and the second secondary region 6 of the sub-pixel are different, and the primary region 4, the first secondary region 5, and the Each of the second sub-regions 6 corresponds to four domains, so that the deflection angle of the liquid crystal molecules in each domain is different, so that the display panel can obtain a wider viewing angle.
  • the application also provides a display panel, including the array substrate and the color filter substrate as described above, and a liquid crystal layer located between the array substrate and the color filter substrate, the display panel including sub-pixels distributed in an array, The main region, the first sub-region and the second sub-region of each of the sub-pixels respectively correspond to four domains of liquid crystal molecules.
  • a display panel including the array substrate and the color filter substrate as described above, and a liquid crystal layer located between the array substrate and the color filter substrate, the display panel including sub-pixels distributed in an array, The main region, the first sub-region and the second sub-region of each of the sub-pixels respectively correspond to four domains of liquid crystal molecules.

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Abstract

一种阵列基板、显示面板。阵列基板包括多个子像素，每一子像素包括四个薄膜晶体管；阵列基板还包括栅极线（1）、数据线（2）以及分压线（3）。通过将第二薄膜晶体管（T2）的沟道长径比设置成大于第一薄膜晶体管（T1）以及第三薄膜晶体管（T3）的沟道长径比，并通过第四薄膜晶体管（T4）的漏极与分压线（3）电连接，从而使显示面板获得更宽广的视角。

Description

一种阵列基板、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板、显示面板。
 背景技术
对于VA模式的显示面板，液晶分子在不同视野角度下的双折射率的差异较大，导致了大视角色偏。目前，在一些宽视角液晶显示器中常使用多畴显示模式来增大显示器的观看视角。多畴显示模式指在一个亚像素内划分出多个区域，位于不同区域内的液晶的偏转角度不同，与传统的单畴显示模式相比，多畴显示模式可降低由于像素内的全部液晶的偏转角度相同而造成的不同观看视角上的对比度差异，进而增大了观看视角。但是，目前现有的宽视角液晶显示器对视角的改善幅度有限，无法满足日益增加的广视角需求，如电子竞技和虚拟现实(VR)屏幕等。
因此，急需提供一种新的显示面板以解决上述问题。
 技术问题
本申请实施例提供一种阵列基板、显示面板，能够解决现有显示面板的视角较窄，无法满足日益增加的广视角需求的技术问题。
 技术解决方案
本申请提供一种阵列基板，包括在基板上阵列分布的子像素，每一所述子像素均包括主区、第一次区和第二次区；
对应每一行所述子像素设置一条栅极线，所述栅极线位于所述主区与所述第二次区之间，对应每一列所述子像素设置一条数据线和一条分压线，相邻两所述数据线界定出像素边界，所述分压线位于相邻两所述数据线之间；
像素电极，包括对应所述主区设置的主像素电极、对应所述第一次区设置的第一次像素电极以及对应所述第二次区设置的第二次像素电极；
所述子像素还包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管，所述第一薄膜晶体管与所述第一次像素电极电连接，所述第二薄膜晶体管与所述主像素电极电连接，所述第三薄膜晶体管与所述第二次像素电极电连接，所述第四薄膜晶体管与所述分压线电连接；
其中，所述第二薄膜晶体管的沟道长径比大于所述第一薄膜晶体管的沟道长径比以及所述第三薄膜晶体管的沟道长径比。
在本申请的阵列基板中，所述第一薄膜晶体管的沟道长径比与所述第三薄膜晶体管的沟道长径比相同。
在本申请的阵列基板中，所述阵列基板还包括公共电极，所述公共电极与所述栅极线同层设置，所述公共电极对应所述主区、所述第一次区和所述第二次区设置。
在本申请的阵列基板中，所述子像素的所述主像素电极与所述公共电极之间形成第一电位差，所述第一次像素电极与所述公共电极之间形成第二电位差，所述第二次像素电极与所述公共电极之间形成第三电位差，且所述第一电位差大于所述第三电位差，所述第三电位差大于所述第二电位差。
在本申请的阵列基板中，所述第一薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第一次像素电极、所述公共电极以及所述第三薄膜晶体管的源极电连接；
所述第二薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述主像素电极以及所述公共电极电连接；
所述第三薄膜晶体管的栅极与所述栅极线电连接，漏极分别与所述第二次像素电极、所述公共电极以及所述第四薄膜晶体管的源极电连接；
所述第四薄膜晶体管的栅极与所述栅极线电连接，漏极与所述分压线电连接。
在本申请的阵列基板中，所述子像素还包括对应所述主区的主存储电容和主液晶电容，对应所述第一次区的第一次存储电容和第一次液晶电容，对应所述第二次区的第二次存储电容和第二次液晶电容。
在本申请的阵列基板中，所述第一薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第一次像素电极以及所述公共电极电连接；
所述第二薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述主像素电极以及所述公共电极电连接；
所述第三薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第二次像素电极、所述公共电极以及所述第四薄膜晶体管的源极电连接；
所述第四薄膜晶体管的栅极与所述栅极线电连接，漏极与所述分压线电连接。
在本申请的阵列基板中，所述子像素还包括对应所述主区的主存储电容和主液晶电容，对应所述第一次区的第一次存储电容和第一次液晶电容，对应所述第二次区的第二次存储电容和第二次液晶电容。
在本申请的阵列基板中，所述第一次存储电容的第一极板以及所述第一次液晶电容的第一极板均与所述第一薄膜晶体管的漏极电连接，所述第一次存储电容的第二极板与所述第一次像素电极电连接，所述第一次液晶电容的第二极板与所述公共电极电连接；
所述主存储电容的第一极板以及所述主液晶电容的第一极板均与所述第二薄膜晶体管的漏极电连接，所述主存储电容的第二极板与所述主像素电极电连接，所述主液晶电容的第二极板与所述公共电极电连接；
所述第二次存储电容的第一极板以及所述第二次液晶电容的第一极板均与所述第三薄膜晶体管的漏极电连接，所述第二次存储电容的第二极板与所述第二次像素电极电连接，所述第二次液晶电容的第二极板与所述公共电极电连接。
在本申请的阵列基板中，对应所述主区、所述第一次区和所述第二次区的所述公共电极的电位相同。
本申请还提供一种显示面板，包括如上所述的阵列基板和彩膜基板，以及位于所述阵列基板与所述彩膜基板之间的液晶层，所述显示面板包括阵列分布的子像素，每一所述子像素的主区、第一次区和第二次区各自对应四个畴的液晶分子。
本申请还提供一种阵列基板，包括在基板上阵列分布的子像素，每一所述子像素均包括主区、第一次区和第二次区；
对应每一行所述子像素设置一条栅极线，所述栅极线位于所述主区与所述第二次区之间，对应每一列所述子像素设置一条数据线和一条分压线，相邻两所述数据线界定出像素边界，所述分压线位于相邻两所述数据线之间；
像素电极，包括对应所述主区设置的主像素电极、对应所述第一次区设置的第一次像素电极以及对应所述第二次区设置的第二次像素电极；
公共电极，所述公共电极与所述栅极线同层设置，所述公共电极对应所述主区、所述第一次区和所述第二次区设置；
所述子像素还包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管，所述第一薄膜晶体管与所述第一次像素电极电连接，所述第二薄膜晶体管与所述主像素电极电连接，所述第三薄膜晶体管与所述第二次像素电极电连接，所述第四薄膜晶体管与所述分压线电连接；
其中，所述第二薄膜晶体管的沟道长径比大于所述第一薄膜晶体管的沟道长径比以及所述第三薄膜晶体管的沟道长径比，且所述第一薄膜晶体管的沟道长径比与所述第三薄膜晶体管的沟道长径比相同。
在本申请的阵列基板中，所述子像素的所述主像素电极与所述公共电极之间形成第一电位差，所述第一次像素电极与所述公共电极之间形成第二电位差，所述第二次像素电极与所述公共电极之间形成第三电位差，且所述第一电位差大于所述第三电位差，所述第三电位差大于所述第二电位差。
在本申请的阵列基板中，所述第一薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第一次像素电极、所述公共电极以及所述第三薄膜晶体管的源极电连接；
所述第二薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述主像素电极以及所述公共电极电连接；
所述第三薄膜晶体管的栅极与所述栅极线电连接，漏极分别与所述第二次像素电极、所述公共电极以及所述第四薄膜晶体管的源极电连接；
所述第四薄膜晶体管的栅极与所述栅极线电连接，漏极与所述分压线电连接。
在本申请的阵列基板中，所述子像素还包括对应所述主区的主存储电容和主液晶电容，对应所述第一次区的第一次存储电容和第一次液晶电容，对应所述第二次区的第二次存储电容和第二次液晶电容。
在本申请的阵列基板中，所述第一薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第一次像素电极以及所述公共电极电连接；
所述第二薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述主像素电极以及所述公共电极电连接；
所述第三薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第二次像素电极、所述公共电极以及所述第四薄膜晶体管的源极电连接；
所述第四薄膜晶体管的栅极与所述栅极线电连接，漏极与所述分压线电连接。
在本申请的阵列基板中，所述子像素还包括对应所述主区的主存储电容和主液晶电容，对应所述第一次区的第一次存储电容和第一次液晶电容，对应所述第二次区的第二次存储电容和第二次液晶电容。
在本申请的阵列基板中，所述第一次存储电容的第一极板以及所述第一次液晶电容的第一极板均与所述第一薄膜晶体管的漏极电连接，所述第一次存储电容的第二极板与所述第一次像素电极电连接，所述第一次液晶电容的第二极板与所述公共电极电连接；
所述主存储电容的第一极板以及所述主液晶电容的第一极板均与所述第二薄膜晶体管的漏极电连接，所述主存储电容的第二极板与所述主像素电极电连接，所述主液晶电容的第二极板与所述公共电极电连接；
所述第二次存储电容的第一极板以及所述第二次液晶电容的第一极板均与所述第三薄膜晶体管的漏极电连接，所述第二次存储电容的第二极板与所述第二次像素电极电连接，所述第二次液晶电容的第二极板与所述公共电极电连接。
在本申请的阵列基板中，对应所述主区、所述第一次区和所述第二次区的所述公共电极的电位相同。
 有益效果
本申请实施例提供的阵列基板、显示面板，设计了一种十二畴的像素结构，每一子像素均包括主区、第一次区和第二次区以及四个薄膜晶体管；主区、第一次区和第二次区这三个显示区分别采用一个薄膜晶体管进行驱动。本申请通过增大驱动主区的薄膜晶体管的沟道长径比，并且通过第四个薄膜晶体管的漏极与分压线电连接以对第二次区进行分压，从而使子像素在主区、第一次区和第二次区的电位差各不相同，使每个畴的液晶分子偏转角度不同，进而使显示面板获得更宽广的视角。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的阵列基板的像素结构示意图。
图2为本申请一种实施例提供的像素结构的等效电路图。
图3为本申请另一种实施例提供的像素结构的等效电路图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
具体的，请参阅图1所示，为本申请实施例提供的阵列基板的像素结构示意图，本申请的阵列基板包括在基板上阵列分布的子像素，此处仅以一个子像素为例进行说明，可以理解的是，其他子像素与该子像素的结构相同。
所述阵列基板包括多条栅极线1与多条数据线2以及多条分压线3，其中，对应每一行所述子像素设置有一条所述栅极线1，对应每一列所述子像素设置有一条所述数据线2和一条所述分压线3，相邻两所述数据线2界定出像素边界，所述分压线3位于相邻两所述数据线2之间。所述子像素包括主区（即主显示区）4、第一次区（即第一次显示区）5和第二次区（即第二次显示区）6，所述栅极线1位于所述主区4与所述第二次区6之间。
所述阵列基板还包括与所述栅极线1同层设置的公共电极7，所述公共电极7包括对应所述主区4的主公共电极71，以及对应所述第一次区5和所述第二次区6设置的次公共电极72。所述公共电极7可以为透明电极，如氧化铟锡、氧化铟镓锡等，此处不做限制。
在其他实施例中，所述公共电极7对应所述第一次区5和所述第二次区6分别设置有第一次公共电极和第二次公共电极。
所述阵列基板还包括像素电极8，所述像素电极8包括对应所述主区4设置的主像素电极81、对应所述第一次区5设置的第一次像素电极82以及对应所述第二次区6设置的第二次像素电极83。所述像素电极8可以为透明电极，如氧化铟锡、氧化铟镓锡等，此处不做限制。
在一种实施例中，所述像素电极8为鱼骨状或“米”字形结构。
所述子像素的所述主像素电极81与所述主公共电极71之间形成第一电位差，所述第一次像素电极82与所述次公共电极72之间形成第二电位差，所述第二次像素电极83与所述次公共电极72之间形成第三电位差。其中，对应所述主区4、所述第一次区5和所述第二次区6的所述公共电极7的电位相同。
所述子像素还包括位于所述主区4与所述第二次区6之间的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3以及第四薄膜晶体管T4，所述第一薄膜晶体管T1的漏极通过过孔与所述第一次像素电极82电连接，所述第二薄膜晶体管T2的漏极通过过孔与所述主像素电极81电连接，所述第三薄膜晶体管T3的漏极通过过孔与所述第二次像素电极83电连接，所述第四薄膜晶体管T4的漏极与所述分压线3电连接。
其中，所述数据线2分别通过第一薄膜晶体管T1、所述第二薄膜晶体管T2和所述第三薄膜晶体管T3向所述子像素的三个显示区充电。其中所述第二薄膜晶体管T2的沟道长径比（W/L）大于所述第一薄膜晶体管T1的沟道长径比以及所述第三薄膜晶体管T3的沟道长径比。即所述第二薄膜晶体管T2的沟道长径比最大，因而其充电能力最强，因此，所述主区4的像素电压最大。所述第一薄膜晶体管T1的沟道长径比与所述第三薄膜晶体管T3的沟道长径比相同。同时，所述第二次区6对应的所述第二次像素电极83的电位通过所述第四薄膜晶体管T4分压到所述分压线3上，导致所述第二次区6的像素电压比所述第一次区5的像素电压低。
因此，所述子像素的所述主区4、所述第一次区5以及所述第二次区6的像素电压各不相同，且所述第一电位差大于所述第三电位差，所述第三电位差大于所述第二电位差，从而使得对应所述主区4、所述第一次区5以及所述第二次区6的液晶分子的偏转角度不同；又由于所述主区4、所述第一次区5和所述第二次区6各自对应四个畴，因此每个畴的液晶分子的偏转角度均不同，从而使显示面板获得更宽广的视角。
结合图2所示，为本申请一种实施例提供的像素结构的等效电路图。此处仅以一个子像素为例进行说明。所述子像素包括第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4。
其中，所述第一薄膜晶体管T1的栅极与所述栅极线1电连接，源极与所述数据线2电连接，漏极分别与所述第一次像素电极82、所述次公共电极72以及所述第三薄膜晶体管T3的源极电连接。
所述第二薄膜晶体管T2的栅极与所述栅极线1电连接，源极与所述数据线2电连接，漏极分别与所述主像素电极81以及所述主公共电极71电连接。
所述第三薄膜晶体管T3的栅极与所述栅极线1电连接，漏极分别与所述第二次像素电极83、所述次公共电极72以及所述第四薄膜晶体管T4的源极电连接。
所述第四薄膜晶体管T4的栅极与所述栅极线1电连接，漏极与所述分压线3电连接。
所述子像素还包括对应所述主区4的主存储电容Cst1和主液晶电容Clc1，对应所述第一次区5的第一次存储电容Cst2和第一次液晶电容Clc2，对应所述第二次区6的第二次存储电容Cst3和第二次液晶电容Clc3。
所述主存储电容Cst1的第一极板以及所述主液晶电容Clc1的第一极板均与所述第二薄膜晶体管T2的漏极电连接，所述主存储电容Cst1的第二极板与所述主像素电极81电连接，所述主液晶电容Clc1的第二极板与所述主公共电极71电连接。
所述第一次存储电容Cst2的第一极板以及所述第一次液晶电容Clc2的第一极板均与所述第一薄膜晶体管T1的漏极电连接，所述第一次存储电容Cst2的第二极板与所述第一次像素电极82电连接，所述第一次液晶电容Clc2的第二极板与所述次公共电极72电连接。
所述第二次存储电容Cst3的第一极板以及所述第二次液晶电容Clc3的第一极板均与所述第三薄膜晶体管T3的漏极电连接，所述第二次存储电容Cst3的第二极板与所述第二次像素电极83电连接，所述第二次液晶电容Clc3的第二极板与所述次公共电极72电连接。
结合图3所示，为本申请另一种实施例提供的像素结构的等效电路图。此处仅以一个子像素为例进行说明。
其中，所述第一薄膜晶体管T1的栅极与所述栅极线1电连接，源极与所述数据线2电连接，漏极分别与所述第一次像素电极82以及所述次公共电极72电连接。
所述第二薄膜晶体管T2的栅极与所述栅极线1电连接，源极与所述数据线2电连接，漏极分别与所述主像素电极81以及所述主公共电极电71连接。
所述第三薄膜晶体管T3的栅极与所述栅极线1电连接，源极与所述数据线2电连接，漏极分别与所述第二次像素电极83、所述次公共电极72以及所述第四薄膜晶体管T4的源极电连接。
所述第四薄膜晶体管T4的栅极与所述栅极线1电连接，漏极与所述分压线3电连接。
所述子像素还包括对应所述主区4的主存储电容Cst1和主液晶电容Clc1，对应所述第一次区5的第一次存储电容Cst2和第一次液晶电容Clc2，对应所述第二次区6的第二次存储电容Cst3和第二次液晶电容Clc3。
所述主存储电容Cst1的第一极板以及所述主液晶电容Clc1的第一极板均与所述第二薄膜晶体管T2的漏极电连接，所述主存储电容Cst1的第二极板与所述主像素电极81电连接，所述主液晶电容Clc1的第二极板与所述主公共电极71电连接。
所述第一次存储电容Cst2的第一极板以及所述第一次液晶电容Clc2的第一极板均与所述第一薄膜晶体管T1的漏极电连接，所述第一次存储电容Cst2的第二极板与所述第一次像素电极82电连接，所述第一次液晶电容Clc2的第二极板与所述次公共电极72电连接。
所述第二次存储电容Cst3的第一极板以及所述第二次液晶电容Clc3的第一极板均与所述第三薄膜晶体管T3的漏极电连接，所述第二次存储电容Cst3的第二极板与所述第二次像素电极83电连接，所述第二次液晶电容Clc3的第二极板与所述次公共电极72电连接。
在本申请中，所述数据线2分别通过第一薄膜晶体管T1、所述第二薄膜晶体管T2和所述第三薄膜晶体管T3向所述子像素的三个显示区充电。其中所述第二薄膜晶体管T2的沟道长径比最大，因而其充电能力最强，因此，所述主区4的像素电压最大。所述第一薄膜晶体管T1的沟道长径比与所述第三薄膜晶体管T3的沟道长径比相同。同时，所述第二次区6对应的所述第二次像素电极83的电位通过所述第四薄膜晶体管T4分压到所述分压线3上，导致所述第二次区6的像素电压比所述第一次区5的像素电压低。因此，所述子像素的所述主区4、所述第一次区5以及所述第二次区6的像素电压各不相同，而所述主区4、所述第一次区5和所述第二次区6各自对应四个畴，从而使得每个畴的液晶分子的偏转角度均不同，进而使显示面板获得更宽广的视角。
本申请还提供一种显示面板，包括如上所述的阵列基板和彩膜基板，以及位于所述阵列基板与所述彩膜基板之间的液晶层，所述显示面板包括阵列分布的子像素，每一所述子像素的主区、第一次区和第二次区各自对应四个畴的液晶分子。所述显示面板的像素结构具体请参照上述对阵列基板中的描述，此处不再赘述。
以上对本申请实施例所提供的一种阵列基板及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (19)

  1. 一种阵列基板，其包括在基板上阵列分布的子像素，每一所述子像素均包括主区、第一次区和第二次区；
    对应每一行所述子像素设置一条栅极线，所述栅极线位于所述主区与所述第二次区之间，对应每一列所述子像素设置一条数据线和一条分压线，相邻两所述数据线界定出像素边界，所述分压线位于相邻两所述数据线之间；
    像素电极，包括对应所述主区设置的主像素电极、对应所述第一次区设置的第一次像素电极以及对应所述第二次区设置的第二次像素电极；
    所述子像素还包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管，所述第一薄膜晶体管与所述第一次像素电极电连接，所述第二薄膜晶体管与所述主像素电极电连接，所述第三薄膜晶体管与所述第二次像素电极电连接，所述第四薄膜晶体管与所述分压线电连接；
    其中，所述第二薄膜晶体管的沟道长径比大于所述第一薄膜晶体管的沟道长径比以及所述第三薄膜晶体管的沟道长径比。
  2. 如权利要求1所述的阵列基板，其中，所述第一薄膜晶体管的沟道长径比与所述第三薄膜晶体管的沟道长径比相同。
  3. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括公共电极，所述公共电极与所述栅极线同层设置，所述公共电极对应所述主区、所述第一次区和所述第二次区设置。
  4. 如权利要求3所述的阵列基板，其中，所述子像素的所述主像素电极与所述公共电极之间形成第一电位差，所述第一次像素电极与所述公共电极之间形成第二电位差，所述第二次像素电极与所述公共电极之间形成第三电位差，且所述第一电位差大于所述第三电位差，所述第三电位差大于所述第二电位差。
  5. 如权利要求3所述的阵列基板，其中，
    所述第一薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第一次像素电极、所述公共电极以及所述第三薄膜晶体管的源极电连接；
    所述第二薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述主像素电极以及所述公共电极电连接；
    所述第三薄膜晶体管的栅极与所述栅极线电连接，漏极分别与所述第二次像素电极、所述公共电极以及所述第四薄膜晶体管的源极电连接；
    所述第四薄膜晶体管的栅极与所述栅极线电连接，漏极与所述分压线电连接。
  6. 如权利要求5所述的阵列基板，其中，所述子像素还包括对应所述主区的主存储电容和主液晶电容，对应所述第一次区的第一次存储电容和第一次液晶电容，对应所述第二次区的第二次存储电容和第二次液晶电容。
  7. 如权利要求3所述的阵列基板，其中，
    所述第一薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第一次像素电极以及所述公共电极电连接；
    所述第二薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述主像素电极以及所述公共电极电连接；
    所述第三薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第二次像素电极、所述公共电极以及所述第四薄膜晶体管的源极电连接；
    所述第四薄膜晶体管的栅极与所述栅极线电连接，漏极与所述分压线电连接。
  8. 如权利要求7所述的阵列基板，其中，所述子像素还包括对应所述主区的主存储电容和主液晶电容，对应所述第一次区的第一次存储电容和第一次液晶电容，对应所述第二次区的第二次存储电容和第二次液晶电容。
  9. 如权利要求8所述的阵列基板，其中，
    所述第一次存储电容的第一极板以及所述第一次液晶电容的第一极板均与所述第一薄膜晶体管的漏极电连接，所述第一次存储电容的第二极板与所述第一次像素电极电连接，所述第一次液晶电容的第二极板与所述公共电极电连接；
    所述主存储电容的第一极板以及所述主液晶电容的第一极板均与所述第二薄膜晶体管的漏极电连接，所述主存储电容的第二极板与所述主像素电极电连接，所述主液晶电容的第二极板与所述公共电极电连接；
    所述第二次存储电容的第一极板以及所述第二次液晶电容的第一极板均与所述第三薄膜晶体管的漏极电连接，所述第二次存储电容的第二极板与所述第二次像素电极电连接，所述第二次液晶电容的第二极板与所述公共电极电连接。
  10. 如权利要求3所述的阵列基板，其中，对应所述主区、所述第一次区和所述第二次区的所述公共电极的电位相同。
  11. 一种显示面板，其包括如权利要求1所述的阵列基板和彩膜基板，以及位于所述阵列基板与所述彩膜基板之间的液晶层，所述显示面板包括阵列分布的子像素，每一所述子像素的主区、第一次区和第二次区各自对应四个畴的液晶分子。
  12. 一种阵列基板，其包括在基板上阵列分布的子像素，每一所述子像素均包括主区、第一次区和第二次区；
    对应每一行所述子像素设置一条栅极线，所述栅极线位于所述主区与所述第二次区之间，对应每一列所述子像素设置一条数据线和一条分压线，相邻两所述数据线界定出像素边界，所述分压线位于相邻两所述数据线之间；
    像素电极，包括对应所述主区设置的主像素电极、对应所述第一次区设置的第一次像素电极以及对应所述第二次区设置的第二次像素电极；
    公共电极，所述公共电极与所述栅极线同层设置，所述公共电极对应所述主区、所述第一次区和所述第二次区设置；
    所述子像素还包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管，所述第一薄膜晶体管与所述第一次像素电极电连接，所述第二薄膜晶体管与所述主像素电极电连接，所述第三薄膜晶体管与所述第二次像素电极电连接，所述第四薄膜晶体管与所述分压线电连接；
    其中，所述第二薄膜晶体管的沟道长径比大于所述第一薄膜晶体管的沟道长径比以及所述第三薄膜晶体管的沟道长径比，且所述第一薄膜晶体管的沟道长径比与所述第三薄膜晶体管的沟道长径比相同。
  13. 如权利要求12所述的阵列基板，其中，所述子像素的所述主像素电极与所述公共电极之间形成第一电位差，所述第一次像素电极与所述公共电极之间形成第二电位差，所述第二次像素电极与所述公共电极之间形成第三电位差，且所述第一电位差大于所述第三电位差，所述第三电位差大于所述第二电位差。
  14. 如权利要求12所述的阵列基板，其中，
    所述第一薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第一次像素电极、所述公共电极以及所述第三薄膜晶体管的源极电连接；
    所述第二薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述主像素电极以及所述公共电极电连接；
    所述第三薄膜晶体管的栅极与所述栅极线电连接，漏极分别与所述第二次像素电极、所述公共电极以及所述第四薄膜晶体管的源极电连接；
    所述第四薄膜晶体管的栅极与所述栅极线电连接，漏极与所述分压线电连接。
  15. 如权利要求14所述的阵列基板，其中，所述子像素还包括对应所述主区的主存储电容和主液晶电容，对应所述第一次区的第一次存储电容和第一次液晶电容，对应所述第二次区的第二次存储电容和第二次液晶电容。
  16. 如权利要求12所述的阵列基板，其中，
    所述第一薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第一次像素电极以及所述公共电极电连接；
    所述第二薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述主像素电极以及所述公共电极电连接；
    所述第三薄膜晶体管的栅极与所述栅极线电连接，源极与所述数据线电连接，漏极分别与所述第二次像素电极、所述公共电极以及所述第四薄膜晶体管的源极电连接；
    所述第四薄膜晶体管的栅极与所述栅极线电连接，漏极与所述分压线电连接。
  17. 如权利要求16所述的阵列基板，其中，所述子像素还包括对应所述主区的主存储电容和主液晶电容，对应所述第一次区的第一次存储电容和第一次液晶电容，对应所述第二次区的第二次存储电容和第二次液晶电容。
  18. 如权利要求17所述的阵列基板，其中，
    所述第一次存储电容的第一极板以及所述第一次液晶电容的第一极板均与所述第一薄膜晶体管的漏极电连接，所述第一次存储电容的第二极板与所述第一次像素电极电连接，所述第一次液晶电容的第二极板与所述公共电极电连接；
    所述主存储电容的第一极板以及所述主液晶电容的第一极板均与所述第二薄膜晶体管的漏极电连接，所述主存储电容的第二极板与所述主像素电极电连接，所述主液晶电容的第二极板与所述公共电极电连接；
    所述第二次存储电容的第一极板以及所述第二次液晶电容的第一极板均与所述第三薄膜晶体管的漏极电连接，所述第二次存储电容的第二极板与所述第二次像素电极电连接，所述第二次液晶电容的第二极板与所述公共电极电连接。
  19. 如权利要求12所述的阵列基板，其中，对应所述主区、所述第一次区和所述第二次区的所述公共电极的电位相同。
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