WO2018184257A1 - 阵列基板 - Google Patents

阵列基板 Download PDF

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Publication number
WO2018184257A1
WO2018184257A1 PCT/CN2017/081035 CN2017081035W WO2018184257A1 WO 2018184257 A1 WO2018184257 A1 WO 2018184257A1 CN 2017081035 W CN2017081035 W CN 2017081035W WO 2018184257 A1 WO2018184257 A1 WO 2018184257A1
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Prior art keywords
sub
electrode
region
pixel electrode
area
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PCT/CN2017/081035
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English (en)
French (fr)
Inventor
甘启明
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/540,032 priority Critical patent/US10541255B2/en
Publication of WO2018184257A1 publication Critical patent/WO2018184257A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate.
  • Liquid crystal display is one of the most widely used flat panel displays.
  • the liquid crystal panel is a core component of liquid crystal displays.
  • the liquid crystal panel is usually composed of a color filter (CF), a thin film transistor array substrate (TFT Array Substrate), and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates. Composition.
  • a pixel electrode and a common electrode are respectively disposed on the array substrate and the color filter substrate. When a voltage is applied to the pixel electrode and the common electrode, an electric field is generated in the liquid crystal layer, which determines the orientation of the liquid crystal molecules, thereby adjusting the polarization of light incident on the liquid crystal layer, so that the liquid crystal panel displays an image.
  • the prior art In order to increase the viewing angle of the liquid crystal display, the prior art generally adopts a multi-domain technique, that is, dividing one sub-pixel into a plurality of regions, and causing the liquid crystal in each region to fall in different directions after applying a voltage. So that the effects seen in all directions tend to be average and consistent.
  • a multi-domain technique that is, dividing one sub-pixel into a plurality of regions, and causing the liquid crystal in each region to fall in different directions after applying a voltage. So that the effects seen in all directions tend to be average and consistent.
  • the pixel electrode As a m-shaped slit electrode structure.
  • the m-shaped slit electrode structure includes: strip-shaped The vertical trunk and the strip-shaped horizontal trunk, and the vertical trunk and the horizontal trunk center intersect perpendicularly.
  • the so-called center-vertical intersection means that the vertical trunk and the horizontal trunk are perpendicular to each other, and the two divide the entire pixel electrode area into four regions on average ( Domain).
  • Each pixel electrode region is composed of strip branches of ⁇ 45° and ⁇ 135° angles to the vertical trunk or horizontal trunk, and each strip branch is located on the same plane as the vertical trunk and the horizontal trunk, through special The oblique electric field generated by the pixel electrode pattern induces liquid crystal molecules in different regions to reversing in different directions.
  • the square-shaped slit electrode has a certain visual chromatic aberration or visual color shift due to the same angle between the strip branches in each pixel electrode region and the vertical trunk and the horizontal stem, and the transmittance of the liquid crystal panel It will also drop.
  • the prior art divides a sub-pixel into a main area and a sub-area, and sets an independent main-area pixel electrode in the main area, and sets an independent sub-area pixel electrode in the sub-area.
  • Both the main-region pixel electrode and the sub-region pixel electrode employ the above-described m-shaped slit electrode, thereby realizing 8-domain display. As shown in FIG.
  • each sub-pixel of the conventional liquid crystal display includes: a main-region thin film transistor T100, a sub-region thin film transistor T200, a charge sharing thin film transistor T300, a main-region liquid crystal capacitor C100, and a sub-region liquid crystal capacitor C200.
  • the Lord a storage capacitor C300 and a secondary storage capacitor C400.
  • the gate of the main-region thin film transistor T100 is electrically connected to the scan line Gate corresponding to the sub-pixel, and the source is electrically connected to the data line Data corresponding to the sub-pixel.
  • One end of the main-region liquid crystal capacitor C100 is connected to the gate of the sub-pixel thin film transistor T200, and the source is electrically connected to the data line Data corresponding to the sub-pixel, and the drain is electrically connected.
  • the gate of the charge sharing thin film transistor T300 is electrically connected to the scan line Gate corresponding to the sub-pixel, the source is connected to the array substrate common voltage Acom, and the drain is electrically connected to the sub-region liquid crystal capacitor
  • One end of the C200, the other end of the main area liquid crystal capacitor C100 and the sub-area liquid crystal capacitor C200 are connected to the color film substrate common voltage Ccom, and one end of the main area storage capacitor C300 is electrically connected to one end of the main area liquid crystal capacitor C100.
  • one end of the sub-region storage capacitor C400 is electrically connected to one end of the sub-region liquid crystal capacitor C200, and the other end is connected to the array substrate common voltage Acom
  • One end of the liquid crystal capacitor C100 is a pixel electrode 101 of the main region
  • one end of the liquid crystal capacitor C200 of the sub-region is a sub-region pixel electrode 201.
  • the main-region thin film transistor T100 charges the pixel electrode 101 of the main region, and the sub-region thin film transistor T200 is used.
  • the pixel electrode 201 is charged, and the charge sharing thin film transistor T300 discharges the sub-region pixel electrode 201, so that the main region and the sub-region generate different potentials to increase the viewing angle, but each of the sub-pixel structures includes three TFT, too many TFTs will cause the aperture ratio of the pixel itself to decrease, and due to the charge sharing technique, the pixel voltages of the main and sub-regions will be different, which will increase the optimum common voltage of the main and sub-regions. (Best Vcom) The difficulty of balancing regulation.
  • An object of the present invention is to provide an array substrate capable of improving color shift, increasing the aperture ratio of a pixel, and reducing the difficulty of optimal common voltage balance regulation of the main area and the sub-area.
  • the present invention provides an array substrate comprising: a plurality of sub-pixels arranged in an array, a plurality of horizontally spaced horizontal scanning lines, and a plurality of vertically spaced data lines arranged in parallel;
  • Each row of sub-pixels corresponds to one scan line, and each column of sub-pixels corresponds to one data line.
  • Each sub-pixel includes: a control thin film transistor and a pixel electrode; and the gate of the control thin film transistor is electrically connected to the row of sub-pixels.
  • a scan line the source is electrically connected to the data line corresponding to the row of sub-pixels, and the drain is electrically connected to the pixel electrode;
  • the pixel electrode comprises: a main area pixel electrode and a sub-area pixel electrode arranged at intervals, and an electrical connection a first connection electrode of the main area pixel electrode and the sub-area pixel electrode;
  • the main area pixel electrode includes: a cross-shaped main area trunk electrode, and the main area trunk electrode divides the main area pixel electrode into four main area alignment areas, and each of the main area alignment areas is provided a plurality of mutually parallel strip-shaped main-area branch electrodes connected to the trunk electrode of the main area, and a main-area slit is formed between the adjacent two main-area branch electrodes, and adjacent two main-area alignment areas
  • the main area branch electrode is symmetrical about the main area trunk electrode;
  • the sub-area pixel electrode includes: a cross-shaped sub-area body electrode, and the cross-shaped sub-area body electrode divides the sub-area pixel electrode into four times a region matching region, wherein each of the sub-region alignment regions is provided with a plurality of mutually parallel strip-shaped sub-region branch electrodes connected to the torso electrodes of the sub-region, and sub-regions are formed between the adjacent two-region branch electrodes a slit, the sub-region branch electrode in the adjacent two sub-region alignment
  • the width of the branch electrode of the main region is smaller than the width of the branch electrode of the sub-region, and the width of the slit of the main region is smaller than the width of the slit of the sub-region.
  • the angle between the main zone branch electrode and the main zone trunk electrode is 40° to 45°.
  • the angle between the secondary region branch electrode and the secondary region trunk electrode is 45°.
  • the width of the main region branch electrode is greater than 2 ⁇ m and less than 5 ⁇ m, and the width of the main region slit is greater than 2 ⁇ m and less than 5 ⁇ m.
  • the width of the sub-region branch electrode is greater than 3.5 ⁇ m and less than 6 ⁇ m, and the width of the sub-region slit is greater than 3.5 ⁇ m and less than 6 ⁇ m.
  • the area ratio of the main area pixel electrode and the sub-area pixel electrode is greater than 1/4 and less than 4.
  • the material of the pixel electrode is ITO.
  • the array substrate further includes: an array substrate common voltage trace, each sub-pixel further includes a storage capacitor, the storage capacitor includes: a first electrode plate and a second electrode plate disposed opposite to each other, the first electrode plate and The array substrate common voltage traces are electrically connected, and the second electrode plate is electrically connected to the drain of the control thin film transistor.
  • the gate of the thin film transistor, the scan line, the common voltage trace of the array substrate, and the first electrode plate are located at the first metal layer, the source and drain of the control thin film transistor, the data line, and the second electrode plate Each is located in a second metal layer that is insulatively laminated with the first metal layer.
  • the pixel electrode further includes a second connection electrode electrically connected to the main area pixel electrode, the second connection electrode being stacked on a drain of the control thin film transistor, the second connection electrode and the control An insulating layer is disposed between the drains of the thin film transistors, wherein the insulating layer is provided with a pixel electrode connection via extending through the insulating layer, and the second connection electrode is connected to the via via the pixel electrode and the control thin film transistor The drain is electrically connected.
  • the present invention also provides an array substrate comprising: a plurality of sub-pixels arranged in an array, a plurality of horizontal scanning lines arranged in parallel, and a plurality of vertical data lines arranged in parallel;
  • Each row of sub-pixels corresponds to one scan line, and each column of sub-pixels corresponds to one data line, and each of the sub-pixels includes: a control thin film transistor and a pixel electrode; the control thin film transistor
  • the gate electrode is electrically connected to the scan line corresponding to the row of sub-pixels, the source is electrically connected to the data line corresponding to the row of sub-pixels, and the drain is electrically connected to the pixel electrode;
  • the pixel electrode comprises: the main-area pixel electrode arranged at intervals And a sub-region pixel electrode, and a first connection electrode electrically connected to the main region pixel electrode and the sub-region pixel electrode;
  • the main area pixel electrode includes: a cross-shaped main area trunk electrode, and the main area trunk electrode divides the main area pixel electrode into four main area alignment areas, and each of the main area alignment areas is provided with a plurality of mutually parallel strip-shaped main-area branch electrodes connected to the trunk electrode of the main area, a main-area slit is formed between adjacent two main-area branch electrodes, and a main area in the adjacent two main-area alignment areas is formed
  • the branch electrode is symmetrical about the main area trunk electrode;
  • the sub-area pixel electrode includes: a cross-shaped sub-area body electrode, the cross-shaped sub-area body electrode separating the sub-area pixel electrode into four sub-area alignments And each of the sub-region alignment regions is provided with a plurality of mutually parallel strip-shaped sub-region branch electrodes connected to the sub-area torso electrodes, and sub-region slits are formed between the adjacent two-region branch electrodes a sub-region branch electrode in the adjacent two sub-region alignment regions is
  • the width of the branch electrode of the main region is smaller than the width of the branch electrode of the sub-region, and the width of the slit of the main region is smaller than the width of the slit of the sub-region;
  • the width of the branch electrode of the main region is greater than 2 ⁇ m and less than 5 ⁇ m, and the width of the slit of the main region is greater than 2 ⁇ m and less than 5 ⁇ m;
  • the width of the sub-region branch electrode is greater than 3.5 ⁇ m and less than 6 ⁇ m
  • the width of the sub-region slit is greater than 3.5 ⁇ m and less than 6 ⁇ m.
  • the present invention provides an array substrate comprising: a plurality of sub-pixels arranged in an array, a plurality of horizontally arranged scanning lines arranged in parallel, and a plurality of vertically arranged data arranged in parallel
  • Each row of sub-pixels corresponds to one scan line
  • each column of sub-pixels corresponds to one data line
  • each of the sub-pixels includes: a control thin film transistor and a pixel electrode
  • the pixel electrode includes a main-area pixel electrode and a second interval a pixel electrode, and a first connection electrode electrically connected to the main area pixel electrode and the sub-area pixel electrode, wherein the main area pixel electrode and the sub-area pixel electrode are both a m-shaped slit electrode, and the main
  • the width of the main area branch electrode of the pixel electrode of the area is smaller than the width of the sub-area branch electrode of the sub-area pixel electrode, and the width of the main area slit of the main area pixel electrode is smaller than
  • 1 is an equivalent circuit diagram of a sub-pixel in a conventional liquid crystal display
  • FIG. 2 is a structural view of an array substrate of the present invention.
  • the present invention provides an array substrate comprising: a plurality of sub-pixels 10 arranged in an array, a plurality of horizontally spaced horizontal scanning lines 20, and a plurality of vertically spaced data lines 30 arranged in parallel;
  • Each row of sub-pixels 10 corresponds to one scan line 20, and each column of sub-pixels 10 corresponds to one data line 30.
  • Each of the sub-pixels 10 includes: a control thin film transistor T1 and a pixel electrode 40; the gate of the control thin film transistor T1 Electrically connecting the scan lines 20 corresponding to the row of sub-pixels, the source is electrically connected to the data line 30 corresponding to the row of sub-pixels, and the drain is electrically connected to the pixel electrode 40;
  • the pixel electrode 40 includes: main-area pixels arranged at intervals The electrode 41 and the sub-region pixel electrode 42, and the first connection electrode 43 electrically connected to the main region pixel electrode 41 and the sub-region pixel electrode 42;
  • the main area pixel electrode 41 includes a cross-shaped main area trunk electrode 411 that divides the main area pixel electrode 41 into four main area alignment areas 410, in each main area alignment area 410 are respectively provided with a plurality of mutually parallel strip-shaped main-area branch electrodes 412 connected to the main-area trunk electrode 411, and a main-region slit 413 is formed between the adjacent two main-area branch electrodes 412, adjacent to each other.
  • the main area branch electrodes 412 in the two main area alignment areas 410 are symmetrical with respect to the main area trunk electrodes 411;
  • the sub-area pixel electrodes 42 include: a cross-shaped sub-area torso electrodes 421, the cross-shaped sub-area torso
  • the electrode 421 divides the sub-region pixel electrode 42 into four sub-region alignment regions 420, and each sub-region alignment region 420 is provided with a plurality of mutually parallel strip-shaped times connected to the sub-region trunk electrode 421.
  • the sub-region slit electrode 423 is formed between the adjacent branch electrodes 422, and the sub-region branch electrode 422 in the adjacent two sub-region alignment regions 420 is symmetric with respect to the sub-region trunk electrode 421 ;
  • the width of the main-region branch electrode 412 is smaller than the width of the sub-region branch electrode 422, and the width of the main-region slit 413 is smaller than the width of the sub-region slit 423, that is, the main-region branch electrode 412 is smaller than the sub-region.
  • the branch electrode 422 is thinner, and the main region branch electrode 412 in the main region pixel electrode 41
  • the sub-region branch electrode 422 in the sub-region pixel electrode 42 is densely distributed.
  • the electric field intensity at the electrode 42 is large, so that the liquid crystal molecules corresponding to the main-region pixel electrode 41 are larger than the liquid crystal molecules corresponding to the sub-region pixel electrode 42, and the transmittance of the corresponding region of the main-region pixel electrode 41 is smaller than that of the sub-region.
  • the area corresponding to the pixel electrode 42 is high, thereby improving the color shift of the liquid crystal display.
  • the present invention can also adjust the area ratio of the main-region pixel electrode 41 to the sub-region pixel electrode 42, the angle between the main-region branch electrode 412 and the main-region trunk electrode 411, and the sub-region branch electrode 422 and the The angle between the trunk electrode 421 of the sub-region further increases the difference between the pixel electrode 41 of the main region and the pixel electrode 42 of the sub-region, thereby further improving the color shift improvement effect of the liquid crystal display.
  • an angle between the main-area branch electrode 412 and the main-area trunk electrode 411 may be 40° to 45°, and preferably, the main-area branch electrode 412 and the main-area trunk electrode 411 The angle between them is 45°.
  • an angle between the sub-region branch electrode 422 and the sub-region trunk electrode 421 may be 45°.
  • the width of the main-region branch electrode 412 (that is, the line width of the main-region pixel electrode 41) is larger than 2 ⁇ m and smaller than 5 ⁇ m, and the main-region slit 413 (that is, the line pitch of the main-region pixel electrode 41)
  • the width is larger than 2 ⁇ m and smaller than 5 ⁇ m.
  • the width of the main-region branch electrode 412 is 3.5 ⁇ m, and the width of the main-region slit 413 is 2.5 ⁇ m.
  • the width of the sub-region branch electrode 422 (that is, the line width of the sub-region pixel electrode 42) is greater than 3.5 ⁇ m and less than 6 ⁇ m, and the width of the sub-region slit 423 (ie, the line of the sub-region pixel electrode 42) The distance is greater than 3.5 ⁇ m and less than 6 ⁇ m.
  • the width of the sub-region branch electrode 422 is 5 ⁇ m, and the width of the sub-region slit 423 is 5 ⁇ m.
  • the area ratio of the main area pixel electrode 41 and the sub-area pixel electrode 42 is greater than 1/4 and less than 4.
  • the area ratio of the main area pixel electrode 41 to the sub-area pixel electrode 42 is 2: 3.
  • the array substrate further includes: an array substrate common voltage trace 60
  • each of the sub-pixels 10 further includes a storage capacitor C
  • the storage capacitor C includes: a first electrode plate 51 disposed opposite to each other.
  • the second electrode plate 52 the first electrode plate 51 is electrically connected to the array substrate common voltage trace 60
  • the second electrode plate 52 is electrically connected to the drain of the control thin film transistor T1.
  • the gate of the control thin film transistor T1, the scan line 20, the array substrate common voltage trace 60, and the first electrode plate 51 are located in the first metal layer, and the source of the control thin film transistor T1 And the drain, the data line 30, and the second electrode plate 52 are both located in a second metal layer that is insulatively laminated with the first metal layer.
  • the pixel electrode 40 further includes a second connection electrode 44 electrically connected to the main area pixel electrode 41.
  • the second connection electrode 44 is stacked on the drain of the control thin film transistor T1, and the second connection An insulating layer is disposed between the electrode 44 and the drain of the control thin film transistor T1, wherein the insulating layer is provided with a pixel electrode connection via 6 penetrating the insulating layer, and the second connection electrode 44 is connected via a pixel electrode
  • the via 6 is electrically connected to the drain of the control thin film transistor T1.
  • the material of the first metal layer and the second metal layer is a combination of one or more of metals such as aluminum, molybdenum and copper, between the first metal layer and the second metal layer, and second
  • the insulating material between the metal layer and the pixel electrode is one or a combination of silicon oxide (SiOx) and silicon nitride (SiNx).
  • the material of the pixel electrode 40 is ITO.
  • the first connecting electrode 43 is electrically connected to the main region trunk electrode 411 and the sub-region trunk electrode 421, and the extending direction thereof corresponds to the arrangement direction of the main region pixel electrode 41 and the sub-region pixel electrode 42.
  • the design of the line width, the line pitch, the area ratio, and the tilt angle of the branch electrodes of the main-region pixel electrode 41 and the sub-region pixel electrode 42 causes the main-region pixel electrode 41 to differ from the sub-region pixel electrode 42, especially such that the array
  • the transmittance of the region corresponding to the main-region pixel electrode 41 is larger than the region corresponding to the sub-region pixel electrode 42, and the color shift of the liquid crystal display can be improved.
  • the first connection electrode 43 of the present invention is further improved.
  • the main area pixel electrode 41 and the sub-area pixel electrode 42 are electrically connected so that the main area pixel electrode 41 and the sub-area pixel electrode 42 can be controlled by one thin film transistor, and the main area pixel electrode 41 and the sub-area pixel electrode 42 have The same voltage can reduce the difficulty of optimal common voltage balance regulation between the main zone and the secondary zone.
  • the present invention provides an array substrate, the array substrate comprising: a plurality of sub-pixels arranged in an array, a plurality of horizontal scanning lines arranged in parallel, and a plurality of vertical data lines arranged in parallel.
  • Each row of sub-pixels corresponds to one scan line
  • each column of sub-pixels corresponds to one data line
  • each of the sub-pixels includes: a control thin film transistor and a pixel electrode
  • the pixel electrode includes a main-area pixel electrode and a sub-region arranged at intervals a pixel electrode, and a first connection electrode electrically connected to the main area pixel electrode and the sub-area pixel electrode, wherein the main area pixel electrode and the sub-area pixel electrode are both a m-shaped slit electrode, and the main area
  • the width of the main-region branch electrode of the pixel electrode is smaller than the width of the sub-region branch electrode of the sub-region pixel electrode, and the width of the main-region slit of the main pixel electrode is
  • the main area pixel electrode and the sub-area are electrically connected through the main area pixel electrode and the sub-area pixel electrode.
  • the voltage on the pixel electrode is the same, which reduces the difficulty of adjusting the optimal common voltage balance between the main region and the sub-region.

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Abstract

提供一种阵列基板。所述阵列基板中每一个子像素（10）均包括：一控制薄膜晶体管（T1）和与控制薄膜晶体管（T1）电性连接的一像素电极（40），所述像素电极（40）包括间隔排列的主区像素电极（41）和次区像素电极（42）、以及电性连接所述主区像素电极（41）和次区像素电极（42）的第一连接电极（43），所述主区像素电极（41）和次区像素电极（42）的均为米字型的狭缝电极，所述主区像素电极（41）的主区分支电极（412）的宽度小于次区像素电极（42）的次区分支电极（422）的宽度，主区像素电极（41）的主区狭缝（413）的宽度小于次区像素电极（42）的次区狭缝（423）的宽度，能够通过主区像素电极（41）和次区像素电极（42）的结构差异来改善色偏，同时减少子像素（10）中的TFT数量，提升了像素的开口率，且降低主区与次区的最佳公共电压平衡调控的难度。

Description

阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板。
背景技术
液晶显示器(Liquid Crystal Display，LCD)是目前最广泛使用的平板显示器之一，液晶面板是液晶显示器的核心组成部分。液晶面板通常是由一彩色滤光片基板(Color Filter，CF)、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成。一般阵列基板、彩色滤光片基板上分别设置像素电极、公共电极。当电压被施加到像素电极与公共电极便会在液晶层中产生电场，该电场决定了液晶分子的取向，从而调整入射到液晶层的光的偏振，使液晶面板显示图像。
为了增大液晶显示器的视角，现有技术通常会采取多畴技术(multi-domain)，即将一个子像素划分成多个区域，并使每个区域中的液晶在施加电压后倒伏向不同的方向，从而使各个方向看到的效果趋于平均，一致。实现多畴技术的方法有多种，其中一种方法是将像素电极设计为米字型的狭缝(Slit)电极结构，具体地，所述米字型的狭缝电极结构包含：条状的竖直主干和条状的水平主干，且竖直主干和水平主干中心垂直相交，所谓中心垂直相交是指竖直主干和水平主干相互垂直，且二者将整个像素电极面积平均分成4个区域(domain)。每个像素电极区域都由与竖直主干或水平主干呈±45°、±135°角度的条状分支平铺组成，各条状分支与竖直主干和水平主干位于同一平面上，通过特殊的像素电极图案产生的倾斜电场诱导不同区域中的液晶分子倒向不同的方向。
这种米字型的狭缝电极，因每一像素电极区域内的条状分支与竖直主干和水平主干的夹角相同，会存在一定的视觉色差或视觉色偏，液晶面板的穿透率也会下降。为了改善视觉色差或视觉色偏，现有技术会将一个子像素分成主区和次区，在主区内设置一个独立的主区像素电极，在次区内设置一个独立的次区像素电极，主区像素电极与次区像素电极均采用上述的米字型的狭缝电极，从而实现8畴显示。如图1所示，现有的液晶显示器的每一个子像素内均包括：主区薄膜晶体管T100、次区薄膜晶体管T200、电荷共享薄膜晶体管T300、主区液晶电容C100、次区液晶电容C200、主 区存储电容C300、次区存储电容C400，所述主区薄膜晶体管T100的栅极电性连接该子像素对应的扫描线Gate，源极电性连接该子像素对应的数据线Data，漏极电性连接主区液晶电容C100的一端，所述次区薄膜晶体管T200的栅极电性连接该子像素对应的扫描线Gate，源极电性连接该子像素对应的数据线Data，漏极电性连接次区液晶电容C200的一端，所述电荷共享薄膜晶体管T300的栅极电性连接该子像素对应的扫描线Gate，源极接入阵列基板公共电压Acom，漏极电性连接次区液晶电容C200的一端，所述主区液晶电容C100与次区液晶电容C200的另一端均接入彩膜基板公共电压Ccom，所述主区存储电容C300的一端电性连接主区液晶电容C100的一端，另一端接入阵列基板公共电压Acom，所述次区存储电容C400的一端电性连接次区液晶电容C200的一端，另一端接入阵列基板公共电压Acom，所述主区液晶电容C100的一端为主区像素电极101，次区液晶电容C200的一端为次区像素电极201，工作时，主区薄膜晶体管T100为主区像素电极101充电，次区薄膜晶体管T200为次区像素电极201充电，电荷共享薄膜晶体管T300为次区像素电极201放电，从而使得主区与次区产生不同的电位，以增大视角，但上述的子像素结构中每一个子像素包含三个TFT，TFT数量过多会导致像素本身的开口率下降，并且由于采用了电荷分享技术，主区与次区的像素电压会产生差异，这又会加大主区与次区的最佳公共电压(Best Vcom)平衡调控的难度。
发明内容
本发明的目的在于提供一种阵列基板，能够改善色偏，提升像素的开口率，降低主区与次区的最佳公共电压平衡调控的难度。
为实现上述目的，本发明提供了一种阵列基板，包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；
每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：一控制薄膜晶体管和一像素电极；所述控制薄膜晶体管的栅极电性连接该行子像素对应的扫描线，源极电性连接该行子像素对应的数据线，漏极电性连接像素电极；所述像素电极包括：间隔排列的主区像素电极和次区像素电极、以及电性连接所述主区像素电极和次区像素电极的第一连接电极；
所述主区像素电极包括：十字形的主区躯干电极，所述主区躯干电极将所述主区像素电极分隔为四个主区配向区，在每一个主区配向区均设有 与所述主区躯干电极相连的多个相互平行的条状的主区分支电极，相邻的两主区分支电极之间形成有主区狭缝，相邻的两个主区配向区内的主区分支电极关于所述主区躯干电极对称；所述次区像素电极包括：十字形的次区躯干电极，所述十字形的次区躯干电极将所述次区像素电极分隔为四个次区配向区，在每一个次区配向区均设有与所述次区躯干电极相连的多个相互平行的条状的次区分支电极，相邻的两次区分支电极之间形成有次区狭缝，相邻的两个次区配向区内的次区分支电极关于所述次区躯干电极对称；
所述主区分支电极的宽度小于次区分支电极的宽度，所述主区狭缝的宽度小于次区狭缝的宽度。
所述主区分支电极与所述主区躯干电极之间的夹角为40°到45°。
所述次区分支电极与所述次区躯干电极之间的夹角为45°。
所述主区分支电极的宽度大于2μm且小于5μm，所述主区狭缝的宽度大于2μm且小于5μm。
所述次区分支电极的宽度大于3.5μm且小于6μm，所述次区狭缝的宽度大于3.5μm且小于6μm。
所述主区像素电极和次区像素电极的面积比大于1/4且小于4。
所述像素电极的材料为ITO。
所述阵列基板还包括：阵列基板公共电压走线，每一个子像素还包括一存储电容，所述存储电容包括：相对设置的第一电极板和第二电极板，所述第一电极板与所述阵列基板公共电压走线电性连接，所述第二电极板与所述控制薄膜晶体管的漏极电性连接。
所述控制薄膜晶体管的栅极、扫描线、阵列基板公共电压走线、以及第一电极板位于第一金属层，所述控制薄膜晶体管的源极和漏极、数据线、以及第二电极板均位于与所述第一金属层绝缘层叠的第二金属层。
所述像素电极还包括与所述主区像素电极电性连接的第二连接电极，所述第二连接电极层叠于所述控制薄膜晶体管的漏极上，所述第二连接电极与所述控制薄膜晶体管的漏极之间设有绝缘层，所述绝缘层中设有贯穿所述绝缘层的像素电极连接过孔，所述第二连接电极经由像素电极连接过孔与所述控制薄膜晶体管的漏极电性连接。
本发明还提供一种阵列基板，包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；
每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：一控制薄膜晶体管和一像素电极；所述控制薄膜晶体管 的栅极电性连接该行子像素对应的扫描线，源极电性连接该行子像素对应的数据线，漏极电性连接像素电极；所述像素电极包括：间隔排列的主区像素电极和次区像素电极、以及电性连接所述主区像素电极和次区像素电极的第一连接电极；
所述主区像素电极包括：十字形的主区躯干电极，所述主区躯干电极将所述主区像素电极分隔为四个主区配向区，在每一个主区配向区均设有与所述主区躯干电极相连的多个相互平行的条状的主区分支电极，相邻的两主区分支电极之间形成有主区狭缝，相邻的两个主区配向区内的主区分支电极关于所述主区躯干电极对称；所述次区像素电极包括：十字形的次区躯干电极，所述十字形的次区躯干电极将所述次区像素电极分隔为四个次区配向区，在每一个次区配向区均设有与所述次区躯干电极相连的多个相互平行的条状的次区分支电极，相邻的两次区分支电极之间形成有次区狭缝，相邻的两个次区配向区内的次区分支电极关于所述次区躯干电极对称；
所述主区分支电极的宽度小于次区分支电极的宽度，所述主区狭缝的宽度小于次区狭缝的宽度；
其中，所述主区分支电极的宽度大于2μm且小于5μm，所述主区狭缝的宽度大于2μm且小于5μm；
其中，所述次区分支电极的宽度大于3.5μm且小于6μm，所述次区狭缝的宽度大于3.5μm且小于6μm。
本发明的有益效果：本发明提供一种阵列基板，所述阵列基板包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：一控制薄膜晶体管和一像素电极，所述像素电极包括间隔排列的主区像素电极和次区像素电极、以及电性连接所述主区像素电极和次区像素电极的第一连接电极，所述主区像素电极和次区像素电极的均为米字型的狭缝电极，所述主区像素电极的主区分支电极的宽度小于次区像素电极的次区分支电极的宽度，主区像素电极的主区狭缝的宽度小于次区像素电极的次区狭缝的宽度，能够通过主区像素电极和次区像素电极的结构差异来改善色偏，同时减少每一个子像素中的TFT数量，提升了像素的开口率，通过主区像素电极和次区像素电极电性连接使得主区像素电极和次区像素电极上的电压相同，降低主区与次区的最佳公共电压平衡调控的难度。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的液晶显示器中的一子像素的等效电路图；
图2为本发明的阵列基板的结构图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明提供一种阵列基板，包括：阵列排布的多个子像素10、多条平行间隔排列的水平的扫描线20、以及多条平行间隔排列的竖直的数据线30；
每一行子像素10对应一条扫描线20，每一列子像素10对应一条数据线30，每一个子像素10均包括：一控制薄膜晶体管T1和一像素电极40；所述控制薄膜晶体管T1的栅极电性连接该行子像素对应的扫描线20，源极电性连接该行子像素对应的数据线30，漏极电性连接像素电极40；所述像素电极40包括：间隔排列的主区像素电极41和次区像素电极42、以及电性连接所述主区像素电极41和次区像素电极42的第一连接电极43；
所述主区像素电极41包括：十字形的主区躯干电极411，所述主区躯干电极411将所述主区像素电极41分隔为四个主区配向区410，在每一个主区配向区410均设有与所述主区躯干电极411相连的多个相互平行的条状的主区分支电极412，相邻的两主区分支电极412之间形成有主区狭缝413，相邻的两个主区配向区410内的主区分支电极412关于所述主区躯干电极411对称；所述次区像素电极42包括：十字形的次区躯干电极421，所述十字形的次区躯干电极421将所述次区像素电极42分隔为四个次区配向区420，在每一个次区配向区420均设有与所述次区躯干电极421相连的多个相互平行的条状的次区分支电极422，相邻的两次区分支电极422之间形成有次区狭缝423，相邻的两个次区配向区420内的次区分支电极422关于所述次区躯干电极421对称；
重点的是，所述主区分支电极412的宽度小于次区分支电极422的宽度，所述主区狭缝413的宽度小于次区狭缝423的宽度，也即主区分支电极412比次区分支电极422更细，且主区像素电极41中的主区分支电极412 比次区像素电极42中的次区分支电极422更密集的分布，使该阵列基板应用于液晶显示器时，在对像素电极40进行通电后，主区像素电极41处的电场强度比次区像素电极42处的电场强度大，从而使与主区像素电极41对应的液晶分子比与次区像素电极42对应的液晶分子的偏转角度大，主区像素电极41对应区域的透过率较次区像素电极42对应的区域高，从而改善液晶显示器的色偏。
进一步地，本发明还可以通过调整主区像素电极41与次区像素电极42的面积比、主区分支电极412与所述主区躯干电极411之间的夹角、次区分支电极422与所述次区躯干电极421之间的夹角，进一步的增加主区像素电极41与次区像素电极42的差异性，从而进一步提升液晶显示器的色偏改善效果。
具体地，所述主区分支电极412与所述主区躯干电极411之间的夹角可以为40°到45°，优选地，所述主区分支电极412与所述主区躯干电极411之间的夹角为45°。
具体地，所述次区分支电极422与所述次区躯干电极421之间的夹角可以为45°。
具体地，所述主区分支电极412的宽度(也即主区像素电极41的线宽)大于2μm且小于5μm，所述主区狭缝413(也即主区像素电极41的线距)的宽度大于2μm且小于5μm，优选地，所述主区分支电极412的宽度为3.5μm，所述主区狭缝413的宽度为2.5μm。
具体地，所述次区分支电极422(也即次区像素电极42的线宽)的宽度大于3.5μm且小于6μm，所述次区狭缝423的宽度(也即次区像素电极42的线距)大于3.5μm且小于6μm，优选地，所述次区分支电极422的宽度为5μm，所述次区狭缝423的宽度为5μm。
可选地，所述主区像素电极41和次区像素电极42的面积比大于1/4且小于4，优选地，所述主区像素电极41与次区像素电极42的面积比为2：3。
进一步地，请参阅图3，所述阵列基板还包括：阵列基板公共电压走线60，每一个子像素10还包括一存储电容C，所述存储电容C包括：相对设置的第一电极板51和第二电极板52，所述第一电极板51与所述阵列基板公共电压走线60电性连接，所述第二电极板52与所述控制薄膜晶体管T1的漏极电性连接。
所述控制薄膜晶体管T1的栅极、扫描线20、阵列基板公共电压走线60、以及第一电极板51位于第一金属层，所述控制薄膜晶体管T1的源极 和漏极、数据线30、以及第二电极板52均位于与所述第一金属层绝缘层叠的第二金属层。
所述像素电极40还包括与所述主区像素电极41电性连接的第二连接电极44，所述第二连接电极44层叠于所述控制薄膜晶体管T1的漏极上，所述第二连接电极44与所述控制薄膜晶体管T1的漏极之间设有绝缘层，所述绝缘层中设有贯穿所述绝缘层的像素电极连接过孔6，所述第二连接电极44经由像素电极连接过孔6与所述控制薄膜晶体管T1的漏极电性连接。
优选地，所述第一金属层和第二金属层的材料为铝、钼及铜等金属中的一种或多种的组合，所述第一金属层与第二金属层之间、第二金属层与像素电极之间的绝缘材料为氧化硅(SiOx)和氮化硅(SiNx)中的一种或二者的组合。所述像素电极40的材料为ITO。
优选地，所述第一连接电极43电性连接所述主区躯干电极411和次区躯干电极421，其延伸方向对应所述主区像素电极41与次区像素电极42的排列方向。
需要说明的是，本发明的阵列基板中，每一个子像素仅设有一个控制薄膜晶体管T1，相比现有技术，减少了薄膜晶体管的数量，提升了像素的开口率，同时本发明通过对主区像素电极41与次区像素电极42的线宽、线距、面积比、以及分支电极的倾斜角度的设计，使得主区像素电极41与次区像素电极42产生差异，尤其是使得该阵列基板在应用于液晶显示器时，与主区像素电极41对应区域的透过率大于与次区像素电极42对应的区域，能够改善液晶显示器的色偏，进一步地，本发明的第一连接电极43电性连接主区像素电极41与次区像素电极42，使得主区像素电极41与次区像素电极42可通过一个薄膜晶体管控制的同时，所述主区像素电极41与次区像素电极42具有相同的电压，能够降低主区与次区的最佳公共电压平衡调控的难度。
综上所述，本发明提供一种阵列基板，所述阵列基板包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：一控制薄膜晶体管和一像素电极，所述像素电极包括间隔排列的主区像素电极和次区像素电极、以及电性连接所述主区像素电极和次区像素电极的第一连接电极，所述主区像素电极和次区像素电极的均为米字型的狭缝电极，所述主区像素电极的主区分支电极的宽度小于次区像素电极的次区分支电极的宽度，主像素电极的主区狭缝的宽度小于次区像素电极的次区狭缝的宽度，能够通过主区像素电极和次 区像素电极的结构差异来改善色偏，同时减少每一个子像素中的TFT数量，提升了像素的开口率，通过主区像素电极和次区像素电极电性连接使得主区像素电极和次区像素电极上的电压相同，降低主区与次区的最佳公共电压平衡调控的难度。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (18)

  1. 一种阵列基板，包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；
    每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：一控制薄膜晶体管和一像素电极；所述控制薄膜晶体管的栅极电性连接该行子像素对应的扫描线，源极电性连接该行子像素对应的数据线，漏极电性连接像素电极；所述像素电极包括：间隔排列的主区像素电极和次区像素电极、以及电性连接所述主区像素电极和次区像素电极的第一连接电极；
    所述主区像素电极包括：十字形的主区躯干电极，所述主区躯干电极将所述主区像素电极分隔为四个主区配向区，在每一个主区配向区均设有与所述主区躯干电极相连的多个相互平行的条状的主区分支电极，相邻的两主区分支电极之间形成有主区狭缝，相邻的两个主区配向区内的主区分支电极关于所述主区躯干电极对称；所述次区像素电极包括：十字形的次区躯干电极，所述十字形的次区躯干电极将所述次区像素电极分隔为四个次区配向区，在每一个次区配向区均设有与所述次区躯干电极相连的多个相互平行的条状的次区分支电极，相邻的两次区分支电极之间形成有次区狭缝，相邻的两个次区配向区内的次区分支电极关于所述次区躯干电极对称；
    所述主区分支电极的宽度小于次区分支电极的宽度，所述主区狭缝的宽度小于次区狭缝的宽度。
  2. 如权利要求1所述的阵列基板，其中，所述主区分支电极与所述主区躯干电极之间的夹角为40°到45°。
  3. 如权利要求1所述的阵列基板，其中，所述次区分支电极与所述次区躯干电极之间的夹角为45°。
  4. 如权利要求1所述的阵列基板，其中，所述主区分支电极的宽度大于2μm且小于5μm，所述主区狭缝的宽度大于2μm且小于5μm。
  5. 如权利要求1所述的阵列基板，其中，所述次区分支电极的宽度大于3.5μm且小于6μm，所述次区狭缝的宽度大于3.5μm且小于6μm。
  6. 如权利要求1所述的阵列基板，其中，所述主区像素电极和次区像素电极的面积比大于1/4且小于4。
  7. 如权利要求1所述的阵列基板，其中，所述像素电极的材料为ITO。
  8. 如权利要求1所述的阵列基板，还包括：阵列基板公共电压走线，每一个子像素还包括一存储电容，所述存储电容包括：相对设置的第一电极板和第二电极板，所述第一电极板与所述阵列基板公共电压走线电性连接，所述第二电极板与所述控制薄膜晶体管的漏极电性连接。
  9. 如权利要求8所述的阵列基板，其中，所述控制薄膜晶体管的栅极、扫描线、阵列基板公共电压走线、以及第一电极板位于第一金属层，所述控制薄膜晶体管的源极和漏极、数据线、以及第二电极板均位于与所述第一金属层绝缘层叠的第二金属层。
  10. 如权利要求9所述的阵列基板，其中，所述像素电极还包括与所述主区像素电极电性连接的第二连接电极，所述第二连接电极层叠于所述控制薄膜晶体管的漏极上，所述第二连接电极与所述控制薄膜晶体管的漏极之间设有绝缘层，所述绝缘层中设有贯穿所述绝缘层的像素电极连接过孔，所述第二连接电极经由像素电极连接过孔与所述控制薄膜晶体管的漏极电性连接。
  11. 一种阵列基板，包括：阵列排布的多个子像素、多条平行间隔排列的水平的扫描线、以及多条平行间隔排列的竖直的数据线；
    每一行子像素对应一条扫描线，每一列子像素对应一条数据线，每一个子像素均包括：一控制薄膜晶体管和一像素电极；所述控制薄膜晶体管的栅极电性连接该行子像素对应的扫描线，源极电性连接该行子像素对应的数据线，漏极电性连接像素电极；所述像素电极包括：间隔排列的主区像素电极和次区像素电极、以及电性连接所述主区像素电极和次区像素电极的第一连接电极；
    所述主区像素电极包括：十字形的主区躯干电极，所述主区躯干电极将所述主区像素电极分隔为四个主区配向区，在每一个主区配向区均设有与所述主区躯干电极相连的多个相互平行的条状的主区分支电极，相邻的两主区分支电极之间形成有主区狭缝，相邻的两个主区配向区内的主区分支电极关于所述主区躯干电极对称；所述次区像素电极包括：十字形的次区躯干电极，所述十字形的次区躯干电极将所述次区像素电极分隔为四个次区配向区，在每一个次区配向区均设有与所述次区躯干电极相连的多个相互平行的条状的次区分支电极，相邻的两次区分支电极之间形成有次区狭缝，相邻的两个次区配向区内的次区分支电极关于所述次区躯干电极对称；
    所述主区分支电极的宽度小于次区分支电极的宽度，所述主区狭缝的宽度小于次区狭缝的宽度；
    其中，所述主区分支电极的宽度大于2μm且小于5μm，所述主区狭缝的宽度大于2μm且小于5μm；
    其中，所述次区分支电极的宽度大于3.5μm且小于6μm，所述次区狭缝的宽度大于3.5μm且小于6μm。
  12. 如权利要求11所述的阵列基板，其中，所述主区分支电极与所述主区躯干电极之间的夹角为40°到45°。
  13. 如权利要求11所述的阵列基板，其中，所述次区分支电极与所述次区躯干电极之间的夹角为45°。
  14. 如权利要求11所述的阵列基板，其中，所述主区像素电极和次区像素电极的面积比大于1/4且小于4。
  15. 如权利要求11所述的阵列基板，其中，所述像素电极的材料为ITO。
  16. 如权利要求11所述的阵列基板，还包括：阵列基板公共电压走线，每一个子像素还包括一存储电容，所述存储电容包括：相对设置的第一电极板和第二电极板，所述第一电极板与所述阵列基板公共电压走线电性连接，所述第二电极板与所述控制薄膜晶体管的漏极电性连接。
  17. 如权利要求16所述的阵列基板，其中，所述控制薄膜晶体管的栅极、扫描线、阵列基板公共电压走线、以及第一电极板位于第一金属层，所述控制薄膜晶体管的源极和漏极、数据线、以及第二电极板均位于与所述第一金属层绝缘层叠的第二金属层。
  18. 如权利要求17所述的阵列基板，其中，所述像素电极还包括与所述主区像素电极电性连接的第二连接电极，所述第二连接电极层叠于所述控制薄膜晶体管的漏极上，所述第二连接电极与所述控制薄膜晶体管的漏极之间设有绝缘层，所述绝缘层中设有贯穿所述绝缘层的像素电极连接过孔，所述第二连接电极经由像素电极连接过孔与所述控制薄膜晶体管的漏极电性连接。
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