WO2021174675A1 - Goa电路、tft基板、显示装置及电子设备 - Google Patents

Goa电路、tft基板、显示装置及电子设备 Download PDF

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Publication number
WO2021174675A1
WO2021174675A1 PCT/CN2020/090122 CN2020090122W WO2021174675A1 WO 2021174675 A1 WO2021174675 A1 WO 2021174675A1 CN 2020090122 W CN2020090122 W CN 2020090122W WO 2021174675 A1 WO2021174675 A1 WO 2021174675A1
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Prior art keywords
pull
thin film
unit
film transistor
control unit
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PCT/CN2020/090122
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English (en)
French (fr)
Inventor
薛炎
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/252,331 priority Critical patent/US11587521B2/en
Publication of WO2021174675A1 publication Critical patent/WO2021174675A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the invention relates to the field of display, in particular to a GOA circuit, a TFT substrate, a display device and electronic equipment.
  • organic light-emitting diodes Organic Light Emitting Diode, abbreviated as OLED
  • OLED Organic Light Emitting Diode
  • the active liquid crystal display is an active-matrix organic light-emitting diode panel (Active-matrix organic light-emitting diode).
  • AMOLED active-matrix organic light-emitting diode
  • each pixel has a thin film transistor (Thin The Film Transistor, referred to as TFT for short, has its gate (Gate) connected to the horizontal scan line, drain (Drain) connected to the vertical data line, and source (Source) connected to the pixel electrode. Applying enough voltage on the horizontal scan line will turn on all the TFTs on this line. At this time, the pixel electrode on the horizontal scan line will be connected to the vertical data line to write the display signal voltage on the data line. Into the pixel, control the transmittance of different liquid crystals to achieve the effect of color control.
  • the horizontal scanning line of the active liquid crystal display panel is mainly driven by an external integrated circuit (Integrated Circuit, abbreviated as IC) to complete the driving of the horizontal scan line, the external IC can control the charging and discharging of each level of the horizontal scan line step by step.
  • IC Integrated Circuit
  • the gate line is connected to the IC, and the frame line is very dense and takes up a lot of space.
  • the current array gate drive gate Driver on array, referred to as GOA
  • GOA gate Driver on array
  • GOA devices replace dense gate lines, reduce the binding process of external ICs, simplify the production process, reduce costs, and narrow the frame of the liquid crystal display device, thereby making the volume and weight of the liquid crystal display lighter and thinner, which is more suitable for manufacturing narrow Display products with or without borders.
  • Indium gallium zinc oxide (Indium Gallium Zinc Oxide, referred to as iIGZO) has high mobility and good device stability, and is currently widely used in IGZO-GOA circuits.
  • the pixel circuit of the AMOLED panel uses thin film transistors to form a current source to light the panel. Please refer to Figure 3.
  • the drain of the GOA driving TFT (T2) is connected to the CK clock signal.
  • TFT (T2) is electrically stressed by Vgs and Vds ,
  • the threshold voltage of TFT (T2) is easy to be forward biased, which causes the output capability of GOA to decrease.
  • the embodiments of the present invention provide a GOA circuit, a TFT substrate, a display device, and an electronic device to solve the problem that the TFT in the GOA circuit in the prior art is subjected to the electrical stress of Vgs and Vds, which causes the threshold voltage of the TFT to be easily positive.
  • the deviation which in turn leads to the problem of a decline in the output capacity of GOA.
  • a GOA circuit is characterized in that the GOA circuit includes m cascaded GOA units, and the nth level GOA unit includes: a pull-up control unit, a pull-up unit, a compensation control unit, and a pull-down unit;
  • the pull-up control unit is respectively connected to the compensation control unit and the pull-up unit
  • the compensation control unit is connected to the pull-up control unit, the pull-up unit and the pull-down unit respectively, so
  • the pull-up unit is respectively connected to the pull-up control unit, the compensation control unit and the pull-down unit, and the pull-down unit is connected to the pull-up unit and the compensation control unit, respectively;
  • the pull-up control unit is connected to the row scan signal Cout(n-1), and is used to raise the potential of the Q point;
  • the pull-up unit is used to control the row scan signal Cout(n) to output a high potential
  • the compensation control unit is configured to control the threshold voltage of the thin film transistor in the pull-up unit to be stored in the capacitor in the pull-up unit;
  • the pull-down unit is used to pull down the potential of the row scan signal Cout(n) to a low potential
  • the compensation control unit includes a fourth thin film transistor, and the gate of the fourth thin film transistor is connected to the row scan signal Cout(n+1),
  • the drain of the fourth thin film transistor is connected to the source of the first thin film transistor in the pull-up control unit and the gate of the second thin film transistor in the pull-up unit, and the source of the fourth thin film transistor It is connected to the drain of the third thin film transistor in the pull-down unit, the source of the second thin film transistor in the pull-up unit, and Cout(n).
  • the pull-up control unit includes the first thin film transistor, and the drain and gate of the first thin film transistor are respectively connected to The row scan signal Cout(n-1) is connected, and the source of the first thin film transistor is connected to the drain of the fourth thin film transistor and the pull-up unit.
  • the pull-up unit includes the second thin film transistor and a first capacitor, and the drain of the second thin film transistor and the clock Signal CK is connected, the gate of the second thin film transistor is connected to the source of the first thin film transistor and the drain of the fourth thin film transistor, and the source of the first thin film transistor passes through the first capacitor It is connected to the row scan signal Cout(n), and the source of the second thin film transistor is connected to the row scan signal Cout(n) and the pull-down unit.
  • the pull-down unit includes a third thin film transistor, the drain of the third thin film transistor and the source of the second thin film transistor
  • the electrode, the row scan signal Cout(n) and the source of the fourth thin film transistor are connected, the gate of the third thin film transistor is connected to the row scan signal Cout(n+2), and the source of the third thin film transistor
  • the pole is connected to VGL.
  • the source of the first thin film transistor and the drain of the fourth thin film transistor are connected through a second capacitor.
  • the thin film transistor is an IGZO thin film transistor.
  • TFT substrate including the GOA circuit described in any one of the above-mentioned embodiments in the first aspect.
  • a display device including the TFT substrate described in the embodiment of the second aspect of the present invention.
  • the fourth aspect of the present invention also provides an electronic device, including the display device described in the above-mentioned embodiment of the third aspect of the present invention.
  • the embodiment of the present invention provides a GOA circuit, a TFT substrate, a display device, and electronic equipment.
  • the GOA circuit includes m cascaded GOA units.
  • the nth-level GOA unit includes: a pull-up control unit, a pull-up unit, and a compensation control Unit and pull-down unit; wherein the pull-up control unit is connected to the compensation control unit and the pull-up unit, respectively, and the compensation control unit is connected to the pull-up control unit, the pull-up unit and the pull-up unit, respectively.
  • the pull-down unit, the pull-up unit is respectively connected to the pull-up control unit, the compensation control unit, and the pull-down unit, and the pull-down unit is connected to the pull-up unit and the compensation control unit, respectively;
  • the pull-up control unit is connected to the row scan signal Cout(n-1) for raising the potential of point Q; the pull-up unit is used to control the row scan signal Cout(n) to output a high potential; the compensation control unit is
  • Figure 1 is a schematic diagram of an external integrated circuit driving a horizontal scan line of a liquid crystal display panel
  • FIG. 2 is a schematic diagram of the horizontal scanning lines of the liquid crystal display panel driven by GOA;
  • Figure 3 is a GOA circuit and timing diagram according to the prior art
  • Fig. 4 is a schematic diagram of a GOA unit according to an embodiment of the present invention.
  • FIG. 5 is a level transmission relationship and signal timing of GOA units according to an embodiment of the present invention.
  • Figure 6 is an equivalent circuit diagram of a thin film transistor
  • Fig. 7 is a circuit diagram of a GOA unit according to an embodiment of the present invention.
  • Fig. 8 is a schematic diagram of a signal source required by a GOA unit according to an embodiment of the present invention.
  • the terms “installed”, “connected”, “connected”, “fixed” and other terms should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. , Or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, it can be the internal connection of two components or the interaction relationship between two components, unless otherwise specified The limit.
  • installed can be a fixed connection or a detachable connection. , Or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, it can be the internal connection of two components or the interaction relationship between two components, unless otherwise specified The limit.
  • the specific meanings of the above-mentioned terms in the present invention can be understood according to specific situations.
  • the word "exemplary” is used to mean “serving as an example, illustration, or illustration.” Any embodiment described as “exemplary” in the present invention is not necessarily construed as being more preferable or advantageous than other embodiments.
  • the present invention sets out details for the purpose of explanation. It should be understood that those of ordinary skill in the art can realize that the present invention can be implemented even without using these specific details. In other examples, well-known structures and processes will not be elaborated to avoid unnecessary details to obscure the description of the present invention. Therefore, the present invention is not intended to be limited to the illustrated embodiments, but should be consistent with the widest scope that conforms to the principles and features disclosed in the present invention.
  • the forward bias stress of IGZO-TFT in the prior art is not ideal. Long-term forward bias stress will cause the threshold voltage (Vth) of the TFT to shift forward, which will slow down the opening speed of the IGZO-TFT device. , which has a serious impact on the gate drive circuit.
  • the embodiment of the present invention provides a GOA circuit embodiment.
  • the GOA circuit can be applied to LCD display or OLED display.
  • the GOA circuit can be included in, for example, LCD TVs, mobile phones, digital cameras, tablet computers, computers, and electronics. Paper, navigator and other products or parts with display function.
  • FIG. 4 is a schematic diagram of a GOA unit according to an embodiment of the present invention. Please refer to FIG. 4, a GOA circuit including m cascaded GOA units.
  • the nth-stage GOA unit includes: a pull-up control unit 101, a pull-up Unit 102, compensation control unit 104, and pull-down unit 103. Where m and n are positive integers, m ⁇ n ⁇ 1.
  • the pull-up control unit 101 is respectively connected to the compensation control unit 104 and the pull-up unit 102, the compensation control unit 104 is respectively connected to the pull-up control unit 101, the pull-up unit 102, and the pull-down unit 103, and the pull-up unit 102 is respectively connected to the pull-up control unit 101 ,
  • the compensation control unit 104 and the pull-down unit 103, the pull-down unit 103 is connected to the pull-up unit 102 and the compensation control unit 104, respectively.
  • the pull-up control unit 101 is an effective method to reduce the leakage current at the Q point.
  • the pull-up control unit 101 can reduce the leakage current of the Q point to a certain extent, and the maintenance ability of the Q point potential is the key to ensuring the stable output of the GOA circuit.
  • the pull-up control unit 101 is connected to the row scan signal Cout(n-1) for raising the potential of point Q, the pull-up unit 102 is used to control the row scan signal Cout(n) to output a high potential, and the compensation control unit 104 is used to prompt
  • the thin film transistor in the pull-up control unit 102 forms a diode connection structure, and the threshold voltage of the thin film transistor in the pull-up unit 102 is controlled to be stored in the capacitor in the pull-up unit 102.
  • the pull-down unit 103 is used to transfer the row scan signal Cout(n ) Is pulled down to a low potential.
  • the capacitor is a bootstrap capacitor.
  • the bootstrap capacitor uses the characteristic that the voltage across the capacitor cannot change suddenly. When a certain voltage is maintained at both ends of the capacitor, the negative terminal voltage of the capacitor is increased, and the positive terminal The voltage still maintains the original pressure difference from the negative terminal, which is equal to the voltage at the positive terminal being lifted by the negative terminal.
  • one end of the bootstrap capacitor is electrically connected to the end where the pull-up control unit 101 outputs the pull-up control signal Q(N), and the other end of the bootstrap capacitor is connected to the current stage output by the pull-up unit 102.
  • One end of the row scan signal G(n) of the row drive circuit unit of the array substrate is electrically connected.
  • the bootstrap capacitor is mainly used to raise the potential, to generate the high level of the scan level signal of the current stage, and to maintain the voltage between the gate and source of the thin film transistor in the pull-up unit 102 to stabilize the thin film
  • the output of the transistor is conducive to the output of the horizontal scanning signal G(n).
  • the GOA circuit includes m cascaded GOA units. Please refer to FIG. 5.
  • FIG. 5 shows the GOA unit level transmission relationship and signal timing according to an embodiment of the present invention.
  • the GOA circuit contains m multi-single-stage GOA units. Each GOA unit correspondingly drives a first-level horizontal scan line.
  • the structure of all single-stage GOA units is almost the same. There are only slight differences in the first and last stages. These differences are irrelevant to this application. , Therefore, I will not go into details here.
  • the nth-stage GOA unit When the nth-stage GOA unit is driven, the nth-stage GOA unit outputs a high-level nth-stage row scan signal G(n) and an nth-stage transfer signal ST(n).
  • the n-th level scan signal G(n) is used to turn on the TFT switch of each pixel in a row of the panel, and to charge the pixel electrode in each pixel, and the n-th level transfer signal ST(n) is used to It provides a level transmission signal for the lower during forward scanning, and is used to provide a level transmission signal for the upper during reverse scanning.
  • the GOA circuit provided in this embodiment is consistent with the working principle of the above-mentioned GOA unit embodiment.
  • the GOA circuit may include a plurality of thin film transistors.
  • Figure 6 is an equivalent circuit diagram of a thin film transistor.
  • the three electrodes of the thin film transistor are called Gate, Source and Drain respectively.
  • the voltage loaded on each electrode can be marked as Vg, Vs and Vd. .
  • the end with a lower voltage may also be referred to as the drain Drain, and the other end with a higher voltage may be referred to as the source Source, that is, when the thin film transistor is in the on state, the current Flow from Source to Drain.
  • the Q point in the GOA circuit is the gate point of the thin film transistor that controls the high level of the output signal.
  • the Q point is at the high potential, the thin film transistor is in the on state, and the output signal remains high.
  • VGL+Vth voltage will always be stored at the Q point, thereby solving the problem that the GOA circuit buffer TFT is stressed by the CK signal Vds in the prior art, and the Vth of the TFT is prone to be forward biased, resulting in serious distortion of the output signal.
  • the stability of the gate drive circuit is improved to a large extent, which is beneficial to the improvement of the display effect of the liquid crystal display panel.
  • the GOA unit can be manufactured based on IGZO-TFT.
  • FIG. 7 is a circuit diagram of a GOA unit according to an embodiment of the present invention. Please refer to FIG. ) Connection, the source of the first thin film transistor T1 is connected to the compensation control unit 104 and the pull-up unit 102, specifically, the source of the first thin film transistor T1 is connected to the drain of the fourth thin film transistor T4 in the compensation control unit 104 , The source of the first thin film transistor T1 is connected to the gate of the second thin film transistor T2 in the pull-up unit 102.
  • the pull-up unit 102 includes a second thin film transistor T2 and a first capacitor Cbt1, the drain of the second thin film transistor T2 is connected to the clock signal CK, the gate of the second thin film transistor T2 is connected to the source of the first thin film transistor T1, The source of a thin film transistor T1 is connected to the row scan signal Cout(n) through the first capacitor Cbt1, and the source of the second thin film transistor T2 is connected to the row scan signal Cout(n) and the pull-down unit 103, specifically, The source of the second thin film transistor T2 is connected to the drain of the third thin film transistor T3 in the pull-down unit 103.
  • the pull-down unit 103 includes a third thin film transistor T3.
  • the drain of the third thin film transistor T3 is respectively connected to the source of the second thin film transistor T2, the row scan signal Cout(n), and the compensation control unit 104.
  • the third thin film transistor T3 The drain of the transistor T3 is connected to the source of the fourth thin film transistor T4 in the compensation control unit 104, the gate of the third thin film transistor T3 is connected to the row scan signal Cout(n+2), and the third thin film transistor T3 The source is connected to VGL.
  • the compensation control unit 104 includes a fourth thin film transistor T4, the gate of the fourth thin film transistor T4 is connected to the row scan signal Cout(n+1), and the drain of the fourth thin film transistor T4 is connected to the source of the first thin film transistor T1. Connected, the source of the fourth thin film transistor T4 is connected to the drain of the third thin film transistor T3 and Cout(n).
  • the source of the first thin film transistor and the drain of the fourth thin film transistor are connected through a second capacitor.
  • the potential of point Q is VGL+Vth.
  • Cout(n-1) becomes a high potential. According to the principle of capacitive coupling, the high potential of VGH is written to point Q, and the potential of point Q It can be VGL+Vth+VGH.
  • FIG. 8 is a schematic diagram of a signal source required by a GOA unit according to an embodiment of the present invention. The working principle of the GOA unit according to an embodiment of the present invention will be described below with reference to FIG. 8.
  • Q point potential is VGL+Vth
  • Cout(n-1) rises to high potential
  • M point potential rises from VGL to VGH
  • Q point is theoretically coupled to (VGH-VGL) ⁇ Cbt2/(Cbt1+ Cbt2) +VGL+Vth
  • the second thin film transistor T2 is turned on, and Cout(n) remains low
  • the transistor used in the embodiment of the present invention may be a thin film transistor or a field effect transistor or other devices with the same characteristics.
  • the thin film transistor is an IGZO thin film transistor.
  • the transistors used in the embodiments of the present invention are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable, and the source is preferably connected to a power source. The middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • Switching transistors include P-type switching transistors and N-type switching transistors.
  • all the thin film transistors described in the GOA unit are metal oxide semiconductor thin film transistors, polysilicon thin film transistors or amorphous silicon thin film transistors. They are all N-type thin film transistors.
  • Another embodiment of the present invention also provides a TFT substrate, including the GOA circuit in the foregoing embodiment.
  • Another embodiment of the present invention also provides a display device including the TFT substrate in the above-mentioned embodiment.
  • the electronic device may be a product with a display function, such as an LCD TV, a mobile phone, a digital camera, a tablet computer, a computer, an electronic paper, and a navigator.
  • a display function such as an LCD TV, a mobile phone, a digital camera, a tablet computer, a computer, an electronic paper, and a navigator.
  • the GOA circuit with the structure of the present invention solves the problem that the buffer TFT of the GOA circuit in the prior art is affected by the stress of the CK signal Vds, and the Vth of the TFT is prone to be forward biased, resulting in serious distortion of the output signal.
  • the stability of the gate driving circuit is improved, which is beneficial to the improvement of the display effect of the liquid crystal display panel.
  • the voltage of the GOA circuit VGL+Vth in the embodiment of the present invention will always be stored at the Q point, thereby solving the problem of the stress effect of the CK signal Vds on the GOA circuit buffer TFT in the prior art, and the Vth of the TFT is prone to be forward biased, resulting in an output signal
  • the problem of severe distortion greatly improves the stability of the gate drive circuit, which is beneficial to the improvement of the display effect of the liquid crystal display panel.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract

一种GOA电路、TFT基板、显示装置及电子设备，GOA电路包括m个级联的GOA单元，第n级GOA单元包括：上拉控制单元（101）、上拉单元（102）、补偿控制单元（104）和下拉单元（103）；上拉控制单元（101）分别连接至补偿控制单元（104）和上拉单元（102），补偿控制单元（104）分别连接至上拉控制单元（101）、上拉单元（102）和下拉单元（103），上拉单元（102）分别连接至上拉控制单元（101）、补偿控制单元（104）和下拉单元（103），下拉单元（103）分别连接至上拉单元（102）和补偿控制单元（104）；上拉控制单元（101）与行扫描信号Cout(n-1)连接，用于抬升Q点的电位；上拉单元（102）用于控制行扫描信号Cout(n)输出高电位；补偿控制单元（104）用于控制上拉单元（102）中的薄膜晶体管（T2）的阈值电压存储于上拉单元（102）中的电容（Cbt1）中；下拉单元（103）用于将行扫描信号Cout(n)的电位拉低至低电位，保证了信号的正确输出。

Description

GOA电路、TFT基板、显示装置及电子设备 技术领域
本发明涉及显示领域，具体涉及一种GOA电路、TFT基板、显示装置及电子设备。
 背景技术
当前世界已进入“信息革命”时代，显示技术及显示器件在信息技术的发展过程中占据了十分重要的地位，电视、电脑、移动电话、个人移动数字终端(Personal Digital Assistant，简称为PDA)等可携式设备以及各类仪器仪表上的显示屏为人们的日常生活和工作提供着大量的信息。没有显示器，就不会有当今迅猛发展的信息技术。
随着电子设备不断向高集成度、低功耗、便携等方向发展，人们对显示器的要求也越来越高，这主要体现在以下几个方面：高分辨率、窄边框、柔性显示等。显示器分辨率已经从传统的720p或者1080p，发展到现在的4K甚至8K。
作为新一代显示器件, 有机发光二极管(Organic Light Emitting Diode, 简称为OLED)显示器有着结构简单、超薄、自发光、高亮度、响应时间快、大视角、高效率、低工作电压、低成本等优点,得到了广泛的应用。
在主动式液晶显示器是有源矩阵有机发光二极体面板（Active-matrix organic light-emitting diode，简称为AMOLED）中，每个像素具有一个薄膜晶体管（Thin Film Transistor，简称为TFT），其栅极（Gate）连接至水平扫描线，漏极（Drain）连接至垂直方向的数据线，源极（Source）则连接至像素电极。在水平扫描线上施加足够的电压，会使该条线上所有的TFT打开，此时该水平扫描线上的像素电极会与垂直方向的数据线连接，从而将数据线上的显示信号电压写入像素，控制不同液晶的透光度进而达到控制色彩的效果。
请参阅图1，目前主动式液晶显示面板水平扫描线的驱动主要由外接集成电路（Integrated Circuit，简称为IC）来完成水平扫描线的驱动，外接的IC可以控制各级水平扫描线的逐级充电和放电。然而栅极（Gate）线连接到IC，边框线路十分密集，占用空间较大。
针对由外接IC驱动水平扫描线导致的边框线路密集、占用空间大的问题，目前阵列栅极驱动(gate driver on array，简称为GOA )技术已经应用于液晶显示器上，请参阅图2，其可以运用液晶显示面板的原有制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接IC来完成水平扫描线的驱动。GOA器件代替密集的Gate线，减少了外接IC的绑定工序，简化了制作程序、降低了成本，窄化了液晶显示装置的边框，进而使得液晶显示器的体积及重量轻薄化，更适合制作窄边框或无边框的显示产品。
铟镓锌氧化物(Indium Gallium Zinc Oxide，简称为 iIGZO)具有高的迁移率，和良好的器件稳定性，目前广泛的应用于IGZO-GOA电路中。AMOLED面板的像素电路是利用薄膜晶体管组成电流源来点亮面板的，请参阅图3，GOA的驱动TFT（T2）的漏极连接CK时钟信号，当TFT（T2）受到Vgs及Vds电学stress时，TFT（T2）的阈值电压容易正偏，导致GOA的输出能力下降。
因此，如何避免GOA电路中TFT受到Vgs及Vds电学stress作用，导致TFT的阈值电压容易发生正偏，进而导致GOA的输出能力下降的问题成为了本领域技术人员亟待解决的技术问题和始终研究的重点。
 技术问题
针对如何避免GOA电路中TFT受到Vgs及Vds电学stress作用，导致TFT的阈值电压容易发生正偏，进而导致GOA的输出能力下降的问题，现有技术中还没有有效的解决方案。
 技术解决方案
有鉴于此，本发明实施例提供了一种GOA电路、TFT基板、显示装置及电子设备，以解决现有技术中GOA电路中TFT受到Vgs及Vds电学stress作用，导致TFT的阈值电压容易发生正偏，进而导致GOA的输出能力下降的问题。
为此，本发明实施例提供了如下技术方案：
本发明第一方面，一种GOA电路，其特征在于，该GOA电路包括m个级联的GOA单元，第n级GOA单元包括：上拉控制单元、上拉单元、补偿控制单元和下拉单元；其中，所述上拉控制单元分别连接至所述补偿控制单元和所述上拉单元，所述补偿控制单元分别连接至所述上拉控制单元、所述上拉单元和所述下拉单元，所述上拉单元分别连接至所述上拉控制单元、所述补偿控制单元和所述下拉单元，所述下拉单元分别连接至所述上拉单元和所述补偿控制单元；
所述上拉控制单元与行扫描信号Cout(n-1)连接，用于抬升Q点的电位；
所述上拉单元用于控制行扫描信号Cout(n)输出高电位；
所述补偿控制单元用于控制所述上拉单元中的薄膜晶体管的阈值电压存储于所述上拉单元中的电容中；
所述下拉单元用于将行扫描信号Cout(n)的电位拉低至低电位；
其中m和n为正整数，m≥n≥1。
结合本发明第一方面，本发明第一方面第一实施方式中，所述补偿控制单元包括第四薄膜晶体管，所述第四薄膜晶体管的栅极与行扫描信号Cout(n+1)连接，所述第四薄膜晶体管的漏极与所述上拉控制单元中第一薄膜晶体管的源极、所述上拉单元中的第二薄膜晶体管的栅极连接，所述第四薄膜晶体管的源极与所述下拉单元中的第三薄膜晶体管的漏极、所述上拉单元中的第二薄膜晶体管的源极及Cout(n)连接。
结合本发明第一方面第一实施方式， 本发明第一方面第二实施方式中，所述上拉控制单元包括所述第一薄膜晶体管，所述第一薄膜晶体管的漏极和栅极分别与行扫描信号Cout(n-1)连接，所述第一薄膜晶体管的源极与所述第四薄膜晶体管的漏极和所述上拉单元连接。
结合本发明第一方面第二实施方式，本发明第一方面第三实施方式中，所述上拉单元包括所述第二薄膜晶体管和第一电容，所述第二薄膜晶体管的漏极与时钟信号CK连接，所述第二薄膜晶体管的栅极与所述第一薄膜晶体管的源极、所述第四薄膜晶体管的漏极连接，所述第一薄膜晶体管的源极通过所述第一电容与行扫描信号Cout(n)连接，所述第二薄膜晶体管的源极与行扫描信号Cout(n)及所述下拉单元连接。
结合本发明第一方面第三实施方式，本发明第一方面第四实施方式中，所述下拉单元包括第三薄膜晶体管，所述第三薄膜晶体管的漏极与所述第二薄膜晶体管的源极、行扫描信号Cout(n)及所述第四薄膜晶体管的源极连接，所述第三薄膜晶体管的栅极与行扫描信号Cout(n+2)连接，所述第三薄膜晶体管的源极连接至VGL。
结合本发明第一方面第四实施方式，本发明第一方面第五实施方式中，所述第一薄膜晶体管的源极和所述第四薄膜晶体管的漏极通过第二电容连接。
结合本发明第一方面，本发明第六实施方式中，所述薄膜晶体管为IGZO薄膜晶体管。
本发明第二方面，还提供了一种TFT基板，包括上述第一方面实施例中任一所述的GOA电路。
本发明第三方面，还提供了一种显示装置，包括上述本发明第二方面实施例中所述的TFT基板。
本发明第四方面，还提供了一种电子设备，包括上述本发明第三方面实施例中所述的显示装置。
本发明实施例技术方案，具有如下优点：
本发明实施例提供了一种GOA电路、TFT基板、显示装置及电子设备，该GOA电路包括m个级联的GOA单元，第n级GOA单元包括：上拉控制单元、上拉单元、补偿控制单元和下拉单元；其中，所述上拉控制单元分别连接至所述补偿控制单元和所述上拉单元，所述补偿控制单元分别连接至所述上拉控制单元、所述上拉单元和所述下拉单元，所述上拉单元分别连接至所述上拉控制单元、所述补偿控制单元和所述下拉单元，所述下拉单元分别连接至所述上拉单元和所述补偿控制单元；所述上拉控制单元与行扫描信号Cout(n-1)连接，用于抬升Q点的电位；所述上拉单元用于控制行扫描信号Cout(n)输出高电位；所述补偿控制单元用于控制所述上拉单元中的薄膜晶体管的阈值电压存储于所述上拉单元中的电容中；所述下拉单元用于将行扫描信号Cout(n)的电位拉低至低电位；其中m和n为正整数，m≥n≥1。
 有益效果
解决了现有技术中GOA电路中TFT受到Vgs及Vds电学stress作用，导致TFT的阈值电压容易发生正偏，进而导致GOA的输出能力下降的问题，保证了信号的正确输出。
 附图说明
为了更清楚地说明本发明具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是由外接集成电路驱动液晶显示面板水平扫描线的示意图；
图2是由GOA驱动液晶显示面板水平扫描线的示意图；
图3是根据现有技术的GOA电路及时序图；
图4是根据本发明实施例的GOA单元示意图；
图5是根据本发明实施例的GOA单元级传关系以及信号时序；
图6是薄膜晶体管的等效电路图；
图7是根据本发明实施例的GOA单元电路图；
图8是根据本发明实施例的GOA单元所需信号源示意图。
 本发明的实施方式
下面结合说明书附图对本发明提供的一种GOA电路、TFT基板、显示装置及电子设备的技术方案进行清楚、完整地描述，显然地，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，所以不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”等仅用于描述目的，而不能将其理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、“第三”的特征可以明示或隐含地包括一个或者更多个特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本发明中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，“示例性”一词用来表示“用作例子、例证或说明”。本发明中被描述为“示例性”的任何实施例不一定被解释为比其它实施例更优选或更具优势。为了使本领域任何技术人员能够实现和使用本发明，给出了以下描述。在以下描述中，本发明为了解释的目的而列出了细节。应当明白的是，本领域普通技术人员可以认识到，即使在不使用这些特定细节的情况下也可以实现本发明。在其它的实例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本发明的描述变得晦涩。因此，本发明并非旨在限于所示的实施例，而是应与符合本发明所公开的原理和特征的最广范围相一致。
针对现有技术中IGZO-TFT的正向偏压应力并不理想，长时间的正向偏压应力会导致TFT的阈值电压(Vth)正向漂移，从而使得IGZO-TFT器件的打开速度变慢，进而对栅极驱动电路产生严重影响的问题。本发明实施例，提供了一种GOA电路实施例，GOA电路可运用于LCD显示，也可运用于OLED显示，该GOA电路可包含在例如液晶电视、手机、数字相机、平板电脑、计算机、电子纸、导航仪等具有显示功能的产品或部件中。
需要说明的是，下面所描述的本发明不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
AMOLED面板的像素电路是利用薄膜晶体管组成电流源来点亮面板的，而IGZO-薄膜晶体管受到stress作用时Vth容易发生偏移，因而像素电路需要使用补偿电路进行Vth补偿。图4是根据本发明实施例的GOA单元示意图，请参阅图4，一种GOA电路，该GOA电路包括m个级联的GOA单元，第n级GOA单元包括：上拉控制单元101、上拉单元102、补偿控制单元104和下拉单元103。其中m和n为正整数，m≥n≥1。
上拉控制单元101分别连接至补偿控制单元104和上拉单元102，补偿控制单元104分别连接至上拉控制单元101、上拉单元102和下拉单元103，上拉单元102分别连接至上拉控制单元101、补偿控制单元104和下拉单元103，下拉单元103分别连接至上拉单元102和补偿控制单元104。上拉控制单元101是一种能够减少Q点漏电流的有效方法。上拉控制单元101能够在一定程度上减少Q点的漏电流，Q点电位的维持能力是保证GOA电路稳定输出的关键所在。
上拉控制单元101与行扫描信号Cout(n-1)连接，用于抬升Q点的电位，上拉单元102用于控制行扫描信号Cout(n)输出高电位，补偿控制单元104用于促使上拉控制单元102中的薄膜晶体管形成二极管连接结构，控制上拉单元102中的薄膜晶体管的阈值电压存储于该上拉单元102中的电容中，下拉单元103用于将行扫描信号Cout(n)的电位拉低至低电位。
在一个具体的可选实施例中，该电容为自举电容，自举电容是利用了电容两端电压不能突变的特性，当电容两端保持有一定电压时，提高电容负端电压，正端电压仍保持与负端的原始压差，等于正端的电压被负端举起来了。在该可选实施例中，自举电容的一端与上拉控制单元101输出上拉控制信号Q(N)的一端电性连接连接，自举电容的另一端与上拉单元102输出的当前级阵列基板行驱动电路单元的行扫描信号G(n)的一端电性连接。自举电容主要用于负责电位抬升，用于生成所述本级的扫描电平信号的高电平，维持上拉单元102中薄膜晶体管的栅极与源极之间的电压，以稳定该薄膜晶体管的输出，即利于行扫描信号G(n)的输出。
GOA电路包括m个级联的GOA单元，请参阅图5，图5是根据本发明实施例的GOA单元级传关系以及信号时序。GOA电路中包含m个多单级GOA单元，每一级GOA单元对应驱动一级水平扫描线，所有单级GOA单元的结构几乎完全相同，仅在首尾级存在细微差异，这些差异与本申请无关，因此，在此不再详述。在第n级GOA单元驱动时，第n级GOA单元输出高电平的第n级行扫描信号G(n)和第n级级传信号ST(n)。其中，第n级行扫描信号G(n)用于打开面板中一行中每个像素的TFT开关，并对每个像素中的像素电极进行充电，第n级级传信号ST(n)用于在正向扫描时为下提供级传信号，并用于在反向扫描时为上提供级传信号。
本实施例提供的GOA电路，与上述GOA单元的实施例工作原理一致，具体结构关系及工作原理参见上述GOA单元实施例，此处不再赘述。
根据本发明的示例实施例的GOA电路可包括多个薄膜晶体管。图6是薄膜晶体管的等效电路图，薄膜晶体管的三个电极分别称为栅极Gate、源极Source和漏极Drain，相应地，加载在各个电极上的电压可以分别标记为Vg、Vs和Vd。在这里，源极Source和漏极Drain实际上是没有区别的，但是为了方便说明，在示例性实施例中通常将电压较低的一端称为源极，将电压较高的另一端称为漏极。因此，决定薄膜晶体管的导通状态的电压Vgs＝Vg-Vs，当Vgs>0时，薄膜晶体管为导通状态，电流从漏极Drain流向源极Source；当Vgs＝0，薄膜晶体管为微导通状态，电流从漏极Drain流向源极Source；当Vgs<0时器件处于截止状态。可选择地，在其他示例性实施例中，也可以将电压较低的一端称为漏极Drain，将电压较高的另一端称为源极Source，即，当薄膜晶体管处于导通状态，电流从源极Source流向漏极Drain。
GOA电路中Q点是控制输出信号高电平的薄膜晶体管栅极点，当Q点处于高电位时，薄膜晶体管处于开启状态，输出信号保持高电位。通过上述GOA电路VGL+Vth的电压会一直存储于Q点，从而解决了现有技术中GOA电路buffer TFT受CK信号Vds的stress作用，TFT的Vth容易发生正偏，导致输出信号严重失真的问题，在很大程度上提高了栅极驱动电路的稳定性，有利于液晶显示面板显示效果的提高。
在一个可选实施例中，GOA单元可以基于IGZO-TFT制造。
图7是根据本发明实施例的GOA单元电路图，请参阅图7，上拉控制单元101包括第一薄膜晶体管T1，第一薄膜晶体管T1的漏极和栅极与行扫描信号Cout(n-1)连接，第一薄膜晶体管T1的源极与补偿控制单元104和上拉单元102连接，具体地，第一薄膜晶体管T1的源极与补偿控制单元104中的第四薄膜晶体管T4的漏极连接，第一薄膜晶体管T1的源极与上拉单元102中的第二薄膜晶体管T2的栅极连接。
上拉单元102包括第二薄膜晶体管T2和第一电容Cbt1，第二薄膜晶体管T2的漏极与时钟信号CK连接，第二薄膜晶体管T2的栅极与第一薄膜晶体管T1的源极连接，第一薄膜晶体管T1的源极通过该第一电容Cbt1与行扫描信号Cout(n)连接，该第二薄膜晶体管T2的源极分别与行扫描信号Cout(n)及下拉单元103连接，具体地，第二薄膜晶体管T2的源极与下拉单元103中的第三薄膜晶体管T3的漏极连接。
下拉单元103包括第三薄膜晶体管T3，该第三薄膜晶体管T3的漏极分别与第二薄膜晶体管T2的源极、行扫描信号Cout(n)及补偿控制单元104连接，具体地，第三薄膜晶体管T3的漏极与补偿控制单元104中的第四薄膜晶体管T4的源极连接，该第三薄膜晶体管T3的栅极与行扫描信号Cout(n+2)连接，该第三薄膜晶体管T3的源极连接至VGL。
补偿控制单元104包括第四薄膜晶体管T4，该第四薄膜晶体管T4的栅极与行扫描信号Cout(n+1)连接，第四薄膜晶体管T4的漏极与该第一薄膜晶体管T1的源极连接，第四薄膜晶体管T4的源极与第三薄膜晶体管T3的漏极及Cout(n)连接。
在一个可选实施例中，该第一薄膜晶体管的源极和该第四薄膜晶体管的漏极通过第二电容连接。请参阅图8 ，S1阶段，Q点的电位是VGL+Vth，在S2阶段，Cout(n-1)变为高电位，根据电容耦合原理，把VGH高电位写入Q点，Q点的电位可为VGL+Vth+VGH。
图8是根据本发明实施例的GOA单元所需信号源示意图，下面结合图8对本发明实施例的GOA单元工作原理进行说明。
S1阶段：Q点电位为VGL+Vth，随后Cout(n-1)升为高电位，M点电位由VGL升为VGH，Q点理论上被耦合至（VGH-VGL）×Cbt2/（Cbt1+Cbt2）+VGL+Vth，第二薄膜晶体管T2打开，Cout(n)保持低电位；
S2阶段：Cout(n-1)降为低电位，第一薄膜晶体管T1关闭，第二薄膜晶体管T2维持打开，Cout（n）电位由VGL升为VGH，Q点电位理论上为(VGH-VGL) ×Cbt1/（Cbt1+Cbt2）+（VGH-VGL）×Cbt2/（Cbt1+Cbt2）+VGL+Vth=VGH+Vth，第二薄膜晶体管T2的电位为Vgs-Vth=VGH，因此第二薄膜晶体管T2电流的大小与Vth无关，GOA的输出波形不受第二薄膜晶体管T2的Vth偏移的影响；
S3阶段：Cout(n+1)升为高电位，第四薄膜晶体管T4打开，时钟信号CK由高电位降为低电位，第二薄膜晶体管T2的栅极以及漏极互相连接，形成二极管结构，第二薄膜晶体管T2会产生电流放电，栅极和漏极的电压会同时降低，降至VGL+Vth时，栅极电压（VGL+Vth）减去源极电压（VGL）刚好等于Vth，因此第二薄膜晶体管T2会截止关闭，栅极电压不会继续降低，由于存储电容Cbt1的存在，VGL+Vth的电压会一直存储于Q点。
S4阶段：Cout (n+2)升为高电位，第三薄膜晶体管T3打开，Cout(n)电位被复位至VGL。
在一个可选实施例中，本发明实施例中采用的晶体管可以是薄膜晶体管或场效应管或其他特性相同的器件，例如该薄膜晶体管为IGZO薄膜晶体管。根据在电路中的作用本发明实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的，优选源极连接电源。晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。开关晶体管包括P型开关晶体管和N型开关晶体管两种，在本发明实施例中，GOA单元中所述的所有薄膜晶体管均为金属氧化物半导体薄膜晶体管、多晶硅薄膜晶体管或非晶硅薄膜晶体管，且均为N型薄膜晶体管。
本发明另一个实施例，还提供了一种TFT基板，包括上述实施例中该的GOA电路。
本发明另一个实施例，还提供了一种显示装置，包括上述实施例中该的TFT基板。
本发明另一个实施例，还提供了一种电子设备，包括上述实施例中该的显示装置。例如该电子设备可以是液晶电视、手机、数字相机、平板电脑、计算机、电子纸、导航仪等具有显示功能的产品。
综上所述，通过本发明结构的GOA电路，解决了现有技术中GOA电路buffer TFT受CK信号Vds的stress作用，TFT的Vth容易发生正偏，导致输出信号严重失真的问题，在很大程度上提高了栅极驱动电路的稳定性，有利于液晶显示面板显示效果的提高。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能(例如其在功能上是等价的)的任意组件(除非另外指示)，即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。
 工业实用性
通过本发明实施例的GOA电路VGL+Vth的电压会一直存储于Q点，从而解决了现有技术中GOA电路buffer TFT受CK信号Vds的stress作用，TFT的Vth容易发生正偏，导致输出信号严重失真的问题，在很大程度上提高了栅极驱动电路的稳定性，有利于液晶显示面板显示效果的提高。

Claims (10)

  1. 一种GOA电路，其中，该GOA电路包括m个级联的GOA单元，第n级GOA单元包括：上拉控制单元、上拉单元、补偿控制单元和下拉单元；其中，所述上拉控制单元分别连接至所述补偿控制单元和所述上拉单元，所述补偿控制单元分别连接至所述上拉控制单元、所述上拉单元和所述下拉单元，所述上拉单元分别连接至所述上拉控制单元、所述补偿控制单元和所述下拉单元，所述下拉单元分别连接至所述上拉单元和所述补偿控制单元；
    所述上拉控制单元与行扫描信号Cout(n-1)连接，用于抬升Q点的电位；
    所述上拉单元用于控制行扫描信号Cout(n)输出高电位；
    所述补偿控制单元用于控制所述上拉单元中的薄膜晶体管的阈值电压存储于所述上拉单元中的电容中；
    所述下拉单元用于将行扫描信号Cout(n)的电位拉低至低电位；
    其中m和n为正整数，m≥n≥1。
  2. 根据权利要求1所述的GOA电路，所述补偿控制单元包括第四薄膜晶体管，所述第四薄膜晶体管的栅极与行扫描信号Cout(n+1)连接，所述第四薄膜晶体管的漏极与所述上拉控制单元中第一薄膜晶体管的源极、所述上拉单元中的第二薄膜晶体管的栅极连接，所述第四薄膜晶体管的源极与所述下拉单元中的第三薄膜晶体管的漏极、所述上拉单元中的第二薄膜晶体管的源极及Cout(n)连接。
  3. 根据权利要求2所述的GOA电路，所述上拉控制单元包括所述第一薄膜晶体管，所述第一薄膜晶体管的漏极和栅极分别与行扫描信号Cout(n-1)连接，所述第一薄膜晶体管的源极与所述第四薄膜晶体管的漏极和所述上拉单元连接。
  4. 根据权利要求3所述的GOA电路，所述上拉单元包括所述第二薄膜晶体管和第一电容，所述第二薄膜晶体管的漏极与时钟信号CK连接，所述第二薄膜晶体管的栅极与所述第一薄膜晶体管的源极、所述第四薄膜晶体管的漏极连接，所述第一薄膜晶体管的源极通过所述第一电容与行扫描信号Cout(n)连接，所述第二薄膜晶体管的源极与行扫描信号Cout(n)及所述下拉单元连接。
  5. 根据权利要求4所述的GOA电路，所述下拉单元包括第三薄膜晶体管，所述第三薄膜晶体管的漏极与所述第二薄膜晶体管的源极、行扫描信号Cout(n)及所述第四薄膜晶体管的源极连接，所述第三薄膜晶体管的栅极与行扫描信号Cout(n+2)连接，所述第三薄膜晶体管的源极连接至VGL。
  6. 根据权利要求5所述的GOA电路，所述第一薄膜晶体管的源极和所述第四薄膜晶体管的漏极通过第二电容连接。
  7. 根据权利要求1-6中任一所述的GOA电路，所述薄膜晶体管为IGZO薄膜晶体管。
  8. 一种TFT基板，其中，包括权利要求1-6中任一所述的GOA电路。
  9. 一种显示装置，其中，包括权利要求8所述的TFT基板。
  10. 一种电子设备，其中，包括权利要求9所述的显示装置。
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