WO2021016956A1 - 电致发光显示面板及显示装置 - Google Patents

电致发光显示面板及显示装置 Download PDF

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Publication number
WO2021016956A1
WO2021016956A1 PCT/CN2019/098731 CN2019098731W WO2021016956A1 WO 2021016956 A1 WO2021016956 A1 WO 2021016956A1 CN 2019098731 W CN2019098731 W CN 2019098731W WO 2021016956 A1 WO2021016956 A1 WO 2021016956A1
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WIPO (PCT)
Prior art keywords
pixel
color sub
substrate
orthographic projection
sub
Prior art date
Application number
PCT/CN2019/098731
Other languages
English (en)
French (fr)
Inventor
黄耀
黄炜赟
龙跃
曾超
李孟
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to RU2019141642A priority Critical patent/RU2721754C1/ru
Priority to PCT/CN2019/098731 priority patent/WO2021016956A1/zh
Priority to MX2019015386A priority patent/MX2019015386A/es
Priority to JP2019569405A priority patent/JP2022550491A/ja
Priority to EP19938108.8A priority patent/EP4006985A4/en
Priority to CN201980001210.3A priority patent/CN112673474B/zh
Priority to CN202210062464.XA priority patent/CN114361236A/zh
Priority to BR112019026866A priority patent/BR112019026866A2/pt
Priority to AU2019279972A priority patent/AU2019279972B2/en
Priority to US16/954,924 priority patent/US11462593B2/en
Priority to KR1020217003719A priority patent/KR20220041036A/ko
Priority to CN202110002391.0A priority patent/CN112820763B/zh
Priority to TW108143771A priority patent/TWI718790B/zh
Priority to PCT/CN2020/106427 priority patent/WO2021018303A2/zh
Priority to US17/274,939 priority patent/US12027124B2/en
Priority to PCT/CN2020/106413 priority patent/WO2021018301A1/zh
Priority to CN202080001420.5A priority patent/CN112585761B/zh
Priority to CN202210569245.0A priority patent/CN114899211A/zh
Priority to CN202080001419.2A priority patent/CN115606325A/zh
Priority to US17/274,229 priority patent/US20210320156A1/en
Priority to US17/272,777 priority patent/US11423840B2/en
Priority to CN202080001429.6A priority patent/CN113056828A/zh
Priority to PCT/CN2020/106429 priority patent/WO2021018304A1/zh
Priority to US17/156,802 priority patent/US11489018B2/en
Publication of WO2021016956A1 publication Critical patent/WO2021016956A1/zh
Priority to US17/682,286 priority patent/US11552131B2/en
Priority to US17/828,211 priority patent/US11776479B2/en
Priority to JP2022090879A priority patent/JP7453277B2/ja
Priority to US18/315,556 priority patent/US11948512B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/814—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular to electroluminescent display panels and display devices.
  • OLED display panels have been increasingly used due to their self-luminous, wide viewing angle, high contrast, low power consumption, and high response speed. Used in various electronic devices. As people's requirements for OLED display panels increase, in order to achieve high-resolution design in display panels, OLED display panels usually adopt SPR pixel arrangement, that is, pixel borrowing.
  • an electroluminescent display panel including:
  • each of the repeating units includes a plurality of sub-pixels, and each of the sub-pixels includes:
  • the first conductive layer is located above the substrate;
  • a first insulating layer located above the first conductive layer and including a first via hole exposing a part of the first conductive layer;
  • the anode is located on the first insulating layer and includes a main body part and an auxiliary part electrically connected to each other; the auxiliary part is electrically connected to the first conductive layer through the first via;
  • the orthographic projection of the main body portion on the substrate and the orthographic projection of the first via on the substrate do not overlap;
  • the size of the body portion in the first direction is greater than the size in the second direction, and in at least one of the sub-pixels, the first via hole and the body portion are in the first direction. Arranged in two directions; wherein the first direction is different from the second direction.
  • the first conductive layer includes: a first power line and a first connection line that are spaced apart from each other;
  • the auxiliary portion is electrically connected to the first connection line through the first via hole.
  • the first power line includes: a plurality of sub power lines arranged along the first direction and extending along the second direction, and a plurality of sub power lines electrically connected to each of the sub power lines Conduction line.
  • the sub-power line and the conduction line roughly form a grid structure, and each grid is provided with one first connection line, and the first connection line There is a space between the sub power line and the conduction line.
  • At least one of the multiple repeating units includes: one first color sub-pixel, one second color sub-pixel pair, and one first color sub-pixel arranged along the second direction.
  • the multiple repeating units are arranged along the second direction to form a repeating unit group, the repeating unit group is arranged along the first direction, and the repeating units in two adjacent repeating unit groups are arranged in a staggered manner.
  • each of the sub-pixels further includes: a pixel driving circuit located on the side of the first conductive layer facing the substrate; wherein, the pixel driving circuits in each of the sub-pixels are arrayed.
  • the first included angle is between 45 degrees and 165 degrees;
  • the size of the area where each layer pattern in each pixel driving circuit is located in the second direction is larger than the size in the first direction.
  • a pair of second-color sub-pixels in two adjacent repeating unit groups is in the adjacent first-color sub-pixel and third-color sub-pixel in another repeating unit group Between the maximum span in the second direction.
  • the size of the body portion of the first color sub-pixel in the second direction is smaller than the size of the body portion of the third color sub-pixel in the second direction ;
  • the size of the body portion of the first color sub-pixel in the first direction is larger than the size of the body portion of the third color sub-pixel in the first direction.
  • the orthographic projection of the main body portion on the substrate and the orthographic projection of the first via on the substrate do not overlap.
  • the main body part is an axisymmetric figure
  • the first via is located on the symmetry axis of the main body part along the second direction on.
  • the orthographic projection of the main body portion on the substrate does not overlap with the driving transistor in the pixel driving circuit, and the main body portion is The orthographic projection of the substrate overlaps the orthographic projection of the reset control signal line and the reset power signal line electrically connected to the pixel driving circuit of the next row adjacent to the pixel driving circuit on the substrate, and the main body is on the substrate
  • the orthographic projection of the two data lines overlaps the orthographic projection of the two data lines on the substrate
  • the orthographic projection of the main body part on the substrate overlaps the orthographic projection of the two second power lines on the substrate.
  • the orthographic projection of the main body portion on the substrate and the orthographic projection of the first via on the substrate do not overlap.
  • the main body part is an axisymmetric figure, and the first via is located on the symmetry axis of the main body part along the second direction on.
  • the orthographic projection of the main body part on the substrate overlaps the driving transistor in the pixel driving circuit, and the main body part is in the The orthographic projection of the substrate overlaps the orthographic projection of the light-emitting control signal line electrically connected to the pixel drive circuit on the substrate, and the orthographic projection of the main body part on the substrate and the two data lines on the substrate are overlapped.
  • the orthographic projection of the main body portion on the substrate and the orthographic projection of the first via on the substrate do not overlap.
  • the second-color sub-pixel pair includes a first second-color sub-pixel and a second second-color sub-pixel; in the same repeating unit, the first The first via hole of the second color sub-pixel is located on the side of the first second color sub-pixel away from the third color sub-pixel;
  • the first via hole of the second second color sub-pixel is located on the side of the second second color sub-pixel away from the third color sub-pixel.
  • the first color sub-pixel and the first second color sub-pixel in the same repeating unit and for the first color sub-pixel and the first color sub-pixel in the same repeating unit.
  • the second color sub-pixels are the nearest neighbors of the third color sub-pixel, and the first via hole of the first second-color sub-pixel is located between the first-color sub-pixel and the third-color sub-pixel In the gap
  • the first color subpixel and the second second color subpixel in the same repeating unit and for the first color subpixel and the second second color subpixel in the same repeating unit that are nearest neighbors Three-color sub-pixels, and the first via hole of the second second-color sub-pixel is located in the gap between the first-color sub-pixel and the third-color sub-pixel.
  • the orthographic projection of the main body portion on the substrate does not overlap with the driving transistor in the pixel driving circuit, and the The orthographic projection of the main body on the substrate overlaps the orthographic projection of the reset control signal line and the scanning signal line on the substrate of the pixel driving circuit of the next row adjacent to the pixel driving circuit;
  • the orthographic projection of the main body part on the substrate and the driving transistor in the pixel driving circuit do not overlap, and the orthographic projection of the main body part on the substrate and the driving transistor
  • the orthographic projection of the reset control signal line and the scanning signal line electrically connected to the pixel drive circuit in the next row adjacent to the pixel drive circuit overlap on the substrate.
  • the pixel driving circuit in the third color sub-pixel, the pixel driving circuit in the first second color sub-pixel, the pixel in the first color sub-pixel is arranged in sequence along the first direction.
  • the first via holes in the sub-pixels of the same color are located on the same side of the sub-pixels of the color.
  • the first via hole of the first second color sub-pixel, the first via hole of the first color sub-pixel, and the second The first via holes of the two second color sub-pixels are sequentially arranged on the same first sub-fold line along the first direction;
  • the first via hole of the first color sub-pixel and The first via holes of the third color sub-pixels are arranged on the same second sub-fold line along a third direction; wherein the third direction crosses the first direction.
  • the fold line includes: the first sub-fold line and the second sub-fold line; among two adjacent repeating units in different columns, the fold line in the first repeating unit The first via hole of the third color sub-pixel and the first via hole of the first second color sub-pixel, the first via hole of the first color sub-pixel, and the second repeating unit in the second repeating unit The first via holes of the two second color sub-pixels are sequentially arranged on the fold line.
  • the first via holes of the third color sub-pixels and the first via holes of the first color sub-pixels in the same repeating unit are arranged along the second direction On the same straight line.
  • the first via of the first second color sub-pixel in one repeating unit and the second via in the other repeating unit are arranged on the same straight line along the second direction.
  • the first via holes of the first color sub-pixels in the same row of repeating units are arranged on the same straight line along the first direction;
  • the first via holes of the third color sub-pixels in the same row of repeating units are arranged in the same direction along the first direction. In a straight line.
  • the electroluminescent display panel further includes:
  • the second conductive layer is located between the first conductive layer and the substrate, and includes: a second power line and a second connection line arranged at intervals;
  • the second insulating layer is located between the second conductive layer and the first conductive layer, and has a second via hole exposing the second connection line and a third via hole exposing a part of the second power line hole;
  • the first connection line and the second connection line are electrically connected to each other through the second via;
  • the first power line and the second power line are electrically connected to each other through the third via.
  • the orthographic projection of the first connection line on the substrate and the second connection line at least partially overlap
  • the orthographic projection of the first power cord on the substrate and the orthographic projection of the second power cord on the substrate at least partially overlap.
  • the first via hole is disposed closer to the driving transistor in the pixel driving circuit than the second via hole;
  • the first via hole is arranged farther away from the driving transistor in the pixel driving circuit than the second via hole;
  • the first via hole is arranged farther away from the driving transistor in the pixel driving circuit than the second via hole.
  • the orthographic projection of the first via on the substrate and the orthographic projection of the second via on the substrate substantially do not overlap.
  • each of the sub-pixels further includes: a fourth via;
  • the orthographic projection of the fourth via on the substrate overlaps the orthographic projection of the second via on the substrate;
  • the orthographic projection of the fourth via on the substrate overlaps the orthographic projection of the first via on the substrate;
  • the orthographic projection of the fourth via on the substrate overlaps the orthographic projection of the first via on the substrate.
  • the fourth via holes are arranged on a straight line along the first direction, and the spacing between two adjacent fourth via holes on the same straight line is substantially the same.
  • the distance between two adjacent first vias along the first direction is substantially the same, and the two adjacent first vias along the second direction
  • the spacing between vias is roughly the same
  • the distance between two adjacent second via holes in the first direction is approximately the same, and the distance between two adjacent second via holes in the second direction is approximately the same.
  • the light emission control signal line electrically connected to the drive circuit of the orthographic projection of the first via on the substrate is on the substrate The orthographic projections overlap, and the orthographic projection of the second via on the substrate and the light emitting control signal line electrically connected to the drive circuit do not overlap on the orthographic projection of the substrate, and the fourth via is on the substrate The orthographic projection of the substrate and the light-emitting control signal line electrically connected to the drive circuit do not overlap the orthographic projection of the substrate.
  • the light emission control signal line electrically connected to the driving circuit of the orthographic projection of the first via on the substrate is on the substrate
  • the orthographic projection does not overlap, and the orthographic projection of the second via on the substrate overlaps the orthographic projection of the light-emitting control signal line electrically connected to the drive circuit on the substrate, and the fourth via is on the substrate.
  • the orthographic projection of the substrate and the light-emitting control signal line electrically connected to the drive circuit do not overlap the orthographic projection of the substrate.
  • the projection of the first via on the substrate is electrically connected to the light emission control signal line of the drive circuit on the substrate
  • the orthographic projection does not overlap, and the orthographic projection of the second via on the substrate overlaps the orthographic projection of the light-emitting control signal line electrically connected to the drive circuit on the substrate, and the fourth via is on the substrate.
  • the orthographic projection of the substrate and the light-emitting control signal line electrically connected to the drive circuit do not overlap the orthographic projection of the substrate.
  • the orthographic projection of the main body portion on the substrate and the orthographic projection of the second via on the substrate at least partially overlap.
  • the orthographic projection of the main body portion on the substrate and the orthographic projection of the two third vias on the substrate at least partially overlap.
  • the first via is close to the two third vias that overlap with the orthographic projection of the main body portion on the substrate
  • the second via is arranged close to the other side of the centerline of the two third vias overlapping with the orthographic projection of the main body on the substrate.
  • the main body part is an axisymmetric figure
  • the second via is located on the symmetry axis of the main body part along the second direction on.
  • the orthographic projection of the main body portion on the substrate and the orthographic projection of the second via on the substrate at least partially overlap.
  • the orthographic projection of the main body portion on the substrate and the orthographic projection of the two third vias on the substrate at least partially overlap.
  • the first via is disposed close to a side of the center line of the two third vias overlapped by the orthographic projection, and
  • the second via is arranged close to the other side of the center line of the two third vias overlapped by the orthographic projection.
  • the main body portion is an axisymmetric figure
  • the second via is located on the symmetry axis of the main body portion along the second direction on.
  • the first color sub-pixel and the first second color sub-pixel in the same repeating unit and for the first color sub-pixel and the first color sub-pixel in the same repeating unit.
  • the second color sub-pixels are the closest third color sub-pixels, and the second via hole of the first second-color sub-pixel is located between the first-color sub-pixel and the third-color sub-pixel In the gap
  • the second via hole of the second second-color sub-pixel is located in the gap between the first-color sub-pixel and the third-color sub-pixel.
  • the first via hole and the second via hole are arranged on the same straight line along the second direction;
  • the first via hole and the second via hole are arranged on the same straight line along the second direction.
  • the second via is located on a side of the first via away from the main portion;
  • the second via hole is located on a side of the first via hole away from the main body portion.
  • the second via hole of the third color sub-pixel in the odd-numbered column repeating unit group and the first via hole of the first color sub-pixel in the even-numbered column repeating unit group and the first The first via holes of the second color sub-pixel and the first via holes of the second second color sub-pixel are arranged on the same straight line along the first direction.
  • the orthographic projection of the main body portion on the substrate covers the orthographic projection of the two sub power lines on the substrate;
  • the two sub-power supply lines overlapped in the orthographic projection of the substrate are arranged in parallel on both sides of the center of the main body portion.
  • the orthographic projection of the main body portion on the substrate covers the orthographic projection of the two sub-power lines on the substrate;
  • the two sub-power supply lines overlapped in the orthographic projection of the substrate are arranged in parallel on both sides of the center of the main body portion.
  • the orthographic projection of the main body portion on the substrate is electrically connected to one of the sub power lines and the sub power lines.
  • the orthographic projections of the lines on the substrate at least partially overlap.
  • the first conductive layer includes: a first power line, a first connection line, and a data line that are spaced apart from each other;
  • the auxiliary portion is electrically connected to the first connection line through the first via hole.
  • the first power line and the data line are arranged along a first direction and extend along a second direction; and the first direction is different from the second direction.
  • the first power line is configured as a power line that transmits a driving voltage.
  • the embodiments of the present disclosure also provide a display device, including the electroluminescent display panel as described above.
  • FIG. 1a is a schematic diagram of a top view structure of a display panel in the related art
  • FIG. 1b is a schematic cross-sectional structure diagram along the AA' direction in the display panel shown in FIG. 1a;
  • FIG. 2a is a schematic structural diagram of some pixel driving circuits in the disclosure.
  • FIG. 2b is a schematic top view of some active semiconductor layers in this disclosure.
  • FIG. 2c is a schematic top view of some gate conductive layers in the disclosure.
  • 2d is a schematic top view of some reference conductive layers in this disclosure.
  • 2e is a schematic top view of some source and drain metal layers in the disclosure.
  • FIG. 2f is a schematic top view of some auxiliary metal layers in the disclosure.
  • 2g is a schematic diagram of the stacking positional relationship of the active semiconductor layer, the gate conductive layer, the reference conductive layer, the source and drain metal layers, and the auxiliary metal layer in the disclosure;
  • FIG. 3a is a schematic diagram of a top view structure of some display panels in this disclosure.
  • FIG. 3b is a schematic diagram of a top view structure of still other display panels in this disclosure.
  • FIG. 3c is a schematic diagram of a top view structure of still other display panels in this disclosure.
  • FIG. 4 is a schematic diagram of the structure of anodes, first via holes, and second via holes of some display panels in this disclosure
  • FIG. 5a is a schematic diagram of the structure of the first conductive layer, the second via hole and the third via hole in some display panels in this disclosure;
  • FIG. 5b is a schematic diagram of the structure of the first conductive layer, the second via hole and the third via hole in some other display panels in the disclosure;
  • Fig. 6a is a schematic sectional view of the display panel shown in Fig. 3a along the AA' direction;
  • 6b is a schematic cross-sectional view of the display panel shown in FIG. 3a along the BB' direction;
  • FIG. 6c is a schematic cross-sectional structure view along the AA' direction in the display panel shown in FIG. 3b;
  • FIG. 7a is a schematic cross-sectional structure view along the CC' direction in the display panel shown in FIG. 3a;
  • Fig. 7b is a schematic cross-sectional view of the display panel shown in Fig. 3a along the DD' direction;
  • Fig. 8a is a schematic cross-sectional view of the display panel shown in Fig. 3a along the EE' direction;
  • Fig. 8b is a schematic cross-sectional view of the display panel shown in Fig. 3a along the FF' direction;
  • FIG. 8c is a schematic cross-sectional view of the display panel shown in FIG. 3b along the BB' direction;
  • FIG. 9a is a schematic top view of some other display panels in this disclosure.
  • FIG. 9b is a schematic diagram of a top view structure of still other display panels in this disclosure.
  • FIG. 10 is a schematic diagram of the structure of the anode and the first via hole of the display panel shown in FIG. 9a;
  • FIG. 11 is a schematic diagram of the structure of the first conductive layer and the first via hole in the display panel shown in FIG. 9a;
  • FIG. 12 is a schematic cross-sectional view of the display panel shown in FIG. 9a along the AA' direction;
  • Fig. 13 is a schematic cross-sectional view of the display panel shown in Fig. 9a along the BB' direction;
  • FIG. 14 is a schematic cross-sectional view of the display panel shown in FIG. 9a along the CC' direction;
  • FIG. 15 is a schematic cross-sectional view of the display panel shown in FIG. 9a along the DD' direction;
  • FIG. 16 is a schematic cross-sectional view of the display panel shown in FIG. 9b along the AA' direction;
  • Fig. 17 is a schematic cross-sectional view of the display panel shown in Fig. 9b along the BB' direction.
  • a typical OLED display panel includes a base substrate, a pixel drive circuit provided on the base substrate, a flat layer provided on the side of the pixel drive circuit away from the base substrate, an anode provided on the side of the flat layer away from the base substrate, The light-emitting layer is arranged on the side of the anode away from the base substrate and the cathode is arranged on the side of the light-emitting layer away from the base substrate.
  • FIG. 1a is a schematic top view of some display panels.
  • FIG. 1b is a schematic cross-sectional view of the display panel shown in FIG. 1a along the AA' direction.
  • the display panel may include: a base substrate 10, a pixel driving circuit 20, a planarization layer 30, an anode 40, a light emitting layer 50, a cathode 60, and a pixel defining layer 80; the pixel defining layer 80 has an opening, The effective light-emitting area is defined by the opening.
  • the pixel driving circuit 20 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor, and the generated electrical signal is input to the anode 40 through the connection line 21.
  • the flat layer 30 has a via 31, and the anode 40 is electrically connected to the connecting wire 21 through the via 31.
  • the via hole 31 has a certain depth, the anode 40 and the light-emitting layer 50 on the anode 40 are recessed in the area where the via hole 31 exists, resulting in unevenness of the anode 40 and color shift in the display panel.
  • the pixel driving circuit 0121 may include: a pixel driving circuit 0122, a first light emission control circuit 0123, a second light emission control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128, and a reset circuit 0129 .
  • the pixel driving circuit 0122 includes a control terminal, a first terminal and a second terminal, and is configured to provide the light-emitting element 0120 with a driving current for driving the light-emitting element 0120 to emit light.
  • the first light emission control circuit 0123 is connected to the first terminal of the pixel driving circuit 0122 and the first voltage terminal VDD, and is configured to realize the on or off the connection between the pixel driving circuit 0122 and the first voltage terminal VDD
  • the second light-emitting control circuit 0124 is electrically connected to the second end of the pixel driving circuit 0122 and the first light-emitting voltage application electrode of the light-emitting element 0120, and is configured to realize on or off the connection between the pixel driving circuit 0122 and the light-emitting element 0120 open.
  • the data writing circuit 0126 is electrically connected to the first terminal of the pixel driving circuit 0122, and is configured to write the data signal into the storage circuit 0127 under the control of the scan signal; the storage circuit 0127 and the control terminal of the pixel driving circuit 0122 and the first terminal
  • the voltage terminal VDD is electrically connected and is configured to store data signals;
  • the threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the pixel drive circuit 0122, and is configured to perform threshold compensation on the pixel drive circuit 0122;
  • the reset circuit 0129 and The control terminal of the pixel drive circuit 0122 and the first light-emitting voltage application electrode of the light-emitting element 0120 are electrically connected, and are configured to apply electrodes to the control terminal of the pixel drive circuit 0122 and the first light-emitting voltage application electrode of the light-emitting element 0120 under the control of a reset control signal Perform a reset.
  • the light-emitting device 0120 includes an anode 40, a light-emitting
  • the pixel driving circuit 0122 includes a driving transistor T1
  • the control terminal of the pixel driving circuit 0122 includes the gate of the driving transistor T1
  • the first terminal of the pixel driving circuit 0122 includes the first of the driving transistor T1.
  • the second terminal of the pixel driving circuit 0122 includes the second terminal of the driving transistor T1.
  • the data writing circuit 0126 includes a data writing transistor T2
  • the storage circuit 0127 includes a third capacitor C2
  • the threshold compensation circuit 0128 includes a threshold compensation transistor T3
  • the first light emission control circuit 0123 includes a first
  • the second light emission control circuit 0124 includes a second light emission control transistor T5
  • the reset circuit 0129 includes a first reset transistor T6 and a second reset transistor T7
  • the reset control signal may include a first sub-reset control signal and a second sub-reset control signal. Reset control signal.
  • the first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1
  • the second electrode of the data writing transistor T2 is configured to be electrically connected to the data line Vd to receive the data signal
  • the data writing transistor The gate of T2 is configured to be electrically connected to the first scan signal line Ga1 to receive the scan signal
  • the first electrode of the third capacitor C2 is electrically connected to the first power supply terminal VDD
  • the second electrode of the third capacitor C2 is electrically connected to the driving transistor T1
  • the gate of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the gate of the threshold compensation transistor T3 Is configured to be electrically connected to the second scan signal line Ga2 to receive the compensation control signal
  • the first electrode of the first reset transistor T6 is configured to be electrically connected to the first reset power terminal Vinit1 to receive the first reset signal, the first reset transistor
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power terminal VSS may be a voltage source to output a constant first voltage.
  • Two voltages, the second voltage is a negative voltage, etc.
  • the second power terminal VSS may be grounded.
  • the pixel driving circuit of the sub-pixel may not only be the structure shown in FIG. 2a, but also may be a structure including other numbers of transistors, which is not limited in the embodiment of the present disclosure. .
  • FIGS. 2b to 2g are schematic diagrams of various layers of a pixel driving circuit provided by some embodiments of the disclosure. The positional relationship of each circuit in the pixel driving circuit on the substrate is described below with reference to FIGS. 2b to 2g.
  • the example shown in FIGS. 2b to 2g takes a pixel driving circuit of a sub-pixel as an example. 2b to 2g also show the first scan signal line Ga1a, the second scan signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, and the first reset connected to the pixel drive circuit 0121.
  • the first power source signal line VDD1, the second power source signal line VDD2, the first power source signal line VDD1 and the second power source signal line VDD2 of the terminal VDD are electrically connected to each other. It should be noted that, in the examples shown in FIGS.
  • the first scan signal line Ga1a and the second scan signal line Ga2a are the same signal line
  • the first reset power signal line Init1a and the second reset power signal line Init2a It is the same signal line
  • the first reset control signal line Rst1a and the second reset control signal line Rst2a are the same signal line
  • the first light emission control signal line EM1a and the second light emission control signal line EM2a are the same signal line.
  • FIG. 2b shows the active semiconductor layer 0310 of the pixel driving circuit 0121.
  • the active semiconductor layer 0310 can be formed by patterning a semiconductor material.
  • the active semiconductor layer 0310 can be used to make the above-mentioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6, and second reset transistor T7
  • Each active layer may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the active layer of each transistor is integrated.
  • the active semiconductor layer 0310 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the gate metal layer of the pixel driving circuit 0121 may include the gate conductive layer 0320.
  • a gate insulating layer (not shown) is formed on the aforementioned active semiconductor layer 0310 for protecting the aforementioned active semiconductor layer 0310.
  • FIG. 2c shows the gate conductive layer 0320 of the pixel driving circuit 0121.
  • the gate conductive layer 0320 is disposed on the gate insulating layer so as to be insulated from the active semiconductor layer 0310.
  • the gate conductive layer 0320 may include the second pole CC2a of the third capacitor C2, the first scan signal line Ga1a, the second scan signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first light emission control The signal line EM1a, the second light emission control signal line EM2a, and the drive transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the second Reset the gate of transistor T7.
  • the gate of the data writing transistor T2 may be the overlapping portion of the first scan signal line Ga1a and the active semiconductor layer 0310
  • the gate of the first light-emitting control transistor T4 may be the first light-emitting control
  • the gate of the second light emission control transistor T5 may be the first light emission control signal line EM1a/the second light emission control signal line EM2a and
  • the gate of the first reset transistor T6 is the first part where the first reset control signal line Rst1a/the second reset control signal line Rst2a overlaps the active semiconductor layer 0310
  • the second reset The gate of the transistor T7 is the second part where the first reset control signal line Rst1a/the second reset control signal line Rst2a overlaps the active semiconductor layer 0310
  • the threshold compensation transistor T3 may be a thin film transistor with
  • each dotted rectangular frame in FIG. 2b shows each part where the gate conductive layer 0320 and the active semiconductor layer 0310 overlap.
  • the signal line EM2a is arranged along the second direction F2.
  • the first scan signal line Ga1a/the second scan signal line Ga2a is located between the first reset control signal line Rst1a/the second reset control signal line Rst2a and the first light emission control signal line EM1a/the second light emission control signal line EM2a.
  • the second pole CC2a of the third capacitor C2 is located between the first scan signal line Ga1a/the second scan signal line Ga2a and the first light emission control signal line EM1/a and the second light emission control signal line EM2a. between.
  • the protrusion protruding from the second scan signal line Ga2a is located on the side of the second scan signal line Ga2a away from the first light emission control signal line EM1a/the second light emission control signal line EM2a.
  • the gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6, and the gate of the second reset transistor T7 are all Located on the first side of the gate of the driving transistor T1, the gate of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 are both located on the second side of the gate of the driving transistor T1.
  • the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located at the gate of the driving transistor T1
  • the gate of the second light emission control transistor T5 and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1.
  • the third side and the fourth side of the gate of the driving transistor T1 are opposite sides of the gate of the driving transistor T1 in the first direction F1.
  • a first interlayer insulating layer (not shown) is formed on the aforementioned gate conductive layer 0320 to protect the aforementioned gate conductive layer 0320.
  • 2d shows the reference conductive layer 0330 of the pixel driving circuit 120a.
  • the reference conductive layer 0330 includes the first pole CC1a of the third capacitor C2, the first reset power signal line Init1a, and the second reset power signal line Init2a.
  • the first pole CC1a of the third capacitor C2 and the second pole CC2a of the third capacitor C2 at least partially overlap to form a third capacitor C2.
  • FIG. 2e shows the source and drain metal layer 0340 of the pixel driving circuit 0121.
  • the source and drain metal layer 0340 includes a data line Vd and a first power signal line VDD1.
  • a third interlayer insulating layer (not shown) is formed on the aforementioned source and drain metal layer 0340 to protect the aforementioned source and drain metal layer 0340.
  • 2f shows the auxiliary metal layer 0350 of the pixel driving circuit 0121, and the auxiliary metal layer 0350 includes the second power signal line VDD2.
  • FIGS. 2e to 2g is a schematic diagram of the stacked positional relationship of the above-mentioned active semiconductor layer 0310, gate conductive layer 0320, reference conductive layer 0330, source and drain metal layer 0340, and auxiliary metal layer 0350.
  • the data line Vd passes through at least one via (for example, via 381a) of the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer and the active semiconductor layer 0310
  • the data writing in the transistor T2 is electrically connected to the source region.
  • the first power signal line VDD1 passes through at least one via (for example, via 382a) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer to correspond to the first light emitting in the active semiconductor layer 0310.
  • the source region of the control transistor T4 is electrically connected.
  • the first power signal line VDD1 is electrically connected to the first pole CC1a of the third capacitor C2 in the reference conductive layer 0330 through at least one via in the second insulating layer (for example, via 3832a).
  • the first power signal line VDD1 is also electrically connected to the second power signal line VDD2 in the auxiliary metal layer 0350 through at least one via (for example, via 3831a) in the second insulating layer.
  • the source-drain metal layer 0340 further includes a connecting portion 341a, a connecting portion 342a, and a connecting portion 343a.
  • One end of the connecting portion 341a passes through at least one via hole (for example, via hole 384a) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer and the corresponding threshold compensation transistor T3 in the active semiconductor layer 0310
  • the drain region is electrically connected.
  • the other end of the connecting portion 341a passes through at least one via hole (for example, via hole 385a) in the first interlayer insulating layer and the second interlayer insulating layer, and the gate electrode (that is, the third via hole 385a) of the driving transistor T1 in the gate conductive layer 0320.
  • the second pole CC2a) of the capacitor C2 is electrically connected.
  • One end of the connecting portion 342a is electrically connected to the first reset power signal line Init1a/the second reset power signal line Init2a through a via (for example, via 386a) in the second insulating layer, and the other end of the connecting portion 342a passes through the gate.
  • At least one via (for example, via 387a) in the insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer is electrically connected to the drain region of the second reset transistor T7 in the active semiconductor layer 0310.
  • the connection portion 343a passes through at least one via hole (for example, via hole 388a) in the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer and the second light emission control transistor T5 in the active semiconductor layer 0310.
  • the drain region is electrically connected.
  • the auxiliary metal layer 0350 further includes a connection portion 351a.
  • the connection portion 351a is electrically connected to the connection portion 343a through a via hole (for example, a via hole 385b) penetrating the third interlayer insulating layer.
  • the first scan signal line Ga1a, the second scan signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first The reset power signal line Init1a and the second reset power signal line Init2a are both located on the first side of the gate of the driving transistor T1.
  • the first light emission control signal line EM1a and the second light emission control signal line EM2a are both located on the second side of the drive transistor T1. side.
  • the first scan signal line Ga1a, the second scan signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first light emission control signal line EM1a, the second light emission control signal line EM2a, the first The reset power signal line Init1a and the second reset power signal line Init2a both extend along the first direction F1, and the data line Vd extends along the second direction F2.
  • the first power signal line VDD1 extends in the second direction F2
  • the second power signal line VDD2 extends in the second direction F2. That is, on the entire display substrate, the first power supply signal line VDD1 and the second power supply signal line VDD2 are electrically connected, so that the signal line of the first power supply terminal VDD has a smaller resistance and a lower voltage drop, thereby increasing the A stability of the power supply voltage provided by the power supply terminal VDD.
  • the first scan signal line Ga1a, the second scan signal line Ga2a, the first reset control signal line Rst1a, the second reset control signal line Rst2a, the first light emission control signal line EM1a, and the second light emission control signal line EM2a are located in the same layer
  • the first reset power signal line Init1a, the second reset power signal line Init2a, and the second power signal line VDD2a are located in the same layer.
  • the first power signal line VDD1 and the data line Vd are located in the same layer.
  • the positional arrangement of the pixel drive circuit, the first light emission control circuit, the second light emission control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit and the reset circuit in each pixel drive circuit is not limited to The examples shown in Figures 2b to 2g can be specifically set according to actual application requirements, the position of the pixel driving circuit, the first light-emitting control circuit, the second light-emitting control circuit, the data writing circuit, the storage circuit, the threshold compensation circuit, and the reset circuit .
  • the electroluminescent display panel provided by the embodiments of the present disclosure may include a plurality of repeating units 001, each repeating unit 001 includes a plurality of sub-pixels, each sub-pixel may include: a first located above the substrate 100 The conductive layer 200, the first insulating layer 300 located above the first conductive layer 200, and the anode 400 located on the first insulating layer 300.
  • the first insulating layer 300 includes a first via hole 310 that exposes a part of the first conductive layer 200.
  • the anode 400 includes a main body part 410 and an auxiliary part 420 electrically connected to each other, and the auxiliary part 420 is electrically connected to the first conductive layer 200 through the first via 310.
  • the orthographic projection of the main body portion 410 on the substrate 100 and the orthographic projection of the first via 310 on the substrate 100 do not overlap.
  • the size of the body portion 410 in the first direction F1 is greater than the size in the second direction F2, and in at least one sub-pixel, the first via 310 and the body portion 410 are arranged in the second direction F2. Wherein, the first direction F1 and the second direction F2 are different.
  • the anode includes a main part and an auxiliary part electrically connected to each other, and the auxiliary part is electrically connected to the first conductive layer through the first via hole, so that the anode passes through the first conductive layer. It is electrically connected to the pixel drive circuit.
  • the size of the body portion in the first direction is greater than the size in the second direction, and in at least one sub-pixel, the first via and the body portion are arranged in the second direction; wherein, the first The direction is different from the second direction.
  • the orthographic projection of the main body on the substrate and the orthographic projection of the first via on the substrate do not overlap, the first via in the sub-pixel can be avoided to make the anode in the sub-pixel
  • the main body part is not affected by the depth of the first via hole, so as to prevent the main body portion of the anode from being recessed, so as to avoid the unevenness of the anode caused by the first via hole, thereby improving the color shift of the display panel.
  • the first via and the main body are arranged in the second direction.
  • the first via and the main body are projected on a straight line parallel to the second direction, and the first The projection of a via hole and the projection of the main body part do not completely overlap, for example, the projection of the first via hole and the projection of the main body part do not overlap, or overlap only a part; the first via and the main body The part is projected on a straight line parallel to the first direction, and the projection of the first via completely falls within the projection of the main body part.
  • the first via hole and the main body portion are arranged in the second direction.
  • the main body portion may have a first side substantially parallel to the first direction, and the first via hole is located in the main body.
  • the first via holes and the main body portion are arranged in the second direction, for example, the angle between a virtual line connecting the center of the first via hole and any point of the main body portion and the second direction It is less than 90°, further, it may be less than 60°, and still further, it may be less than 45°.
  • the main part and the auxiliary part in the same sub-pixel are of an integrated structure.
  • one patterning process is used to form the main part and the auxiliary part in the same sub-pixel.
  • the first conductive layer 200 may include: a first power line 210 and a first connection line 220 that are spaced apart from each other; wherein, each sub-pixel
  • the auxiliary part 420 is electrically connected to the first connection line 220 through the first via 310.
  • the first conductive layer 200 is, for example, the aforementioned auxiliary metal layer 0350.
  • the first power line 210 is, for example, the above-mentioned second power signal line VDD2
  • the first connection line 220 is, for example, the above-mentioned connecting portion 351a.
  • the corresponding relationship of the vias is not described here.
  • the electroluminescent display panel may further include: a second conductive layer 600 located between the first conductive layer 200 and the substrate 100, and The second insulating layer 500 between the second conductive layer 600 and the first conductive layer 200.
  • the second conductive layer 600 has a second power supply line 610 and a second connection line 620 arranged at intervals.
  • the second insulating layer 500 has a second via 520 exposing the second connection line 620 and a third via 630 exposing a part of the second power line 610.
  • the first power line 210 and the second power line 610 are electrically connected to each other through the third via 530 to achieve the effect of reducing resistance.
  • the first connection line 220 is electrically connected to each other through the second via 520 and the second connection line 620, and the second connection line 620 is electrically connected to the drain of the transistor in the pixel driving circuit to realize signal transmission.
  • the second conductive layer 600 is, for example, the aforementioned source and drain metal layer 0340.
  • the second power line 610 is, for example, the aforementioned first power signal line VDD1
  • the second connection line 620 is, for example, the aforementioned connecting portion 343a.
  • the corresponding relationship between the via hole and the insulating layer and the remaining film layers can be referred to the implementation of the active semiconductor layer 0310, the gate conductive layer 0320, and the reference conductive layer 0330, which will not be repeated here.
  • the orthographic projection of the first connection line 220 on the substrate 100 and The orthographic projection of the second connecting line 620 on the substrate 100 at least partially overlaps.
  • the orthographic projection of the first connecting line 220 on the substrate 100 overlaps with the orthographic projection of the second connecting line 620 on the substrate 100.
  • the orthographic projection of the first connecting line 220 on the substrate 100 and the orthographic projection of the second connecting line 620 on the substrate 100 overlap. This can improve the effect of mutual electrical connection.
  • the orthographic projection of the first power cord 210 on the substrate 100 and the orthographic projection of the second power cord 610 on the substrate 100 at least partially overlap.
  • the orthographic projection of the first power cord 210 on the substrate 100 and the orthographic projection of the second power cord 610 on the substrate 100 overlap.
  • the orthographic projection of the first power cord 210 on the substrate 100 and the orthographic projection of the second power cord 610 on the substrate 100 overlap. This can improve the effect of mutual electrical connection.
  • the third via 530 is arrayed on the substrate 100.
  • the plurality of third via holes 530 are uniformly arranged along the first direction F1 and the second direction F2.
  • the first power line 210 may be configured as a power line that transmits a driving voltage.
  • the second power line 610 can also be configured as a power line for transmitting the driving voltage. Therefore, the adverse effect of the load on the transmitted driving voltage can be reduced.
  • the second conductive layer 600 also has data lines and bridge lines that are respectively arranged at intervals from the second power line 610 and the second connection line 620.
  • the bridge line is configured to electrically connect two of the gate, source, and drain of some transistors in the pixel driving circuit.
  • the data line is configured to transmit data signals, and the setting method of the data line and the bridge line can be basically the same as the setting method in the related art, which will not be repeated here.
  • each sub-pixel may further include a pixel defining layer 80 on the side of the anode 400 away from the substrate 100, and a light-emitting layer 50 on the side of the anode 400 away from the substrate 100. , And a cathode 60 on the side of the anode away from the light-emitting layer 50.
  • the pixel defining layer 80 has an opening, and the opening exposes at least a part of the area of the body portion 410 of the anode 400.
  • the light emitting layer 50 is located in the opening and is in contact with the area of the body portion 410 exposed by the opening, and the light emitting layer 50 in the opening is located
  • the area is used for light emission, so that the effective light-emitting area 90 can be defined by the opening.
  • the area where the opening of the pixel defining layer 80 and the main body portion 410 of the anode 400 overlap is the effective light-emitting area 90 of each sub-pixel.
  • the area where the opening of the pixel defining layer 80 in the third color sub-pixel 030 overlaps with the main body portion 413 of the anode 400 is the effective light-emitting area 90-030 of the third color sub-pixel 030.
  • the area where the opening of the pixel defining layer 80 in the first color sub-pixel 010 overlaps with the main body portion 411 of the anode 400 is the effective light-emitting area 90-010 of the first color sub-pixel 010.
  • the area where the opening of the pixel defining layer 80 in the second color sub-pixel 021 overlaps with the main body portion 4121 of the anode 400 is the effective light-emitting area 90-021 of the second color sub-pixel 021.
  • the area where the opening of the pixel defining layer 80 in the second color sub-pixel 022 overlaps with the main body portion 4122 of the anode 400 is the effective light-emitting area 90-022 of the second color sub-pixel 022.
  • each light-emitting layer may include the electroluminescent layer itself and other common layers located on both sides of the electroluminescent layer, for example, a hole injection layer, a hole transport layer, and an electron An injection layer and an electron transport layer, etc., but in the drawings of the present disclosure, only the electroluminescent layer in the light-emitting layer is shown, and other common layers are not shown.
  • the material of the electroluminescent layer may include: organic electroluminescent material, so that the electroluminescent display panel can be an OLED display panel.
  • the material of the electroluminescent layer may also include: quantum dot electroluminescent material, so that the electroluminescent display panel can be a Quantum Dot Light Emitting Diode (QLED) display panel.
  • QLED Quantum Dot Light Emitting Diode
  • the orthographic projection of the first via 310 on the substrate 100 is different from the orthographic projection of the second via 520 on the substrate 100. overlap. In this way, the problem that the anode cannot be electrically connected to the second connection line due to the too deep via hole can be avoided.
  • the first power line 210 may include: arranged along the first direction F1 and extending along the second direction F2 Multiple sub power lines 211.
  • the first direction F1 is different from the second direction F2.
  • the first direction F1 is perpendicular to the second direction F2.
  • the first direction F1 may be the row direction of the display panel, that is, the direction in which the gate lines extend
  • the second direction F2 may be the column direction of the display panel, that is, the direction in which the data lines extend.
  • the embodiments of the present disclosure include but are not limited to this.
  • the first power line 210 may include: a plurality of sub power lines 211 arranged along the first direction F1 and extending along the second direction F2, and The conduction line 212 of each sub-power supply line 211 is connected. In this way, the resistance of the first power line 210 can be further reduced.
  • the first direction F1 is perpendicular to the second direction F2.
  • the embodiments of the present disclosure include but are not limited to this.
  • the sub power line 211 and the conduction line 212 roughly form a grid structure, and each grid is provided with a first connection line 220, In addition, there is an interval between the first connecting line 220 and the sub-power line 211 and the conducting line 212.
  • each of the multiple repeating units 001 may include: one first color sub-pixel 010 arranged along the second direction F2, and a first Two-color sub-pixel pair 020 and one third-color sub-pixel 030.
  • the pair of second color sub-pixels 020 may include two second-color sub-pixels 021 and 022 arranged along the first direction F1.
  • the first color sub-pixel 010 is configured to emit light of the first color
  • the second color sub-pixels 021 and 022 are configured to emit light of the second color
  • the third color sub-pixel is configured to emit light of the third color.
  • the first color, the second color, and the third color can be selected from red, green, and blue.
  • the first color is red
  • the second color is green
  • the third color is blue.
  • the repeating unit 001 is an arrangement structure of red, green and blue sub-pixels.
  • the embodiments of the present disclosure include but are not limited to this.
  • the aforementioned first color, second color, and third color may also be other colors.
  • a plurality of repeating units 001 are arranged along the second direction F2 to form a repeating unit group, and the repeating unit groups are arranged along the first direction F1 and are adjacent to each other.
  • the repeating units 001 in the two repeating unit groups are arranged in a staggered manner.
  • the repeating unit 001 in two adjacent repeating unit groups differs by 1/2 the size of the repeating unit 001.
  • the size of one repeating unit 001 described above may be the distance between the centers of the same color sub-pixels in two adjacent repeating units 001 in the second direction F2.
  • the size of one repeating unit 001 described above may be: the distance between the centers of the first color sub-pixels 010 in two adjacent repeating units 001 in the second direction F2.
  • the repeating units in adjacent repeating unit groups are staggered from each other along the second direction, that is, the adjacent repeating units in adjacent repeating unit groups have a certain offset along the second direction. Therefore, the sub-pixels of the same color in adjacent repeating unit groups are not aligned in the second direction.
  • the offset in the second direction of the same color sub-pixels in the adjacent repeating unit group may be half of the size of the repeating unit in the second direction.
  • the size of the repeating unit in the second direction may be the pitch of the repeating unit in the second direction.
  • the second color sub-pixel pair 020 may include two second-color sub-pixels 021, 022 arranged along the first direction F1
  • the light-emitting layers of the two second-color sub-pixels 021 and 022 in each second-color sub-pixel pair 020 can be connected, and each is formed through an evaporation hole of the FMM.
  • the light-emitting layers of the two second-color sub-pixels 021 and 022 in the second-color sub-pixel pair 020 When the second color is green, the process difficulty of preparing the light-emitting layer of the green sub-pixel can be reduced to a certain extent.
  • the shape of the main part of each sub-pixel in the drawings includes strictly a corner formed by two line segments
  • the shape of the effective light-emitting area of each sub-pixel may be rounded. That is to say, on the basis of the above-mentioned various graphic shapes, the corners of the effective light-emitting area of each sub-pixel are rounded. For example, when the light-emitting layer is vapor-deposited through a mask, the corners of the light-emitting layer may naturally form a rounded shape.
  • the shapes of the body portions of the first color sub-pixel 010 and the third color sub-pixel 030 may both be hexagons, and the three sets of opposite sides of the hexagon are all parallel.
  • the shape of the main part of each second color sub-pixel 021, 022 may be a pentagon, which includes two non-right-angled crossing sides, a set of parallel opposite sides, and a vertical side. The parallel opposite sides are vertical, and the two non-right-angled crossing sides are connected between a set of parallel opposite sides; wherein, the vertical sides of the second color sub-pixels 021 and 022 in each second color sub-pixel pair 020 are opposite to each other. O setting.
  • a set of longer parallel pairs in the main part of the first color sub-pixel 010 and a set of longer parallel pairs in the main part of the third color sub-pixel 030 The sides are respectively parallel to a set of parallel opposite sides of the main part of the second color sub-pixels 021 and 022.
  • a set of relatively long parallel sides in the effective light-emitting regions 90-010 of the first color sub-pixel 010 and a set of relatively long parallel sides in the effective light-emitting regions 90-030 of the third color sub-pixel 030 The opposite sides are respectively parallel to a group of parallel opposite sides in the effective light-emitting regions 90-021 and 90-022 of the second color sub-pixels 021 and 022.
  • the area of the first color sub-pixel 010 is larger than the area of a second color sub-pixel 020
  • the area of the third color sub-pixel 030 is larger than that of the second color sub-pixel 020. area.
  • the area of the effective light-emitting area 90-010 of the first color sub-pixel 010 is larger than the area of the effective light-emitting area 90-021, 90-022 of the second color sub-pixel 020
  • the area of -030 is larger than the area of the effective light-emitting regions 90-021 and 90-022 of one second color sub-pixel 020.
  • the interleaving distance of two adjacent repeating units in the first direction F1 in the second direction F2 is greater than that from the first color sub-pixel One of the maximum span of 010, the maximum span of the second color sub-pixel 021, the maximum span of the second color sub-pixel 022, and the maximum span of the third color sub-pixel 030, or a combination thereof.
  • the interleaving distance of two adjacent repeating units in the second direction F2 in the first direction F1 is greater than the maximum span d010 from the effective light-emitting area 90-010 of the first color sub-pixel 010, and the second color sub-pixel 021
  • the maximum span d020 of the effective light-emitting area 90-021, the maximum span d020 of the effective light-emitting area 90-022 of the second color sub-pixel 022, and the maximum span d030 of the effective light-emitting area 90-030 of the third color sub-pixel 030 Or a combination.
  • the second color subpixel 021 and the second color subpixel 022 in the second color subpixel pair 020 The farthest distance in the first direction F1 is greater than the farthest distance of any two points of the first color sub-pixel 010 in the first direction F1.
  • the effective light-emitting areas 90-021 of the second color sub-pixel 021 in the second color sub-pixel pair 020 and the effective light-emitting areas 90-022 of the second color sub-pixel 022 are in the first direction F1
  • the farthest distance on is greater than the farthest distance in the first direction F1 between any two points of the effective light-emitting regions 90-010 of the first color sub-pixel 010.
  • the second color subpixel 021 and the second color subpixel 022 in the second color subpixel pair 020 The farthest distance in the first direction F1 is greater than the farthest distance of any two points of the third color sub-pixel 030 in the first direction F1.
  • the effective light-emitting areas 90-021 of the second color sub-pixel 021 in the second color sub-pixel pair 020 and the effective light-emitting areas 90-022 of the second color sub-pixel 022 are in the first direction F1
  • the farthest distance above is greater than the farthest distance in the first direction F1 between any two points of the effective light-emitting regions 90-030 of the third color sub-pixel 030.
  • the adjacent sub-pixels of the first color sub-pixel do not include the first color sub-pixel, and the adjacent sub-pixels of the second color sub-pixel pair The second color sub-pixel is not included, and adjacent sub-pixels of the third color sub-pixel do not include the third color sub-pixel.
  • the two first-color sub-pixels 010 are composed of other than the first-color sub-pixels.
  • the two third-color sub-pixels 030 are divided by other sub-pixels except the third-color sub-pixel, and the two second-color sub-pixel pairs are divided by other sub-pixels except the second-color sub-pixel. segmentation.
  • two adjacent repeating units in the first direction F1 are arranged as a repeating group.
  • the effective light-emitting area of the second color sub-pixel pair in one repeating unit is the effective light-emitting area of a first color sub-pixel and the effective light-emitting area of a third color sub-pixel in another repeating unit
  • the zone is between the maximum span in the second direction F2.
  • two adjacent repeating units in the first direction F1 are arranged as a repeating group.
  • the effective light-emitting area of the first color sub-pixel in one repeating unit is the effective light-emitting area of a second-color sub-pixel pair and the effective light-emitting area of a third-color sub-pixel in another repeating unit
  • the zone is between the maximum span in the second direction F2.
  • two adjacent repeating units in the first direction F1 are arranged as a repeating group.
  • the effective light-emitting area of the third color sub-pixel in one repeating unit is the effective light-emitting area of a second color sub-pixel pair and the effective light-emitting area of a first color sub-pixel in another repeating unit
  • the zone is between the maximum span in the second direction F2.
  • two second color subpixels 021 and 022 of the same second color subpixel pair 020 are in the first
  • the minimum distance in one direction F1 is smaller than the maximum span of one first color sub-pixel 010 in the first direction F1.
  • the effective light-emitting areas 90-021 of the second color sub-pixel 021 and the effective light-emitting areas 90-022 of the second color sub-pixel 022 in the same second color sub-pixel pair 020 are in the first direction
  • the minimum distance on F1 is smaller than the maximum span d010 of the effective light-emitting area 90-010 of one first color sub-pixel 010 in the first direction F1.
  • two second color subpixels 021 and 022 of the same second color subpixel pair 020 are in the first
  • the minimum distance in one direction F1 is smaller than the maximum span of one third color sub-pixel 030 in the first direction F1.
  • the effective light-emitting areas 90-021 of the second color sub-pixel 021 and the effective light-emitting areas 90-022 of the second color sub-pixel 022 in the same second color sub-pixel pair 020 are in the first direction
  • the minimum distance on F1 is smaller than the maximum span d030 of the effective light-emitting area 90-030 of one third color sub-pixel 030 in the first direction F1.
  • the arrangement of the sub-pixels in the repeating unit in the odd-numbered column repeating unit group is the same, and the sub-pixels in the repeating unit in the even-numbered column repeating unit group are arranged The same way.
  • the center line of two green sub-pixels in each repeating unit is located between the centers of two adjacent red and blue sub-pixels in adjacent repeating unit groups. between.
  • the edges of the two green sub-pixels are inside the outer edges of the two adjacent red and blue sub-pixels, and the outer edge here refers to the edges of the two sub-pixels opposite to each other in the first direction F1.
  • the extension range of a green sub-pixel pair in the first direction F1 is not greater than the extension range of the two adjacent red and blue sub-pixels in the first direction F1.
  • the "center" of the sub-pixel refers to the geometry of the shape of the sub-pixel (for example, the first-color sub-pixel, the second-color sub-pixel, or the third-color sub-pixel). center.
  • the sub-pixels are generally designed in a regular shape, such as a hexagon, a pentagon, a trapezoid, or other shapes.
  • the center of the sub-pixel can be the geometric center of the aforementioned regular shape.
  • the shape of the formed sub-pixels generally has a certain deviation from the regular shape designed above. For example, the corners of the aforementioned regular shape may become rounded corners, and therefore, the shape of the sub-pixels may be rounded corners.
  • the shape of the actually manufactured sub-pixel may have other changes from the designed shape. For example, the shape of a sub-pixel designed as a hexagon may become approximately elliptical in actual manufacturing.
  • the center of the sub-pixel may not be a strict geometric center of the irregular shape of the sub-pixel formed by fabrication.
  • the center of the sub-pixel may have a certain offset from the geometric center of the shape of the sub-pixel.
  • the center of a sub-pixel refers to any point in the area enclosed by a specific point on the radial line segment starting from the geometric center of the sub-pixel to each point on the edge of the sub-pixel, and the specific point on the radial line segment is 1 distance from the geometric center. /3 at the length of the radial line segment.
  • the definition of the center of the sub-pixel is applicable to the center of a regular-shaped sub-pixel, and it is also applicable to the center of an irregular-shaped sub-pixel.
  • the three adjacent columns are along the row direction (ie, the first direction F1) It includes the first column, the second column and the third column in sequence.
  • the shortest distance between the centers of the two second-color sub-pixels 021 and 022 in the second-color sub-pixel 020 pair in the second column in the row direction is smaller than that in the first column
  • the side of the first color sub-pixel 010 in the second direction F2 and the side of the third color sub-pixel 030 in the second direction F2 Arranged in parallel.
  • the size of the body portion 411 of the first color sub-pixel 010 in the second direction F2 is smaller than the size of the body portion 413 of the third color sub-pixel 030 The size in the second direction F2. Also, the size of the body portion 411 of the first color sub-pixel 010 in the first direction F1 is larger than the size of the body portion 413 of the third color sub-pixel 030 in the first direction F1.
  • the size of the body portion 413 of the third color sub-pixel 030 in the second direction F2 is smaller than the size of the body portion 413 of the third color sub-pixel 030 in the first direction F1, and the size of the first color sub-pixel 010
  • the size of the body portion 411 in the second direction F2 is smaller than the size of the body portion 411 of the first color sub-pixel 010 in the first direction F1.
  • the embodiments of the present disclosure include but are not limited thereto, and the relationship between the above-mentioned dimensions may also be in other forms.
  • each sub-pixel further includes: a pixel driving circuit located on the side of the first conductive layer 200 facing the substrate 100; wherein, the pixel in each sub-pixel Drive circuit array distribution.
  • a pixel driving circuit located on the side of the first conductive layer 200 facing the substrate 100; wherein, the pixel in each sub-pixel Drive circuit array distribution.
  • the pixel driving circuit in the third color sub-pixel 030, the pixel driving circuit in the first second color sub-pixel 021, and the first The pixel driving circuit in the color sub-pixel 010 and the pixel driving circuit in the second second color sub-pixel 022 are sequentially arranged along the first direction F1.
  • the present disclosure includes but is not limited to this.
  • the size of the area where each layer pattern in each pixel driving circuit is located in the second direction F2 is larger than the size in the first direction F1.
  • the present disclosure includes but is not limited to this.
  • the extension direction S1 of the main body portion 411 of the first color sub-pixel 010 and the length of the area where the pixel driving circuit of the first color sub-pixel 010 is located There is a first included angle ⁇ 1 between the directions S2; wherein, the first included angle ⁇ 1 is between 45 degrees and 165 degrees.
  • ⁇ 1 may be approximately 90 degrees, that is, the extension direction S1 of the body portion 411 of the first color sub-pixel 010 (for example, the extension direction of the body portion 411 of the first color sub-pixel 010 may be the first direction F1) is substantially perpendicular to the length direction of the area where the pixel driving circuit of the first color sub-pixel 010 is located (for example, the length direction of the area where the pixel driving circuit of the first color sub-pixel 010 is located may be the second direction F2).
  • ⁇ 1 can also be approximately between 45 degrees and 135 degrees, between 75 degrees and 115 degrees, or 50 degrees, 80 degrees, 100 degrees, 120 degrees, or 140 degrees. The present disclosure is not limited to this.
  • the extension direction S3 of the main body portion 413 of the third color sub-pixel 030 and the length of the area where the pixel driving circuit of the third color sub-pixel 010 is located There is a second included angle ⁇ 2 between the directions S2; wherein, the second included angle ⁇ 2 is between 45 degrees and 165 degrees.
  • ⁇ 2 may be approximately 90 degrees, that is, the extension direction S1 of the body portion 413 of the third color sub-pixel 030 (for example, the extension direction of the body portion 411 of the third color sub-pixel 030 is the first direction F1 ) Is substantially perpendicular to the length direction S2 of the area where the pixel driving circuit of the third color sub-pixel 010 is located (for example, the length direction of the area where the pixel driving circuit of the third color sub-pixel 010 is located is the second direction F2).
  • ⁇ 2 may also be approximately 45 degrees, 75 degrees, 115 degrees, or 135 degrees. The present disclosure is not limited to this.
  • the extension direction S4 of the second color sub-pixel pair 020 and the length direction S2 of the area where the pixel driving circuit of the second color sub-pixel pair 020 is located There is a third included angle ⁇ 3 therebetween; wherein, the third included angle ⁇ 3 is between 45 degrees and 165 degrees.
  • ⁇ 3 may be approximately 90 degrees, that is, the extension direction S4 of the second color sub-pixel pair 020 (for example, the extension direction of the second color sub-pixel pair 020 is the first direction F1) and the second color sub-pixel
  • the length direction S2 of the area where the pixel driving circuit of the pixel pair 020 is located is approximately vertical.
  • ⁇ 3 can also be approximately between 45 degrees and 135 degrees, between 75 degrees and 115 degrees, or 50 degrees, 80 degrees, 100 degrees, 120 degrees, or 140 degrees. The present disclosure is not limited to this.
  • a rectangular area is defined including the pattern of each film layer of the pixel driving circuit of one sub-pixel.
  • the rectangular areas of the pixel driving circuit defining each sub-pixel are arranged in a matrix on the substrate. Then, the long side direction of the rectangular area is substantially perpendicular to the extension direction of the main part of the first color sub-pixel.
  • a rectangular area is defined including the pattern of each film layer of the pixel driving circuit of one sub-pixel.
  • the rectangular areas of the pixel driving circuit defining each sub-pixel are arranged in a matrix on the substrate. Then the long side direction of the rectangular area is substantially perpendicular to the extension direction of the main part of the third color sub-pixel.
  • the orthographic projection of the main body portion 413 on the substrate 100 does not overlap with the driving transistor in the pixel driving circuit.
  • the front projection of the main body portion 413 on the substrate 100 is electrically connected to the reset control signal line of the next row of pixel drive circuits adjacent to the pixel drive circuit (that is, the first reset control signal line Rst1a or the second reset control signal line Rst2a of the next row) and
  • the reset power signal line ie, the first reset power signal line Init1a or the second reset power signal line Init2a of the next row
  • the orthographic projection of the main body 413 on the substrate 100 overlaps the two data lines Vd.
  • the orthographic projection of the substrate 100 overlaps, and the orthographic projection of the main body 413 on the substrate 100 overlaps the orthographic projection of the two second power lines 610 on the substrate 100.
  • the data line Vd and the power line 610 whose orthographic projection overlaps the main body portion 413 are alternately arranged.
  • the present disclosure includes but is not limited to this.
  • the orthographic projection of the main body portion 413 on the substrate 100 covers the orthographic projection of the two sub-power lines 211 on the substrate 100 .
  • two sub power lines 211 overlapping with the orthographic projection of the main body part 413 on the substrate 100 are arranged in parallel on both sides of the center of the main body part 413.
  • the orthographic projection of the two sub power lines 211 overlapping the orthographic projection of the main body portion 413 on the substrate 100 passes through the orthographic projection of the main body portion 413.
  • the orthographic projection of the main body portion 411 on the substrate 100 covers the orthographic projection of the two sub-power lines 211 on the substrate 100 .
  • two sub power lines 211 overlapping with the orthographic projection of the main body portion 411 on the substrate 100 are arranged in parallel on both sides of the center of the main body portion 411.
  • the orthographic projection of the two sub power lines 211 overlapping the orthographic projection of the main body portion 411 on the substrate 100 passes through the orthographic projection of the main body portion 411.
  • the orthographic projection of the main body portion 411 on the substrate 100 overlaps the driving transistor in the pixel driving circuit, and the main body
  • the orthographic projection of the part 411 on the substrate 100 and the emission control signal line (the first emission control signal line EM1a or the second emission control signal line EM2a) that are electrically connected to the pixel drive circuit overlap the orthographic projection of the substrate 100, and the main body part 411 is on the substrate
  • the orthographic projection of 100 overlaps the orthographic projection of the two data lines Vd on the substrate 100
  • the orthographic projection of the main body portion 411 on the substrate 100 overlaps the orthographic projection of the two second power lines 610 on the substrate 100.
  • the present disclosure includes but is not limited to this.
  • the orthographic projection of the main body part on the substrate is electrically connected to a sub-power line and the sub-power line.
  • the orthographic projections of the lines on the substrate at least partially overlap.
  • the second-color sub-pixel pair 020 may include a first second-color sub-pixel 021 and a second second-color sub-pixel 022.
  • the orthographic projection of the main body portion 4121 on the substrate 100 overlaps with a sub-power line 211 and a conductive line 212 electrically connected to the sub-power line 211 in the orthographic projection of the substrate 100.
  • the sub power lines 211 and the conduction lines 212 that overlap with the orthographic projection of the main body portion 4121 on the substrate 100 may be arranged in a cross shape.
  • the embodiments of the present disclosure include but are not limited to this.
  • the aforementioned sub-power line 211 and the conducting line 212 that overlap the orthographic projection of the main body portion 4121 on the substrate 100 may also be provided in other forms.
  • the main portion 4121 is projected on the substrate 100 and the pixel drive circuit
  • the driving transistors do not overlap, and the orthographic projection of the main body part 4121 on the substrate 100 is electrically connected to the reset control signal line of the next row of pixel driving circuits adjacent to the pixel driving circuit (that is, the first reset control signal line Rst1a or the second reset The control signal line Rst2a) and the scan signal line (that is, the first scan signal line Ga1a or the second scan signal line Ga2a of the next row) overlap the orthographic projection of the substrate.
  • the present disclosure includes but is not limited to this.
  • the main part 4122 is projected on the substrate 100 and the pixel drive circuit
  • the driving transistors do not overlap
  • the orthographic projection of the main body part 4122 on the substrate 100 is the reset control signal line electrically connected to the pixel driving circuit of the next row adjacent to the pixel driving circuit (that is, the first reset control signal line Rst1a or the second reset The control signal line Rst2a) and the scanning signal line (that is, the first scanning signal line Ga1a or the second scanning signal line Ga2a of the next row) overlap the orthographic projection of the substrate 100.
  • the present disclosure includes but is not limited to this.
  • the orthographic projection of the main body portion 4122 on the substrate 100 is electrically connected to a sub-power line 211 and the sub-power line 211.
  • the line 212 overlaps in the orthographic projection portion of the substrate 100.
  • the sub power lines 211 and the conduction lines 212 that overlap with the orthographic projection of the main body part 4122 on the substrate 100 may adopt a cross-shaped arrangement.
  • the embodiments of the present disclosure include but are not limited to this.
  • the above-mentioned sub-power line 211 and the conducting line 212 overlapping with the orthographic projection of the main body part 4122 on the substrate 100 may also be provided in other forms.
  • the sub-power line 211 and the conducting line 212 are electrically connected to each other, so that the first power line 210 forms a grid-like structure.
  • the conductive lines 212 are arranged on the substrate 100 in an array.
  • the main part 413 and the first-color sub-pixels in the third-color sub-pixel 030 A conductive line 212 is provided between the main body portions 411 in the sub-pixel 010.
  • the conductive line 212 covered by the main body portion 4121 and the main body portion 4122 in the second color sub-pixel pair 020 extends on the same straight line along the first direction F1.
  • the main portion 413 and the auxiliary portion 423 are electrically connected to each other, and the auxiliary portion 423 passes through the first via 310
  • the first connection line 223 is electrically connected to each other through the second via 520 and the second connection line 623
  • the second connection line 623 is electrically connected to the drain of the transistor in the pixel driving circuit to
  • the electrical signal generated by the pixel driving circuit is input to the anode 400, and a corresponding voltage is also applied to the cathode 60 to drive the light-emitting layer 50 to emit light.
  • each of the third color sub-pixels 030 in each of the third color sub-pixels 030, the orthographic projection of the main body portion 413 on the substrate 100 and the first via hole The orthographic projections of 310 on the substrate 100 do not overlap. In this way, the main body portion 413 in each third color sub-pixel 030 is not affected by the first via hole 310, so as to avoid unevenness of the main body portion 413 caused by the first via hole 310, thereby improving the display panel's performance. Color cast phenomenon.
  • the distance between the first via hole 310 and the second via hole 520 should not be too far or too close.
  • the minimum value of the distance W between the first via hole 310 and the second via hole 520 can satisfy the range of 1 ⁇ m to 2 ⁇ m.
  • the minimum value of the distance W between the first via hole 310 and the second via hole 520 can be set to be. It is also possible to set the minimum value of the distance W between the first via hole 310 and the second via hole 520 to be, or to set the minimum value of the distance W between the first via hole 310 and the second via hole 520 to be.
  • the distance W between the first via hole 310 and the second via hole 520 can be designed and determined according to the actual application environment, and is not limited here.
  • the first insulating layer may be configured as a flat layer, so that the body portion on the first insulating layer may have a higher flatness.
  • the orthographic projection of the main body portion 413 on the substrate 100 and the second via 520 at least partially overlap.
  • the orthographic projection of the main body 413 on the substrate 100 covers the orthographic projection of the second via 520 on the substrate 100. Since the second via 520 is located in the second insulating layer 500, the first insulating layer 300 and the first conductive layer 200 are located between the second insulating layer 500 and the body portion 413, so the influence of the second via 520 on the body portion 413 Small, even negligible.
  • the first via 310 is disposed close to the driving transistor in the pixel driving circuit relative to the second via 520.
  • the present disclosure includes but is not limited to this.
  • each sub-pixel further includes a fourth via 710.
  • the fourth via holes 710 are arranged on a straight line along the first direction F1, and the distance between two adjacent fourth via holes 710 on the same straight line is approximately the same.
  • the fourth via 710 may be a via 388a.
  • the orthographic projection of the fourth via 710 on the substrate 100 and the orthographic projection of the second via 520 on the substrate 100 overlap.
  • the present disclosure includes but is not limited to this.
  • the front projection of the first via 310 on the substrate 100 is an emission control signal line electrically connected to the driving circuit (Ie, the first light emission control signal line EM1a or the second light emission control signal line EM2a of this row) overlaps the orthographic projection of the substrate 100, and the orthographic projection of the second via 520 on the substrate 100 is electrically connected to the driving circuit.
  • the driving circuit Ie, the first light emission control signal line EM1a or the second light emission control signal line EM2a of this row
  • the orthographic projection of the signal line (ie, the first emission control signal line EM1a or the second emission control signal line EM2a of this row) on the substrate 100 does not overlap, and the orthographic projection of the fourth via 710 on the substrate 100 is electrically connected to the drive circuit
  • the front projection of the light emission control signal line (the first light emission control signal line EM1a or the second light emission control signal line EM2a of this row) on the substrate 100 does not overlap.
  • the orthographic projection of the main body portion 413 on the substrate 100 and the two third vias 530 on the substrate 100 overlap at least partially.
  • the orthographic projection of the main body portion 413 on the substrate 100 overlaps the orthographic projection of the two third vias 530 on the substrate 100.
  • the first via 310 is close to overlap with the orthographic projection of the main body 413 on the substrate 100
  • the two third vias 530 are arranged on one side of the center line LZ1 of the two third vias 530, and the second via 520 is close to the other of the center lines LZ1 of the two third vias 530 that overlap the orthographic projection of the main body portion 413 on the substrate 100 Set on one side.
  • the first via hole 310 and the second via hole 520 in the third color sub-pixel 030 can be arranged closer together.
  • the center line LZ1 is parallel to the first direction F1.
  • the center line LZ1 is a line passing through the centers of the two third via holes 530, which is virtual, not a real line.
  • the cross section of the via hole may be a regular pattern, such as a rectangle or a regular polygon (square, regular pentagon, regular hexagon, etc.). Circle, ellipse, etc.
  • the center of the via may refer to the geometric center of the regular pattern.
  • the cross-section of the via hole may also be an irregular pattern, and the center of the via hole may refer to the equivalent geometric center of the irregular pattern.
  • the main body portion 413 in the third color sub-pixel 030, may be an axially symmetrical figure, and the first via 310 may be located along the first through hole 310 of the main body portion 413.
  • the main body portion 413 in the third color sub-pixel 030 may have a first symmetry axis along the second direction F2, and the first via 310 in the third color sub-pixel 030 is approximately axisymmetric about the first symmetry axis.
  • the shape of the body portion 413 in the third color sub-pixel 030 is approximately a hexagon or an ellipse
  • the long axis of symmetry of the hexagon or the long axis of the ellipse is approximately parallel to the first direction F1
  • the short axis of symmetry of the polygon or the short axis of the ellipse is substantially parallel to the second direction F2
  • the short axis of symmetry of the hexagon or the short axis of the ellipse can be used as the first axis of symmetry.
  • the first via hole 310 in the third color sub-pixel 030 may be arranged approximately axisymmetrically with respect to the first symmetry axis, or the first via hole 310 in the third color sub-pixel 030 may only be arranged with respect to the first symmetry axis.
  • the intersection of a symmetry axis is not approximately axisymmetric about the first symmetry axis.
  • the implementation of the first via 310 in the third color sub-pixel 030 can be designed and determined according to the actual application environment, which is not limited here.
  • the second via 520 in the third color sub-pixel 030, may be located on the symmetry axis of the main body portion 413 along the second direction F2.
  • the second via 520 in the third color sub-pixel 030 is substantially axisymmetrically arranged about the first symmetry axis.
  • the second via 520 in the third color sub-pixel 030 may be arranged approximately axisymmetrically with respect to the first symmetry axis, or the second via 520 in the third color sub-pixel 030 may only be arranged with respect to the first symmetry axis.
  • the intersection of a symmetry axis is not approximately axisymmetric about the first symmetry axis.
  • the implementation of the second via 520 in the third color sub-pixel 030 can be designed and determined according to the actual application environment, which is not limited here.
  • the main body portion 411 and the auxiliary portion 421 are electrically connected to each other, and the auxiliary portion 421
  • the first connection line 221 is electrically connected to each other through the first via 310 and the first connection line 221
  • the first connection line 221 is electrically connected to each other through the second via 520 and the second connection line 621
  • the second connection line 621 is connected to the transistor in the pixel driving circuit.
  • the drain is electrically connected to input the electrical signal generated by the pixel driving circuit to the anode 400, and the cathode 60 is also applied with a corresponding voltage to drive the light-emitting layer 50 to emit light.
  • each first color sub-pixel 010 in each first color sub-pixel 010, the orthographic projection of the main body portion 411 on the substrate 100 and the first via hole The orthographic projections of 310 on the substrate 100 do not overlap. In this way, the main body portion 411 in each first color sub-pixel 010 is not affected by the first via hole 310, so as to avoid unevenness in the main body portion 411 caused by the first via hole, thereby improving the color of the display panel. Partial phenomenon.
  • the orthographic projection of the main body portion 411 on the substrate 100 and the second via 520 at least partially overlap.
  • the orthographic projection of the main body portion 411 on the substrate 100 covers the orthographic projection of the second via 520 on the substrate 100. Since the second via 520 is located in the second insulating layer 500, the first insulating layer 300 and the first conductive layer 200 are located between the second insulating layer 500 and the body portion 411, so the influence of the second via 520 on the body portion 411 Small, even negligible.
  • the first via 310 is disposed farther away from the driving transistor in the pixel driving circuit than the second via 520.
  • the present disclosure includes but is not limited to this.
  • the orthographic projection of the fourth via 710 on the substrate 100 and the orthographic projection of the first via 310 on the substrate 100 overlap.
  • the present disclosure includes but is not limited to this.
  • the front projection of the first via 310 on the substrate 100 is an emission control signal line electrically connected to the driving circuit (Ie, the first light emission control signal line EM1a or the second light emission control signal line EM2a of this row) the orthographic projection of the substrate 100 does not overlap, and the orthographic projection of the second via on the substrate is electrically connected to the driving circuit.
  • the line (ie, the first light emission control signal line EM1a or the second light emission control signal line EM2a of this row) overlaps the orthographic projection of the substrate 100, and the orthographic projection of the fourth via 710 on the substrate 100 is electrically connected to the driving circuit.
  • the orthographic projection of the control signal line ie, the first light-emission control signal line EM1a or the second light-emission control signal line EM2a of this row
  • the present disclosure includes but is not limited to this.
  • the orthographic projection of the main body portion 411 on the substrate 100 and the two third passes The orthographic projection of the hole 530 on the substrate 100 at least partially overlaps.
  • the orthographic projection of the main body portion 411 on the substrate 100 overlaps the orthographic projection of the two third vias 530 on the substrate 100.
  • the first via 310 in the first color sub-pixel 010, is close to the center line of the two third vias 530 whose orthographic projections overlap.
  • One side of LZ2 is provided, and the second via 520 is provided close to the other side of the center line LZ2 of the two third vias 530 overlapped by the orthographic projection.
  • the center line LZ2 is parallel to the first direction F1.
  • the center line LZ2 is a line passing through the centers of the two third via holes 530, which is a virtual line, not a real line.
  • the main body portion 411 in the first color sub-pixel 010, may be an axisymmetric pattern, and the first via 310 is located along the second body portion 411.
  • the direction F2 is on the axis of symmetry.
  • the body portion 411 in the first color sub-pixel 010 may have a second symmetry axis along the second direction F2.
  • the shape of the body portion 411 in the first color sub-pixel 010 is approximately a hexagon or an ellipse
  • the long axis of symmetry of the hexagon or the long axis of the ellipse is approximately parallel to the first direction F1
  • the hexagon If the short axis of symmetry of the ellipse or the short axis of the ellipse is substantially parallel to the second direction F2, the short axis of symmetry of the hexagon or the short axis of the ellipse can be used as the second axis of symmetry.
  • the first via hole 310 in the first color sub-pixel 010 may be arranged approximately axisymmetrically with respect to the second symmetry axis, or the first via hole 310 in the first color sub-pixel 010 may only be arranged with respect to the second symmetry axis.
  • the intersection of the two symmetry axes is not approximately axisymmetric about the second symmetry axis.
  • the implementation of the first via 310 in the first color sub-pixel 010 can be designed and determined according to the actual application environment, which is not limited here.
  • the second via 520 in the first color sub-pixel 010, is located on the symmetry axis of the main body portion 411 along the second direction F2.
  • the second via hole 520 in the first color sub-pixel 010 may be arranged approximately axisymmetrically with respect to the second symmetry axis, or the second via hole 520 in the first color sub-pixel 010 may only be arranged with respect to the second axis of symmetry.
  • the intersection of the two symmetry axes is not approximately axisymmetric about the second symmetry axis.
  • the implementation of the second via 520 in the first color sub-pixel 010 can be designed and determined according to the actual application environment, which is not limited here.
  • each first second color sub-pixel 021 in each first second color sub-pixel 021, the main portion 4121 and the auxiliary portion 4221 are electrically connected to each other,
  • the auxiliary portion 4221 is electrically connected to the first connection line 2221 through the first via hole 310, the first connection line 2221 is electrically connected to each other through the second via hole 520 and the second connection line 6221, and the second connection line 6221 is connected to the pixel driving circuit.
  • the drain of the transistor is electrically connected to input the electrical signal generated by the pixel driving circuit to the anode 400, and the cathode 60 is also applied with a corresponding voltage to drive the light-emitting layer 50 to emit light.
  • each second second color sub-pixel 022 in each second second color sub-pixel 022, the main portion 4122 and the auxiliary portion 4222 are electrically connected to each other,
  • the auxiliary portion 4222 is electrically connected to each other through the first via 310 and the first connection line 2222, the first connection line 2222 is electrically connected to each other through the second via 520 and the second connection line 6222, and the second connection line 6222 is connected to the pixel driving circuit.
  • the drain of the transistor is electrically connected to input the electrical signal generated by the pixel driving circuit to the anode 400, and the cathode 60 is also applied with a corresponding voltage to drive the light-emitting layer 50 to emit light.
  • the orthographic projection of the main body portion on the substrate and the orthographic projection of the first via on the substrate do not overlap.
  • the orthographic projection of the main body portion 4121 on the substrate 100 and the first via 310 on the front of the substrate 100 do not overlap.
  • the main body portion 4121 in each first second color sub-pixel 021 is not affected by the first via hole 310, so as to avoid unevenness of the main body portion 4121 caused by the first via hole 310, thereby improving The color cast phenomenon of the display panel.
  • the orthographic projection of the main body portion 4122 on the substrate 100 and the first via 310 on the front of the substrate 100 do not overlap.
  • the main body portion 4122 in each second second color sub-pixel 022 is not affected by the first via hole 310, so as to avoid unevenness of the main body portion 4122 caused by the first via hole 310, thereby improving The color cast phenomenon of the display panel.
  • the second color sub-pixel pair 020 includes a first second color sub-pixel 021 and a second second color sub-pixel 022; wherein
  • the first via 310 of the first second-color sub-pixel 021 is located on the side of the first second-color sub-pixel 021 away from the third-color sub-pixel 030.
  • the first via 310 of the second second color sub-pixel 022 is located on the side of the second second color sub-pixel 022 away from the third color sub-pixel 030.
  • the first color sub-pixel 010 and the first second color sub-pixel 021 in the same repeating unit 001 are both the nearest third-color sub-pixel 030, and the first via 310 of the first second-color sub-pixel 021 is located in the first In the gap between the one-color sub-pixel 010 and the third-color sub-pixel 030.
  • the pixels 022 are the nearest neighbors of the third color sub-pixel 030, and the first via 310 of the second second-color sub-pixel 022 is located in the gap between the first-color sub-pixel 010 and the third-color sub-pixel 030 .
  • the first color sub-pixel 010 and the first second color sub-pixel 021 in the same repeating unit 001 are both the nearest third color sub-pixel 030, and the second via 520 of the first second-color sub-pixel 021 is located in the first In the gap between the color sub-pixel 010 and the third color sub-pixel 030.
  • the nearest third color sub-pixel 030 for the first color subpixel 010 and the second second color subpixel 022 in the same repeating unit 001, and for the first color subpixel 010 and the second second color subpixel in the same repeating unit 001 022 is the nearest third color sub-pixel 030, and the second via 520 of the second second-color sub-pixel 022 is located in the gap between the first-color sub-pixel 010 and the third-color sub-pixel 030.
  • the first vias 310 in the sub-pixels of the same color are located on the same side of the sub-pixels of the color.
  • the first via 310 of the first color sub-pixel 010 is located on the same side of the first color sub-pixel 010.
  • the first via 310 of the second color sub-pixels 021 and 022 is located on the same side of the second color sub-pixels 021 and 022.
  • the first via 310 of the third color sub-pixel 030 is located on the same side of the third color sub-pixel 030.
  • the first via 310 and the second via 520 of the first second color sub-pixel 021 are close to the first One side of the one-color sub-pixel 010 is disposed, and the first via 310 and the second via 520 of the second second-color sub-pixel 022 are disposed close to the other side of the first-color sub-pixel 010. That is, the first via 310 of the first second color sub-pixel 021 and the first via 310 of the second second color sub-pixel 022 are respectively located on both sides of the first color sub-pixel 010.
  • the second via hole 520 of the first second color sub-pixel 021 and the second via hole 520 of the second second color sub-pixel 022 are located on both sides of the first color sub-pixel 010, respectively.
  • the first via 310 and the second via 520 of the first second color sub-pixel 021 may be disposed in the main part of the first color sub-pixel 010 in the repeating unit 001 411 and the main part 413 in the third color sub-pixel 030 adjacent to the left side of the main part 411.
  • the first via 310 and the second via 520 of the second second color sub-pixel 022 may be disposed in the main portion 411 and the first via 520 of the first color sub-pixel 010 in the repeating unit 001. Between the main part 413 in the third color sub-pixel 030 adjacent to the right side of the main part 411.
  • the second via 520 may be located away from the first via 310.
  • the embodiments of the present disclosure include but are not limited to this.
  • the first via 310 and the second via 520 may be arranged along The second direction F2 is arranged on the same straight line.
  • the embodiments of the present disclosure include but are not limited to this.
  • the first via 310 is far from the second via 520 in the pixel driving circuit.
  • Drive transistor settings in an embodiment of the present disclosure, as shown in FIG. 3b, the embodiments of the present disclosure include but are not limited to this.
  • the orthographic projection of the fourth via 710 on the substrate 100 and the first The via 310 overlaps the orthographic projection of the substrate 100.
  • the embodiments of the present disclosure include but are not limited to this.
  • the first via 310 is in the orthographic projection and driving circuit of the substrate 100
  • the electrical connection of the light emission control signal line (ie the first light emission control signal line EM1a or the second light emission control signal line EM2a of this row) on the substrate 100 does not overlap in the orthographic projection, and the second via 520 is on the orthographic projection of the substrate 100
  • the light-emission control signal line (ie, the first light-emission control signal line EM1a or the second light-emission control signal line EM2a of this row) electrically connected to the drive circuit overlaps the orthographic projection of the substrate 100
  • the fourth via 710 is on the substrate 100
  • the second via 520 may be located The first via 310 is away from the side of the main body 4122.
  • the embodiments of the present disclosure include but are not limited to this.
  • the first via 310 and The second via holes 520 are arranged on the same straight line along the second direction F2.
  • the embodiments of the present disclosure include but are not limited to this.
  • the first via 310 is farther away from the pixel driving circuit than the second via 520.
  • Drive transistor settings are not limited to this.
  • the orthographic projection of the fourth via 710 on the substrate 100 and the first The via 310 overlaps the orthographic projection of the substrate 100.
  • the embodiments of the present disclosure include but are not limited to this.
  • the first via 310 is in the orthographic projection and driving circuit of the substrate 100
  • the electrical connection of the light emission control signal line (ie the first light emission control signal line EM1a or the second light emission control signal line EM2a of this row) on the substrate 100 does not overlap in the orthographic projection, and the second via 520 is on the orthographic projection of the substrate 100
  • the light-emission control signal line (ie, the first light-emission control signal line EM1a or the second light-emission control signal line EM2a of this row) electrically connected to the drive circuit overlaps the orthographic projection of the substrate 100
  • the fourth via 710 is on the substrate 100
  • the first second color subpixel 021 in the second color subpixel pair 020 in the same repeating unit 001, the first second color subpixel 021 in the second color subpixel pair 020
  • the first via 310, the first via 310 of the first color sub-pixel 010, and the first via 310 of the second second color sub-pixel 022 are sequentially arranged on the same first sub-fold line Z1 along the first direction F1.
  • the first via 310 of the first second color subpixel 021 in the second color subpixel pair 020, and the first via 310 of the first color subpixel 010 One via 310 and the first via 310 of the second second color sub-pixel 022 can be arranged in sequence along the first sub-fold line Z1 along the direction indicated by the arrow of the first direction F1. Therefore, the design difficulty of the mask used in the preparation of the three first via holes 310 can be reduced.
  • the first via 310 of the first-color sub-pixel 010 and the first via 310 of the third-color sub-pixel 030 are arranged along the third direction on the same second sub-fold line Z2 Up; where the third direction crosses the first direction and is not perpendicular.
  • the fold line may include: a first sub-fold line Z1 and a second sub-fold line Z2; two adjacent sub-fold lines in different columns In the repeating unit 001, the first via 310 of the third color sub-pixel 030 in the first repeating unit and the first via 310 of the first second color sub-pixel 021 in the second repeating unit, the first The first via 310 of the color sub-pixel 010 and the first via 310 of the second second-color sub-pixel 022 are sequentially arranged on the fold line.
  • the first via 310 of the third color sub-pixel 030 in the first repeating unit and the first second in the second repeating unit The first via 310 of the color sub-pixel 021, the first via 310 of the first color sub-pixel 010, and the first via 310 of the second second color sub-pixel 022 are repeatedly arranged. This can also reduce the design difficulty of the mask used in the preparation of the first vias 310.
  • the first via 310 and the first color subpixel 010 of the third color subpixel 030 in the same repeating unit 001 are arranged on the same straight line along the second direction F2. In this way, the design difficulty of the mask used in the preparation of the three first via holes 310 can also be reduced.
  • the first second color in one repeating unit 001 in two adjacent repeating units 001 in different columns, the first second color in one repeating unit 001 are arranged on the same straight line along the second direction F2. This can also reduce the design difficulty of the mask used in the preparation of the first vias 310.
  • the second via 520 of the third color sub-pixel 030 in the odd-numbered column repeating unit group and the first in the even-numbered column repeating unit group The first via 310 of the color sub-pixel 010, the first via 310 of the first second color sub-pixel 021, and the first via 310 of the second second color sub-pixel 022 are arranged in the same direction along the first direction F1. In a straight line.
  • the second via 520 of the third color sub-pixel 030 in the first and third column repeating unit groups and the first via 310 of the first color sub-pixel 010 in the second column repeating unit group The first via 310 of the first second color sub-pixel 021 and the first via 310 of the second second color sub-pixel 022 are arranged on the same straight line along the first direction F1.
  • the first via 310 and the second via 310 of the first color sub-pixel 010 in the same row of repeating unit 001 are arranged on the same straight line along the first direction F1. This can also reduce the design difficulty of the mask used when preparing the three first via holes 310 in the display panel.
  • the first via 310 of the third color sub-pixel 030 in the same row of repeating unit 001 is along the first The direction F1 is arranged on the same straight line. This can also reduce the design difficulty of the mask used when preparing the three first via holes 310 in the display panel.
  • the first via 310 and the second via 310 of the first color sub-pixel 010 in the same row of repeating unit 001 are arranged on the same straight line along the first direction F1. This can also reduce the design difficulty of the mask used when preparing the three first via holes 310 in the display panel.
  • the first via 310 of the third color sub-pixel 030 in the repeating unit 001 in the same row runs along the first The direction F1 is arranged on the same straight line. This can also reduce the design difficulty of the mask used when preparing the three first via holes 310 in the display panel.
  • the distance between two adjacent first via holes 310 along the first direction F1 may be approximately the same.
  • the embodiments of the present disclosure include but are not limited to this.
  • the spacing between two adjacent first via holes 310 in the second direction F2 may be approximately the same.
  • the embodiments of the present disclosure include but are not limited to this.
  • the spacing between two adjacent second via holes 520 in the first direction F1 may be approximately the same.
  • the embodiments of the present disclosure include but are not limited to this.
  • the spacing between two adjacent second via holes 520 in the second direction F2 may be substantially the same.
  • the embodiments of the present disclosure include but are not limited to this.
  • the embodiments of the present disclosure also provide other electroluminescent display panels, as shown in FIGS. 9a to 15, which are modified for some implementations in the above-mentioned embodiments.
  • FIGS. 9a to 15 are modified for some implementations in the above-mentioned embodiments.
  • the following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities are not repeated here.
  • each repeating unit 001 includes a plurality of sub-pixels, and each sub-pixel may include: A conductive layer 200, a first insulating layer 300 located above the first conductive layer 200, and an anode 400 located on the first insulating layer 300.
  • the first insulating layer 300 includes a first via 310 that exposes a part of the first conductive layer 200.
  • the anode 400 includes a main body part 410 and an auxiliary part 420 electrically connected to each other, and the auxiliary part 420 is electrically connected to the first conductive layer 200 through the first via 310.
  • the orthographic projection of the main body portion 410 on the substrate 100 and the orthographic projection of the first via 310 on the substrate 100 do not overlap.
  • the size of the body portion 410 in the first direction F1 is greater than the size in the second direction F2, and in at least one sub-pixel, the first via 310 and the body portion 410 are arranged in the second direction F2. Wherein, the first direction F1 and the second direction F2 are different.
  • the anode includes a main part and an auxiliary part electrically connected to each other, and the auxiliary part is electrically connected to the first conductive layer through the first via hole, so that the anode passes through the first conductive layer. It is electrically connected to the pixel drive circuit.
  • the orthographic projection of the main body portion on the substrate and the orthographic projection of the first via on the substrate do not overlap, the first via in the sub-pixel can be avoided to make the sub-pixel
  • the body part of the anode is not affected by the depth of the first via hole, so as to prevent the body part of the anode from being recessed, so as to avoid the unevenness of the anode caused by the first via hole, thereby improving the color shift of the display panel.
  • the first conductive layer 200 may include: a first power line 210 and a first connection line 220 that are spaced apart from each other. And data line 230.
  • the auxiliary portion 420 is electrically connected to the first connection line 220 through the first via 310.
  • the first connection line 220 is electrically connected to the drain of the transistor in the pixel driving circuit to realize signal transmission.
  • the first conductive layer 200 may further include: respectively connecting with the first power line 210 and the first The wire 220 and the data wire 230 are provided with bridge wires 240 at intervals.
  • the bridge line is configured to electrically connect two of the gate, source, and drain of some transistors in the pixel driving circuit.
  • the setting method of the bridging line can be basically the same as the setting method in the related art, which will not be repeated here.
  • the first conductive layer 200 may be the aforementioned source and drain metal layer 0340, for example.
  • the first power line 210 may be, for example, the aforementioned first power signal line VDD1
  • the data line 230 may be, for example, the aforementioned data line Vd
  • the first connecting line 220 may be, for example, the aforementioned connecting portion 343a
  • the bridge line 240 may be, for example, the aforementioned At least one of the connecting portions 341a, 342a.
  • this embodiment does not provide the auxiliary metal layer 0350, and the corresponding relationship between the via hole, the insulating layer and the remaining film layers can be referred to the above-mentioned active semiconductor layer 0310, gate conductive layer 0320, reference The implementation of the conductive layer 0330 will not be repeated here.
  • each sub-pixel may further include a pixel defining layer 80 on the side of the anode 400 away from the substrate 100, and a light-emitting layer 50 on the side of the anode 400 away from the substrate 100. , And a cathode 60 on the side of the anode away from the light-emitting layer 50.
  • the pixel defining layer 80 has an opening, and the opening exposes at least a part of the area of the body portion 410 of the anode 400.
  • the light emitting layer 50 is located in the opening and is in contact with the area of the body portion 410 exposed by the opening, and the light emitting layer 50 in the opening is located
  • the area is used for light emission, so that the effective light-emitting area 90 can be defined by the opening. It should be noted that, for the implementation of the effective light-emitting area 90 of each sub-pixel described above, reference may be made to the foregoing embodiment, and will not be repeated here.
  • the first power line may be configured as a power line that transmits a driving voltage.
  • the data line may be configured as a signal line that transmits data voltage.
  • the first power line 210 and the data line 230 are arranged along the first direction F1 and extend along the second direction F2; and the first direction F1 and the second direction F1 The direction F2 is different.
  • the first direction F1 is perpendicular to the second direction F2.
  • the first direction F1 may be the row direction of the display panel, that is, the direction in which the gate lines extend
  • the second direction F2 may be the column direction of the display panel, that is, the direction in which the data lines extend.
  • the embodiments of the present disclosure include but are not limited to this.
  • each of the multiple repeating units 001 may include: one first color sub-pixel 010 and one first color sub-pixel 010 arranged along the second direction F2.
  • the pair of second color sub-pixels 020 may include two second-color sub-pixels 021 and 022 arranged along the first direction F1.
  • the first color sub-pixel 010 is configured to emit light of the first color
  • the second color sub-pixels 021 and 022 are configured to emit light of the second color
  • the third color sub-pixel is configured to emit light of the third color.
  • the first color, the second color, and the third color can be selected from red, green, and blue.
  • the first color is red
  • the second color is green
  • the third color is blue.
  • the repeating unit 001 is an arrangement structure of red, green and blue sub-pixels.
  • the embodiments of the present disclosure include but are not limited to this.
  • the aforementioned first color, second color, and third color may also be other colors. It should be noted that the arrangement of the sub-pixels described above can be referred to the above-mentioned embodiments, and will not be repeated here.
  • a plurality of repeating units 001 are arranged along the second direction F2 to form a repeating unit group, and the repeating unit groups are arranged along the first direction F1 and are adjacent to each other.
  • the repeating units 001 in the two repeating unit groups are arranged in a staggered manner.
  • the repeating unit 001 in two adjacent repeating unit groups differs by 1/2 the size of the repeating unit 001.
  • the size of one repeating unit 001 described above may be the distance between the centers of the same color sub-pixels in two adjacent repeating units 001 in the second direction F2.
  • the size of one repeating unit 001 described above may be: the distance between the centers of the first color sub-pixels 010 in two adjacent repeating units 001 in the second direction F2.
  • the size of the body portion 411 of the first color sub-pixel 010 in the second direction F2 is smaller than that of the body portion 413 of the third color sub-pixel 030 The size in the second direction F2. Also, the size of the body portion 411 of the first color sub-pixel 010 in the first direction F1 is larger than the size of the body portion 413 of the third color sub-pixel 030 in the first direction F1.
  • the size of the body portion 413 of the third color sub-pixel 030 in the second direction F2 is smaller than the size of the body portion 413 of the third color sub-pixel 030 in the first direction F1, and the size of the first color sub-pixel 010
  • the size of the body portion 411 in the second direction F2 is smaller than the size of the body portion 411 of the first color sub-pixel 010 in the first direction F1.
  • the embodiments of the present disclosure include but are not limited thereto, and the relationship between the above-mentioned dimensions may also be in other forms.
  • an adjacent first power line 210 and a data line 230 are used as a signal line group.
  • the orthographic projection of the main body 413 on the substrate 100 covers the orthographic projection of the two signal line groups on the substrate 100.
  • the two signal line groups overlapping with the orthographic projection of the main body portion 413 on the substrate 100 are arranged on both sides of the center of the main body portion 413 in parallel.
  • the orthographic projection of the main body portion 413 on the substrate 100 covers the orthographic projection of the two first power lines 210 and the two data lines 230 on the substrate 100.
  • one first power line 210 and one data line 230 are arranged in parallel on one side of the main body portion 413, and another first power line 210 and another data line 230 are arranged in parallel on the other side of the main body portion 413.
  • the orthographic projection of the main body portion 413 on the substrate 100 and the two bridge lines 240 on the substrate 100 The orthographic projections of at least partially overlap.
  • the orthographic projection of the main body part 413 on the substrate 100 overlaps the orthographic projection of one bridge line 240 on the substrate 100, and the orthographic projection of the main body part 413 on the substrate 100 and the orthographic projection of the other bridge line 240 on the substrate 100 The edges overlap.
  • the orthographic projection of the main body portion 411 on the substrate 100 covers the orthographic projection of the two signal line groups on the substrate 100.
  • two signal line groups overlapping with the orthographic projection of the main body portion 411 on the substrate 100 are arranged on both sides of the main body portion 411 in parallel.
  • the orthographic projection of the main body portion 411 on the substrate 100 covers the orthographic projection of the two first power lines 210 and the two data lines 230 on the substrate 100.
  • one first power line 210 and one data line 230 are arranged in parallel on one side of the main body portion 411, and another first power line 210 and another data line 230 are arranged in parallel on the other side of the main body portion 411.
  • the orthographic projection of the main body portion 411 on the substrate 100 and a bridge line 240 on the substrate 100 overlap.
  • the orthographic projection of the main body portion 411 on the substrate 100 overlaps an edge of the orthographic projection of a bridge line 240 on the substrate 100.
  • the orthographic projection of the main part on the substrate 100 overlaps the orthographic projection of a signal line group on the substrate 100.
  • the signal line group that overlaps the orthographic projection of the main parts of the two second-color sub-pixels on the substrate 100 is adjacently arranged.
  • the second-color sub-pixel pair 020 may include a first second-color sub-pixel 021 and a second second-color sub-pixel 022.
  • the orthographic projection of the main body portion 4121 on the substrate 100 overlaps the orthographic projection of a first power line 210 and a data line 220 on the substrate 100.
  • the orthographic projection of the main body portion 4122 on the substrate 100 overlaps the orthographic projection of the other first power line 210 and the other data line 220 on the substrate 100.
  • the orthographic projection of the main body portion 4121 of the first second color sub-pixel 021 on the substrate 100 may also be the orthographic projection of a bridge line 240 on the substrate 100.
  • the edges overlap.
  • the orthographic projection of the main body portion 4122 of the second second color sub-pixel 022 on the substrate 100 may also be aligned with the two bridge lines 240 on the front of the substrate 100. The edges of the projection overlap.
  • the main portion 413 and the auxiliary portion 423 are electrically connected to each other, and the auxiliary portion 423
  • the first via 310 and the first connection line 223 are electrically connected to each other, and the first connection line 223 is electrically connected to the drain of the transistor in the pixel driving circuit 20 to input the electrical signal generated by the pixel driving circuit 20 to the anode 400, and A corresponding voltage is also applied to the cathode 60 to drive the light-emitting layer 50 to emit light.
  • each third color sub-pixel 030 in each third color sub-pixel 030, the orthographic projection of the main body portion 413 on the substrate 100 and the first via hole The orthographic projections of 310 on the substrate 100 do not overlap. In this way, the main body portion 413 in each third color sub-pixel 030 is not affected by the first via hole 310, so as to avoid unevenness of the main body portion 413 caused by the first via hole 310, thereby improving the display panel's performance. Color cast phenomenon.
  • the first insulating layer may be configured as a flat layer, so that the body portion on the first insulating layer may have a higher flatness.
  • the main body portion 413 may be an axisymmetric pattern, and the first via 310 It may be located on the axis of symmetry of the body part 413 along the second direction F2.
  • the body portion 413 in the third color sub-pixel 030 may have a first symmetry axis along the second direction F2.
  • the shape of the body portion 413 in the third color sub-pixel 030 is approximately a hexagon or an ellipse
  • the long axis of symmetry of the hexagon or the long axis of the ellipse is approximately parallel to the first direction F1
  • the short axis of symmetry or the short axis of the ellipse is approximately parallel to the second direction F2
  • the short axis of symmetry of the hexagon or the short axis of the ellipse can be used as the first axis of symmetry.
  • the first via hole 310 in the third color sub-pixel 030 may be arranged approximately axisymmetrically about the first symmetry axis.
  • first via hole 310 in the third color sub-pixel 030 only intersects the first symmetry axis, and is not arranged approximately axisymmetrically about the first symmetry axis.
  • the implementation of the first via 310 in the third color sub-pixel 030 can be designed and determined according to the actual application environment, which is not limited here.
  • the main body part 411 and the auxiliary part 421 are electrically connected to each other, and the auxiliary part 421
  • the first via 310 and the first connection line 221 are electrically connected to each other, and the first connection line 221 is electrically connected to the drain of the transistor in the pixel driving circuit 20 to input the electrical signal generated by the pixel driving circuit 20 to the anode 400, and A corresponding voltage is also applied to the cathode 60 to drive the light-emitting layer 50 to emit light.
  • each first color sub-pixel 010 in each first color sub-pixel 010, the orthographic projection of the main body portion 411 on the substrate 100 and the first via hole The orthographic projections of 310 on the substrate 100 do not overlap. In this way, the main body portion 411 in each first color sub-pixel 010 is not affected by the first via hole 310, so as to avoid unevenness in the main body portion 411 caused by the first via hole, thereby improving the color of the display panel. Partial phenomenon.
  • the main body portion 411 in the first color sub-pixel 010, may be an axisymmetric pattern, and the first via 310 may be located in the main body.
  • the portion 411 is on the axis of symmetry along the second direction F2.
  • the body portion 411 in the first color sub-pixel 010 may have a second symmetry axis along the second direction F2.
  • the shape of the body portion 411 in the first color sub-pixel 010 is approximately a hexagon or an ellipse
  • the long axis of symmetry of the hexagon or the long axis of the ellipse is approximately parallel to the first direction F1
  • the hexagon If the short axis of symmetry of the ellipse or the short axis of the ellipse is substantially parallel to the second direction F2, the short axis of symmetry of the hexagon or the short axis of the ellipse can be used as the second axis of symmetry.
  • the first via hole 310 in the first color sub-pixel 010 may be arranged approximately axisymmetrically about the second symmetry axis.
  • first via hole 310 in the first color sub-pixel 010 only intersects the second symmetry axis, and is not arranged approximately axisymmetrically about the second symmetry axis.
  • the implementation of the first via 310 in the first color sub-pixel 010 can be designed and determined according to the actual application environment, which is not limited here.
  • the main portion 4121 and the auxiliary portion 4221 are mutually
  • the auxiliary part 4221 is electrically connected to the first connection line 2221 through the first via 310
  • the first connection line 2221 is electrically connected to the drain of the transistor in the pixel driving circuit 20 to connect the electricity generated by the pixel driving circuit 20.
  • a signal is input to the anode 400, and a corresponding voltage is also applied to the cathode 60 to drive the light-emitting layer 50 to emit light.
  • the main portion 4122 and the auxiliary portion 4222 are mutually
  • the auxiliary portion 4222 is electrically connected to the first connection line 2222 through the first via 310, and the first connection line 2222 is electrically connected to the drain of the transistor in the pixel driving circuit 20 to connect the electricity generated by the pixel driving circuit 20.
  • a signal is input to the anode 400, and a corresponding voltage is also applied to the cathode 60 to drive the light-emitting layer 50 to emit light.
  • the orthographic projection of the main body part on the substrate and the orthographic projection of the first via on the substrate do not overlap .
  • the orthographic projection of the main body portion 4121 on the substrate 100 and the first via 310 on the substrate The orthographic projection of 100 does not overlap.
  • the main body portion 4121 in each first second color sub-pixel 021 is not affected by the first via hole 310, so as to avoid unevenness of the main body portion 4121 caused by the first via hole 310, thereby improving The color cast phenomenon of the display panel.
  • the orthographic projection of the main body part 4122 on the substrate 100 and the first via 310 on the substrate does not overlap.
  • the main body portion 4122 in each second second color sub-pixel 022 is not affected by the first via hole 310, so as to avoid unevenness of the main body portion 4122 caused by the first via hole 310, thereby improving The color cast phenomenon of the display panel.
  • the first via 310 of the first second color sub-pixel 021 is close to the first color sub-pixel 010 One side is disposed, and the first via 310 of the second second color sub-pixel 022 is disposed close to the other side of the first color sub-pixel 010. That is, the first via 310 of the first second color sub-pixel 021 and the first via 310 of the second second color sub-pixel 022 are respectively located on both sides of the first color sub-pixel 010.
  • the first via 310 of the first second color sub-pixel 021 may be disposed in the main body portion 411 of the first color sub-pixel 010 in the repeating unit 001 and the main body portion Between the main part 413 in the third color sub-pixel 030 adjacent to the left of 411.
  • the first via 310 of the second second color sub-pixel 022 may be disposed in the main body portion 411 of the first color sub-pixel 010 in the repeating unit 001 and right to the main body portion 411. Between the body portions 413 in the third color sub-pixels 030 adjacent to the side.
  • the first via 310 and the second color sub-pixel pair of the first color sub-pixel 010 are arranged on the same straight line along the first direction F1.
  • the first via 310 of the first color sub-pixel 010 and the first second color sub-pixel 021 of the second color sub-pixel pair 020 can arrange the three first vias 310 on the same straight line along the first direction F1, so that the preparation of the three first vias can be reduced. It is difficult to design a mask used in a via 310.
  • the first via 310 and the first color subpixel 010 of the third color subpixel 030 in the same repeating unit 001 are arranged on the same straight line along the second direction F2. In this way, the design difficulty of the mask used in the preparation of the three first via holes 310 can also be reduced.
  • the first via 310 of the third color sub-pixel 030 and the first color sub-pixel 010 The first vias 310 are arranged on the same straight line along the second direction F2.
  • the first vias 310 of the first second color sub-pixel 021 in each second-color sub-pixel pair 020 are arranged on the same straight line along the second direction F2.
  • the first vias 310 of the second second color sub-pixel 022 in each second-color sub-pixel pair 020 are arranged on the same straight line along the second direction F2. This can also reduce the design difficulty of the mask used in the preparation of the first vias 310.
  • the first via 310 and the second via 310 of the first color sub-pixel 010 in the same row of repeating unit 001 are arranged on the same straight line along the first direction F1. This can also reduce the design difficulty of the mask used when preparing the three first via holes 310 in the display panel.
  • the first via 310 of the third color sub-pixel 030 in the same row of repeating unit 001 is along the first The direction F1 is arranged on the same straight line. This can also reduce the design difficulty of the mask used when preparing the three first via holes 310 in the display panel.
  • the first via 310 and the second via 310 of the first color sub-pixel 010 in the same row of repeating unit 001 The first via 310 of the first second color sub-pixel 021 and the first via 310 of the second second color sub-pixel 022 in the color sub-pixel pair 020 are arranged on the same straight line along the first direction F1. This can also reduce the design difficulty of the mask used when preparing the three first via holes 310 in the display panel.
  • the first via 310 of the third color sub-pixel 030 in the same row of repeating unit 001 is along the first The direction F1 is arranged on the same straight line. This can also reduce the design difficulty of the mask used when preparing the three first via holes 310 in the display panel.
  • the embodiments of the present disclosure also provide a display device, including the above-mentioned electroluminescent display panel provided by the embodiments of the present disclosure.
  • the principle of the display device to solve the problem is similar to that of the aforementioned electroluminescent display panel. Therefore, the implementation of the display device can refer to the implementation of the aforementioned electroluminescent display panel, and the repetition is not repeated here.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • the other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the anode includes a main body part and an auxiliary part electrically connected to each other, and the auxiliary part is electrically connected to the first conductive layer through the first via hole, so that the anode passes through the first conductive layer.
  • a conductive layer and the pixel driving circuit are electrically connected to each other.
  • the orthographic projection of the main body portion on the substrate and the orthographic projection of the first via on the substrate do not overlap, the first via in the sub-pixel can be avoided to make the sub-pixel
  • the body part of the anode is not affected by the depth of the first via hole, so as to prevent the body part of the anode from being recessed, so as to avoid the unevenness of the anode caused by the first via hole, thereby improving the color shift of the display panel.

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Abstract

本公开公开了电致发光显示面板及显示装置，其中，电致发光显示面板包括：多个重复单元，各重复单元包括多个子像素，各子像素包括：第一导电层，位于基板上方；第一绝缘层，位于第一导电层上方，并且包括第一过孔，第一过孔暴露第一导电层的一部分；阳极，位于第一绝缘层上，并且包括相互电连接的主体部分和辅助部分；辅助部分通过第一过孔与第一导电层电连接；至少一个子像素中，主体部分在基板的正投影与第一过孔在基板的正投影不交叠。

Description

电致发光显示面板及显示装置 技术领域
本公开实施例涉及显示技术领域，特别涉及电致发光显示面板及显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)显示面板因其自发光、广视角、高对比度、低功耗、高反应速度等优点，已经越来越多地被应用于各种电子设备中。随着人们对于OLED显示面板的要求的提高，为了实现显示面板中的高分辨率设计，OLED显示面板通常会采用SPR像素排列，即像素借用的方式。
发明内容
本公开实施例提供了电致发光显示面板，包括：
多个重复单元，各所述重复单元包括多个子像素，各所述子像素包括：
第一导电层，位于基板上方；
第一绝缘层，位于所述第一导电层上方，并且包括第一过孔，所述第一过孔暴露所述第一导电层的一部分；
阳极，位于所述第一绝缘层上，并且包括相互电连接的主体部分和辅助部分；所述辅助部分通过所述第一过孔与所述第一导电层电连接；
至少一个所述子像素中，所述主体部分在所述基板的正投影与所述第一过孔在所述基板的正投影不交叠；
至少一个所述子像素中，所述主体部分在第一方向的尺寸大于在第二方向的尺寸，且至少一个所述子像素中，所述第一过孔与所述主体部分在所述第二方向上排布；其中，所述第一方向与所述第二方向不同。
可选地，在本公开实施例中，所述第一导电层包括：相互间隔设置的第 一电源线和第一连接线；
各所述子像素中，所述辅助部分通过所述第一过孔与所述第一连接线电连接。
可选地，在本公开实施例中，所述第一电源线包括：沿所述第一方向排列且沿所述第二方向延伸的多个子电源线，以及电连接各个所述子电源线的导通线。
可选地，在本公开实施例中，所述子电源线与所述导通线大致形成网格结构，每个网格内部设置有一个所述第一连接线，且所述第一连接线与所述子电源线和所述导通线之间均有间隔。
可选地，在本公开实施例中，所述多个重复单元中的至少一个重复单元包括：沿所述第二方向排列的一个第一颜色子像素、一个第二颜色子像素对以及一个第三颜色子像素；其中，所述第二颜色子像素对包括沿所述第一方向排列的两个第二颜色子像素；
所述多个重复单元沿所述第二方向排列形成重复单元组，所述重复单元组沿所述第一方向排列，且相邻两个所述重复单元组中的重复单元错位排列。
可选地，在本公开实施例中，各所述子像素还包括：位于第一导电层面向所述基板一侧的像素驱动电路；其中，各所述子像素中像素驱动电路阵列分布。
可选地，在本公开实施例中，第一颜色子像素的主体部分的延伸方向与第一颜色子像素的像素驱动电路所在区域的长度方向之间具有第一夹角；其中，所述第一夹角在45度至165度之间；
第三颜色子像素的主体部分的延伸方向与第一颜色子像素的像素驱动电路所在区域的长度方向之间具有第二夹角；其中，所述第二夹角在45度至165度之间；
第二颜色子像素对的延伸方向与第二颜色子像素对的像素驱动电路所在区域的长度方向之间具有第三夹角；其中，所述第三夹角在45度至165度之间。
可选地，在本公开实施例中，各所述像素驱动电路中的各层图案所在区域在所述第二方向上的尺寸大于在第一方向上的尺寸。
可选地，在本公开实施例中，两个相邻的重复单元组中的一个第二颜色子像素对在另一个重复单元组中的相邻的第一颜色子像素和第三颜色子像素在所述第二方向上的最大跨度之间。
可选地，在本公开实施例中，所述第一颜色子像素的主体部分在所述第二方向上的尺寸小于所述第三颜色子像素的主体部分在所述第二方向上的尺寸；
所述第一颜色子像素的主体部分在所述第一方向上的尺寸大于所述第三颜色子像素的主体部分在所述第一方向上的尺寸。
可选地，在本公开实施例中，各所述第三颜色子像素中，所述主体部分在所述基板的正投影与所述第一过孔在所述基板的正投影不交叠。
可选地，在本公开实施例中，所述第三颜色子像素中，所述主体部分为轴对称图形，且所述第一过孔位于所述主体部分沿所述第二方向的对称轴上。
可选地，在本公开实施例中，所述第三颜色子像素中，所述主体部分在所述基板的正投影与所述像素驱动电路中的驱动晶体管不交叠，所述主体部分在所述基板的正投影与所述像素驱动电路相邻的下一行像素驱动电路电连接的复位控制信号线和复位电源信号线在所述基板的正投影交叠，所述主体部分在所述基板的正投影与两条数据线在所述基板的正投影交叠，所述主体部分在所述基板的正投影与两条第二电源线在所述基板的正投影交叠。
可选地，在本公开实施例中，各所述第一颜色子像素中，所述主体部分在所述基板的正投影与所述第一过孔在所述基板的正投影不交叠。
可选地，在本公开实施例中，所述第一颜色子像素中，所述主体部分为轴对称图形，且所述第一过孔位于所述主体部分沿所述第二方向的对称轴上。
可选地，在本公开实施例中，所述第一颜色子像素中，所述主体部分在所述基板的正投影与所述像素驱动电路中的驱动晶体管交叠，所述主体部分在所述基板的正投影与所述像素驱动电路电连接的发光控制信号线在所述基 板的正投影交叠，所述主体部分在所述基板的正投影与两条数据线在所述基板的正投影交叠，所述主体部分在所述基板的正投影与两条第二电源线在所述基板的正投影交叠。
可选地，在本公开实施例中，各所述第二颜色子像素中，所述主体部分在所述基板的正投影与所述第一过孔在所述基板的正投影不交叠。
可选地，在本公开实施例中，所述第二颜色子像素对包括第一个第二颜色子像素和第二个第二颜色子像素；同一所述重复单元中，所述第一个第二颜色子像素的第一过孔位于所述第一个第二颜色子像素背离所述第三颜色子像素一侧；
同一所述重复单元中，所述第二个第二颜色子像素的第一过孔位于所述第二个第二颜色子像素背离所述第三颜色子像素一侧。
可选地，在本公开实施例中，针对同一重复单元中的第一颜色子像素和第一个第二颜色子像素，以及针对与所述同一重复单元中的第一颜色子像素和第一个第二颜色子像素均最近邻的第三颜色子像素，所述第一个第二颜色子像素的第一过孔位于所述第一颜色子像素与所述第三颜色子像素之间的间隙中；
针对同一重复单元中的第一颜色子像素和第二个第二颜色子像素，以及针对与所述同一重复单元中的第一颜色子像素和第二个第二颜色子像素均最近邻的第三颜色子像素，所述第二个第二颜色子像素的第一过孔位于所述第一颜色子像素与所述第三颜色子像素之间的间隙中。
可选地，在本公开实施例中，所述第一个第二颜色子像素中，所述主体部分在所述基板的正投影与所述像素驱动电路中的驱动晶体管无交叠，所述主体部分在所述基板的正投影与所述像素驱动电路相邻的下一行像素驱动电路电连接的复位控制信号线和扫描信号线在所述基板的正投影交叠；
所述第二个第二颜色子像素中，所述主体部分在所述基板的正投影与所述像素驱动电路中的驱动晶体管无交叠，所述主体部分在所述基板的正投影与所述像素驱动电路相邻的下一行像素驱动电路电连接的复位控制信号线和 扫描信号线在所述基板的正投影交叠。
可选地，在本公开实施例中，所述第三颜色子像素中的像素驱动电路、所述第一个第二颜色子像素中的像素驱动电路、所述第一颜色子像素中的像素驱动电路以及所述第二个第二颜色子像素中的像素驱动电路沿第一方向依次排布。
可选地，在本公开实施例中，同种颜色子像素中的第一过孔位于所述颜色子像素的同一侧。
可选地，在本公开实施例中，同一所述重复单元中，所述第一个第二颜色子像素的第一过孔、所述第一颜色子像素的第一过孔以及所述第二个第二颜色子像素的第一过孔沿所述第一方向顺序排列于同一第一子折线上；
针对一个重复单元组中的第一颜色子像素和相邻重复单元组中且与所述第一颜色子像素最近邻的第三颜色子像素，所述第一颜色子像素的第一过孔和所述第三颜色子像素的第一过孔沿第三方向排列于同一第二子折线上；其中，所述第三方向与所述第一方向交叉。
可选地，在本公开实施例中，所述折线包括：所述第一子折线和所述第二子折线；不同列中的相邻的两个重复单元中，第一个重复单元中的第三颜色子像素的第一过孔与第二个重复单元中的所述第一个第二颜色子像素的第一过孔、所述第一颜色子像素的第一过孔以及所述第二个第二颜色子像素的第一过孔依次顺序排列于折线上。
可选地，在本公开实施例中，同一所述重复单元中的所述第三颜色子像素的第一过孔和所述第一颜色子像素的第一过孔沿所述第二方向排列于同一直线上。
可选地，在本公开实施例中，不同列且相邻的两个重复单元中，一个重复单元中的第一个第二颜色子像素的第一过孔与另一个重复单元中的第二个第二颜色子像素的第一过孔沿所述第二方向排列于同一直线上。
可选地，在本公开实施例中，奇数类重复单元组和偶数类重复单元组中的至少一类重复单元组中，同一行重复单元中的所述第一颜色子像素的第一 过孔、所述第二颜色子像素对中的第一个第二颜色子像素的第一过孔以及第二个第二颜色子像素的第一过孔沿所述第一方向排列于同一直线上；
并且，奇数类重复单元组和偶数类重复单元组中的至少一类重复单元组中，同一行重复单元中的所述第三颜色子像素的第一过孔沿所述第一方向排列于同一直线上。
可选地，在本公开实施例中，所述电致发光显示面板还包括：
第二导电层，位于所述第一导电层与所述基板之间，并且包括：间隔设置的第二电源线和第二连接线；
第二绝缘层，位于所述第二导电层与所述第一导电层之间，并且具有暴露所述第二连接线的第二过孔以及暴露所述第二电源线的一部分的第三过孔；
所述第一连接线通过所述第二过孔与所述第二连接线彼此电连接；
所述第一电源线通过所述第三过孔与所述第二电源线彼此电连接。
可选地，在本公开实施例中，针对相互电连接的所述第一连接线和所述第二连接线，所述第一连接线在所述基板的正投影与所述第二连接线在所述基板的正投影至少部分交叠；
所述第一电源线在所述基板的正投影与所述第二电源线在所述基板的正投影至少部分交叠。
可选地，在本公开实施例中，所述第三颜色子像素中，所述第一过孔相对所述第二过孔靠近像素驱动电路中的驱动晶体管设置；
所述第一颜色子像素中，所述第一过孔相对所述第二过孔远离像素驱动电路中的驱动晶体管设置；
所述第二颜色子像素中，所述第一过孔相对所述第二过孔远离像素驱动电路中的驱动晶体管设置。
可选地，在本公开实施例中，同一所述子像素中，所述第一过孔在所述基板的正投影与所述第二过孔在所述基板的正投影大致不交叠。
可选地，在本公开实施例中，各所述子像素还包括：第四过孔；
所述第三颜色子像素中，所述第四过孔在所述基板的正投影与所述第二 过孔在所述基板的正投影交叠；
所述第一颜色子像素中，所述第四过孔在所述基板的正投影与所述第一过孔在所述基板的正投影交叠；
所述第二颜色子像素中，所述第四过孔在所述基板的正投影与所述第一过孔在所述基板的正投影交叠。
可选地，在本公开实施例中，所述第四过孔沿第一方向排列于一条直线上，且位于同一直线上相邻的两个第四过孔之间的间距大致相同。
可选地，在本公开实施例中，沿所述第一方向上的相邻的两个第一过孔之间的间距大致相同，沿所述第二方向上的相邻的两个第一过孔之间的间距大致相同；
沿所述第一方向上的相邻的两个第二过孔之间的间距大致相同，沿所述第二方向上的相邻的两个第二过孔之间的间距大致相同。
可选地，在本公开实施例中，所述第三颜色子像素中，所述第一过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影交叠，且所述第二过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠，以及所述第四过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠。
可选地，在本公开实施例中，所述第一颜色子像素中，所述第一过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠，且所述第二过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影交叠，以及所述第四过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠。
可选地，在本公开实施例中，所述第二颜色子像素中，所述第一过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠，且所述第二过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影交叠，以及所述第四过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠。
可选地，在本公开实施例中，所述第三颜色子像素中，所述主体部分在所述基板的正投影与所述第二过孔在所述基板的正投影至少部分交叠。
可选地，在本公开实施例中，所述第三颜色子像素中，所述主体部分在所述基板的正投影与两个第三过孔在所述基板的正投影至少部分交叠。
可选地，在本公开实施例中，所述第三颜色子像素中，所述第一过孔靠近与所述主体部分在所述基板的正投影交叠的所述两个第三过孔的中心线的一侧设置，并且所述第二过孔靠近与所述主体部分在所述基板的正投影交叠的所述两个第三过孔的中心线的另一侧设置。
可选地，在本公开实施例中，所述第三颜色子像素中，所述主体部分为轴对称图形，并且所述第二过孔位于所述主体部分沿所述第二方向的对称轴上。
可选地，在本公开实施例中，所述第一颜色子像素中，所述主体部分在所述基板的正投影与所述第二过孔在所述基板的正投影至少部分交叠。
可选地，在本公开实施例中，所述第一颜色子像素中，所述主体部分在所述基板的正投影与两个第三过孔在所述基板的正投影至少部分交叠。
可选地，在本公开实施例中，所述第一颜色子像素中，所述第一过孔靠近正投影交叠的所述两个第三过孔的中心线的一侧设置，并且所述第二过孔靠近正投影交叠的所述两个第三过孔的中心线的另一侧设置。
可选地，在本公开实施例中，所述第一颜色子像素中，所述主体部分为轴对称图形，并且所述第二过孔位于所述主体部分沿所述第二方向的对称轴上。
可选地，在本公开实施例中，针对同一重复单元中的第一颜色子像素和第一个第二颜色子像素，以及针对与所述同一重复单元中的第一颜色子像素和第一个第二颜色子像素均最近邻的第三颜色子像素，所述第一个第二颜色子像素的第二过孔位于所述第一颜色子像素与所述第三颜色子像素之间的间隙中；
针对同一重复单元中的第一颜色子像素和第二个第二颜色子像素，以及 针对与所述同一重复单元中的第一颜色子像素和第二个第二颜色子像素均最近邻的第三颜色子像素，所述第二个第二颜色子像素的第二过孔位于所述第一颜色子像素与所述第三颜色子像素之间的间隙中。
可选地，在本公开实施例中，所述第一个第二颜色子像素中，所述第一过孔和所述第二过孔沿所述第二方向排列于同一直线上；所述第二个第二颜色子像素中，所述第一过孔和所述第二过孔沿所述第二方向排列于同一直线上。
可选地，在本公开实施例中，所述第一个第二颜色子像素中，所述第二过孔位于所述第一过孔背离所述主体部分一侧；
所述第二个第二颜色子像素中，所述第二过孔位于所述第一过孔背离所述主体部分一侧。
可选地，在本公开实施例中，奇数列重复单元组中的第三颜色子像素的第二过孔与偶数列重复单元组中的第一颜色子像素的第一过孔、第一个第二颜色子像素的第一过孔以及第二个第二颜色子像素的第一过孔沿所述第一方向排列于同一直线上。
可选地，在本公开实施例中，所述第三颜色子像素中，所述主体部分在所述基板的正投影覆盖两条子电源线在所述基板的正投影；并且与所述主体部分在所述基板的正投影交叠的所述两条子电源线平行设置于所述主体部分的中心的两侧。
可选地，在本公开实施例中，所述第一颜色子像素中，所述主体部分在所述基板的正投影覆盖两条子电源线在所述基板的正投影；并且与所述主体部分在所述基板的正投影交叠的所述两条子电源线平行设置于所述主体部分的中心的两侧。
可选地，在本公开实施例中，所述第二颜色子像素中，所述主体部分在所述基板的正投影与一条所述子电源线以及与所述子电源线电连接的导通线在所述基板的正投影至少部分交叠。
可选地，在本公开实施例中，所述第一导电层包括：相互间隔设置的第 一电源线、第一连接线以及数据线；
各所述子像素中，所述辅助部分通过所述第一过孔与所述第一连接线电连接。
可选地，在本公开实施例中，所述第一电源线和所述数据线沿第一方向排列且沿第二方向延伸；并且所述第一方向与所述第二方向不同。
可选地，在本公开实施例中，所述第一电源线被配置为传输驱动电压的电源线。
本公开实施例还提供了显示装置，包括如上述电致发光显示面板。
附图说明
图1a为相关技术中的显示面板的俯视结构示意图；
图1b为图1a所示的显示面板中沿AA’方向的剖视结构示意图；
图2a为本公开中的一些像素驱动电路的结构示意图；
图2b为本公开中的一些有源半导体层的俯视结构示意图；
图2c为本公开中的一些栅导电层的俯视结构示意图；
图2d为本公开中的一些参考导电层的俯视结构示意图；
图2e为本公开中的一些源漏极金属层的俯视结构示意图；
图2f为本公开中的一些辅助金属层的俯视结构示意图；
图2g为本公开中的有源半导体层、栅导电层、参考导电层和源漏极金属层以及辅助金属层的层叠位置关系的示意图；
图3a为本公开中的一些显示面板的俯视结构示意图；
图3b为本公开中的又一些显示面板的俯视结构示意图；
图3c为本公开中的又一些显示面板的俯视结构示意图；
图4为本公开中的一些显示面板的阳极、第一过孔以及第二过孔的结构示意图；
图5a为本公开中的一些显示面板中的第一导电层、第二过孔以及第三过孔的结构示意图；
图5b为本公开中的又一些显示面板中的第一导电层、第二过孔以及第三过孔的结构示意图；
图6a为图3a所示的显示面板中沿AA’方向的剖视结构示意图；
图6b为图3a所示的显示面板中沿BB’方向的剖视结构示意图；
图6c为图3b所示的显示面板中沿AA’方向的剖视结构示意图；
图7a为图3a所示的显示面板中沿CC’方向的剖视结构示意图；
图7b为图3a所示的显示面板中沿DD’方向的剖视结构示意图；
图8a为图3a所示的显示面板中沿EE’方向的剖视结构示意图；
图8b为图3a所示的显示面板中沿FF’方向的剖视结构示意图；
图8c为图3b所示的显示面板中沿BB’方向的剖视结构示意图；
图9a为本公开中的又一些显示面板的俯视结构示意图；
图9b为本公开中的又一些显示面板的俯视结构示意图；
图10为图9a所示的显示面板的阳极与第一过孔的结构示意图；
图11为图9a所示的显示面板中的第一导电层与第一过孔的结构示意图；
图12为图9a所示的显示面板中沿AA’方向的剖视结构示意图；
图13为图9a所示的显示面板中沿BB’方向的剖视结构示意图；
图14为图9a所示的显示面板中沿CC’方向的剖视结构示意图；
图15为图9a所示的显示面板中沿DD’方向的剖视结构示意图；
图16为图9b所示的显示面板中沿AA’方向的剖视结构示意图；
图17为图9b所示的显示面板中沿BB’方向的剖视结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“电连接”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
通常的OLED显示面板包括衬底基板、设置在衬底基板上的像素驱动电路、设置在像素驱动电路远离衬底基板的一侧的平坦层、设置在平坦层远离衬底基板一侧的阳极、设置在阳极远离衬底基板一侧的发光层以及设置在发光层远离衬底基板一侧的阴极。
图1a为一些显示面板的俯视结构示意图。图1b为图1a所示的显示面板沿AA’方向的剖视结构示意图。如图1a和图1b所示，显示面板可以包括：衬底基板10、像素驱动电路20、平坦层30、阳极40、发光层50、阴极60以及像素限定层80；像素限定层80具有开口，以通过开口限定出有效发光区。其中，像素驱动电路20具有晶体管和电容，并通过晶体管和电容的相互作用产生电信号，产生的电信号通过连接线21输入到阳极40。并且对阴极60加载相应的电压，可以驱动发光层50发光。平坦层30中具有过孔31，阳极40通过过孔31与连接线21相互电连接。然而，由于过孔31具有一定深度，使得阳极40和阳极40上的发光层50在该过孔31存在的区域出现凹陷，从而导致阳极40不平整，进而导致显示面板产生色偏现象。
结合图2a所示，像素驱动电路0121可以包括：像素驱动电路0122、第一发光控制电路0123、第二发光控制电路0124、数据写入电路0126、存储电路0127、阈值补偿电路0128和复位电路0129。其中，像素驱动电路0122包括控制端、第一端和第二端，且被配置为发光元件0120提供驱动发光元件0120发光的驱动电流。例如，第一发光控制电路0123与像素驱动电路0122的第一端和第一电压端VDD连接，且被配置为实现像素驱动电路0122和第一电 压端VDD之间的连接导通或断开，第二发光控制电路0124与像素驱动电路0122的第二端和发光元件0120的第一发光电压施加电极电连接，且被配置为实现像素驱动电路0122和发光元件0120之间的连接导通或断开。数据写入电路0126与像素驱动电路0122的第一端电连接，且被配置为在扫描信号的控制下将数据信号写入存储电路0127；存储电路0127与像素驱动电路0122的控制端和第一电压端VDD电连接，且被配置为存储数据信号；阈值补偿电路0128与像素驱动电路0122的控制端和第二端电连接，且被配置为对像素驱动电路0122进行阈值补偿；复位电路0129与像素驱动电路0122的控制端和发光元件0120的第一发光电压施加电极电连接，且配置为在复位控制信号的控制下对像素驱动电路0122的控制端和发光元件0120的第一发光电压施加电极进行复位。其中，发光器件0120包括层叠设置的阳极40、发光层50、阴极60。
示例性地，结合图2a所示，像素驱动电路0122包括：驱动晶体管T1，像素驱动电路0122的控制端包括驱动晶体管T1的栅极，像素驱动电路0122的第一端包括驱动晶体管T1的第一极，像素驱动电路0122的第二端包括驱动晶体管T1的第二极。
示例性地，结合图2a所示，数据写入电路0126包括数据写入晶体管T2，存储电路0127包括第三电容C2，阈值补偿电路0128包括阈值补偿晶体管T3，第一发光控制电路0123包括第一发光控制晶体管T4，第二发光控制电路0124包括第二发光控制晶体管T5，复位电路0129包括第一复位晶体管T6和第二复位晶体管T7，复位控制信号可以包括第一子复位控制信号和第二子复位控制信号。
具体地，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线Vd电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与第一扫描信号线Ga1电连接以接收扫描信号；第三电容C2的第一极与第一电源端VDD电连接，第三电容C2的第二极与驱动晶体管T1的栅极电连接；阈值补偿晶体管T3的第一极与驱动晶 体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与第二扫描信号线Ga2电连接以接收补偿控制信号；第一复位晶体管T6的第一极被配置为与第一复位电源端Vinit1电连接以接收第一复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的栅极电连接，第一复位晶体管T6的栅极被配置为与第一复位控制信号线Rst1电连接以接收第一子复位控制信号；第二复位晶体管T7的第一极被配置为与第二复位电源端Vinit2电连接以接收第二复位信号，第二复位晶体管T7的第二极与发光元件120的第一发光电压施加电极电连接，第二复位晶体管T7的栅极被配置为与第二复位控制信号线Rst2电连接以接收第二子复位控制信号；第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶体管T4的栅极被配置为与第一发光控制信号线EM1电连接以接收第一发光控制信号；第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与发光元件120的第一发光电压施加电极电连接，第二发光控制晶体管T5的栅极被配置为与第二发光控制信号线EM2电连接以接收第二发光控制信号；发光元件120的第二发光电压施加电极与第二电源端VSS电连接。其中，第一极和第二极可以根据实际应用确定为源极或漏极，在此不作限定。
示例性地，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图2a所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
需要说明的是，在本公开实施例中，子像素的像素驱动电路除了可以为图2a所示的的结构之外，还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。
图2b至图2g为本公开一些实施例提供的像素驱动电路的各层的示意图。 下面结合附图2b～2g描述像素驱动电路中的各个电路在基板上的位置关系，图2b～2g所示的示例以一个子像素的像素驱动电路为例。其中，图2b～2g还示出了连接到像素驱动电路0121的第一扫描信号线Ga1a、第二扫描信号线Ga2a、第一复位控制信号线Rst1a、第二复位控制信号线Rst2a、第一复位电源端Vinit1a的第一复位电源信号线Init1a、第二复位电源端Vinit2a的第二复位电源信号线Init2a、第一发光控制信号线EM1a、第二发光控制信号线EM2a、数据线Vd、第一电源端VDD的第一电源信号线VDD1、第二电源信号线VDD2，第一电源信号线VDD1和第二电源信号线VDD2彼此电连接。需要说明的是，在图2b～2g所示的示例中，第一扫描信号线Ga1a和第二扫描信号线Ga2a为同一条信号线，第一复位电源信号线Init1a和第二复位电源信号线Init2a为同一条信号线，第一复位控制信号线Rst1a和第二复位控制信号线Rst2a为同一条信号线，第一发光控制信号线EM1a和第二发光控制信号线EM2a为同一条信号线。
例如，图2b示出了该像素驱动电路0121的有源半导体层0310。有源半导体层0310可采用半导体材料图案化形成。有源半导体层0310可用于制作上述的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的有源层，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，各晶体管的有源层一体设置。
例如，有源半导体层0310可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
例如，像素驱动电路0121的栅极金属层可以包括栅导电层0320。在上述的有源半导体层0310上形成有栅极绝缘层(未示出)，用于保护上述的有源半导体层0310。图2c示出了该像素驱动电路0121的栅导电层0320，栅导电层0320设置在栅极绝缘层上，从而与有源半导体层0310绝缘。栅导电层0320可以包括第三电容C2的第二极CC2a、第一扫描信号线Ga1a、第二扫描信号 线Ga2a、第一复位控制信号线Rst1a、第二复位控制信号线Rst2a、第一发光控制信号线EM1a、第二发光控制信号线EM2a、以及驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的栅极。
例如，如图2c所示，数据写入晶体管T2的栅极可以为第一扫描信号线Ga1a与有源半导体层0310交叠的部分，第一发光控制晶体管T4的栅极可以为第一发光控制信号线EM1a/第二发光控制信号线EM2a与有源半导体层0310交叠的第一部分，第二发光控制晶体管T5的栅极可以为第一发光控制信号线EM1a/第二发光控制信号线EM2a与有源半导体层0310交叠的第二部分，第一复位晶体管T6的栅极为第一复位控制信号线Rst1a/第二复位控制信号线Rst2a与有源半导体层0310交叠的第一部分，第二复位晶体管T7的栅极为第一复位控制信号线Rst1a/第二复位控制信号线Rst2a与有源半导体层0310交叠的第二部分，阈值补偿晶体管T3可为双栅结构的薄膜晶体管，阈值补偿晶体管T3的第一个栅极可为第二扫描信号线Ga2a与有源半导体层0310交叠的部分，阈值补偿晶体管T3的第二个栅极可为从第二扫描信号线Ga2a突出的突出部与有源半导体层0310交叠的部分。如图2a和2c所示，驱动晶体管T1的栅极可为第三电容C2的第二极CC2a。
需要说明的是，图2b中的各虚线矩形框示出了栅导电层0320与有源半导体层0310交叠的各个部分。
例如，如图2c所示，第一扫描信号线Ga1a/第二扫描信号线Ga2a、第一复位控制信号线Rst1a/第二复位控制信号线Rst2a和第一发光控制信号线EM1a/第二发光控制信号线EM2a沿第二方向F2排布。第一扫描信号线Ga1a/第二扫描信号线Ga2a位于第一复位控制信号线Rst1a/第二复位控制信号线Rst2a和第一发光控制信号线EM1a/第二发光控制信号线EM2a之间。
例如，在第二方向F2上，第三电容C2的第二极CC2a位于第一扫描信号线Ga1a/第二扫描信号线Ga2a和第一发光控制信号线EM1/a第二发光控制信号线EM2a之间。从第二扫描信号线Ga2a突出的突出部位于第二扫描信号 线Ga2a的远离第一发光控制信号线EM1a/第二发光控制信号线EM2a的一侧。
例如，结合图2b所示，在第二方向F2上，数据写入晶体管T2的栅极、阈值补偿晶体管T3的栅极、第一复位晶体管T6的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第一侧，第一发光控制晶体管T4的栅极、第二发光控制晶体管T5的栅极均位于驱动晶体管T1的栅极的第二侧。
例如，在一些实施例中，如图2b至图2g所示，在第一方向F1上，数据写入晶体管T2的栅极和第一发光控制晶体管T4的栅极均位于驱动晶体管T1的栅极的第三侧，阈值补偿晶体管T3的第一个栅极、第二发光控制晶体管T5的栅极和第二复位晶体管T7的栅极均位于驱动晶体管T1的栅极的第四侧。其中，驱动晶体管T1的栅极的第三侧和第四侧为在第一方向F1上驱动晶体管T1的栅极的彼此相对的两侧。
例如，在上述的栅导电层0320上形成有第一层间绝缘层(未示出)，用于保护上述的栅导电层0320。图2d示出了该像素驱动电路120a的参考导电层0330，参考导电层0330包括第三电容C2的第一极CC1a、第一复位电源信号线Init1a、第二复位电源信号线Init2a。第三电容C2的第一极CC1a与第三电容C2的第二极CC2a至少部分交叠以形成第三电容C2。
例如，在上述的参考导电层0330上形成有第二层间绝缘层(未示出)，用于保护上述的参考导电层0330。图2e示出了该像素驱动电路0121的源漏极金属层0340，源漏极金属层0340包括数据线Vd和第一电源信号线VDD1。
例如，在上述的源漏极金属层0340上形成有第三层间绝缘层(未示出)，用于保护上述的源漏极金属层0340。图2f示出了该像素驱动电路0121的辅助金属层0350，辅助金属层0350包括第二电源信号线VDD2。
图2g为上述的有源半导体层0310、栅导电层0320、参考导电层0330和源漏极金属层0340以及辅助金属层0350的层叠位置关系的示意图。如图2e至图2g所示，数据线Vd通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔(例如，过孔381a)与有源半导体层0310中的数据写入晶体管T2的源极区域电连接。第一电源信号线VDD1通过栅极绝缘层、第一 层间绝缘层和第二层间绝缘层中的至少一个过孔(例如，过孔382a)与有源半导体层0310中对应的第一发光控制晶体管T4的源极区域电连接。第一电源信号线VDD1通过第二绝缘层中的至少一个过孔(例如，过孔3832a)与参考导电层0330中的第三电容C2的第一极CC1a电连接。第一电源信号线VDD1还通过第二绝缘层中的至少一个过孔(例如，过孔3831a)与辅助金属层0350中的第二电源信号线VDD2电连接。
例如，如图2e和2g所示，源漏极金属层0340还包括连接部341a、连接部342a和连接部343a。连接部341a的一端通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔(例如，过孔384a)与有源半导体层0310中对应的阈值补偿晶体管T3的漏极区域电连接。连接部341a的另一端通过第一层间绝缘层和第二层间绝缘层中的至少一个过孔(例如，过孔385a)与栅导电层0320中的驱动晶体管T1的栅极(即第三电容C2的第二极CC2a)电连接。连接部342a的一端通过第二绝缘层中的一个过孔(例如，过孔386a)与第一复位电源信号线Init1a/第二复位电源信号线Init2a电连接，连接部342a的另一端通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔(例如，过孔387a)与有源半导体层0310中的第二复位晶体管T7的漏极区域电连接。连接部343a通过栅极绝缘层、第一层间绝缘层和第二层间绝缘层中的至少一个过孔(例如，过孔388a)与有源半导体层0310中的第二发光控制晶体管T5的漏极区域电连接。
例如，如图2f和2g所示，辅助金属层0350还包括连接部351a。连接部351a通过贯穿第三层间绝缘层的过孔(例如，过孔385b)与连接部343a电连接。
例如，如图2b至图2g所示，在第二方向F2上，第一扫描信号线Ga1a、第二扫描信号线Ga2a、第一复位控制信号线Rst1a、第二复位控制信号线Rst2a、第一复位电源信号线Init1a和第二复位电源信号线Init2a均位于的驱动晶体管T1的栅极的第一侧，第一发光控制信号线EM1a、第二发光控制信号线EM2a均位于驱动晶体管T1的第二侧。
例如，第一扫描信号线Ga1a、第二扫描信号线Ga2a、第一复位控制信号线Rst1a、第二复位控制信号线Rst2a、第一发光控制信号线EM1a、第二发光控制信号线EM2a、第一复位电源信号线Init1a和第二复位电源信号线Init2a均沿第一方向F1延伸，数据线Vd沿第二方向F2延伸。
例如，第一电源信号线VDD1沿第二方向F2延伸，第二电源信号线VDD2沿第二方向F2延伸。也就是说，在整个显示基板上，第一电源信号线VDD1和第二电源信号线VDD2电性连接，从而第一电源端VDD的信号线的电阻较小、压降较低，进而可以提高第一电源端VDD提供的电源电压的稳定性。
例如，第一扫描信号线Ga1a、第二扫描信号线Ga2a、第一复位控制信号线Rst1a、第二复位控制信号线Rst2a、第一发光控制信号线EM1a、第二发光控制信号线EM2a位于同一层，第一复位电源信号线Init1a、第二复位电源信号线Init2a和第二电源信号线VDD2a位于同一层。第一电源信号线VDD1和数据线Vd位于同一层。
需要说明的是，每个像素驱动电路中的像素驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、存储电路、阈值补偿电路和复位电路等的位置排布关系不限于图2b至图2g所示的示例，根据实际应用需求，可以具体设置像素驱动电路、第一发光控制电路、第二发光控制电路、数据写入电路、存储电路、阈值补偿电路和复位电路的位置。
结合图3a至图8c所示，本公开实施例提供的电致发光显示面板可以包括多个重复单元001，各重复单元001包括多个子像素，各子像素可以包括：位于基板100上方的第一导电层200，位于第一导电层200上方的第一绝缘层300，位于第一绝缘层300上的阳极400。第一绝缘层300包括第一过孔310，第一过孔310暴露第一导电层200的一部分。阳极400包括相互电连接的主体部分410和辅助部分420，辅助部分420通过第一过孔310与第一导电层200电连接。其中，至少一个子像素中，主体部分410在基板100的正投影与第一过孔310在基板100的正投影不交叠。并且，至少一个子像素中，主体部分410在第一方向F1的尺寸大于在第二方向F2的尺寸，且至少一个子像 素中，第一过孔310与主体部分410在第二方向F2上排布；其中，第一方向F1与第二方向F2不同。
本公开实施例提供的电致发光显示面板，通过使阳极包括相互电连接的主体部分和辅助部分，采用辅助部分通过第一过孔与第一导电层电连接，以使阳极通过第一导电层与像素驱动电路相互电连接。并且，至少一个子像素中，主体部分在第一方向的尺寸大于在第二方向的尺寸，且至少一个子像素中，第一过孔与主体部分在第二方向上排布；其中，第一方向与第二方向不同。由于至少一个子像素中，主体部分在基板的正投影与第一过孔在基板的正投影不交叠，可以使该子像素中的第一过孔进行避让，以使该子像素中阳极的主体部分不受第一过孔的深度影响，从而避免阳极的主体部分出现凹陷，以避免由于第一过孔导致的阳极不平整的情况出现，进而改善显示面板的色偏现象。
在具体实施时，第一过孔与主体部分在第二方向上排布，例如可以为，所述第一过孔和所述主体部分在平行于第二方向的一条直线上投影，所述第一过孔的投影和所述主体部分的投影不完全重叠，例如第一过孔的投影和所述主体部分的投影不交叠，或者仅交叠一部分；所述第一过孔和所述主体部分在平行于第一方向的一条直线上投影，第一过孔的投影完全落入所述主体部分的投影内。在具体实施时，第一过孔与主体部分在第二方向上排布，例如可以为，所述主体部分具有大致平行于第一方向的第一边，所述第一过孔位于所述主体部分第一边远离所述主体部分的一侧。在具体实施时，第一过孔与主体部分在第二方向上排布，例如可以为，连接所述第一过孔中心和所述主体部分任意一点的一条虚拟线与第二方向的夹角小于90°，进一步的，可以小于60°，再进一步的，可以小于45°。
在具体实施时，在本公开实施例中，如图3a至图8c所示，同一子像素中的主体部分和辅助部分是一体结构。例如，采用一次构图工艺形成同一子像素中的主体部分和辅助部分。
在具体实施时，在本公开实施例中，如图3a至图8c所示，第一导电层 200可以包括：相互间隔设置的第一电源线210和第一连接线220；其中，各子像素中，辅助部分420通过第一过孔310与第一连接线220电连接。示例性地，第一导电层200例如为上述的辅助金属层0350。其中，第一电源线210例如为上述的第二电源信号线VDD2，第一连接线220例如为上述的连接部351a。并且，其中过孔的对应关系，在此不作赘述。
在具体实施时，在本公开实施例中，如图3a至图8c所示，电致发光显示面板还可以包括：位于第一导电层200与基板100之间的第二导电层600，以及位于第二导电层600与第一导电层200之间的第二绝缘层500。第二导电层600具有间隔设置的第二电源线610和第二连接线620。第二绝缘层500具有暴露第二连接线620的第二过孔520以及暴露第二电源线610的一部分的第三过孔630。并且，第一电源线210通过第三过孔530与第二电源线610彼此电连接，以实现降低电阻的效果。第一连接线220通过第二过孔520与第二连接线620彼此电连接，第二连接线620与像素驱动电路中的晶体管的漏极电连接，以实现信号的传输。示例性地，第二导电层600例如为上述的源漏极金属层0340。第二电源线610例如为上述的第一电源信号线VDD1，第二连接线620例如为上述的连接部343a。并且，其中过孔和绝缘层以及其余膜层的对应关系可以参见上述有源半导体层0310、栅导电层0320、参考导电层0330的实施，在此不作赘述。
在具体实施时，在本公开实施例中，如图3a至图8c所示，针对相互电连接的第一连接线220和第二连接线620，第一连接线220在基板100的正投影与第二连接线620在基板100的正投影至少部分交叠。可选地，第一连接线220在基板100的正投影与第二连接线620在基板100的正投影重叠。可选地，第一连接线220在基板100的正投影与第二连接线620在基板100的正投影部分交叠。这样可以提高相互电连接的效果。
在具体实施时，在本公开实施例中，如图3a至图8c所示，第一电源线210在基板100的正投影与第二电源线610在基板100的正投影至少部分交叠。可选地，第一电源线210在基板100的正投影与第二电源线610在基板100 的正投影重叠。可选地，第一电源线210在基板100的正投影与第二电源线610在基板100的正投影部分交叠。这样可以提高相互电连接的效果。
在具体实施时，在本公开实施例中，如图3a所示，第三过孔530阵列分布于基板100上。示例性地，多个第三过孔530沿第一方向F1和第二方向F2进行均匀排列。示例性地，第一电源线210可以被配置为传输驱动电压的电源线。这样使得第二电源线610也可以被配置为传输驱动电压的电源线。从而可以降低负载对传输的驱动电压的不利影响。进一步地，在具体实施时，第二导电层600还具有分别与第二电源线610和第二连接线620间隔设置的数据线和桥接线。该桥接线被配置为使像素驱动电路中的部分晶体管的栅极、源极以及漏极中的两个极进行电连接。该数据线被配置为传输数据信号，并且数据线和桥接线的设置方式可以与相关技术中的设置方式基本相同，在此不作赘述。
在具体实施时，在本公开实施例中，如图6a所示，各子像素还可以包括位于阳极400背离基板100一侧的像素界定层80，位于阳极400背离基板100一侧的发光层50，以及位于阳极背离发光层50一侧的阴极60。其中，像素限定层80具有开口，且开口暴露阳极400的主体部分410的至少部分区域，发光层50位于开口内且与开口暴露的主体部分410的区域接触，则开口中的发光层50所处于的区域用于发光，从而可以通过开口限定出有效发光区90。也就是说，像素限定层80的开口与阳极400的主体部分410交叠的部分区域为各子像素的有效发光区90。示例性地，第三颜色子像素030中的像素限定层80的开口与阳极400的主体部分413交叠的部分区域为第三颜色子像素030的有效发光区90-030。第一颜色子像素010中的像素限定层80的开口与阳极400的主体部分411交叠的部分区域为第一颜色子像素010的有效发光区90-010。第二颜色子像素021中的像素限定层80的开口与阳极400的主体部分4121交叠的部分区域为第二颜色子像素021的有效发光区90-021。第二颜色子像素022中的像素限定层80的开口与阳极400的主体部分4122交叠的部分区域为第二颜色子像素022的有效发光区90-022。
需要说明的是，在本公开的实施例中，每个发光层可以包括电致发光层本身以及位于电致发光层两侧的其他公共层，例如，空穴注入层、空穴传输层、电子注入层以及电子传输层等等，但是在本公开的附图中，仅示出了发光层中的电致发光层，而没有示出其他公共层。示例性地，电致发光层的材料可以包括：有机电致发光材料，这样可以使电致发光显示面板为OLED显示面板。或者，电致发光层的材料也可以包括：量子点电致发光材料，这样可以使电致发光显示面板为量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示面板。
在具体实施时，在本公开实施例中，结合图3a与图4所示，同一子像素中，第一过孔310在基板100的正投影与第二过孔520在基板100的正投影不交叠。这样可以避免由于过孔过深导致阳极不能与第二连接线电连接的问题。
示例性地，在具体实施时，在本公开实施例中，如图3a、图3b与图5a所示，第一电源线210可以包括：沿第一方向F1排列且沿第二方向F2延伸的多个子电源线211。其中，第一方向F1与第二方向F2不同。示例性地，第一方向F1与第二方向F2垂直。示例性地，第一方向F1可以为显示面板的行方向，即栅线延伸的方向，第二方向F2可以为显示面板的列方向，即数据线延伸的方向。当然，本公开实施例包括但不限于此。
在具体实施时，在本公开实施例中，如图3c与图5b所示，第一电源线210可以包括：沿第一方向F1排列且沿第二方向F2延伸的多个子电源线211以及电连接各个子电源线211的导通线212。这样可以进一步降低第一电源线210的电阻。示例性地，第一方向F1与第二方向F2垂直。当然，本公开实施例包括但不限于此。
在具体实施时，在本公开实施例中，如图3c与图5b所示，子电源线211与导通线212大致形成网格结构，每个网格内部设置有一个第一连接线220，且第一连接线220与子电源线211和导通线212之间均有间隔。
一般在显示领域，一个像素通常包括多个可分别显示单色(例如红色、 绿色或蓝色)的子像素，通过控制不同颜色的子像素的比例以实现显示不同的颜色，因此上述子像素可以为单色子像素。在具体实施时，在本公开实施例中，如图3a至图4所示，多个重复单元001中的每个可以包括：沿第二方向F2排列的一个第一颜色子像素010、一个第二颜色子像素对020以及一个第三颜色子像素030。其中，第二颜色子像素对020可以包括沿第一方向F1排列的两个第二颜色子像素021、022。其中，第一颜色子像素010被配置为发第一颜色的光，第二颜色子像素021、022被配置为发第二颜色的光，第三颜色子像素被配置为发第三颜色的光。在一些示例中，第一颜色、第二颜色以及第三颜色可以从红色、绿色以及蓝色中进行选取。例如，第一颜色为红色、第二颜色为绿色、第三颜色为蓝色。由此，该重复单元001为红绿蓝子像素的排列结构。当然，本公开实施例包括但不限于此。上述的第一颜色、第二颜色和第三颜色还可为其他颜色。
在具体实施时，在本公开实施例中，如图3a至图4所示，多个重复单元001沿第二方向F2排列形成重复单元组，重复单元组沿第一方向F1排列，且相邻两个重复单元组中的重复单元001错位排列。示例性地，相邻两个重复单元组中的重复单元001相差1/2个重复单元001的尺寸。需要说明的是，上述的一个重复单元001的尺寸可以为：第二方向F2上相邻两个重复单元001中的相同颜色子像素的中心之间的距离。例如上述的一个重复单元001的尺寸可以为：第二方向F2上相邻两个重复单元001中的第一颜色子像素010的中心之间的距离。
或者，例如，相邻重复单元组中的重复单元沿第二方向是彼此错开的，也就是说，相邻的重复单元组中的相邻的重复单元沿第二方向有一定的偏移量。因此，相邻重复单元组中相同颜色的子像素在第二方向上并不是对齐的。在一些示例中，相邻重复单元组中的相同颜色子像素在第二方向上的偏移量可以为重复单元在第二方向上的尺寸的一半。例如，重复单元在第二方向上的尺寸可以为重复单元在第二方向上的节距。
在具体实施时，在本公开实施例中，如图3a至图4所示，由于第二颜色 子像素对020可以包括沿第一方向F1排列的两个第二颜色子像素021、022，在采用FMM蒸镀工艺制备发光层时，可将每个第二颜色子像素对020中的两个第二颜色子像素021、022的发光层连起来，通过FMM的一个蒸镀孔来形成每个第二颜色子像素对020中的两个第二颜色子像素021、022的发光层。在第二颜色为绿色时，可以在一定程度上降低制备绿色子像素的发光层的工艺难度。
此外，虽然在附图中的各子像素的主体部分的形状包括严格的由两条线段形成的角，但在一些实施例中，各个子像素的有效发光区的形状可以均为圆角图形。也就是说，在上述各种图形形状的基础上，各个子像素的有效发光区的角被倒圆。例如，对于发光层通过掩模版进行蒸镀的情况下，发光层位于角落处的部分则可能会自然形成圆角形状。
在一些示例中，如图3a至图4所示，第一颜色子像素010和第三颜色子像素030的主体部分的形状可以均为六边形，该六边形的三组对边均平行。每个第二颜色子像素021、022的主体部分的形状可以为五边形，该五边形包括非直角交叉的两条边、一组平行的对边以及一条垂直边，垂直边与一组平行的对边垂直，非直角交叉的两条边连接于一组平行的对边之间；其中，每个第二颜色子像素对020中的第二颜色子像素021、022中的垂直边相邻设置。
在一些示例中，如图3a至图4所示，第一颜色子像素010的主体部分中一组较长的平行对边和第三颜色子像素030的主体部分中一组较长的平行对边，分别与第二颜色子像素021、022中的主体部分的一组平行的对边平行。进一步地，示例性地，第一颜色子像素010的有效发光区90-010中一组较长的平行对边和第三颜色子像素030的有效发光区90-030中一组较长的平行对边，分别与第二颜色子像素021、022的有效发光区90-021、90-022中的一组平行的对边平行。
在一些示例中，如图3a至图4所示，第一颜色子像素010的面积大于一个第二颜色子像素020的面积，第三颜色子像素030的面积大于一个第二颜色子像素020的面积。例如，第一颜色子像素010的有效发光区90-010的面 积大于一个第二颜色子像素020的有效发光区90-021、90-022的面积，第三颜色子像素030的有效发光区90-030的面积大于一个第二颜色子像素020的有效发光区90-021、90-022的面积。
在具体实施时，在本公开实施例中，如图3a至图4所示，在第一方向F1上相邻的两个重复单元在第二方向F2上的交错距离大于从第一颜色子像素010的最大跨度、第二颜色子像素021的最大跨度、第二颜色子像素022的最大跨度以及第三颜色子像素030的最大跨度中的一个或其结合。例如，在第一方向F1上相邻的两个重复单元在第二方向F2上的交错距离大于从第一颜色子像素010的有效发光区90-010的最大跨度d010、第二颜色子像素021的有效发光区90-021的最大跨度d020、第二颜色子像素022的有效发光区90-022的最大跨度d020以及第三颜色子像素030的有效发光区90-030的最大跨度d030中的一个或其结合。
在具体实施时，在本公开实施例中，如图3a至图4所示，在一个重复单元001中，第二颜色子像素对020中的第二颜色子像素021与第二颜色子像素022在第一方向F1上的最远距离大于第一颜色子像素010的任意两点在第一方向F1上的最远距离。例如，在一个重复单元001中，第二颜色子像素对020中的第二颜色子像素021的有效发光区90-021与第二颜色子像素022的有效发光区90-022在第一方向F1上的最远距离大于第一颜色子像素010的有效发光区90-010的任意两点在第一方向F1上的最远距离。
在具体实施时，在本公开实施例中，如图3a至图4所示，在一个重复单元001中，第二颜色子像素对020中的第二颜色子像素021与第二颜色子像素022在第一方向F1上的最远距离大于第三颜色子像素030的任意两点在第一方向F1上的最远距离。例如，在一个重复单元001中，第二颜色子像素对020中的第二颜色子像素021的有效发光区90-021与第二颜色子像素022的有效发光区90-022在第一方向F1上的最远距离大于第三颜色子像素030的有效发光区90-030的任意两点在第一方向F1上的最远距离。
在具体实施时，在本公开实施例中，如图3a至图4所示，第一颜色子像 素的相邻子像素不包括第一颜色子像素，第二颜色子像素对的相邻子像素不包括第二颜色子像素，第三颜色子像素的相邻子像素不包括第三颜色子像素。
在具体实施时，在本公开实施例中，如图3a至图4所示，在第一方向F1和第二方向F2上，两个第一颜色子像素010由除第一颜色子像素之外的其他子像素分割，两个第三颜色子像素030由除第三颜色子像素之外的其他子像素分割，两个第二颜色子像素对由除第二颜色子像素之外的其他子像素分割。
在具体实施时，在本公开实施例中，如图3a至图4所示，以第一方向F1上的两个相邻的重复单元排列为一个重复组。示例性地，同一个重复组中，一个重复单元中的第二颜色子像素对在另一个重复单元中的一个第一颜色子像素和一个第三颜色子像素在第二方向F2上的最大跨度之间。例如，同一个重复组中，一个重复单元中的第二颜色子像素对的有效发光区在另一个重复单元中的一个第一颜色子像素的有效发光区和一个第三颜色子像素的有效发光区在第二方向F2上的最大跨度之间。
在具体实施时，在本公开实施例中，如图3a至图4所示，以第一方向F1上的两个相邻的重复单元排列为一个重复组。示例性地，同一个重复组中，一个重复单元中的第一颜色子像素在另一个重复单元中的一个第二颜色子像素对和一个第三颜色子像素在第二方向F2上的最大跨度之间。例如，同一个重复组中，一个重复单元中的第一颜色子像素的有效发光区在另一个重复单元中的一个第二颜色子像素对的有效发光区和一个第三颜色子像素的有效发光区在第二方向F2上的最大跨度之间。
在具体实施时，在本公开实施例中，如图3a至图4所示，以第一方向F1上的两个相邻的重复单元排列为一个重复组。示例性地，同一个重复组中，一个重复单元中的第三颜色子像素在另一个重复单元中的一个第二颜色子像素对和一个第一颜色子像素在第二方向F2上的最大跨度之间。例如，同一个重复组中，一个重复单元中的第三颜色子像素的有效发光区在另一个重复单元中的一个第二颜色子像素对的有效发光区和一个第一颜色子像素的有效发光区在第二方向F2上的最大跨度之间。
在具体实施时，在本公开实施例中，如图3a至图4所示，同一个重复单元001中，同一第二颜色子像素对020中的两个第二颜色子像素021、022在第一方向F1上的最小距离小于一个第一颜色子像素010在第一方向F1上的最大跨度。例如，同一个重复单元001中，同一第二颜色子像素对020中的第二颜色子像素021的有效发光区90-021与第二颜色子像素022的有效发光区90-022在第一方向F1上的最小距离小于一个第一颜色子像素010的有效发光区90-010在第一方向F1上的最大跨度d010。
在具体实施时，在本公开实施例中，如图3a至图4所示，同一个重复单元001中，同一第二颜色子像素对020中的两个第二颜色子像素021、022在第一方向F1上的最小距离小于一个第三颜色子像素030在第一方向F1上的最大跨度。例如，同一个重复单元001中，同一第二颜色子像素对020中的第二颜色子像素021的有效发光区90-021与第二颜色子像素022的有效发光区90-022在第一方向F1上的最小距离小于一个第三颜色子像素030的有效发光区90-030在第一方向F1上的最大跨度d030。
在具体实施时，在本公开实施例中，如图3a至图4所示，奇数列重复单元组中重复单元中的子像素排列方式相同，偶数列重复单元组中重复单元中的子像素排列方式相同。例如，除了在基板的显示区的边缘部分之外，每个重复单元中两个绿色子像素的中心连线位于相邻的重复单元组中两个相邻的红色和蓝色子像素的中心之间。此外，上述两个绿色子像素的边缘在上述两个相邻的红色和蓝色子像素的外侧边缘的内侧，这里的外侧边缘是指两个子像素的沿第一方向F1上彼此相对的边缘。也就是说，在第一方向F1上，一个绿色子像素对在第一方向F1上的延伸的范围不大于上述两个相邻的红色和蓝色子像素在第一方向F1上的延伸的范围。另外，在本公开的实施例中，如果没有特别说明，子像素的“中心”是指子像素(例如：第一颜色子像素、第二颜色子像素或第三颜色子像素)的形状的几何中心。
需要说明的是，在对子像素排列结构进行设计时，子像素一般会设计为规则的形状，比如，六边形、五边形、梯形或其他形状。在进行设计时，子 像素的中心可以是上述规则形状的几何中心。然而，在实际制造工艺中，所形成的子像素的形状一般会与上述设计的规则形状有一定的偏差。例如，上述规则的形状的各个角可能会变成圆角，因此，子像素的形状可以为圆角图形。此外，实际制造的子像素的形状还可能会与设计的形状有其他的变化。例如，设计为六边形的子像素的形状在实际制造中可能变成近似椭圆形。因此，子像素的中心也可能并非制作形成的子像素的不规则形状的严格的几何中心。在本公开的实施例中，子像素的中心可以与子像素的形状的几何中心有一定的偏移量。子像素的中心是指从子像素的几何中心出发到子像素的边缘各点的辐射线段上的特定点所围成的区域内的任一点，该辐射线段上的特定点在距离该几何中心1/3该辐射线段的长度处。该子像素中心的定义适用于规则形状的子像素形状的中心，也适用于不规则形状的子像素的中心。
在具体实施时，在本公开实施例中，如图3a至图4所示，在每相邻的三个重复单元组中，该三个相邻列沿着行方向(即第一方向F1)依次包括第一列、第二列和第三列，第二列中第二颜色子像素020对中的两个第二颜色子像素021、022的中心在行方向上的最短距离小于第一列中第一颜色子像素010的中心与第三列中第一颜色子像素010的中心在行方向上的最小距离。
在具体实施时，在本公开实施例中，如图3a至图4所示，第一颜色子像素010在第二方向F2上的边与第三颜色子像素030在第二方向F2上的边平行排列。
在具体实施时，在本公开实施例中，如图3a至图4所示，每个重复单元001中，第一颜色子像素010、第二颜色子像素对020以及第三颜色子像素030的排列顺序相同。
在具体实施时，在本公开实施例中，如图3a至图4所示，第一颜色子像素010的主体部分411在第二方向F2上的尺寸小于第三颜色子像素030的主体部分413在第二方向F2上的尺寸。并且，第一颜色子像素010的主体部分411在第一方向F1上的尺寸大于第三颜色子像素030的主体部分413在第一方向F1上的尺寸。示例性地，第三颜色子像素030的主体部分413在第二方 向F2上的尺寸小于第三颜色子像素030的主体部分413在第一方向F1上的尺寸，并且第一颜色子像素010的主体部分411在第二方向F2上的尺寸小于第一颜色子像素010的主体部分411在第一方向F1上的尺寸。当然，本公开实施例包括但不限于此，上述的各尺寸之间的关系还可为其他形式。
在具体实施时，在本公开实施例中，如图3a至图8c所示，各子像素还包括：位于第一导电层200面向基板100一侧的像素驱动电路；其中，各子像素中像素驱动电路阵列分布。需要说明的是，像素驱动电路的各层结构可以参见图2a至图2g所示的结构，在此不作赘述。
在具体实施时，在本公开实施例中，如图2g与图3b所示，第三颜色子像素030中的像素驱动电路、第一个第二颜色子像素021中的像素驱动电路、第一颜色子像素010中的像素驱动电路以及第二个第二颜色子像素022中的像素驱动电路沿第一方向F1依次排布。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图2g与图3b所示，各像素驱动电路中的各层图案所在区域在第二方向F2上的尺寸大于在第一方向F1上的尺寸。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图2g与图3b所示，第一颜色子像素010的主体部分411的延伸方向S1与第一颜色子像素010的像素驱动电路所在区域的长度方向S2之间具有第一夹角θ1；其中，第一夹角θ1在45度至165度之间。示例性地，θ1大致可以为90度，也就是说，第一颜色子像素010的主体部分411的延伸方向S1(例如，第一颜色子像素010的主体部分411的延伸方向可以为第一方向F1)与第一颜色子像素010的像素驱动电路所在区域的长度方向(例如，第一颜色子像素010的像素驱动电路所在区域的长度方向可以为第二方向F2)大致垂直。当然，θ1大致也可以为45度至135度之间，75度至115度之间，或者50度、80度、100度、120度、140度。本公开包括在不限于此。
在具体实施时，在本公开实施例中，如图2g与图3b所示，第三颜色子像素030的主体部分413的延伸方向S3与第三颜色子像素010的像素驱动电 路所在区域的长度方向S2之间具有第二夹角θ2；其中，第二夹角θ2在45度至165度之间。示例性地，θ2大致可以为90度，也就是说，第三颜色子像素030的主体部分413的延伸方向S1(例如，第三颜色子像素030的主体部分411的延伸方向为第一方向F1)与第三颜色子像素010的像素驱动电路所在区域的长度方向S2(例如，第三颜色子像素010的像素驱动电路所在区域的长度方向为第二方向F2)大致垂直。当然，θ2大致也可以为45度、75度、115度、135度。本公开包括在不限于此。
在具体实施时，在本公开实施例中，如图2g与图3b所示，第二颜色子像素对020的延伸方向S4与第二颜色子像素对020的像素驱动电路所在区域的长度方向S2之间具有第三夹角θ3；其中，第三夹角θ3在45度至165度之间。示例性地，θ3大致可以为90度，也就是说，第二颜色子像素对020的延伸方向S4(例如，第二颜色子像素对020的延伸方向为第一方向F1)与第二颜色子像素对020的像素驱动电路所在区域的长度方向S2(例如，第二颜色子像素对020的像素驱动电路所在区域的长度方向为第二方向F2)大致垂直。当然，θ3大致也可以为45度至135度之间，75度至115度之间，或者50度、80度、100度、120度、140度。本公开包括在不限于此。
在具体实施时，例如限定一个矩形区域包括一个子像素的像素驱动电路各个膜层的图案，例如图2g虚线框所示，限定各个子像素的像素驱动电路的矩形区域矩阵式排列于基板上，则该矩形区域的长边方向与第一颜色子像素的主体部分的延伸方向大致垂直。
在具体实施时，例如限定一个矩形区域包括一个子像素的像素驱动电路各个膜层的图案，例如图2g虚线框所示，限定各个子像素的像素驱动电路的矩形区域矩阵式排列于基板上，则该矩形区域的长边方向与第三颜色子像素的主体部分的延伸方向大致垂直。
在具体实施时，在本公开实施例中，如图2a至图6c所示，第三颜色子像素030中，主体部分413在基板100的正投影与像素驱动电路中的驱动晶体管不交叠，主体部分413在基板100的正投影与像素驱动电路相邻的下一行 像素驱动电路电连接的复位控制信号线(即下一行的第一复位控制信号线Rst1a或第二复位控制信号线Rst2a)和复位电源信号线(即下一行的第一复位电源信号线Init1a或第二复位电源信号线Init2a)在基板100的正投影交叠，主体部分413在基板100的正投影与两条数据线Vd在基板100的正投影交叠，主体部分413在基板100的正投影与两条第二电源线610在基板100的正投影交叠。示例性地，正投影与主体部分413交叠的数据线Vd和电源线610交替排列。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图3a至图5b所示，第三颜色子像素030中，主体部分413在基板100的正投影覆盖两条子电源线211在基板100的正投影。并且与主体部分413在基板100的正投影交叠的两条子电源线211平行设置于主体部分413的中心的两侧。示例性地，与主体部分413在基板100的正投影交叠的两条子电源线211的正投影穿过主体部分413的正投影。
在具体实施时，在本公开实施例中，如图3a至图5b所示，第一颜色子像素010中，主体部分411在基板100的正投影覆盖两条子电源线211在基板100的正投影。并且与主体部分411在基板100的正投影交叠的两条子电源线211平行设置于主体部分411的中心的两侧。示例性地，与主体部分411在基板100的正投影交叠的两条子电源线211的正投影穿过主体部分411的正投影。
在具体实施时，在本公开实施例中，如图3a至图6c所示，第一颜色子像素010中，主体部分411在基板100的正投影与像素驱动电路中的驱动晶体管交叠，主体部分411在基板100的正投影与像素驱动电路电连接的发光控制信号线(第一发光控制信号线EM1a或第二发光控制信号线EM2a)在基板100的正投影交叠，主体部分411在基板100的正投影与两条数据线Vd在基板100的正投影交叠，主体部分411在基板100的正投影与两条第二电源线610在基板100的正投影交叠。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图3c与图5b所示，第二颜色子 像素中，主体部分在基板的正投影与一条子电源线以及与子电源线电连接的导通线在基板的正投影至少部分交叠。示例性地，如图3c与图5b所示，第二颜色子像素对020可以包括第一个第二颜色子像素021和第二个第二颜色子像素022。其中，第一个第二颜色子像素021中，主体部分4121在基板100的正投影与一条子电源线211以及与子电源线211电连接的导通线212在基板100的正投影部分交叠。示例性地，与主体部分4121在基板100的正投影交叠的子电源线211和导通线212可以采用十字型设置。当然，本公开实施例包括但不限于此。上述的与主体部分4121在基板100的正投影交叠的子电源线211和导通线212还可设置为其他形式。
在具体实施时，在本公开实施例中，如图3b、图5b以及图6c所示，第一个第二颜色子像素021中，主体部分4121在基板100的正投影与像素驱动电路中的驱动晶体管无交叠，主体部分4121在基板100的正投影与像素驱动电路相邻的下一行像素驱动电路电连接的复位控制信号线(即下一行的第一复位控制信号线Rst1a或第二复位控制信号线Rst2a)和扫描信号线(即下一行的第一扫描信号线Ga1a或第二扫描信号线Ga2a)在基板的正投影交叠。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图3b、图5b以及图6c所示，第二个第二颜色子像素022中，主体部分4122在基板100的正投影与像素驱动电路中的驱动晶体管无交叠，主体部分4122在基板100的正投影与像素驱动电路相邻的下一行像素驱动电路电连接的复位控制信号线(即下一行的第一复位控制信号线Rst1a或第二复位控制信号线Rst2a)和扫描信号线(即下一行的第一扫描信号线Ga1a或第二扫描信号线Ga2a)在基板100的正投影交叠。当然，本公开包括但不限于此。
示例性地，如图3c与图5b所示，第二个第二颜色子像素022中，主体部分4122在基板100的正投影与一条子电源线211以及与子电源线211电连接的导通线212在基板100的正投影部分交叠。示例性地，与主体部分4122在基板100的正投影交叠的子电源线211和导通线212可以采用十字型设置。 当然，本公开实施例包括但不限于此。上述的与主体部分4122在基板100的正投影交叠的子电源线211和导通线212还可设置为其他形式。
在具体实施时，在本公开实施例中，如图3c与图5b所示，子电源线211和导通线212相互电连接，使第一电源线210形成网格状结构。示例性地，导通线212阵列排布于基板100上。例如，如图3c与图5b所示，针对同一重复单元组中相邻的第三颜色子像素030和第一颜色子像素010，该第三颜色子像素030中的主体部分413和第一颜色子像素010中的主体部分411之间设置一条导通线212。第二颜色子像素对020中的主体部分4121和主体部分4122覆盖的导通线212沿第一方向F1延伸于同一直线上。
在具体实施时，在本公开实施例中，如图3a至图6c所示，各第三颜色子像素030中，主体部分413和辅助部分423相互电连接，辅助部分423通过第一过孔310与第一连接线223相互电连接，第一连接线223通过第二过孔520与第二连接线623彼此电连接，第二连接线623与像素驱动电路中的晶体管的漏极电连接，以将像素驱动电路产生的电信号输入阳极400，并且还通过对阴极60加载相应的电压，以驱动发光层50发光。
在具体实施时，在本公开实施例中，如图3a至图4以及图6a与图6c所示，各第三颜色子像素030中，主体部分413在基板100的正投影与第一过孔310在基板100的正投影不交叠。这样可以使各第三颜色子像素030中的主体部分413不受第一过孔310的影响，以避免由于第一过孔310导致的主体部分413出现不平整的情况，从而可以改善显示面板的色偏现象。
一般，第一过孔310与第二过孔520之间的距离不应过远或过近，在具体实施时，在本公开实施例中，各第三颜色子像素030中，沿第二方向F2上，第一过孔310与第二过孔520之间的距离W中的最小值可以满足的1微米～2微米范围。其中，可以使第一过孔310与第二过孔520之间的距离W中的最小值为。也可以使第一过孔310与第二过孔520之间的距离W中的最小值为，也可以使第一过孔310与第二过孔520之间的距离W中的最小值为。当然，在实际应用中，第一过孔310与第二过孔520之间的距离W可以根据实际应 用环境来设计确定，在此不作限定。
可选地，第一绝缘层可以被配置为平坦层，从而使得位于第一绝缘层上的主体部分可以具有较高的平坦度。
在具体实施时，在本公开实施例中，如图3a至图4以及图6a与图6c所示，第三颜色子像素030中，主体部分413在基板100的正投影与第二过孔520在基板100的正投影至少部分交叠。例如，主体部分413在基板100的正投影覆盖第二过孔520在基板100的正投影。由于第二过孔520位于第二绝缘层500中，第二绝缘层500与主体部分413之间具有第一绝缘层300和第一导电层200，因此第二过孔520对主体部分413的影响较小，甚至可以忽略不计。
在具体实施时，在本公开实施例中，如图3b与图6c所示，第三颜色子像素030中，第一过孔310相对第二过孔520靠近像素驱动电路中的驱动晶体管设置。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图3b所示，各子像素还包括：第四过孔710。可选地，第四过孔710沿第一方向F1排列于一条直线上，且位于同一直线上相邻的两个第四过孔710之间的间距大致相同。其中，第四过孔710可以为过孔388a。
在具体实施时，在本公开实施例中，如图3b与图6c所示，第三颜色子像素030中，第四过孔710在基板100的正投影与第二过孔520在基板100的正投影交叠。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，结合图3b至图8c所示，第三颜色子像素030中，第一过孔310在基板100的正投影与驱动电路电连接的发光控制信号线(即本行的第一发光控制信号线EM1a或第二发光控制信号线EM2a)在基板100的正投影交叠，且第二过孔520在基板100的正投影与驱动电路电连接的发光控制信号线(即本行的第一发光控制信号线EM1a或第二发光控制信号线EM2a)在基板100的正投影不交叠，以及第四过孔710在基板100的正投影与驱动电路电连接的发光控制信号线(本行的第一发光控 制信号线EM1a或第二发光控制信号线EM2a)在基板100的正投影不交叠。
在具体实施时，在本公开实施例中，如图3a与图6b所示，第三颜色子像素030中，主体部分413在基板100的正投影与两个第三过孔530在基板100的正投影至少部分交叠。例如，第三颜色子像素030中，主体部分413在基板100的正投影与两个第三过孔530在基板100的正投影部分交叠。
在具体实施时，在本公开实施例中，如图3a、图3c与图6b所示，第三颜色子像素030中，第一过孔310靠近与主体部分413在基板100的正投影交叠的两个第三过孔530的中心线LZ1的一侧设置，并且第二过孔520靠近与主体部分413在基板100的正投影交叠的两个第三过孔530的中心线LZ1的另一侧设置。这样可以使第三颜色子像素030中的第一过孔310与第二过孔520可以距离较近设置。需要说明的是，中心线LZ1与第一方向F1平行。并且，中心线LZ1为通过这两个第三过孔530的中心的线，其是虚拟的，并不是真实存在的线。
需要说明的是，在本公开实施例中，在平行于基板所在平面的平面中，过孔的截面可以为规则图形，例如长方形、正多边形(正方形、正五边形、正六边形等)，圆形、椭圆形等，此时过孔的中心可以是指该规则图形的几何中心。当然，在平行于基板所在平面的平面中，过孔的截面也可以为不规则图形，此时过孔的中心可以是指该不规则图形的等效几何中心。
在具体实施时，在本公开实施例中，如图3a至图4所示，第三颜色子像素030中，主体部分413可以为轴对称图形，第一过孔310可以位于主体部分413沿第二方向F2的对称轴上。示例性地，第三颜色子像素030中的主体部分413可以具有沿第二方向F2的第一对称轴，第三颜色子像素030中的第一过孔310关于第一对称轴大致呈轴对称设置，示例性地，第三颜色子像素030中的主体部分413的形状大致为六边形或椭圆形，六边形的长对称轴或椭圆形的长轴与第一方向F1大致平行，六边形的短对称轴或椭圆形的短轴与第二方向F2大致平行，则可以将六边形的短对称轴或椭圆形的短轴作为第一对称轴。示例性地，可以使第三颜色子像素030中的第一过孔310关于第一对 称轴大致呈轴对称设置，也可以使第三颜色子像素030中的第一过孔310仅是与第一对称轴相交，并不是关于第一对称轴大致呈轴对称设置。当然，在实际应用中，可以根据实际应用环境来设计确定第三颜色子像素030中的第一过孔310的实施方式，在此不作限定。
在具体实施时，在本公开实施例中，如图3a至图4所示，第三颜色子像素030中，第二过孔520可以位于主体部分413沿第二方向F2的对称轴上。示例性地，第三颜色子像素030中的第二过孔520关于第一对称轴大致呈轴对称设置。示例性地，可以使第三颜色子像素030中的第二过孔520关于第一对称轴大致呈轴对称设置，也可以使第三颜色子像素030中的第二过孔520仅是与第一对称轴相交，并不是关于第一对称轴大致呈轴对称设置。当然，在实际应用中，可以根据实际应用环境来设计确定第三颜色子像素030中的第二过孔520的实施方式，在此不作限定。
在具体实施时，在本公开实施例中，如图3a至图3c以及图6c与图7a所示，各第一颜色子像素010中，主体部分411和辅助部分421相互电连接，辅助部分421通过第一过孔310与第一连接线221相互电连接，第一连接线221通过第二过孔520与第二连接线621彼此电连接，第二连接线621与像素驱动电路中的晶体管的漏极电连接，以将像素驱动电路产生的电信号输入阳极400，并且还通过对阴极60加载相应的电压，以驱动发光层50发光。
在具体实施时，在本公开实施例中，如图3a至图4以及图6c与图7a所示，各第一颜色子像素010中，主体部分411在基板100的正投影与第一过孔310在基板100的正投影不交叠。这样可以使各第一颜色子像素010中的主体部分411不受第一过孔310的影响，以避免由于第一过孔导致的主体部分411出现不平整的情况，从而可以改善显示面板的色偏现象。
在具体实施时，在本公开实施例中，如图3a至图4以及图6c至图7a所示，第一颜色子像素010中，主体部分411在基板100的正投影与第二过孔520在基板100的正投影至少部分交叠。示例性地，主体部分411在基板100的正投影覆盖第二过孔520在基板100的正投影。由于第二过孔520位于第 二绝缘层500中，第二绝缘层500与主体部分411之间具有第一绝缘层300和第一导电层200，因此第二过孔520对主体部分411的影响较小，甚至可以忽略不计。
在具体实施时，在本公开实施例中，如图3b所示，第一颜色子像素010中，第一过孔310相对第二过孔520远离像素驱动电路中的驱动晶体管设置。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图3b与图6c所示，第一颜色子像素010中，第四过孔710在基板100的正投影与第一过孔310在基板100的正投影交叠。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图3b与图6c所示，第一颜色子像素010中，第一过孔310在基板100的正投影与驱动电路电连接的发光控制信号线(即本行的第一发光控制信号线EM1a或第二发光控制信号线EM2a)在基板100的正投影不交叠，且第二过孔在基板的正投影与驱动电路电连接的发光控制信号线(即本行的第一发光控制信号线EM1a或第二发光控制信号线EM2a)在基板100的正投影交叠，以及第四过孔710在基板100的正投影与驱动电路电连接的发光控制信号线(即本行的第一发光控制信号线EM1a或第二发光控制信号线EM2a)在基板100的正投影不交叠。当然，本公开包括但不限于此。
在具体实施时，在本公开实施例中，如图3a至图4以及图6c与图7b所示，第一颜色子像素010中，主体部分411在基板100的正投影与两个第三过孔530在基板100的正投影至少部分交叠。示例性地，第一颜色子像素010中，主体部分411在基板100的正投影与两个第三过孔530在基板100的正投影部分交叠。
在具体实施时，在本公开实施例中，如图3a至图4所示，第一颜色子像素010中，第一过孔310靠近正投影交叠的两个第三过孔530的中心线LZ2的一侧设置，并且第二过孔520靠近正投影交叠的两个第三过孔530的中心线LZ2的另一侧设置。这样可以使第一颜色子像素010中的第一过孔310与 第二过孔520可以距离较近设置。需要说明的是，中心线LZ2与第一方向F1平行。并且中心线LZ2为通过这两个第三过孔530的中心的线，其是虚拟的，并不是真实存在的线。
在具体实施时，在本公开实施例中，如图3a至图4所示，第一颜色子像素010中，主体部分411可以为轴对称图形，第一过孔310位于主体部分411沿第二方向F2的对称轴上。示例性地，第一颜色子像素010中的主体部分411可以具有沿第二方向F2的第二对称轴。示例性地，第一颜色子像素010中的主体部分411的形状大致为六边形或椭圆形，六边形的长对称轴或椭圆形的长轴与第一方向F1大致平行，六边形的短对称轴或椭圆形的短轴与第二方向F2大致平行，则可以将六边形的短对称轴或椭圆形的短轴作为第二对称轴。示例性地，可以使第一颜色子像素010中的第一过孔310关于第二对称轴大致呈轴对称设置，也可以使第一颜色子像素010中的第一过孔310仅是与第二对称轴相交，并不是关于第二对称轴大致呈轴对称设置。当然，在实际应用中，可以根据实际应用环境来设计确定第一颜色子像素010中的第一过孔310的实施方式，在此不作限定。
在具体实施时，在本公开实施例中，如图3a至图4所示，第一颜色子像素010中，第二过孔520位于主体部分411沿第二方向F2的对称轴上。示例性地，可以使第一颜色子像素010中的第二过孔520关于第二对称轴大致呈轴对称设置，也可以使第一颜色子像素010中的第二过孔520仅是与第二对称轴相交，并不是关于第二对称轴大致呈轴对称设置。当然，在实际应用中，可以根据实际应用环境来设计确定第一颜色子像素010中的第二过孔520的实施方式，在此不作限定。
在具体实施时，在本公开实施例中，如图3a至图4以及图8a与图8c所示，各第一个第二颜色子像素021中，主体部分4121和辅助部分4221相互电连接，辅助部分4221通过第一过孔310与第一连接线2221相互电连接，第一连接线2221通过第二过孔520与第二连接线6221彼此电连接，第二连接线6221与像素驱动电路中的晶体管的漏极电连接，以将像素驱动电路产生 的电信号输入阳极400，并且还通过对阴极60加载相应的电压，以驱动发光层50发光。
在具体实施时，在本公开实施例中，如图3a至图4以及图8b与图8c所示，各第二个第二颜色子像素022中，主体部分4122和辅助部分4222相互电连接，辅助部分4222通过第一过孔310与第一连接线2222相互电连接，第一连接线2222通过第二过孔520与第二连接线6222彼此电连接，第二连接线6222与像素驱动电路中的晶体管的漏极电连接，以将像素驱动电路产生的电信号输入阳极400，并且还通过对阴极60加载相应的电压，以驱动发光层50发光。
可选地，如图3a至图4以及图8a至图8c所示，各第二颜色子像素中，主体部分在基板的正投影与第一过孔在基板的正投影不交叠。示例性地，如图3a至图4以及图8a与图8c所示，第一个第二颜色子像素021中，主体部分4121在基板100的正投影与第一过孔310在基板100的正投影不交叠。这样可以使各第一个第二颜色子像素021中的主体部分4121不受第一过孔310的影响，以避免由于第一过孔310导致的主体部分4121出现不平整的情况，从而可以改善显示面板的色偏现象。
示例性地，如图3a至图4以及图8a与图8c所示，第二个第二颜色子像素021中，主体部分4122在基板100的正投影与第一过孔310在基板100的正投影不交叠。这样可以使各第二个第二颜色子像素022中的主体部分4122不受第一过孔310的影响，以避免由于第一过孔310导致的主体部分4122出现不平整的情况，从而可以改善显示面板的色偏现象。
在具体实施时，在本公开实施例中，如图3a至图4所示，第二颜色子像素对020包括第一个第二颜色子像素021和第二个第二颜色子像素022；其中，同一重复单元001中，第一个第二颜色子像素021的第一过孔310位于该第一个第二颜色子像素021背离第三颜色子像素030一侧。并且，同一重复单元001中，第二个第二颜色子像素022的第一过孔310位于该第二个第二颜色子像素022背离第三颜色子像素030一侧。
在具体实施时，在本公开实施例中，如图3a至图4所示，针对同一重复单元001中的第一颜色子像素010和第一个第二颜色子像素021，以及针对与上述同一重复单元001中的第一颜色子像素010和第一个第二颜色子像素021均最近邻的第三颜色子像素030，第一个第二颜色子像素021的第一过孔310位于该第一颜色子像素010与该第三颜色子像素030之间的间隙中。并且，针对同一重复单元001中的第一颜色子像素010和第二个第二颜色子像素022，以及针对与上述同一重复单元001中的第一颜色子像素010和第二个第二颜色子像素022均最近邻的第三颜色子像素030，该第二个第二颜色子像素022的第一过孔310位于该第一颜色子像素010与该第三颜色子像素030之间的间隙中。
在具体实施时，在本公开实施例中，如图3a至图4所示，针对同一重复单元001中的第一颜色子像素010和第一个第二颜色子像素021，以及针对与同一重复单元001中的第一颜色子像素010和第一个第二颜色子像素021均最近邻的第三颜色子像素030，第一个第二颜色子像素021的第二过孔520位于该第一颜色子像素010与该第三颜色子像素030之间的间隙中。并且，针对同一重复单元001中的第一颜色子像素010和第二个第二颜色子像素022，以及针对与同一重复单元001中的第一颜色子像素010和第二个第二颜色子像素022均最近邻的第三颜色子像素030，第二个第二颜色子像素022的第二过孔520位于第一颜色子像素010与第三颜色子像素030之间的间隙中。
在具体实施时，在本公开实施例中，如图3a至图4所示，同种颜色子像素中的第一过孔310位于该颜色子像素的同一侧。示例性地，第一颜色子像素010的第一过孔310位于所在的第一颜色子像素010的同一侧。第二颜色子像素021、022的第一过孔310位于所在的第二颜色子像素021、022的同一侧。第三颜色子像素030的第一过孔310位于所在的第三颜色子像素030的同一侧。
在具体实施时，在本公开实施例中，如图3a至图4所示，同一重复单元001中，第一个第二颜色子像素021的第一过孔310和第二过孔520靠近第一 颜色子像素010的一侧设置，第二个第二颜色子像素022的第一过孔310和第二过孔520靠近第一颜色子像素010的另一侧设置。即第一个第二颜色子像素021的第一过孔310和第二个第二颜色子像素022的第一过孔310分别位于第一颜色子像素010的两侧。第一个第二颜色子像素021的第二过孔520和第二个第二颜色子像素022的第二过孔520分别位于第一颜色子像素010的两侧。示例性地，同一重复单元001中，第一个第二颜色子像素021的第一过孔310和第二过孔520可以设置于该重复单元001中的第一颜色子像素010中的主体部分411以及与该主体部分411左侧相邻的第三颜色子像素030中的主体部分413之间。并且，同一重复单元001中，第二个第二颜色子像素022的第一过孔310和第二过孔520可以设置于该重复单元001中的第一颜色子像素010中的主体部分411以及与该主体部分411右侧相邻的第三颜色子像素030中的主体部分413之间。
可选地，在具体实施时，在本公开实施例中，如图3a至图4所示，第一个第二颜色子像素021中，可以使第二过孔520位于第一过孔310背离主体部分4121一侧。当然，本公开实施例包括但不限于此。
可选地，在具体实施时，在本公开实施例中，如图3a至图4所示，第一个第二颜色子像素021中，可以使第一过孔310和第二过孔520沿第二方向F2排列于同一直线上。当然，本公开实施例包括但不限于此。
可选地，在具体实施时，在本公开实施例中，如图3b所示，第一个第二颜色子像素021中，第一过孔310相对第二过孔520远离像素驱动电路中的驱动晶体管设置。当然，本公开实施例包括但不限于此。
可选地，在具体实施时，在本公开实施例中，如图3b与图8c所示，第一个第二颜色子像素021中，第四过孔710在基板100的正投影与第一过孔310在基板100的正投影交叠。当然，本公开实施例包括但不限于此。
可选地，在具体实施时，在本公开实施例中，如图3b与图8c所示，第一个第二颜色子像素021中，第一过孔310在基板100的正投影与驱动电路电连接的发光控制信号线(即本行的第一发光控制信号线EM1a或第二发光 控制信号线EM2a)在基板100的正投影不交叠，且第二过孔520在基板100的正投影与驱动电路电连接的发光控制信号线(即本行的第一发光控制信号线EM1a或第二发光控制信号线EM2a)在基板100的正投影交叠，以及第四过孔710在基板100的正投影与驱动电路电连接的发光控制信号线(即本行的第一发光控制信号线EM1a或第二发光控制信号线EM2a)在基板100的正投影不交叠。当然，本公开实施例包括但不限于此。
可选地，在具体实施时，在本公开实施例中，如图3a至图4以及图8b与图8c所示，第二个第二颜色子像素022中，可以使第二过孔520位于第一过孔310背离主体部分4122一侧。当然，本公开实施例包括但不限于此。
可选地，在具体实施时，在本公开实施例中，如图3a至图4以及图8b与图8c所示，第二个第二颜色子像素022中，可以使第一过孔310和第二过孔520沿第二方向F2排列于同一直线上。当然，本公开实施例包括但不限于此。
可选地，在具体实施时，在本公开实施例中，如图3b所示，第二个第二颜色子像素022中，第一过孔310相对第二过孔520远离像素驱动电路中的驱动晶体管设置。当然，本公开实施例包括但不限于此。
可选地，在具体实施时，在本公开实施例中，如图3b与图8c所示，第二个第二颜色子像素022中，第四过孔710在基板100的正投影与第一过孔310在基板100的正投影交叠。当然，本公开实施例包括但不限于此。
可选地，在具体实施时，在本公开实施例中，如图3b与图8c所示，第二个第二颜色子像素022中，第一过孔310在基板100的正投影与驱动电路电连接的发光控制信号线(即本行的第一发光控制信号线EM1a或第二发光控制信号线EM2a)在基板100的正投影不交叠，且第二过孔520在基板100的正投影与驱动电路电连接的发光控制信号线(即本行的第一发光控制信号线EM1a或第二发光控制信号线EM2a)在基板100的正投影交叠，以及第四过孔710在基板100的正投影与驱动电路电连接的发光控制信号线(即本行的第一发光控制信号线EM1a或第二发光控制信号线EM2a)在基板100的正 投影不交叠。当然，本公开实施例包括但不限于此。
可选地，在具体实施时，在本公开实施例中，如图3a至图4所示，同一重复单元001中，第二颜色子像素对020中的第一个第二颜色子像素021的第一过孔310、第一颜色子像素010的第一过孔310以及第二个第二颜色子像素022的第一过孔310沿第一方向F1顺序排列于同一第一子折线Z1上。示例性地，第二列重复单元组的一个重复单元001中，第二颜色子像素对020中的第一个第二颜色子像素021的第一过孔310、第一颜色子像素010的第一过孔310以及第二个第二颜色子像素022的第一过孔310，可以使这三个第一过孔310沿第一方向F1的箭头所指的方向顺序排列于第一子折线Z1上，从而可以降低制备这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
可选地，在具体实施时，在本公开实施例中，如图3a至图4所示，针对一个重复单元组中的第一颜色子像素010和相邻重复单元组中且与第一颜色子像素010最近邻的第三颜色子像素030，第一颜色子像素010的第一过孔310和第三颜色子像素030的第一过孔310沿第三方向排列于同一第二子折线Z2上；其中，第三方向与第一方向交叉且不垂直。
可选地，在具体实施时，在本公开实施例中，如图3a至图4所示，折线可以包括：第一子折线Z1和第二子折线Z2；不同列中的相邻的两个重复单元001中，第一个重复单元中的第三颜色子像素030的第一过孔310与第二个重复单元中的第一个第二颜色子像素021的第一过孔310、第一颜色子像素010的第一过孔310以及第二个第二颜色子像素022的第一过孔310依次顺序排列于该折线上。也就是说，不同列中的相邻的两个重复单元001中，第一个重复单元中的第三颜色子像素030的第一过孔310与第二个重复单元中的第一个第二颜色子像素021的第一过孔310、第一颜色子像素010的第一过孔310以及第二个第二颜色子像素022的第一过孔310重复排列。这样也可以降低制备这些第一过孔310时使用的掩膜版(Mask)的设计难度。
可选地，在具体实施时，在本公开实施例中，如图3a至图4所示，同一重复单元001中的第三颜色子像素030的第一过孔310和第一颜色子像素010 的第一过孔310沿第二方向F2排列于同一直线上。这样也可以降低制备这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
可选地，在具体实施时，在本公开实施例中，如图3a至图4所示，不同列且相邻的两个重复单元001中，一个重复单元001中的第一个第二颜色子像素021的第一过孔310与另一个重复单元001中的第二个第二颜色子像素022的第一过孔310沿第二方向F2排列于同一直线上。这样也可以降低制备这些第一过孔310时使用的掩膜版(Mask)的设计难度。
在具体实施时，在本公开实施例中，如图3a至图4所示，奇数列重复单元组中的第三颜色子像素030的第二过孔520与偶数列重复单元组中的第一颜色子像素010的第一过孔310、第一个第二颜色子像素021的第一过孔310以及第二个第二颜色子像素022的第一过孔310沿第一方向F1排列于同一直线上。示例性地，第一列和第三列重复单元组中的第三颜色子像素030的第二过孔520与第二列重复单元组中的第一颜色子像素010的第一过孔310、第一个第二颜色子像素021的第一过孔310以及第二个第二颜色子像素022的第一过孔310沿第一方向F1排列于同一直线上。
在具体实施时，在本公开实施例中，如图3a至图4所示，奇数类重复单元组中，同一行重复单元001中的第一颜色子像素010的第一过孔310、第二颜色子像素对020中的第一个第二颜色子像素021的第一过孔310以及第二个第二颜色子像素022的第一过孔310沿第一方向F1排列于同一直线上。这样也可以降低制备显示面板中的这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
在具体实施时，在本公开实施例中，如图3a至图4所示，奇数类重复单元组中，同一行重复单元001中的第三颜色子像素030的第一过孔310沿第一方向F1排列于同一直线上。这样也可以降低制备显示面板中的这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
在具体实施时，在本公开实施例中，如图3a至图4所示，偶数类重复单元组中，同一行重复单元001中的第一颜色子像素010的第一过孔310、第二 颜色子像素对020中的第一个第二颜色子像素021的第一过孔310以及第二个第二颜色子像素022的第一过孔310沿第一方向F1排列于同一直线上。这样也可以降低制备显示面板中的这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
在具体实施时，在本公开实施例中，如图3a至图4所示，偶数类重复单元组中，同一行重复单元001中的第三颜色子像素030的第一过孔310沿第一方向F1排列于同一直线上。这样也可以降低制备显示面板中的这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
在具体实施时，在本公开实施例中，如图3a至图4所示，沿第一方向F1上的相邻的两个第一过孔310之间的间距可以大致相同。当然，本公开实施例包括但不限于此。
在具体实施时，在本公开实施例中，如图3a至图4所示，沿第二方向F2上的相邻的两个第一过孔310之间的间距可以大致相同。当然，本公开实施例包括但不限于此。
在具体实施时，在本公开实施例中，如图3a至图4所示，沿第一方向F1上的相邻的两个第二过孔520之间的间距可以大致相同。当然，本公开实施例包括但不限于此。
在具体实施时，在本公开实施例中，如图3a至图4所示，沿第二方向F2上的相邻的两个第二过孔520之间的间距可以大致相同。当然，本公开实施例包括但不限于此。
基于同一发明构思，本公开实施例还提供了另一些电致发光显示面板，如图9a至图15所示，其针对上述实施例中的部分实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图9a至图15所示，可以包括多个重复单元001，各重复单元001包括多个子像素，各子像素可以包括：位于基板100上方的第一导电层200，位于第一导电层200上方的第一绝缘层300，位于第一绝缘层300上的阳极400。第一绝缘层300包括第一过孔310，第一 过孔310暴露第一导电层200的一部分。阳极400包括相互电连接的主体部分410和辅助部分420，辅助部分420通过第一过孔310与第一导电层200电连接。其中，至少一个子像素中，主体部分410在基板100的正投影与第一过孔310在基板100的正投影不交叠。并且，至少一个子像素中，主体部分410在第一方向F1的尺寸大于在第二方向F2的尺寸，且至少一个子像素中，第一过孔310与主体部分410在第二方向F2上排布；其中，第一方向F1与第二方向F2不同。
本公开实施例提供的电致发光显示面板，通过使阳极包括相互电连接的主体部分和辅助部分，采用辅助部分通过第一过孔与第一导电层电连接，以使阳极通过第一导电层与像素驱动电路相互电连接。并且，由于至少一个子像素中，主体部分在基板的正投影与第一过孔在基板的正投影不交叠，可以使该子像素中的第一过孔进行避让，以使该子像素中阳极的主体部分不受第一过孔的深度影响，从而避免阳极的主体部分出现凹陷，以避免由于第一过孔导致的阳极不平整的情况出现，进而改善显示面板的色偏现象。
在具体实施时，在本公开实施例中，如图9a、图9b、图11、图12所示，第一导电层200可以包括：相互间隔设置的第一电源线210、第一连接线220以及数据线230。其中，各子像素中，辅助部分420通过第一过孔310与第一连接线220电连接。第一连接线220与像素驱动电路中的晶体管的漏极电连接，以实现信号的传输。需要说明的是，上述仅是以第三颜色子像素030为例进行说明，其余子像素中的设置以此类推，在此不作赘述。
进一步地，在具体实施时，在本公开实施例中，如图9a与图9b、图11、图12所示，第一导电层200还可以包括：分别与第一电源线210、第一连接线220以及数据线230间隔设置的桥接线240。该桥接线被配置为使像素驱动电路中的部分晶体管的栅极、源极以及漏极中的两个极进行电连接。并且桥接线的设置方式可以与相关技术中的设置方式基本相同，在此不作赘述。
示例性地，第一导电层200例如可以为上述的源漏极金属层0340。第一电源线210例如可以为上述的第一电源信号线VDD1，数据线230例如可以 为上述的数据线Vd，第一连接线220例如可以为上述的连接部343a，桥接线240例如可以为上述的连接部341a、342a中的至少一个。也就是说，本实施例与上述实施例相比，未设置辅助金属层0350，而其中过孔和绝缘层以及其余膜层的对应关系可以参见上述有源半导体层0310、栅导电层0320、参考导电层0330的实施，在此不作赘述。
在具体实施时，在本公开实施例中，如图12所示，各子像素还可以包括位于阳极400背离基板100一侧的像素界定层80，位于阳极400背离基板100一侧的发光层50，以及位于阳极背离发光层50一侧的阴极60。其中，像素限定层80具有开口，且开口暴露阳极400的主体部分410的至少部分区域，发光层50位于开口内且与开口暴露的主体部分410的区域接触，则开口中的发光层50所处于的区域用于发光，从而可以通过开口限定出有效发光区90。需要说明的是，上述各子像素的有效发光区90的实施方式可以参见上述实施例，在此不作赘述。
在具体实施时，第一电源线可以被配置为传输驱动电压的电源线。数据线可以被配置为传输数据电压的信号线。在本公开实施例中，如图9a、图9b与图11所示，第一电源线210和数据线230沿第一方向F1排列且沿第二方向F2延伸；并且第一方向F1与第二方向F2不同。示例性地，第一方向F1与第二方向F2垂直。示例性地，第一方向F1可以为显示面板的行方向，即栅线延伸的方向，第二方向F2可以为显示面板的列方向，即数据线延伸的方向。当然，本公开实施例包括但不限于此。
一般在显示领域，一个像素通常包括多个可分别显示单色(例如红色、绿色或蓝色)的子像素，通过控制不同颜色的子像素的比例以实现显示不同的颜色，因此上述子像素可以为单色子像素。在具体实施时，在本公开实施例中，如图9a至图10所示，多个重复单元001中的每个可以包括：沿第二方向F2排列的一个第一颜色子像素010、一个第二颜色子像素对020以及一个第三颜色子像素030。其中，第二颜色子像素对020可以包括沿第一方向F1排列的两个第二颜色子像素021、022。其中，第一颜色子像素010被配置 为发第一颜色的光，第二颜色子像素021、022被配置为发第二颜色的光，第三颜色子像素被配置为发第三颜色的光。在一些示例中，第一颜色、第二颜色以及第三颜色可以从红色、绿色以及蓝色中进行选取。例如，第一颜色为红色、第二颜色为绿色、第三颜色为蓝色。由此，该重复单元001为红绿蓝子像素的排列结构。当然，本公开实施例包括但不限于此。上述的第一颜色、第二颜色和第三颜色还可为其他颜色。需要说明的是，上述各子像素的排列方式可以参见上述实施方式，在此不作赘述。
在具体实施时，在本公开实施例中，如图9a至图10所示，多个重复单元001沿第二方向F2排列形成重复单元组，重复单元组沿第一方向F1排列，且相邻两个重复单元组中的重复单元001错位排列。示例性地，相邻两个重复单元组中的重复单元001相差1/2个重复单元001的尺寸。需要说明的是，上述的一个重复单元001的尺寸可以为：第二方向F2上相邻两个重复单元001中的相同颜色子像素的中心之间的距离。例如上述的一个重复单元001的尺寸可以为：第二方向F2上相邻两个重复单元001中的第一颜色子像素010的中心之间的距离。
在具体实施时，在本公开实施例中，如图9a至图10所示，第一颜色子像素010的主体部分411在第二方向F2上的尺寸小于第三颜色子像素030的主体部分413在第二方向F2上的尺寸。并且，第一颜色子像素010的主体部分411在第一方向F1上的尺寸大于第三颜色子像素030的主体部分413在第一方向F1上的尺寸。示例性地，第三颜色子像素030的主体部分413在第二方向F2上的尺寸小于第三颜色子像素030的主体部分413在第一方向F1上的尺寸，并且第一颜色子像素010的主体部分411在第二方向F2上的尺寸小于第一颜色子像素010的主体部分411在第一方向F1上的尺寸。当然，本公开实施例包括但不限于此，上述的各尺寸之间的关系还可为其他形式。
在具体实施时，如图9a至图11所示，以相邻的一条第一电源线210和一条数据线230为一个信号线组，在本公开实施例中，第三颜色子像素030中，主体部分413在基板100的正投影覆盖两个信号线组在基板100的正投影。 并且，与主体部分413在基板100的正投影交叠的两个信号线组平行设置于主体部分413的中心的两侧。示例性地，第三颜色子像素030中，主体部分413在基板100的正投影覆盖两条第一电源线210和两条数据线230在基板100的正投影。并且，一条第一电源线210和一条数据线230平行设置于主体部分413一侧，另一条第一电源线210和另一条数据线230平行设置于主体部分413另一侧。
进一步地，在具体实施时，在本公开实施例中，如图9a至图11所示，第三颜色子像素030中，主体部分413在基板100的正投影与两条桥接线240在基板100的正投影至少部分交叠。示例性地，主体部分413在基板100的正投影覆盖一条桥接线240在基板100的正投影交叠，并且，主体部分413在基板100的正投影与另一条桥接线240在基板100的正投影的边缘交叠。
在具体实施时，如图9a至图11所示，第一颜色子像素010中，主体部分411在基板100的正投影覆盖两个信号线组在基板100的正投影。并且，与主体部分411在基板100的正投影交叠的两个信号线组平行设置于主体部分411两侧。示例性地，第一颜色子像素010中，主体部分411在基板100的正投影覆盖两条第一电源线210和两条数据线230在基板100的正投影。并且，一条第一电源线210和一条数据线230平行设置于主体部分411一侧，另一条第一电源线210和另一条数据线230平行设置于主体部分411另一侧。
进一步地，在具体实施时，在本公开实施例中，如图9a至图11所示，第一颜色子像素010中，主体部分411在基板100的正投影与一条桥接线240在基板100的正投影交叠。示例性地，主体部分411在基板100的正投影与一条桥接线240在基板100的正投影的边缘交叠。
在具体实施时，如图9a至图11所示，第二颜色子像素中，主体部分在基板100的正投影与一个信号线组在基板100的正投影交叠。并且，同一第二颜色子像素对020中，与两个第二颜色子像素的主体部分在基板100的正投影交叠的信号线组相邻设置。示例性地，第二颜色子像素对020可以包括第一个第二颜色子像素021和第二个第二颜色子像素022。其中，第一个第二颜 色子像素021中，主体部分4121在基板100的正投影与一条第一电源线210与一条数据线220在基板100的正投影交叠。第二个第二颜色子像素022中，主体部分4122在基板100的正投影与另一条第一电源线210与另一条数据线220在基板100的正投影交叠。
进一步地，在具体实施时，如图9a至图11所示，第一个第二颜色子像素021中的主体部分4121在基板100的正投影还可以与一条桥接线240在基板100的正投影的边缘交叠。
进一步地，在具体实施时，如图9a至图11所示，第二个第二颜色子像素022中的主体部分4122在基板100的正投影还可以与两条桥接线240在基板100的正投影的边缘交叠。
在具体实施时，在本公开实施例中，如图9a、图9b、图12以及图16所示，各第三颜色子像素030中，主体部分413和辅助部分423相互电连接，辅助部分423通过第一过孔310与第一连接线223相互电连接，第一连接线223与像素驱动电路20中的晶体管的漏极电连接，以将像素驱动电路20产生的电信号输入阳极400，并且还通过对阴极60加载相应的电压，以驱动发光层50发光。
在具体实施时，在本公开实施例中，如图9a、图9b、图12以及图16所示，各第三颜色子像素030中，主体部分413在基板100的正投影与第一过孔310在基板100的正投影不交叠。这样可以使各第三颜色子像素030中的主体部分413不受第一过孔310的影响，以避免由于第一过孔310导致的主体部分413出现不平整的情况，从而可以改善显示面板的色偏现象。
可选地，第一绝缘层可以被配置为平坦层，从而使得位于第一绝缘层上的主体部分可以具有较高的平坦度。
在具体实施时，在本公开实施例中，如图9a至图10、图12以及图16所示，第三颜色子像素030中，主体部分413可以为轴对称图形，并且第一过孔310可以位于主体部分413沿第二方向F2的对称轴上。示例性地，第三颜色子像素030中的主体部分413可以具有沿第二方向F2的第一对称轴。示例 性地，第三颜色子像素030中的主体部分413的形状大致为六边形或椭圆形，六边形的长对称轴或椭圆形的长轴与第一方向F1大致平行，六边形的短对称轴或椭圆形的短轴与第二方向F2大致平行，则可以将六边形的短对称轴或椭圆形的短轴作为第一对称轴。示例性地，可以使第三颜色子像素030中的第一过孔310关于第一对称轴大致呈轴对称设置。也可以使第三颜色子像素030中的第一过孔310仅是与第一对称轴相交，并不是关于第一对称轴大致呈轴对称设置。当然，在实际应用中，可以根据实际应用环境来设计确定第三颜色子像素030中的第一过孔310的实施方式，在此不作限定。
在具体实施时，在本公开实施例中，如图9a、图9b、图13以及图16所示，各第一颜色子像素010中，主体部分411和辅助部分421相互电连接，辅助部分421通过第一过孔310与第一连接线221相互电连接，第一连接线221与像素驱动电路20中的晶体管的漏极电连接，以将像素驱动电路20产生的电信号输入阳极400，并且还通过对阴极60加载相应的电压，以驱动发光层50发光。
在具体实施时，在本公开实施例中，如图9a、图9b、图13以及图16所示，各第一颜色子像素010中，主体部分411在基板100的正投影与第一过孔310在基板100的正投影不交叠。这样可以使各第一颜色子像素010中的主体部分411不受第一过孔310的影响，以避免由于第一过孔导致的主体部分411出现不平整的情况，从而可以改善显示面板的色偏现象。
在具体实施时，在本公开实施例中，如图9a、图9b、图10所示，第一颜色子像素010中，主体部分411可以为轴对称图形，并且第一过孔310可以位于主体部分411沿第二方向F2的对称轴上。示例性地，第一颜色子像素010中的主体部分411可以具有沿第二方向F2的第二对称轴。示例性地，第一颜色子像素010中的主体部分411的形状大致为六边形或椭圆形，六边形的长对称轴或椭圆形的长轴与第一方向F1大致平行，六边形的短对称轴或椭圆形的短轴与第二方向F2大致平行，则可以将六边形的短对称轴或椭圆形的短轴作为第二对称轴。示例性地，可以使第一颜色子像素010中的第一过孔 310关于第二对称轴大致呈轴对称设置。也可以使第一颜色子像素010中的第一过孔310仅是与第二对称轴相交，并不是关于第二对称轴大致呈轴对称设置。当然，在实际应用中，可以根据实际应用环境来设计确定第一颜色子像素010中的第一过孔310的实施方式，在此不作限定。
在具体实施时，在本公开实施例中，如图9a、图9b、图10、图14与图17所示，各第一个第二颜色子像素021中，主体部分4121和辅助部分4221相互电连接，辅助部分4221通过第一过孔310与第一连接线2221相互电连接，第一连接线2221与像素驱动电路20中的晶体管的漏极电连接，以将像素驱动电路20产生的电信号输入阳极400，并且还通过对阴极60加载相应的电压，以驱动发光层50发光。
在具体实施时，在本公开实施例中，如图9a、图9b、图10、图15与图17所示，各第二个第二颜色子像素022中，主体部分4122和辅助部分4222相互电连接，辅助部分4222通过第一过孔310与第一连接线2222相互电连接，第一连接线2222与像素驱动电路20中的晶体管的漏极电连接，以将像素驱动电路20产生的电信号输入阳极400，并且还通过对阴极60加载相应的电压，以驱动发光层50发光。
可选地，如图9a、图9b、图10、图14至图17所示，各第二颜色子像素中，主体部分在基板的正投影与第一过孔在基板的正投影不交叠。示例性地，如图9a、图9b、图10、图14与图17所示，第一个第二颜色子像素021中，主体部分4121在基板100的正投影与第一过孔310在基板100的正投影不交叠。这样可以使各第一个第二颜色子像素021中的主体部分4121不受第一过孔310的影响，以避免由于第一过孔310导致的主体部分4121出现不平整的情况，从而可以改善显示面板的色偏现象。
示例性地，如图9a、图9b、图10、图15与图17所示，第二个第二颜色子像素021中，主体部分4122在基板100的正投影与第一过孔310在基板100的正投影不交叠。这样可以使各第二个第二颜色子像素022中的主体部分4122不受第一过孔310的影响，以避免由于第一过孔310导致的主体部分4122出 现不平整的情况，从而可以改善显示面板的色偏现象。
在具体实施时，在本公开实施例中，如图9a至图10所示，同一重复单元001中，第一个第二颜色子像素021的第一过孔310靠近第一颜色子像素010的一侧设置，第二个第二颜色子像素022的第一过孔310靠近第一颜色子像素010的另一侧设置。即第一个第二颜色子像素021的第一过孔310和第二个第二颜色子像素022的第一过孔310分别位于第一颜色子像素010的两侧。示例性地，同一重复单元001中，第一个第二颜色子像素021的第一过孔310可以设置于该重复单元001中的第一颜色子像素010中的主体部分411以及与该主体部分411左侧相邻的第三颜色子像素030中的主体部分413之间。并且，同一重复单元001中，第二个第二颜色子像素022的第一过孔310可以设置于该重复单元001中的第一颜色子像素010中的主体部分411以及与该主体部分411右侧相邻的第三颜色子像素030中的主体部分413之间。
可选地，在具体实施时，在本公开实施例中，如图9a至图10所示，同一重复单元001中，第一颜色子像素010的第一过孔310、第二颜色子像素对020中的第一个第二颜色子像素021的第一过孔310以及第二个第二颜色子像素022的第一过孔310沿第一方向F1排列于同一直线上。示例性地，第二列重复单元组的一个重复单元001中，第一颜色子像素010的第一过孔310、第二颜色子像素对020中的第一个第二颜色子像素021的第一过孔310以及第二个第二颜色子像素022的第一过孔310，可以使这三个第一过孔310沿第一方向F1排列于同一直线上，从而可以降低制备这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
可选地，在具体实施时，在本公开实施例中，如图9a至图10所示，同一重复单元001中的第三颜色子像素030的第一过孔310和第一颜色子像素010的第一过孔310沿第二方向F2排列于同一直线上。这样也可以降低制备这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
可选地，在具体实施时，在本公开实施例中，如图9a至图10所示，同一重复单元组中，第三颜色子像素030的第一过孔310和第一颜色子像素010 的第一过孔310沿第二方向F2排列于同一直线上。并且，同一重复单元组中，各第二颜色子像素对020中的第一个第二颜色子像素021的第一过孔310沿第二方向F2排列于同一直线上。以及同一重复单元组中，各第二颜色子像素对020中的第二个第二颜色子像素022的第一过孔310沿第二方向F2排列于同一直线上。这样也可以降低制备这些第一过孔310时使用的掩膜版(Mask)的设计难度。
在具体实施时，在本公开实施例中，如图9a至图10所示，奇数类重复单元组中，同一行重复单元001中的第一颜色子像素010的第一过孔310、第二颜色子像素对020中的第一个第二颜色子像素021的第一过孔310以及第二个第二颜色子像素022的第一过孔310沿第一方向F1排列于同一直线上。这样也可以降低制备显示面板中的这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
在具体实施时，在本公开实施例中，如图9a至图10所示，奇数类重复单元组中，同一行重复单元001中的第三颜色子像素030的第一过孔310沿第一方向F1排列于同一直线上。这样也可以降低制备显示面板中的这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
在具体实施时，在本公开实施例中，如图9a至图10所示，偶数类重复单元组中，同一行重复单元001中的第一颜色子像素010的第一过孔310、第二颜色子像素对020中的第一个第二颜色子像素021的第一过孔310以及第二个第二颜色子像素022的第一过孔310沿第一方向F1排列于同一直线上。这样也可以降低制备显示面板中的这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
在具体实施时，在本公开实施例中，如图9a至图10所示，偶数类重复单元组中，同一行重复单元001中的第三颜色子像素030的第一过孔310沿第一方向F1排列于同一直线上。这样也可以降低制备显示面板中的这三个第一过孔310时使用的掩膜版(Mask)的设计难度。
并且，需要说明的是，本实施例中的第一过孔的实施方式也可以参见上 述实施例中第一过孔的实施方式，在此不作赘述。
需要说明的是，由于工艺条件的限制或其他因素，上述各特征中的相同并不能完全相同，可能会有一些偏差，因此上述各特征之间的相同关系只要大致满足上述条件即可，均属于本发明的保护范围。例如，上述相同可以是在误差允许范围之内所允许的相同。
并且，由于工艺条件的限制或其他因素，也并不能使上述不同过孔完全沿第一方向或第二方向排列于一条直线上，可能会有一些偏差，因此上述排列于一条直线上的关系只要大致满足上述条件即可，均属于本发明的保护范围。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述电致发光显示面板。该显示装置解决问题的原理与前述电致发光显示面板相似，因此该显示装置的实施可以参见前述电致发光显示面板的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的电致发光显示面板及显示装置，通过使阳极包括相互电连接的主体部分和辅助部分，采用辅助部分通过第一过孔与第一导电层电连接，以使阳极通过第一导电层与像素驱动电路相互电连接。并且，由于至少一个子像素中，主体部分在基板的正投影与第一过孔在基板的正投影不交叠，可以使该子像素中的第一过孔进行避让，以使该子像素中阳极的主体部分不受第一过孔的深度影响，从而避免阳极的主体部分出现凹陷，以避免由于第一过孔导致的阳极不平整的情况出现，进而改善显示面板的色偏现象。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些 改动和变型在内。

Claims (55)

  1. 一种电致发光显示面板，其中，包括：
    多个重复单元，各所述重复单元包括多个子像素，各所述子像素包括：
    第一导电层，位于基板上方；
    第一绝缘层，位于所述第一导电层上方，并且包括第一过孔，所述第一过孔暴露所述第一导电层的一部分；
    阳极，位于所述第一绝缘层上，并且包括相互电连接的主体部分和辅助部分；所述辅助部分通过所述第一过孔与所述第一导电层电连接；
    至少一个所述子像素中，所述主体部分在所述基板的正投影与所述第一过孔在所述基板的正投影不交叠；
    至少一个所述子像素中，所述主体部分在第一方向的尺寸大于在第二方向的尺寸，且至少一个所述子像素中，所述第一过孔与所述主体部分在所述第二方向上排布；其中，所述第一方向与所述第二方向不同。
  2. 如权利要求1所述的电致发光显示面板，其中，所述第一导电层包括：相互间隔设置的第一电源线和第一连接线；
    各所述子像素中，所述辅助部分通过所述第一过孔与所述第一连接线电连接。
  3. 如权利要求2所述的电致发光显示面板，其中，所述第一电源线包括：沿所述第一方向排列且沿所述第二方向延伸的多个子电源线，以及电连接各个所述子电源线的导通线。
  4. 如权利要求3所述的电致发光显示面板，其中，所述子电源线与所述导通线大致形成网格结构，每个网格内部设置有一个所述第一连接线，且所述第一连接线与所述子电源线和所述导通线之间均有间隔。
  5. 如权利要求3或4所述的电致发光显示面板，其中，所述多个重复单元中的至少一个重复单元包括：沿所述第二方向排列的一个第一颜色子像素、一个第二颜色子像素对以及一个第三颜色子像素；其中，所述第二颜色子像 素对包括沿所述第一方向排列的两个第二颜色子像素；
    所述多个重复单元沿所述第二方向排列形成重复单元组，所述重复单元组沿所述第一方向排列，且相邻两个所述重复单元组中的重复单元错位排列。
  6. 如权利要求5所述的电致发光显示面板，其中，各所述子像素还包括：位于第一导电层面向所述基板一侧的像素驱动电路；其中，各所述子像素中像素驱动电路阵列分布。
  7. 如权利要求6所述的电致发光显示面板，其中，第一颜色子像素的主体部分的延伸方向与第一颜色子像素的像素驱动电路所在区域的长度方向之间具有第一夹角；其中，所述第一夹角在45度至165度之间；
    第三颜色子像素的主体部分的延伸方向与第三颜色子像素的像素驱动电路所在区域的长度方向之间具有第二夹角；其中，所述第二夹角在45度至165度之间；
    第二颜色子像素对的延伸方向与第二颜色子像素对的像素驱动电路所在区域的长度方向之间具有第三夹角；其中，所述第三夹角在45度至165度之间。
  8. 如权利要求7所述的电致发光显示面板，其中，各所述像素驱动电路中的各层图案所在区域在所述第二方向上的尺寸大于在第一方向上的尺寸。
  9. 如权利要求4-8任一项所述的电致发光显示面板，其中，所述第一颜色子像素的主体部分在所述第二方向上的尺寸小于所述第三颜色子像素的主体部分在所述第二方向上的尺寸；
    所述第一颜色子像素的主体部分在所述第一方向上的尺寸大于所述第三颜色子像素的主体部分在所述第一方向上的尺寸。
  10. 如权利要求4-9任一项所述的电致发光显示面板，其中，各所述第三颜色子像素中，所述主体部分在所述基板的正投影与所述第一过孔在所述基板的正投影不交叠。
  11. 如权利要求10所述的电致发光显示面板，其中，所述第三颜色子像素中，所述主体部分为轴对称图形，且所述第一过孔位于所述主体部分沿所 述第二方向的对称轴上。
  12. 如权利要求6-11任一项所述的电致发光显示面板，其中，所述第三颜色子像素中，所述主体部分在所述基板的正投影与所述像素驱动电路中的驱动晶体管不交叠，所述主体部分在所述基板的正投影与所述像素驱动电路相邻的下一行像素驱动电路电连接的复位控制信号线和复位电源信号线在所述基板的正投影交叠，所述主体部分在所述基板的正投影与两条数据线在所述基板的正投影交叠，所述主体部分在所述基板的正投影与两条第二电源线在所述基板的正投影交叠。
  13. 如权利要求4-12任一项所述的电致发光显示面板，其中，各所述第一颜色子像素中，所述主体部分在所述基板的正投影与所述第一过孔在所述基板的正投影不交叠。
  14. 如权利要求13所述的电致发光显示面板，其中，所述第一颜色子像素中，所述主体部分为轴对称图形，且所述第一过孔位于所述主体部分沿所述第二方向的对称轴上。
  15. 如权利要求14所述的电致发光显示面板，其中，所述第一颜色子像素中，所述主体部分在所述基板的正投影与所述像素驱动电路中的驱动晶体管交叠，所述主体部分在所述基板的正投影与所述像素驱动电路电连接的发光控制信号线在所述基板的正投影交叠，所述主体部分在所述基板的正投影与两条数据线在所述基板的正投影交叠，所述主体部分在所述基板的正投影与两条第二电源线在所述基板的正投影交叠。
  16. 如权利要求4-15任一项所述的电致发光显示面板，其中，各所述第二颜色子像素中，所述主体部分在所述基板的正投影与所述第一过孔在所述基板的正投影不交叠。
  17. 如权利要求16所述的电致发光显示面板，其中，所述第二颜色子像素对包括第一个第二颜色子像素和第二个第二颜色子像素；同一所述重复单元中，所述第一个第二颜色子像素的第一过孔位于所述第一个第二颜色子像素背离所述第三颜色子像素一侧；
    同一所述重复单元中，所述第二个第二颜色子像素的第一过孔位于所述第二个第二颜色子像素背离所述第三颜色子像素一侧。
  18. 如权利要求17所述的电致发光显示面板，其中，针对同一重复单元中的第一颜色子像素和第一个第二颜色子像素，以及针对与所述同一重复单元中的第一颜色子像素和第一个第二颜色子像素均最近邻的第三颜色子像素，所述第一个第二颜色子像素的第一过孔位于所述第一颜色子像素与所述第三颜色子像素之间的间隙中；
    针对同一重复单元中的第一颜色子像素和第二个第二颜色子像素，以及针对与所述同一重复单元中的第一颜色子像素和第二个第二颜色子像素均最近邻的第三颜色子像素，所述第二个第二颜色子像素的第一过孔位于所述第一颜色子像素与所述第三颜色子像素之间的间隙中。
  19. 如权利要求17所述的电致发光显示面板，其中，所述第一个第二颜色子像素中，所述主体部分在所述基板的正投影与所述像素驱动电路中的驱动晶体管无交叠，所述主体部分在所述基板的正投影与所述像素驱动电路相邻的下一行像素驱动电路电连接的复位控制信号线和扫描信号线在所述基板的正投影交叠；
    所述第二个第二颜色子像素中，所述主体部分在所述基板的正投影与所述像素驱动电路中的驱动晶体管无交叠，所述主体部分在所述基板的正投影与所述像素驱动电路相邻的下一行像素驱动电路电连接的复位控制信号线和扫描信号线在所述基板的正投影交叠。
  20. 如权利要求17-19任一项所述的电致发光显示面板，其中，所述第三颜色子像素中的像素驱动电路、所述第一个第二颜色子像素中的像素驱动电路、所述第一颜色子像素中的像素驱动电路以及所述第二个第二颜色子像素中的像素驱动电路沿第一方向依次排布。
  21. 如权利要求4-20任一项所述的电致发光显示面板，其中，同种颜色子像素中的第一过孔位于所述颜色子像素的同一侧。
  22. 如权利要求4-21任一项所述的电致发光显示面板，其中，同一所述 重复单元中，所述第一个第二颜色子像素的第一过孔、所述第一颜色子像素的第一过孔以及所述第二个第二颜色子像素的第一过孔沿所述第一方向顺序排列于同一第一子折线上；
    针对一个重复单元组中的第一颜色子像素和相邻重复单元组中且与所述第一颜色子像素最近邻的第三颜色子像素，所述第一颜色子像素的第一过孔和所述第三颜色子像素的第一过孔沿第三方向排列于同一第二子折线上；其中，所述第三方向与所述第一方向交叉。
  23. 如权利要求22所述的电致发光显示面板，其中，所述折线包括：所述第一子折线和所述第二子折线；不同列中的相邻的两个重复单元中，第一个重复单元中的第三颜色子像素的第一过孔与第二个重复单元中的所述第一个第二颜色子像素的第一过孔、所述第一颜色子像素的第一过孔以及所述第二个第二颜色子像素的第一过孔依次顺序排列于折线上。
  24. 如权利要求23所述的电致发光显示面板，其中，同一所述重复单元中的所述第三颜色子像素的第一过孔和所述第一颜色子像素的第一过孔沿所述第二方向排列于同一直线上。
  25. 如权利要求24所述的电致发光显示面板，其中，不同列且相邻的两个重复单元中，一个重复单元中的第一个第二颜色子像素的第一过孔与另一个重复单元中的第二个第二颜色子像素的第一过孔沿所述第二方向排列于同一直线上。
  26. 如权利要求4-25任一项所述的电致发光显示面板，其中，奇数类重复单元组和偶数类重复单元组中的至少一类重复单元组中，同一行重复单元中的所述第一颜色子像素的第一过孔、所述第二颜色子像素对中的第一个第二颜色子像素的第一过孔以及第二个第二颜色子像素的第一过孔沿所述第一方向排列于同一直线上；
    并且，奇数类重复单元组和偶数类重复单元组中的至少一类重复单元组中，同一行重复单元中的所述第三颜色子像素的第一过孔沿所述第一方向排列于同一直线上。
  27. 如权利要求2-26任一项所述的电致发光显示面板，其中，所述电致发光显示面板还包括：
    第二导电层，位于所述第一导电层与所述基板之间，并且包括：间隔设置的第二电源线和第二连接线；
    第二绝缘层，位于所述第二导电层与所述第一导电层之间，并且具有暴露所述第二连接线的第二过孔以及暴露所述第二电源线的一部分的第三过孔；
    所述第一连接线通过所述第二过孔与所述第二连接线彼此电连接；
    所述第一电源线通过所述第三过孔与所述第二电源线彼此电连接。
  28. 如权利要求27所述的电致发光显示面板，其中，针对相互电连接的所述第一连接线和所述第二连接线，所述第一连接线在所述基板的正投影与所述第二连接线在所述基板的正投影至少部分交叠；
    所述第一电源线在所述基板的正投影与所述第二电源线在所述基板的正投影至少部分交叠。
  29. 如权利要求28所述的电致发光显示面板，其中，所述第三颜色子像素中，所述第一过孔相对所述第二过孔靠近像素驱动电路中的驱动晶体管设置；
    所述第一颜色子像素中，所述第一过孔相对所述第二过孔远离像素驱动电路中的驱动晶体管设置；
    所述第二颜色子像素中，所述第一过孔相对所述第二过孔远离像素驱动电路中的驱动晶体管设置。
  30. 如权利要求27-29任一项所述的电致发光显示面板，其中，同一所述子像素中，所述第一过孔在所述基板的正投影与所述第二过孔在所述基板的正投影大致不交叠。
  31. 如权利要求27-30任一项所述的电致发光显示面板，其中，各所述子像素还包括：第四过孔；
    所述第三颜色子像素中，所述第四过孔在所述基板的正投影与所述第二过孔在所述基板的正投影交叠；
    所述第一颜色子像素中，所述第四过孔在所述基板的正投影与所述第一过孔在所述基板的正投影交叠；
    所述第二颜色子像素中，所述第四过孔在所述基板的正投影与所述第一过孔在所述基板的正投影交叠。
  32. 如权利要求31所述的电致发光显示面板，其中，所述第四过孔沿第一方向排列于一条直线上，且位于同一直线上相邻的两个第四过孔之间的间距大致相同。
  33. 如权利要求32所述的电致发光显示面板，其中，沿所述第一方向上的相邻的两个第一过孔之间的间距大致相同，沿所述第二方向上的相邻的两个第一过孔之间的间距大致相同；
    沿所述第一方向上的相邻的两个第二过孔之间的间距大致相同，沿所述第二方向上的相邻的两个第二过孔之间的间距大致相同。
  34. 如权利要求6-33任一项所述的电致发光显示面板，其中，所述第三颜色子像素中，所述第一过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影交叠，且所述第二过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠，以及所述第四过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠。
  35. 如权利要求6-34任一项所述的电致发光显示面板，其中，所述第一颜色子像素中，所述第一过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠，且所述第二过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影交叠，以及所述第四过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠。
  36. 如权利要求6-34任一项所述的电致发光显示面板，其中，所述第二颜色子像素中，所述第一过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠，且所述第二过孔在所述基板的 正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影交叠，以及所述第四过孔在所述基板的正投影与所述驱动电路电连接的发光控制信号线在所述基板的正投影不交叠。
  37. 如权利要求26-36任一项所述的电致发光显示面板，其中，所述第三颜色子像素中，所述主体部分在所述基板的正投影与所述第二过孔在所述基板的正投影至少部分交叠。
  38. 如权利要求37所述的电致发光显示面板，其中，所述第三颜色子像素中，所述主体部分在所述基板的正投影与两个第三过孔在所述基板的正投影至少部分交叠。
  39. 如权利要求38所述的电致发光显示面板，其中，所述第三颜色子像素中，所述第一过孔靠近与所述主体部分在所述基板的正投影交叠的所述两个第三过孔的中心线的一侧设置，并且所述第二过孔靠近与所述主体部分在所述基板的正投影交叠的所述两个第三过孔的中心线的另一侧设置。
  40. 如权利要求27-39任一项所述的电致发光显示面板，其中，所述第三颜色子像素中，所述主体部分为轴对称图形，并且所述第二过孔位于所述主体部分沿所述第二方向的对称轴上。
  41. 如权利要求27-40任一项所述的电致发光显示面板，其中，所述第一颜色子像素中，所述主体部分在所述基板的正投影与所述第二过孔在所述基板的正投影至少部分交叠。
  42. 如权利要求41所述的电致发光显示面板，其中，所述第一颜色子像素中，所述主体部分在所述基板的正投影与两个第三过孔在所述基板的正投影至少部分交叠。
  43. 如权利要求42所述的电致发光显示面板，其中，所述第一颜色子像素中，所述第一过孔靠近正投影交叠的所述两个第三过孔的中心线的一侧设置，并且所述第二过孔靠近正投影交叠的所述两个第三过孔的中心线的另一侧设置。
  44. 如权利要求27-43任一项所述的电致发光显示面板，其中，所述第一 颜色子像素中，所述主体部分为轴对称图形，并且所述第二过孔位于所述主体部分沿所述第二方向的对称轴上。
  45. 如权利要求25所述的电致发光显示面板，其中，针对同一重复单元中的第一颜色子像素和第一个第二颜色子像素，以及针对与所述同一重复单元中的第一颜色子像素和第一个第二颜色子像素均最近邻的第三颜色子像素，所述第一个第二颜色子像素的第二过孔位于所述第一颜色子像素与所述第三颜色子像素之间的间隙中；
    针对同一重复单元中的第一颜色子像素和第二个第二颜色子像素，以及针对与所述同一重复单元中的第一颜色子像素和第二个第二颜色子像素均最近邻的第三颜色子像素，所述第二个第二颜色子像素的第二过孔位于所述第一颜色子像素与所述第三颜色子像素之间的间隙中。
  46. 如权利要求45所述的电致发光显示面板，其中，所述第一个第二颜色子像素中，所述第一过孔和所述第二过孔沿所述第二方向排列于同一直线上；所述第二个第二颜色子像素中，所述第一过孔和所述第二过孔沿所述第二方向排列于同一直线上。
  47. 如权利要求46所述的电致发光显示面板，其中，所述第一个第二颜色子像素中，所述第二过孔位于所述第一过孔背离所述主体部分一侧；
    所述第二个第二颜色子像素中，所述第二过孔位于所述第一过孔背离所述主体部分一侧。
  48. 如权利要求27-47任一项所述的电致发光显示面板，其中，奇数列重复单元组中的第三颜色子像素的第二过孔与偶数列重复单元组中的第一颜色子像素的第一过孔、第一个第二颜色子像素的第一过孔以及第二个第二颜色子像素的第一过孔沿所述第一方向排列于同一直线上。
  49. 如权利要求27-48任一项所述的电致发光显示面板，其中，所述第三颜色子像素中，所述主体部分在所述基板的正投影覆盖两条子电源线在所述基板的正投影；并且与所述主体部分在所述基板的正投影交叠的所述两条子电源线平行设置于所述主体部分的中心的两侧。
  50. 如权利要求49所述的电致发光显示面板，其中，所述第一颜色子像素中，所述主体部分在所述基板的正投影覆盖两条子电源线在所述基板的正投影；并且与所述主体部分在所述基板的正投影交叠的所述两条子电源线平行设置于所述主体部分的中心的两侧。
  51. 如权利要求50所述的电致发光显示面板，其中，所述第二颜色子像素中，所述主体部分在所述基板的正投影与一条所述子电源线以及与所述子电源线电连接的导通线在所述基板的正投影至少部分交叠。
  52. 如权利要求2-26任一项所述的电致发光显示面板，其中，所述第一导电层包括：相互间隔设置的第一电源线、第一连接线以及数据线；
    各所述子像素中，所述辅助部分通过所述第一过孔与所述第一连接线电连接。
  53. 如权利要求52所述的电致发光显示面板，其中，所述第一电源线和所述数据线沿第一方向排列且沿第二方向延伸；并且所述第一方向与所述第二方向不同。
  54. 如权利要求2-53任一项所述的电致发光显示面板，其中，所述第一电源线被配置为传输驱动电压的电源线。
  55. 一种显示装置，其中，包括如权利要求1-54任一项所述的电致发光显示面板。
PCT/CN2019/098731 2019-07-31 2019-07-31 电致发光显示面板及显示装置 WO2021016956A1 (zh)

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JP2019569405A JP2022550491A (ja) 2019-07-31 2019-07-31 エレクトロルミネセント表示パネル、及び表示装置
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US17/274,229 US20210320156A1 (en) 2019-07-31 2020-07-31 Display substrate and display device
US17/274,939 US12027124B2 (en) 2019-07-31 2020-07-31 Display substrate and display device
CN202080001429.6A CN113056828A (zh) 2019-07-31 2020-07-31 显示基板以及显示装置
PCT/CN2020/106429 WO2021018304A1 (zh) 2019-07-31 2020-07-31 显示基板以及显示装置
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US17/828,211 US11776479B2 (en) 2019-07-31 2022-05-31 Display substrate and display device
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