WO2021004439A1 - 时钟信号的相位检测方法、装置及通信设备 - Google Patents

时钟信号的相位检测方法、装置及通信设备 Download PDF

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Publication number
WO2021004439A1
WO2021004439A1 PCT/CN2020/100503 CN2020100503W WO2021004439A1 WO 2021004439 A1 WO2021004439 A1 WO 2021004439A1 CN 2020100503 W CN2020100503 W CN 2020100503W WO 2021004439 A1 WO2021004439 A1 WO 2021004439A1
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Prior art keywords
phase
clock
value
sampling
detected
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PCT/CN2020/100503
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English (en)
French (fr)
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刘俊
韦兆碧
王珊
雷梦毕
张国俊
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中兴通讯股份有限公司
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Priority to US17/625,207 priority Critical patent/US11700108B2/en
Priority to EP20836462.0A priority patent/EP3998719A4/en
Publication of WO2021004439A1 publication Critical patent/WO2021004439A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements

Definitions

  • the present invention relates to the field of communication technology, and in particular to a phase detection method, device and communication equipment of a clock signal.
  • Massive MIMO technology in multi-array antenna base stations is a key technology in 4.5G and 5G communications.
  • SDMA Space Division Multiple Access
  • 5G communications Space Division Multiple Access (SDMA, Space Division Multiple Access) is an important example of the application of Massive MIMO technology.
  • SDMA uses beamforming technology to concentrate the signal energy in a specific direction, thereby increasing spectrum utilization efficiency and reducing interference to other receivers.
  • Beamforming has stringent requirements on the phase difference between the multiple channels of the transceiver. For example, the phase difference between the multiple channels of a sub 6G 5G base station transceiver should be less than 5°. Therefore, the wireless base station system will adopt a series of phase detection and adjustment measures to reduce the phase error between channels, and then align the phase of the multi-channel signal.
  • phase synchronization mechanism In the phase synchronization mechanism, the detection of the phase of the RF clock signal is the first step, and the phase detection accuracy of the RF clock signal directly affects the effect of multi-channel synchronization.
  • phase detection accuracy of the RF clock signal directly affects the effect of multi-channel synchronization.
  • the embodiment of the present invention provides a clock signal phase detection method, device, and communication equipment to solve how to accurately detect the phase of the radio frequency clock signal, thereby ensuring the phase synchronization effect.
  • an embodiment of the present invention provides a method for detecting the phase of a clock signal, including:
  • the clock signal of the clock to be detected is sampled according to the sampling period set by the sampling clock;
  • phase angle value is subtracted from the phase difference value corresponding to the current sampling period to obtain the initial phase value of the to-be-detected clock in the current sampling period, and the phase difference is the value of the to-be-detected clock and the sampling clock in the current sampling The phase difference of the period;
  • the final phase value of the clock to be detected is obtained according to the initial phase value obtained in each sampling period.
  • an embodiment of the present invention also provides a clock signal phase detection device, including:
  • the sampling module is configured to sample the clock signal of the clock to be detected according to the sampling period set by the sampling clock;
  • the coarse phase calculation module is set to obtain the phase angle value corresponding to the clock signal sampled in the current sampling period according to the mapping relationship between the sampling signal and the phase angle value; and set to subtract the phase angle value corresponding to the current sampling period from the phase angle value Value to obtain the initial phase value of the clock to be detected in the current sampling period, and the phase difference value is the phase difference value between the clock to be detected and the sampling clock in the current sampling period;
  • the phase statistics module is configured to obtain the final phase value of the clock to be detected according to the initial phase value obtained in each sampling period after the sampling ends.
  • an embodiment of the present invention also provides a communication device, which includes at least one phase detection device of a clock signal as described above.
  • the clock signal of the clock to be detected is sampled according to the sampling period set by the sampling clock, and the current sampling signal is obtained according to the mapping relationship between the sampling signal and the phase angle value.
  • the phase angle value corresponding to the clock signal sampled in the sampling period is subtracted from the phase difference value corresponding to the current sampling period to obtain the initial phase value of the clock to be detected in the current sampling period.
  • the phase difference is the value of the clock to be detected and the sampling clock
  • the phase difference value in the current sampling period; after the end of the sampling, the final phase value of the clock to be detected can be obtained according to the initial phase value obtained in each sampling period; because the final phase value is the initial phase obtained from multiple sampling periods
  • the obtained final phase value has both higher accuracy and better fault tolerance, which can improve the reliability of the clock signal phase detection method provided by the embodiment of the present invention, and can ensure that when multiple channels are required Phase synchronization effect when phase synchronization.
  • FIG. 1 is a schematic flowchart of a method for detecting a phase of a clock signal according to Embodiment 1 of the present invention
  • FIG. 2 is a schematic diagram of a phase angle value acquisition process in Embodiment 1 of the present invention.
  • 3 is a schematic diagram of the mapping relationship between the digital pulse signal sequence and the phase angle value in the first embodiment of the present invention
  • FIG. 4 is a schematic diagram of sampling point coverage in a normal mode and a high-precision mode according to Embodiment 1 of the present invention
  • FIG. 5 is a schematic diagram of error analysis of the normal mode and the high-precision mode in Embodiment 1 of the present invention.
  • FIG. 6 is a schematic diagram of the structure of a clock signal phase detection device according to the second embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a sampling module according to Embodiment 2 of the present invention.
  • FIG. 8 is a schematic diagram of signal sampling according to Embodiment 2 of the present invention.
  • FIG. 9 is a schematic structural diagram of a phase rough calculation module according to the second embodiment of the present invention.
  • FIG. 10 is a schematic diagram of the initial phase of the first sampling period in the second embodiment of the present invention.
  • FIG. 11 is a schematic diagram of the initial phase of the second sampling period in the second embodiment of the present invention.
  • phase difference accumulation module 12 is a schematic diagram of the structure of the phase difference accumulation module according to the second embodiment of the present invention.
  • FIG. 13 is a schematic structural diagram of a first standardized module according to Embodiment 2 of the present invention.
  • FIG. 15 is a schematic structural diagram of a second standardized module according to Embodiment 2 of the present invention.
  • FIG. 16 is a schematic diagram of the configuration of the phase detection device in the first application scenario of the third embodiment of the present invention.
  • FIG. 17 is a schematic diagram of the configuration of the phase detection device in the second application scenario of the third embodiment of the present invention.
  • FIG. 19 is a schematic diagram of the configuration of the phase detection device in the fourth application scenario of the third embodiment of the present invention.
  • FIG. 21 is a schematic structural diagram of a base station according to Embodiment 4 of the present invention.
  • this embodiment provides a phase detection method of the clock signal, as shown in FIG. 1, including:
  • S101 The clock signal of the clock to be detected is sampled according to the sampling period set by the sampling clock.
  • the clock to be detected in this embodiment may be, but is not limited to, various radio frequency clocks. And for a multi-channel application scenario, and multiple channels use at least two radio frequency clocks, the clock signal generated for each radio frequency clock can use the phase detection method provided in this embodiment.
  • the selection of the sampling clock in this embodiment can be flexibly selected according to the characteristics of the current clock to be detected. For example, it can be flexibly set according to the frequency of the clock to be detected and the current detection accuracy requirements.
  • the number of sampling periods when detecting the clock to be detected, can also be flexibly set according to specific application scenarios. In some examples, it can also be set based on the least common multiple between the frequency of the sampling clock and the frequency of the clock to be detected. For example, the number of sampling periods can be set to 1000, 2000, 3000, 6000, etc.
  • the clock signal of the clock to be detected can be supported as but not limited to any one of the following signal types: single-ended signal, differential signal, and quadrature signal.
  • S102 Obtain the phase angle value corresponding to the clock signal sampled in the current sampling period according to the mapping relationship between the sampling signal and the phase angle value.
  • the mapping relationship between the sampling signal and the phase angle value can be preset.
  • the analog amplitude information clksig can be converted into a discrete digital pulse signal sequence bin.
  • the conversion here in this embodiment can only perform the conversion of the digital pulse signal sequence according to the positive and negative value direction of the amplitude information, and does not involve the extraction of the amplitude information of the clock to be detected. Therefore, even for the clock signal to be detected with a high frequency, High reliability can still be achieved.
  • the preset mapping relationship between the sampling signal and the phase angle value in this embodiment may include: the mapping relationship between the digital pulse signal sequence and the phase angle value;
  • the intermediate value of each interval may be taken as the mapping value of the interval according to the phase interval of the clock signal to be checked at the rising edge of each sampling clock.
  • the mapping relationship between a digital pulse signal sequence and a phase angle value as shown in Figure 3.
  • the clock signal of the clock to be detected is a differential signal or a quadrature signal
  • the corresponding phase angle value is ⁇ /4
  • the output digital pulse signal sequence is 01
  • the corresponding phase angle value is 3 ⁇ /4
  • the output digital pulse signal sequence When it is 00, the corresponding phase angle value is 5 ⁇ /4; when the output digital pulse signal sequence is 00, the corresponding phase angle value is 7 ⁇ /4.
  • the clock signal of the clock to be detected is a single-ended signal, when the output digital pulse signal sequence is 1, the corresponding phase angle value is ⁇ /2; when the output digital pulse signal sequence is 0, the corresponding phase angle value Is 3 ⁇ /2.
  • mapping relationship between the digital pulse signal sequence and the phase angle value in this embodiment is not limited to the above-mentioned example, and can be flexibly set according to requirements.
  • the phase difference corresponding to the current sampling period is the phase difference between the to-be-detected clock and the sampling clock in the current sampling period
  • the calculation method of the phase difference between the to-be-detected clock and the sampling clock may be but not limited to:
  • the phase difference between the clock to be detected and the sampling clock corresponding to a sampling period is calculated
  • the phase difference between the clock to be detected and the sampling clock in the current sampling period is the value obtained by multiplying the phase difference between the clock to be detected and the sampling clock by the current sampling period and dividing by 2 ⁇ to obtain the remainder.
  • the current sampling period is k
  • the phase difference between the clock to be detected and the sampling clock in the current sampling period is:
  • the initial phase value of the clock to be detected in the current sampling period can be obtained, and after k adopting cycles, the initial phase value of k sampling periods can be obtained.
  • the initial phase value obtained in each sampling period is used to obtain the before detecting the final phase value of the clock, the following first standardization process is also included:
  • the initial phase value obtained in the first sampling period (of course, other sampling periods can also be used according to requirements) is a reference, and the initial phase value calculated in the subsequent sampling period is calculated Standardization processing to facilitate accurate determination of the subsequent final phase value.
  • S104 After sampling, obtain the final phase value of the clock to be detected according to the initial phase value obtained in each sampling period.
  • n initial phase values can be obtained after sampling detection for each sampling period of n, which are represented by ⁇ 1 , ⁇ 2 ,..., ⁇ n respectively .
  • obtaining the final phase value of the clock to be detected according to the initial phase value obtained in each sampling period in S104 includes:
  • obtaining the final phase value of the clock to be detected according to the initial phase value obtained in each sampling period in S104 includes:
  • phase detection method of the clock signal allows multiple sampling errors to occur during the sampling process. And optionally, the initial phase value calculated in the first sampling period can be used as a reference, and an error in the first sampling period will affect the final initial phase value. Therefore, optionally, in some application scenarios, after the final phase value of the clock to be detected is obtained, the following second normalization process may be performed on the obtained final phase value:
  • the sampling clock with a higher frequency than the current sampling clock can be updated to sample to increase the frequency of the sampling clock and the least common multiple of the frequency of the clock to be detected, and reduce the frequency of the clock to be detected and the sampling clock The correlation, avoid sampling into the loop.
  • the sampling point can cover the entire [0, 2 ⁇ ) phase interval, increasing the diversity of sampling samples, thereby Significantly improve the phase detection accuracy of the overall phase detection scheme.
  • the phase detection method provided by this embodiment can detect the phase of the clock signal of each detection clock with high accuracy.
  • the phase value of each channel can be detected with high precision, and then the accurate phase difference between each channel can be obtained, which provides an accurate basis for subsequent synchronization control.
  • phase frequency detector Phase and Frequency Detector
  • the PFD is composed of two D flip-flops and a NAND gate.
  • the D flip-flop outputs a high level after receiving the rising edge of the input clock, and is reset after the outputs of the two D flip-flops reach the high level. Therefore, the PFD can output a pulse signal representing the frequency or phase difference between the two input clock signals.
  • the PFD application in the phase detection of the transceiver channel or other scenes has the following difficulties and problems.
  • PFD phase detection will dramatically increase the complexity of the original system.
  • the number of transceiver channels has reached dozens or even hundreds.
  • the same number of PFDs will be used.
  • the MIMO system generally uses multiple chips. The connection between the chip and the PFD will make the layout of the PCB board very complicated, and will reduce the reliability of the circuit.
  • PFD cannot directly or indirectly give phase information of the input clock signal.
  • the PFD characterizes the frequency or phase difference of the two input clock signals as a pulse signal of a certain width, rather than a series of high and low levels or binary sequences. It is difficult for the subsequent digital circuit to convert it into pure phase information. In scenarios where the phase value needs to be directly detected, PFD cannot meet application requirements.
  • the PFD's frequency and phase discrimination capability is greatly challenged.
  • communication technology continues to evolve, and wireless communication frequency bands are developing in the direction of high frequency and large bandwidth.
  • the PFD's frequency and phase discrimination capability has been stretched, not to mention the 5G high frequency band up to 24.25GHz to 29.5GHz.
  • high-frequency clock signals are no longer simple square waves or quasi-square waves. After receiving these signals, the PFD can no longer display its frequency and phase discrimination ability normally or reliably.
  • NCO Numerically Controlled Oscillator
  • digital circuit modules that implement arctangent function.
  • These digital circuit modules can achieve The accuracy is limited. If the number of operation iterations is small, the phase detection accuracy will be greatly restricted. If the number of iterations is large, it will also significantly increase the computing resource overhead.
  • these solutions include complex matrix multiplication and complex conjugate operations, and the algorithm is complex , It is not conducive to the application system to reduce the circuit scale and power consumption.
  • these schemes have quadrature requirements for the two input signals to be detected, so only the phase detection of quadrature signals can be realized.
  • the phase detection method of the clock signal obtaineds a series of discrete binary sequences by sampling the clock signal to be detected, and based on these discrete digital sampling information and the frequency relationship between the clock to be detected and the sampling clock, in each sample Periodically determine the phase interval of the clock to be checked, and obtain a low-precision initial phase value, and then through a large number of sampling and statistical averaging or taking the minimum value, a very high-precision phase value detection is finally realized.
  • the frequency value of the sampling clock can also be flexibly selected, so that the frequency value of the clock to be detected and the frequency value of the sampling clock have a larger least common multiple, so that the accuracy required for detection can be flexibly adjusted according to requirements .
  • the phase detection method provided in this embodiment can realize the phase detection of clock signals in the form of single-ended, differential, or quadrature according to the requirements of application scenarios, has good versatility and compatibility, and is applicable to various application scenarios.
  • the solution provided by this embodiment can converge the final final phase value through statistics of a large amount of data, in which multiple process data errors are allowed, the fault tolerance is high, and the very high reliability of the solution is ensured.
  • the design of the loose sampling circuit required by the solution provided by this embodiment is low in difficulty, and the operating frequency of the subsequent digital circuit can be reduced, thereby improving the ease of implementation of the circuit.
  • the solution provided in this embodiment only involves coarse sampling of the clock to be checked, and does not extract the amplitude information of the clock to be checked. Therefore, even for a signal to be checked with a high frequency, higher reliability can still be achieved.
  • the rest of the circuits are all digital circuits, and the sampling circuit can also use a digital form, namely TSPC (True Single Phase Clock, TSPC) or CML ( Current Mode Logic (Current Mode Logic) triggers are implemented, so the overall circuit scheme is not sensitive to PVT (Process Voltage Temperature) changes, and can achieve higher robustness.
  • TSPC Truste Single Phase Clock, TSPC
  • CML Current Mode Logic (Current Mode Logic) triggers are implemented, so the overall circuit scheme is not sensitive to PVT (Process Voltage Temperature) changes, and can achieve higher robustness.
  • PVT Process Voltage Temperature
  • This embodiment provides a clock signal phase detection device, which can implement but is not limited to the clock signal phase detection method shown in the foregoing embodiment. And the phase detection device can be installed in various communication devices with clocks. See Figure 6, which includes:
  • the sampling module 61 is configured to sample the clock signal of the clock to be detected according to the sampling period set by the sampling clock.
  • the clock to be detected in this embodiment may be, but is not limited to, various radio frequency clocks. And for a multi-channel application scenario, and multiple channels use at least two radio frequency clocks, the clock signal generated for each radio frequency clock can be detected by the phase detection device provided in this embodiment, and one radio frequency clock can be used accordingly One phase detection device, or multiple radio frequency clocks can correspond to a common phase detection device.
  • the selection of the sampling clock in this embodiment can be flexibly selected according to the characteristics of the current clock to be detected. For example, it can be flexibly set according to the frequency of the clock to be detected and the current detection accuracy requirements.
  • the sampling module 61 may include a core sampler and a post-stage waveform shaper, with the purpose of converting the input analog amplitude information into discrete digital pulse signals.
  • the core sampler can be implemented by triggers in the form of TSPC or CML.
  • the latter-stage waveform shaper can be realized by Schmitt trigger or inverter circuit, and is set to signal swing amplification and waveform shaping. According to the type of the clock signal to be tested, the sampler can be selected as differential, single-ended, or quadrature.
  • a sampling clock of a certain frequency can be selected to weaken the correlation between the clock to be detected and the frequency of the sampling clock, that is, to increase the least common multiple of the clock frequency to be detected and the frequency of the sampling clock.
  • the sampling module 61 includes a sampler 610 composed of triggers such as TSPC or CML, and also includes a waveform shaper 611.
  • the waveform shaper 611 corresponds to the sampler 610.
  • the output signal undergoes swing amplitude amplification and waveform shaping, and outputs an ideal digital pulse signal bin.
  • the sampler 610 samples the to-be-detected clock at the rising edge of each sampling clock clkref, and outputs 0 if the sampling level is higher than or equal to the common-mode level. If the sampling level is lower than the common mode level, 1 is output, and the digital pulse signal bin corresponding to the output in each sampling period is shown in the table on the right in Figure 8.
  • the phase rough calculation module 62 is set to obtain the phase angle value corresponding to the clock signal sampled in the current sampling period according to the mapping relationship between the sampling signal and the phase angle value; and set to subtract the phase angle value corresponding to the current sampling period from the phase angle value
  • the initial phase value of the clock to be detected in the current sampling period is obtained, and the phase difference is the phase difference between the clock to be detected and the sampling clock in the current sampling period.
  • the mapping relationship between the sampling signal and the phase angle value can be set in advance, and can be set through the corresponding register.
  • the preset mapping relationship between the sampling signal and the phase angle value in this embodiment may include: the mapping relationship between the digital pulse signal sequence and the phase angle value.
  • the phase rough calculation module 62 includes an angle mapper 620, a normalizer 621, and a subtractor 622 inside.
  • the angle mapper 620 obtains the phase angle value corresponding to the current sampling signal according to the mapping relationship between the input digital pulse signal bin and the digital pulse signal sequence written by the register reg and the phase angle value.
  • the subtractor 622 subtracts the phase angle value obtained by the angle mapper 620 from the phase difference value corresponding to the current sampling period to obtain the initial phase value of the clock to be detected in the current sampling period.
  • the phase detection device also includes a phase difference accumulation module 64, which is set to multiply the phase difference value between the clock to be detected and the sampling clock by the current number of sampling cycles (also can be superimposed cycle by cycle). Cumulative phase difference Send to the phase rough calculation module.
  • the normalizer 621 of the rough phase calculation module 62 is set to calculate the accumulated phase difference Divide by 2 ⁇ and take the remainder to get the phase difference corresponding to the current sampling period, namely So as to The value is normalized to between 0 and 2 ⁇ .
  • the subtractor 622 normalizes the phase angle value and The subtraction of, the initial phase value ⁇ x * is obtained for output.
  • the initial phase value output by the phase rough calculation module 62 in the first sampling period T 1 is ⁇ 1 in Fig. 10
  • the initial phase value output by the phase rough calculation module 62 in the second sampling period T 2 The initial phase value is ⁇ 2 in Figure 11, and so on for subsequent periods.
  • the phase difference accumulating module 64 can be implemented based on an adder or a multiplier. According to the frequency relationship between the clock signal to be checked and the sampling clock signal and the number of sampling cycles experienced, statistics are collected since the sampling operation is triggered. The accumulated phase difference between the clock and the clock to be detected.
  • the phase difference accumulation module 64 includes a sampling period phase difference calculator 640 and an adder 641. The sampling period phase difference calculator 640 is set to calculate the difference between the sampling clock of a single sampling period and the clock to be detected.
  • the phase difference value for example, the sampling period phase difference calculator 640 calculates the phase difference value between the test clock and the sampling clock in a single sampling period according to the relationship between the sampling clock frequency value val ref and the to-be-detected clock frequency value val sig
  • the adder 641 is set to accumulate the obtained phase difference value to obtain the accumulated phase difference corresponding to the current sampling period.
  • the phase detection device may further include a first normalization module 65 configured to obtain, in the phase rough calculation module 62, that the initial phase value of the clock to be detected in the current sampling period is greater than the initial phase value obtained in the first sampling period When the phase value is added to ⁇ , the initial phase value obtained in the current sampling period is subtracted by 2 ⁇ and sent to the phase statistics module; the initial phase value of the clock to be detected in the current sampling period is less than the initial phase obtained in the first sampling period in the phase rough calculation module When the value is subtracted by ⁇ , the initial phase value obtained in the current sampling period is added by 2 ⁇ and then sent to the phase statistics module 63.
  • a first normalization module 65 configured to obtain, in the phase rough calculation module 62, that the initial phase value of the clock to be detected in the current sampling period is greater than the initial phase value obtained in the first sampling period
  • the initial phase value obtained in the current sampling period is subtracted by 2 ⁇ and sent to the phase statistics module
  • the initial phase value of the clock to be detected in the current sampling period is less
  • a first standardization module 65 includes a first determiner 650 and a first scaler 651. As shown in FIG. 14, the first determiner 650 uses the initial phase angle value ⁇ 1 * value obtained in the first sampling period as a reference, and determines the value of ⁇ x * every subsequent time.
  • the second normalization module 66 is configured to add 2 ⁇ to the final phase value when the final phase value obtained by the phase statistics module 63 is less than 0.
  • a second standardization module 66 includes a second determiner 660 and a second scaler 661.
  • the phase detection device also includes a control module 67, which can be configured to update a sampling clock with a frequency greater than that of the current sampling clock when it is determined that the detected phase error is greater than the preset error threshold according to the final phase value. Sampling is performed to increase the least common multiple of the frequency of the sampling clock and the frequency of the clock to be detected.
  • the control module 67 can also be set to configure the number of sampling cycles val sam to achieve control such as enabling and resetting of other modules in FIG. 6.
  • phase detection device of the clock signal provided by this embodiment can achieve high-precision detection of the phase of the clock signal of the radio frequency clock, so that the radio frequency clock can be used in scenarios that require phase synchronization such as multiple channels. Meet phase synchronization requirements more accurately and improve communication performance.
  • the configuration of the phase detection device for this application scenario is shown in Figure 16.
  • the clock signal of the clock to be detected is a single-ended signal, and its frequency is set to 2GHz, and a clock signal with a frequency of 122.88MHz commonly used in the system (ie sampling The frequency of the clock is 122.88MHz) for sampling.
  • Configure the val ref of the phase difference accumulation module 64 to 122.88x10 6 and val sig to 2x10 9 , and the phase difference between the to-be-detected clock and the sampling clock in a single sampling period can be calculated as:
  • the bin outputted by the sampling module 61 every sampling period is 1bit data, and the angle mapping relationship in the phase rough calculation module 62 is shown in Table 1:
  • the phase of the clock to be detected at the initial time of sampling is 130°
  • the number of sampling cycles val sum configured by the control module 67 is 6000.
  • the initial phase ⁇ 0 of the clock to be detected converges to 130.19°
  • the phase detection error is 0.19°.
  • the to-be-detected clock is a quadrature signal, its frequency is set to 2GHz, and a clock signal with a frequency of 122.88MHz commonly used in the system is used for sampling.
  • Configure the val ref of the phase difference accumulation module 64 to 122.88x10 6 and val sig to 2x10 9 , and the phase difference between the to-be-detected clock and the sampling clock in a single sampling period can be calculated as:
  • the bin output by the sampling module 61 is 2bit data per sampling period, and the angle mapping relationship in the phase rough calculation module 62 is shown in Table 2:
  • the number of sampling cycles val sum configured by the control module 67 is 3000.
  • the initial phase ⁇ 0 of the clock to be detected converges to 130.19°, and the phase detection error is 0.19°.
  • This application scenario is dedicated to improving the accuracy of phase detection.
  • the configuration of the phase detection device in this scenario is shown in Figure 18, the clock to be detected is a quadrature signal, and its frequency is set to 2 GHz.
  • a 122.881MHz clock signal is used for sampling here.
  • Configure the val ref of the phase difference accumulation module 64 to 122.881x10 6 and val sig to 2x10 9 , and the phase difference between the to-be-detected clock and the sampling clock in a single sampling period can be calculated as:
  • the bin output by the sampling module 61 every sampling period is 2bit data
  • the angle mapping relationship in the phase rough calculation module 62 is shown in Table 3:
  • the initial phase statistical average relationship after sampling, the initial phase ⁇ 0 of the clock to be detected converges to 130.003°, and the phase detection error is 0.003°, which improves the accuracy of phase detection.
  • This application scenario uses the fault-tolerant processing for sampling errors that may occur when sampling near the zero-crossing point of the clock to be detected as an example.
  • the configuration of the scene phase detection device is shown in Figure 19.
  • the specific clock to be detected is a quadrature signal, and its frequency is set to 2GHz, and a clock signal with a frequency of 122.88MHz commonly used in the system is used for sampling.
  • Configure the val ref of the phase difference accumulation module 64 to 122.88x10 6 and val sig to 2x10 9 , and the phase difference between the to-be-detected clock and the sampling clock in a single sampling period can be calculated as:
  • the bin output by the sampling module 61 in each sampling period is 2bit data
  • the angle mapping relationship in the phase rough calculation module 62 is shown in Table 4:
  • the self-convergence algorithm in this embodiment counts the average value of a large number of calculated values, the influence of sampling errors or calculation errors in the intermediate calculation process on the final result is negligible, but the first sampling is used as the subsequent phase rough calculation module 62.
  • the judgment basis of the second calculation if a zero-crossing point sampling error occurs, the final initial phase calculation result will be deviated, and the second standardization module 66 will correct it.
  • the initial phase ⁇ 0 of the clock to be detected converges to 350.18°, and the phase detection error is 0.18°.
  • the communication device may be, but is not limited to, a base station or various transceivers, which includes at least one phase detection apparatus shown in the foregoing embodiments.
  • the communication device adopts multi-channel communication, one phase detection device can be used for one channel, or one phase detection device can be shared by multiple channels.
  • the base station in this embodiment uses a communication device as a base station for illustration.
  • the base station in this embodiment may be a cabinet macro base station, a distributed base station or a multi-mode base station.
  • the base station in this example includes a baseband unit (Building Baseband Unit, BBU) 211, a radio remote unit (RRU) 212, and an antenna 213, of which:
  • BBU Building Baseband Unit
  • RRU radio remote unit
  • the baseband unit 211 is responsible for centralized control and management of the entire base station system, completes uplink and downlink baseband processing functions, and provides physical interfaces with radio frequency units and transmission networks to complete information exchange.
  • the baseband unit 211 may include a baseband processing unit 2112, a main control unit 2111, a transmission interface unit 2113, and so on.
  • the main control unit 2111 mainly implements baseband unit control management, signaling processing, data transmission, interactive control, system clock provision and other functions;
  • the baseband processing unit 2112 is set to complete baseband protocol processing such as signal encoding and modulation, resource scheduling, and data encapsulation.
  • the transmission interface unit 2113 is responsible for providing the transmission interface connected to the core network.
  • the above-mentioned logical function units can be distributed on different physical boards, or integrated on the same board.
  • the baseband unit 211 may adopt a baseband master control integrated type or a baseband master control separated type.
  • the baseband master control integrated type the master control, transmission, and baseband integrated design, that is, the baseband processing unit, the master control unit, and the transmission interface unit are integrated on a physical board.
  • the architecture has higher reliability and lower cost. Delay, higher resource sharing and scheduling efficiency, while lower power consumption.
  • the baseband processing unit and the main control unit are distributed on different boards, corresponding to the baseband board and the main control board.
  • the separated architecture supports free combination between boards and facilitates flexible expansion of the baseband. Specific settings can be flexibly adopted according to requirements.
  • the remote radio unit 212 communicates with the BBU through the baseband radio frequency interface to complete the conversion between the baseband signal and the radio frequency signal.
  • an exemplary radio remote unit 212 mainly includes an interface unit 2121, an uplink signal processing unit 2124, a downlink signal processing unit 2122, a power amplifier unit 2123, a low noise amplifier unit 2125, a duplexer unit 2126, etc. Form the downlink signal processing link and the uplink signal processing link.
  • the interface unit 2121 provides a fronthaul interface with the baseband unit to receive and send baseband IQ signals;
  • the downstream signal processing unit 2122 performs signal processing functions such as signal up-conversion, digital-to-analog conversion, and radio frequency modulation;
  • the upstream signal processing unit 2124 mainly completes Signal filtering, mixing, analog-to-digital conversion, down-conversion and other functions;
  • the power amplifier unit 2123 is set to amplify the downlink signal and then sent through the antenna 213;
  • the low-noise amplifier unit 2125 is set to amplify the uplink signal received by the antenna 213 and send it
  • the uplink signal processing unit 2124 is processed;
  • the duplexer unit 2126 supports multiplexing of received and received signals and filters the received and received signals.
  • the base station in this embodiment can also adopt a CU (Central Unint, Central Unit)-DU (Distributed Unit) architecture, where DU is a distributed access point and is responsible for completing the underlying baseband protocol. And radio frequency processing function, CU is the central unit, responsible for processing high-level protocol functions and centralized management of multiple DUs. CU and DU jointly complete the baseband and radio frequency processing functions of the base station.
  • CU Central Unint, Central Unit
  • DU distributed access point and is responsible for completing the underlying baseband protocol.
  • radio frequency processing function CU is the central unit, responsible for processing high-level protocol functions and centralized management of multiple DUs.
  • CU and DU jointly complete the baseband and radio frequency processing functions of the base station.
  • communication media usually contain computer-readable instructions, data structures, computer program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium. Therefore, the present invention is not limited to any specific combination of hardware and software.

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Abstract

本发明实施例提供一种时钟信号的相位检测方法、装置及通信设备，通过对待检测时钟的时钟信号根据采样时钟所设定的采样周期进行采样，根据采样信号与相位角度值映关系，获取当前采样周期采样到的时钟信号对应的相位角度值，将相位角度值减去当前采样周期对应的相位差值得到待检测时钟在当前采样周期的初相位值，相位差值为待检测时钟与采样时钟在当前采样周期的相位差值；在采样结束后，即可根据各采样周期得到的初相位值，获取到待检测时钟的终相位值；由于终相位值是根据多次采样周期得到的初相位值得到的，得到的终相位值既具备较高的精度，又具备较好的容错性。

Description

时钟信号的相位检测方法、装置及通信设备 技术领域
本发明涉及通信技术领域，尤其涉及一种时钟信号的相位检测方法、装置及通信设备。
背景技术
多阵列天线基站中的Massive MIMO技术是4.5G以及5G通信中的关键技术。在5G通信中，空分复用(SDMA，Space Division Multiple Access)是Massive MIMO技术应用的一个重要例子。SDMA使用波束赋型beamforming技术使信号能量集中在特定的方向传播，从而增大频谱利用效率，减小对其它接收机的干扰。beamforming对收发信机多通道之间信号的相位差异有着严苛的要求，例如sub 6G的5G基站收发信机多通道间的相位差异应小于5°。因此，无线基站***会采用一系列相位检测及调整措施来减小通道间的相位误差，进而对齐多通道信号的相位。
在相位同步机制中，对射频时钟信号相位的检测是首要一环，射频时钟信号的相位检测精度直接影响多通道同步的效果。而当前并没有一个很好的针对射频时钟信号的相位进行准确检测的方案，从而很难保证相位同步效果。
发明内容
本发明实施例提供的一种时钟信号的相位检测方法、装置及通信设备，解决如何实现对射频时钟信号的相位进行准确检测，从而保证相位同步效果。
为解决上述技术问题，本发明实施例提供一种时钟信号的相位检测方法，包括：
对待检测时钟的时钟信号根据采样时钟所设定的采样周期进行采样；
根据采样信号与相位角度值映关系，获取当前采样周期采样到的时钟信号对应的相位角度值；
将所述相位角度值减去当前采样周期对应的相位差值得到所述待检测时钟在当前采样周期的初相位值，所述相位差值为所述待检测时钟与所述采样时钟在当前采样周期的相位差值；
采样结束后，根据各采样周期得到的初相位值，获取所述待检测时钟的终相位值。
为解决上述技术问题，本发明实施例还提供一种时钟信号的相位检测装置，包括：
采样模块，设置为对待检测时钟的时钟信号根据采样时钟所设定的采样周期进行采样；
相位粗算模块，设置为根据采样信号与相位角度值映关系，获取当前采样周期采样到的时钟信号对应的相位角度值；以及设置为将所述相位角度值减去当前采样周期对应的相位差值得到所述待检测时钟在当前采样周期的初相位值，所述相位差值为所述待检测时钟与所述采样时钟在当前采样周期的相位差值；
相位统计模块，设置为在采样结束后，根据各采样周期得到的初相位值，获取所述待检测时钟的终相位值。
为解决上述技术问题，本发明实施例还提供一种通信设备，包括至少一个如上所述的时钟信号的相位检测装置。
有益效果
根据本发明实施例提供的时钟信号的相位检测方法、装置及通信设备，通过对待检测时钟的时钟信号根据采样时钟所设定的采样周期进行采样，根据采样信号与相位角度值映关系，获取当前采样周期采样到的时钟信号对应的相位角度值，将相位角度值减去当前采样周期对应的相位差值得到待检测时钟在当前采样周期的初相位值，相位差值为待检测时钟与采样时钟在当前采样周期的相位差值；在采样结束后，即可根据各采样周期得到的初相位值，获取到待检测时钟的终相位值；由于终相位值是根据多次采样周期得到的初相位值得到的， 得到的终相位值既具备较高的精度，又具备较好的容错性，从而可提升本发明实施例提供的钟信号的相位检测方法的可靠性，同时可保证在需要多通道相位同步时相位同步效果。
本发明其他特征和相应的有益效果在说明书的后面部分进行阐述说明，且应当理解，至少部分有益效果从本发明说明书中的记载变的显而易见。
附图说明
图1为本发明实施例一的时钟信号的相位检测方法流程示意图；
图2为本发明实施例一的相位角度值获取流程示意图；
图3为本发明实施例一的数字脉冲信号序列与相位角度值映关系示意图；
图4为本发明实施例一的普通模式和高精度模式的采样点覆盖示意图；
图5为本发明实施例一的普通模式和高精度模式的误差分析示意图；
图6为本发明实施例二的时钟信号的相位检测装置结构示意图；
图7为本发明实施例二的采样模块结构示意图；
图8为本发明实施例二的信号采样示意图；
图9为本发明实施例二的相位粗算模块结构示意图；
图10为本发明实施例二的第一采样周期的初相位示意图；
图11为本发明实施例二的第二采样周期的初相位示意图；
图12为本发明实施例二的相位差累计模块结构示意图；
图13为本发明实施例二的第一标准化模块结构示意图；
图14为本发明实施例二的相位标准化示意图；
图15为本发明实施例二的第二标准化模块结构示意图；
图16为本发明实施例三的应用场景一中相位检测装置配置示意图；
图17为本发明实施例三的应用场景二中相位检测装置配置示意图；
图18为本发明实施例三的应用场景三中相位检测装置配置示意图；
图19为本发明实施例三的应用场景四中相位检测装置配置示意图；
图20为本发明实施例三的初相位值统计平均示意图；
图21为本发明实施例四的基站结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，下面通过具体实施方式结合附图对本发明实施例作进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
实施例一：
为了实现时钟信号的相位的准确检测，本实施例提供了一种时钟信号的相位检测方法，请参见图1所示，包括：
S101：对待检测时钟的时钟信号根据采样时钟所设定的采样周期进行采样。
本实施例的中的待检测时钟可以为但不限于各种射频时钟。且对于多通道应用场景，且多通道采用至少两个射频时钟时，针对每一个射频时钟所产生的时钟信号都可采用本实施例提供的相位检测方法。
本实施例中的采样时钟的选择可以根据当前待检测时钟的特性灵活选择。例如可以根据待检测时钟的频率，当前的检测精度要求等灵活设定。
在本实施例中，对待检测时钟进行检测时，采样周期的个数也可根据具体应用场景灵活设定。在一些示例中也可基于采样时钟的频率与待检测时钟的频率之间的最小公倍数设定。例如，采样周期的个数可以设置为1000个，2000个，3000个，6000个等。
且在本实施例中，待检测时钟的时钟信号可支持为但不限于以下信号类型中的任意一种：单端信号、差分信号、正交信号。
S102：根据采样信号与相位角度值映关系，获取当前采样周期采样到的时钟信号对应的相位角度值。
本实施例中，可以预先设置好采样信号与相位角度值映关系。且在本实施 例的一些应用场景中，由于采样得到的时钟信号为模拟信号，因此可以将模拟的幅度信息clksig转换为离散的数字脉冲信号序列bin。本实施例中此处的转换可仅根据幅度信息的正负取值方向进行数字脉冲信号序列的转换，可不涉及待检时钟的幅度信息的提取，因此即便对于频率很高的待检测时钟信号，依然能够达到较高的可靠性。
因此，在本实施例中所预设的采样信号与相位角度值映关系可包括：数字脉冲信号序列与相位角度值映关系；
此时获取当前采样周期采样到的时钟信号对应的相位角度值请参见图2所示，可包括：
S201：将采样到的时钟信号转换为数字脉冲信号序列。
S202：根据得到的数字脉冲信号序列和数字脉冲信号序列与相位角度值映关系，匹配到对应的相位角度值。
在本实施例的一些应用场景中，可根据各采样时钟上升沿待检时钟信号的相位区间，取各个区间的中间值作为区间的映射值。例如请参见图3所示例的一种数字脉冲信号序列与相位角度值映关系，当待检测时钟的时钟信号为差分信号或正交信号时，当对采样到的时钟信号转换为数字脉冲信号序列后，输出的数字脉冲信号序列为11时，则对应的相位角度值为π/4；输出的数字脉冲信号序列为01时，则对应的相位角度值为3π/4；输出的数字脉冲信号序列为00时，则对应的相位角度值为5π/4；输出的数字脉冲信号序列为00时，则对应的相位角度值为7π/4。当待检测时钟的时钟信号为单端信号时，输出的数字脉冲信号序列为1时，则对应的相位角度值为π/2；输出的数字脉冲信号序列为0时，则对应的相位角度值为3π/2。
应当理解的是，本实施例中数字脉冲信号序列与相位角度值映关系的设置并不限于上述示例的方式，可以根据需求灵活的设置。
S103：将相位角度值减去当前采样周期对应的相位差值得到待检测时钟在当前采样周期的初相位值。
在本实施例中，当前采样周期对应的相位差值为待检测时钟与采样时钟在 当前采样周期的相位差值
Figure PCTCN2020100503-appb-000001
在本实施例中，待检测时钟与采样时钟的相位差值的计算方式可以为但不限于：
根据采样时钟的频率值valref与待检测时钟的频率值valsig的关系，计算出一个采样周期对应的待检测时钟与采样时钟间的相位差值
Figure PCTCN2020100503-appb-000002
Figure PCTCN2020100503-appb-000003
在本实施例中，待检测时钟与采样时钟在当前采样周期的相位差值为：待检测时钟与采样时钟的相位差值乘以当前的采样周期数后，除以2π取余得到的值。例如，假设当前采样周期数为k，则待检测时钟与采样时钟在当前采样周期的相位差值为：
Figure PCTCN2020100503-appb-000004
通过以上过程则可得到待检测时钟在当前采样周期的初相位值，在经历k个采用周期之后，则可得到k个采样周期的初相位值。
可选的，在一些应用场景中，将相位角度值减去当前采样周期对应的相位差值得到待检测时钟在当前采样周期的初相位值之后，根据各采样周期得到的初相位值，得到待检测时钟的终相位值之前，还包括以下第一标准化过程：
在当前采样周期得到的初相位值大于第一采样周期得到的初相位值加π时，将当前采样周期得到的初相位值减2π；
在当前采样周期得到的初相位值小于第一采样周期得到的初相位值减π时，将当前采样周期得到的初相位值加2π；
在当前采样周期得到的初相位值不满足上述两种情况时，则不做上述标准化处理。
也即可选地，在本实施例中，还可以第一采样周期(当然根据需求也可采用其他次数的采样周期)得到的初相位值为基准，对后续采样周期计算出的初相位值进行标准化处理，以便于后续终相位值的准确确定。
S104：采样结束后，根据各采样周期得到的初相位值，获取待检测时钟的终相位值。
例如，假设设置的采样周期个数为n，则在完成n各采样周期的采样检测之后，即可得到n个初相位值，分别用θ 1，θ 2，...，θ n表征。
在本实施例中，当当前的待检测时钟的时钟信号为单端信号时，上述S104中根据各采样周期得到的初相位值，得到待检测时钟的终相位值包括：
从各采样周期得到的初相位值中，选择最小的初相位值作为待检测时钟的终相位值θ 0；也即θ 0＝min(θ 1，θ 2，...，θ n)。
在本实施例中，当当前的待检测时钟的时钟信号为差分信号或正交信号时，上述S104中根据各采样周期得到的初相位值，得到待检测时钟的终相位值包括：
取各采样周期得到的初相位值的平均值作为待检测时钟的终相位值；也即θ 0＝(θ 1+θ 2+...+θ n)/n。
本实施例提供的时钟信号的相位检测方法允许采样过程中出现多次采样错误。且可选地的可将第一次采样周期计算得到的初相位值作为基准，第一次采样周期出错会影响终初相位值。因此可选地，在一些应用场景中，还可在得到待检测时钟的终相位值之后，对得到的终相位值进行以下第二标准化过程：
在得到的终相位值小于0(也即为负)时，将终相位值加2π。在得到的终相位值大于0(也即为正)时，则不做该第二标准化处理。
可选地，在本实施例的一些应用场景中，在得到终相位值之后，还可该根据终相位值确定检测出的相位误差(也即检测精度)大于预设误差阈值时(也即确定检测精度是不满足当前要求时)，可更新频率比当前采样时钟的频率大的采样时钟进行采样，以增加采样时钟的频率与待检测时钟的频率的最小公倍数，减弱待检测时钟与采样时钟频率的相关性，避免采样进入循环。如图4、图5所示，通过选择频率值与待检时钟频率相关性较弱的采样时钟，可使采样点覆盖整个[0,2π)的相位区间，增大采样样本的多样性，从而显著地提高整体检相方案的相位检测精度。
可见，采用本实施例提供的相位检测方法，可以高精度的检测出各检测时钟的时钟信号的相位。当应用于多通道场景时，则可高精度的检测出各通道的相位值，进而得到各通道之间的准确的相位差值，为后续同步控制提供准确的 依据。
当然，在相关技术中，也有通过鉴频鉴相器(PFD，Phase and Frequency Detector)鉴别两输入时钟信号频率和相位差值的电路。在相关技术中，PFD由两D触发器和一个与非门构成，D触发器在接收输入时钟上升沿后，输出高电平，并在两D触发器输出均达到高电平后复位。因此，PFD可以输出表征两输入时钟信号频率或相位差值的脉冲信号。但PFD应用在收发机通道或其它场景的相位检测中存在以下困难和问题。
首先，PFD鉴相将急剧增大原有***的复杂度。在需要进行相位检测的MIMO***中，收发信机通道数目已达到几十甚至上百，根据PFD鉴别两通路信号的特性，将要使用同等数量的PFD，而且，MIMO***一般采用多芯片组成，芯片与芯片之间的连线及存在的PFD将使PCB板布局变得十分复杂，且会降低电路可靠性。
其次，PFD无法直接或很难间接给出输入时钟信号的相位信息。PFD将两输入时钟信号的频率或相位差值表征为一定宽度的脉冲信号，而非一系列的高低电平或二进制序列，后级数字电路难以将其转化为单纯的相位信息。在需要直接检测出相位值的场景中，PFD无法满足应用需求。
最后，在无线通信场景中，PFD的鉴频鉴相能力受到很大的挑战。随着频谱资源的日益紧张以及传输数据量的剧增，通信技术不断演进，无线通信频段向高频大带宽方向发展。对5G NR中Sub 6G低频段来说，PFD的鉴频鉴相能力已显得捉襟见肘，更不用说高达24.25GHz～29.5GHz的5G高频段了。并且，这样高频的时钟信号已不是简单的方波或类方波，在接收这些信号后，PFD已不能正常或可靠地表现出其鉴频鉴相能力。
另外，在相关技术中也有解决无线通信场景中的相位检测问题的方案，这些方案中使用NCO(Numerically Controlled Oscillator，数字控制振荡器)及实现反正切功能的数字电路模块，这些数字电路模块能达到的精度有限，若运算迭代次数较小，将极大地限制相位检测精度，若迭代次数较大也会显著地增加运算资源开销，另外，这些方案包含复杂的矩阵乘法和复共轭运算，算法复杂，不利于应用***降低电路规模及功耗。且这些方案对输入的两待检信号有正交 要求，因此仅能实现对正交信号的相位检测。
本实施例提供的时钟信号的相位检测方法，通过采样待检测时钟信号，得到一系列离散的二进制序列，并基于这些离散的数字采样信息及待检测时钟与采样时钟间的频率关系，在各采样周期判定待检时钟的相位区间，得出一个精度较低的初相位值，然后通过大量的采样和统计平均或取最小值之后，最终实现精度非常高的相位值检测。且为了保证采样的多样性，还可灵活的选择采样时钟的频率值，使待检测时钟的频率值与采样时钟的频率值具有较大的最小公倍数，从而灵活的根据需求调整检测所需的精度。
本实施例提供的相位检测方法，根据应用场景需求，可实现对单端、差分或正交等形式时钟信号的相位检测，通用性和兼容性好，可适用于各种应用场景。
本实施例提供的方案可通过大量数据的统计收敛出最终的终相位值，其中允许多次过程数据出错，容错性高，且保证了方案非常高的可靠性。
本实施例提供的方案所需的宽松采样电路的设计难度低，并可降低后级数字电路的工作频率，因此可提高电路易实现性。
本实施例提供的方案只涉及对待检时钟的粗采样，而不提取待检时钟的幅度信息，因此即便对于频率很高的待检信号，依然能够达到较高的可靠性。
最后，本实施例提供的方案除采样电路外，其余电路均为数字电路，并且采样电路也可使用数字形式，即TSPC(True Single Phase Clock，真单向钟控触发器，TSPC)或CML(Current Mode Logic，电流模逻辑)触发器实现，因此整体电路方案对PVT(Process Voltage Temperature)变化不敏感，可以实现较高的鲁棒性。
实施例二：
本实施例提供了一种时钟信号的相位检测装置，其可实现但不限于上述实施例所示的时钟信号的相位检测方法。且该相位检测装置可以设置于各种具有时钟的通信设备内。请参见图6所示，其包括：
采样模块61，设置为对待检测时钟的时钟信号根据采样时钟所设定的采样 周期进行采样。
本实施例的中的待检测时钟可以为但不限于各种射频时钟。且对于多通道应用场景，且多通道采用至少两个射频时钟时，针对每一个射频时钟所产生的时钟信号都可采用本实施例提供的相位检测装置进行相位检测，且一个射频时钟可对应采用一个相位检测装置，也可多个射频时钟可对应共用一个相位检测装置。本实施例中的采样时钟的选择可以根据当前待检测时钟的特性灵活选择。例如可以根据待检测时钟的频率，当前的检测精度要求等灵活设定。
在本实施例的一些应用场景中，采样模块61可包括核心采样器及后级波形整形器，目的是将输入的模拟幅度信息，转换为离散的数字脉冲信号。核心采样器可由TSPC或CML等形式的触发器来实现。后级波形整形器可由施密特触发器或反相器电路实现，设置为信号摆幅放大及波形整形。根据待检时钟信号的类型，采样器可选择为差分、单端或正交等形式。根据对相位检测精度的要求，可选择一定频率的采样时钟，减弱待检测时钟与采样时钟频率的相关性，即增大待检时钟频率与采样时钟频率的最小公倍数。
例如，一种示例的采样模块61结构请参见图7所示，采样模块61包括由TSPC或CML等形式触发器组成的采样器610，还包括波形整形器611，波形整形器611对采样器610输出的信号进行摆幅放大和波形整形，并输出理想的数字脉冲信号bin。例如图8所示的待检测时钟为正交形式的场景，采样器610在每个采样时钟clkref的时钟上升沿采样待检时钟，若采样电平高于或等于共模电平则输出0，若采样电平低于共模电平则输出1，在各采样周期对应输出的数字脉冲信号bin参见图8中右侧表格所示。
相位粗算模块62，设置为根据采样信号与相位角度值映关系，获取当前采样周期采样到的时钟信号对应的相位角度值；以及设置为将相位角度值减去当前采样周期对应的相位差值得到待检测时钟在当前采样周期的初相位值，相位差值为待检测时钟与采样时钟在当前采样周期的相位差值。可以预先设置好采样信号与相位角度值映关系，并可通过相应的寄存器设置。在本实施例中所预设的采样信号与相位角度值映关系可包括：数字脉冲信号序列与相位角度值映关系。
可选地，在本实施例的一些应用场景中，请参见图9所示，相位粗算模块62内部包括角度映射器620、标准化器621和减法器622。角度映射器620根据输入的数字脉冲信号bin及由寄存器reg写入的数字脉冲信号序列与相位角度值映关系，得出当前的采样信号对应的相位角度值。减法器622将角度映射器620得到的相位角度值减去当前采样周期对应的相位差值得到待检测时钟在当前采样周期的初相位值。
其中，请参见图6所示，相位检测装置还包括相位差累计模块64，设置为将待检测时钟与采样时钟的相位差值乘以当前的采样周期数(也可通过逐个周期叠加)之后所得到的累计相位差
Figure PCTCN2020100503-appb-000005
发给所述相位粗算模块。相位粗算模块62的标准化器621，设置为将得到的累计相位差
Figure PCTCN2020100503-appb-000006
除以2π取余得到当前采样周期对应的相位差值，即
Figure PCTCN2020100503-appb-000007
从而将
Figure PCTCN2020100503-appb-000008
值归一化到0到2π之间。减法器622将相位角度值与归一化后
Figure PCTCN2020100503-appb-000009
的相减，得到初相位值θ x *进行输出。例如请参见图10和图11所示，在第一采样周期T 1相位粗算模块62输出的初相位值为图10中的θ 1，在第二采样周期T 2相位粗算模块62输出的初相位值为图11中的θ 2，对于后续周期则以此类推。
可选的，在一些应用场景中，相位差累计模块64可基于加法器或乘法器实现，根据待检时钟信号与采样时钟信号的频率关系及经历的采样周期数，统计自触发采样操作起采样时钟相对待检测时钟的累计相位差值。例如，请参见图12所示，相位差累计模块64包括采样周期相位差计算器640和加法器641，采样周期相位差计算器640设置为计算单个采样周期的采样时钟与待检测时钟之间的相位差值，例如采样周期相位差计算器640根据采样时钟频率值val ref与待检测时钟频率值val sig的关系，计算单采样周期待检时钟与采样时钟间的相位差值
Figure PCTCN2020100503-appb-000010
加法器641设置为对得到的相位差值进行累加得到与当前采样周期数相对应的累计相位差
Figure PCTCN2020100503-appb-000011
可选的，在一些应用场景中，相位检测装置还可包括第一标准化模块65，设置为在相位粗算模块62得到待检测时钟在当前采样周期的初相位值大于第一采样周期得到的初相位值加π时，将当前采样周期得到的初相位值减2π后发给相位统计模块；在相位粗算模块得到待检测时钟在当前采样周期的初相位值小 于第一采样周期得到的初相位值减π时，将当前采样周期得到的初相位值加2π后发给相位统计模块63。
例如，请参见图13所示，一种第一标准化模块65包括第一判断器650和第一缩放器651。请参见图14所示，第一判断器650以第一次采样周期得到的初相位角度值θ 1 *值为基准，判断后续每一次θ x *值。如果后续计算的初相位θ x *值大于第一次初相位θ 1 *值加π，则θ x *通过第一缩放器651进行减2π，输出θ x＝θ x *-2π；如果后续计算的初相位θ x *值小于第一次初相位θ 1 *值减π，则θ x *通过第一缩放器651进行加2π，输出θ x＝θ x *+2π；其他情况，不做标准化处理，θ x＝θ x *。
相位统计模块63，设置为在采样结束后，根据各采样周期得到的初相位值，获取待检测时钟的终相位值。如果待检测的时钟信号为差分或正交输入信号，相位统计模块63可为统计平均值模块，取各采样周期得到的初相位值的平均值作为待检测时钟的终相位值；也即θ 0＝(θ 1+θ 2+...+θ n)/n；如果待检测的时钟信号为单端信号，则该相位统计模块63选择最小的初相位值作为待检测时钟的终相位值θ 0，也即θ 0＝min(θ 1，θ 2，...，θ n)。
第二标准化模块66，设置为在相位统计模块63得到的终相位值小于0时，将终相位值加2π。请参见图15所述，一种第二标准化模块66包括第二判断器660和第二缩放器661，第二判断器660判断终相位值θ 0 *为负时，第二缩放器661对其θ 0 *加2π，输出θ 0＝θ 0 *+2π；第二判断器660判断终相位值θ 0 *为正时，第二缩放器661不做处理，输出θ 0＝θ 0 *。
请参见图6所示，相位检测装置还包括控制模块67，其可设置为在根据终相位值确定检测出的相位误差大于预设误差阈值时，更新频率比当前采样时钟的频率大的采样时钟进行采样，以增加采样时钟的频率与待检测时钟的频率的最小公倍数。控制模块67还可设置为配置采样周期数val sam，实现图6中其他模块的使能、复位等控制。
可见，通过本实施例所提供的时钟信号的相位检测装置，可以实现对射频时钟的时钟信号之相位进行较高精度的检测，可使得射频时钟在多通道等需要相位同步的场景应用时，可更精确的满足相位同步需求，提升通信性能。
实施例三：
为了便于理解，本实施例下面以几种具体的应用场景为示例进行说明。
应用场景一：
该应用场景的相位检测装置的配置如图16所示，待检测时钟的时钟信号为单端信号，设定其频率为2GHz，并采用***中常用的频率为122.88MHz的时钟信号(也即采样时钟的频率为122.88MHz)进行采样。配置相位差累计模块64的val ref为122.88x10 6，val sig为2x10 9，可计算出单采样周期待检测时钟与采样时钟间的相位差值为：
Figure PCTCN2020100503-appb-000012
在经历k个采样周期后，待检测时钟与采样时钟的累积相位差值为：
Figure PCTCN2020100503-appb-000013
待检测时钟为单端信号时，每采样周期采样模块61输出的bin为1bit的数据，相位粗算模块62中的角度映射关系如表1所示：
表1
Figure PCTCN2020100503-appb-000014
假设采样初始时刻待检测时钟相位为130°，控制模块67配置的采样周期数val sum为6000。如图20初相位统计平均关系所示，采样结束后，待检测时钟的初始相位θ 0收敛至130.19°，检相误差为0.19°。
应用场景二：
该应用场景的相位检测装置的配置图17所示，待检测时钟为正交信号，设定其频率为2GHz，并采用***中常用的频率为122.88MHz的时钟信号进行采样。配置相位差累计模块64的val ref为122.88x10 6，val sig为2x10 9，可计算出单采样周期待检测时钟与采样时钟间的相位差值为：
Figure PCTCN2020100503-appb-000015
在经历k个采样周期后，待检测时钟与采样时钟的累积相位差值为：
Figure PCTCN2020100503-appb-000016
待检测时钟为正交信号时，每采样周期采样模块61输出的bin为2bit的数据，相位粗算模块62中的角度映射关系如表2所示：
表2
Figure PCTCN2020100503-appb-000017
假设采样初始时刻待检测时钟相位为130°，控制模块67配置的采样周期数val sum为3000。如图20初相位统计平均关系所示，采样结束后，待检测时钟的初始相位θ 0收敛至130.19°，检相误差为0.19°。
应用场景三：
该应用场景致力于提高相位检测的精度，对采样模块61来说，若待检测时钟频率值与采样时钟频率值的最小公倍数较小，即存在较小的整数m和n，使得m ×val sig＝n×val ref，则采样模块61输出的二进制数据在经历n个采样周期后将进入周期性循环，即在n个采样周期达到最大的采样多样性。该场景下的相位检测装置的配置如图18所示，待检测时钟为正交信号，设定其频率为2GHz。为提高检相精度，这里采用122.881MHz的时钟信号进行采样。配置相位差累计模块64的val ref为122.881x10 6，val sig为2x10 9，可计算出单采样周期待检测时钟与采样时钟间的相位差值为：
Figure PCTCN2020100503-appb-000018
在经历k个采样周期后，待检测时钟与采样时钟的累积相位差值为：
Figure PCTCN2020100503-appb-000019
待检测时钟为正交信号时，每采样周期采样模块61输出的bin为2bit的数据，相位粗算模块62中的角度映射关系如表3所示：
表3
Figure PCTCN2020100503-appb-000020
假设采样初始时刻待检测时钟相位为130°，控制模块67的采样周期数val sum为3000。如图20所示的初相位统计平均关系，采样结束后，待检测时钟的初始相位θ 0收敛至130.003°，检相误差为0.003°，提升了相位检测的精度。
应用场景四：
本应用场景以在待检测时钟过零点位置附近采样时可能出现的采样错误时的容错处理为示例进行说明。该场景相位检测装置的配置如图19所示。特定待检测时钟为正交信号，设定其频率为2GHz，并采用***中常用的频率为122.88MHz的时钟信号进行采样。配置相位差累计模块64的val ref为122.88x10 6，val sig为2x10 9，可计算出单采样周期待检测时钟与采样时钟间的相位差值为：
Figure PCTCN2020100503-appb-000021
在经历k个采样周期后，待检测时钟与采样时钟的累积相位差值为：
Figure PCTCN2020100503-appb-000022
待检测时钟为正交信号时，每采样周期采样模块61输出的bin为2bit的数据，相位粗算模块62中的角度映射关系如表4所示：
表4
Figure PCTCN2020100503-appb-000023
Figure PCTCN2020100503-appb-000024
由于本实施例中的自身收敛算法是统计大量计算值的平均值，中间计算过程出现采样错误或计算错误对最终结果的影响可忽略不计，但第一次采样是作为后续相位粗算模块62每次计算的判断依据，如果出现过零点采样错误会导致最终初相位计算结果出现偏差，第二标准化模块66会对其进行纠正。
设定采样初始时刻待检测时钟相位为350°，控制模块67配置的采样周期数val sum为3000。收敛初相位与采样值对应关系如表5所示：
表5
Figure PCTCN2020100503-appb-000025
经过统计平均以及第二标准化模块66实现初相位标准化，采样结束后，待检测时钟的初始相位θ 0收敛至350.18°，检相误差为0.18°。
实施例四：
本实施例还提供了一种通信设备，该通信设备可以为但不限于基站或各种收发机，其包括至少一个上述各实施例所示的相位检测装置。在一种示例中，通信设备采用多通道通信时，可一个通道对应使用一个相位检测装置，也可多个通道共用一个相位检测装置。
为了便于理解，本实施例的一种示例中以通信设备为基站进行示例说明。且应当理解的是，本实施例中的基站可以为机柜式宏基站、分布式基站或多模基站。请参见图21所示，本示例中的基站包括基带单元(Building Base band Unit，BBU)211和射频拉远单元(Radio Remote Unit，RRU)212以及天线213，其中：
基带单元211负责集中控制与管理整个基站***，完成上下行基带处理功 能，并提供与射频单元、传输网络的物理接口，完成信息交互。按照逻辑功能的不同，请参见图21所示，基带单元211可包括基带处理单元2112、主控单元2111、传输接口单元2113等。其中，主控单元2111主要实现基带单元的控制管理、信令处理、数据传输、交互控制、***时钟提供等功能；基带处理单元2112设置为完成信号编码调制、资源调度、数据封装等基带协议处理，提供基带单元和射频拉远单元间的接口；传输接口单元2113负责提供与核心网连接的传输接口。在本示例中，上述各逻辑功能单元可分布在不同的物理板卡上，也可以集成在同一块板卡上。且可选的，基带单元211可采用基带主控集成式，也可采用基带主控分离式。对于基带主控集成式，主控、传输、基带一体化设计，即基带处理单元与主控单元、传输接口单元集成在一块物理板卡上，该架构具有更高的可靠性、更低的低延、更高的资源共享及调度效率，同时功耗更低。对于基带主控分离式，基带处理单元与主控单元分布在不同的板卡上，对应于基带板、主控板，分离式架构支持板卡间自由组合、便于基带灵活扩容。具体可根据需求灵活采用设置。
射频拉远单元212通过基带射频接口与BBU通信，完成基带信号与射频信号的转换。参见图21所示，一种示例的射频拉远单元212主要包括接口单元2121、上行信号处理单元2124、下行信号处理单元2122、功放单元2123、低噪放单元2125、双工器单元2126等，构成下行信号处理链路与上行信号处理链路。其中，接口单2121提供与基带单元之间的前传接口，接收和发送基带IQ信号；下行信号处理单元2122完成信号上变频、数模转换、射频调制等信号处理功能；上行信号处理单元2124主要完成信号滤波、混频、模数转换、下变频等功能；功放单元2123设置为对下行信号进行放大后通过天线213发出；低噪放单元2125设置为对天线213接收到的上行信号进行放大后发给上行信号处理单元2124进行处理；双工器单元2126支持收发信号复用并对收发信号进行滤波。
另外，应当理解的是，本实施例中的基站还可采用CU(Central Unint，中央单元)-DU(Distributed Unit，分布式单元)架构，其中DU是分布式接入点，负责完成底层基带协议及射频处理功能，CU是中央单元，负责处理高层协议功能并集中管理多个DU。CU和DU共同完成基站的基带及射频处理功能。
可见，本领域的技术人员应该明白，上文中所公开方法中的全部或某些步骤、***、装置中的功能模块/单元可以被实施为软件(可以用计算装置可执行的计算机程序代码来实现)、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。
此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、计算机程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。所以，本发明不限制于任何特定的硬件和软件结合。
以上内容是结合具体的实施方式对本发明实施例所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (17)

  1. 一种时钟信号的相位检测方法，包括：
    对待检测时钟的时钟信号根据采样时钟所设定的采样周期进行采样；
    根据采样信号与相位角度值映关系，获取当前采样周期采样到的时钟信号对应的相位角度值；
    将所述相位角度值减去当前采样周期对应的相位差值得到所述待检测时钟在当前采样周期的初相位值，所述相位差值为所述待检测时钟与所述采样时钟在当前采样周期的相位差值；
    采样结束后，根据各采样周期得到的初相位值，获取所述待检测时钟的终相位值。
  2. 如权利要求1所述的时钟信号的相位检测方法，其中，所述采样信号与相位角度值映关系包括：数字脉冲信号序列与相位角度值映关系；
    所述获取当前采样周期采样到的时钟信号对应的相位角度值包括：
    将采样到的时钟信号转换为数字脉冲信号序列；
    根据得到的数字脉冲信号序列和所述数字脉冲信号序列与相位角度值映关系，匹配到对应的相位角度值。
  3. 如权利要求1所述的时钟信号的相位检测方法，其中，所述待检测时钟与所述采样时钟在当前采样周期的相位差值为：所述待检测时钟与所述采样时钟的相位差值乘以当前的采样周期数后，除以2π取余得到的值。
  4. 如权利要求1-3任一项所述的时钟信号的相位检测方法，其中，将所述相位角度值减去当前采样周期对应的相位差值得到所述待检测时钟在当前采样周期的初相位值之后，根据各采样周期得到的初相位值，得到所述待检测时钟的终相位值之前，还包括以下第一标准化过程：
    在当前采样周期得到的初相位值大于第一采样周期得到的初相位值加π时，将当前采样周期得到的初相位值减2π；
    在当前采样周期得到的初相位值小于第一采样周期得到的初相位值减π时，将当前采样周期得到的初相位值加2π。
  5. 如权利要求1-3任一项所述的时钟信号的相位检测方法，其中，得到所述待检测时钟的终相位值之后，还包括以下第二标准化过程：
    在所述终相位值小于0时，将所述终相位值加2π。
  6. 如权利要求1-3任一项所述的时钟信号的相位检测方法，其中，所述待检测时钟的时钟信号为以下信号类型中的任意一种：
    单端信号、差分信号、正交信号。
  7. 如权利要求6所述的时钟信号的相位检测方法，其中，所述待检测时钟的时钟信号为单端信号时，所述根据各采样周期得到的初相位值，得到所述待检测时钟的终相位值包括：
    从所述各采样周期得到的初相位值中，选择最小的初相位值作为待检测时钟的终相位值。
  8. 如权利要求6所述的时钟信号的相位检测方法，其中，所述待检测时钟的时钟信号为差分信号或正交信号时，所述根据各采样周期得到的初相位值，得到所述待检测时钟的终相位值包括：
    取各采样周期得到的初相位值的平均值作为待检测时钟的终相位值。
  9. 如权利要求1-3任一项所述的时钟信号的相位检测方法，其中，所述方法还包括：
    得到所述终相位值之后，根据所述终相位值确定检测出的相位误差大于预设误差阈值时，更新频率比当前采样时钟的频率大的采样时钟进行采样，以增加采样时钟的频率与待检测时钟的频率的最小公倍数。
  10. 一种时钟信号的相位检测装置，包括：
    采样模块，设置为对待检测时钟的时钟信号根据采样时钟所设定的采样周期进行采样；
    相位粗算模块，设置为根据采样信号与相位角度值映关系，获取当前采样周期采样到的时钟信号对应的相位角度值；以及设置为将所述相位角度值减去当前采样周期对应的相位差值得到所述待检测时钟在当前采样周期的初相位值，所述相位差值为所述待检测时钟与所述采样时钟在当前采样周期的相位差值；
    相位统计模块，设置为在采样结束后，根据各采样周期得到的初相位值，获取所述待检测时钟的终相位值。
  11. 如权利要求10所述的时钟信号的相位检测装置，其中，所述采样模块包括采样器和波形整形器；
    所述采样器对待检测时钟的时钟信号根据采样时钟所设定的采样周期进行采样，所述波形整形器设置为将所述采样器采样到的采样信号进行波形整形输出数字脉冲信号序列。
  12. 如权利要求11所述的时钟信号的相位检测装置，其中，所述采样信号与相位角度值映关系包括：数字脉冲信号序列与相位角度值映关系；
    所述相位粗算模块包括角度映射器和减法器；
    所述角度映射器根据所述采样模块输出的数字脉冲信号序列和所述数字脉冲信号序列与相位角度值映关系，匹配到对应的相位角度值；
    所述减法器将所述相位角度值减去当前采样周期对应的相位差值得到所述待检测时钟在当前采样周期的初相位值。
  13. 如权利要求12所述的时钟信号的相位检测装置，其中，还包括相位差累计模块，设置为将所述待检测时钟与所述采样时钟的相位差值乘以当前的采样周期数之后所得到的累计相位差发给所述相位粗算模块；
    所述相位粗算模块还包括标准化器，设置为将所述累计相位差除以2π取余得到当前采样周期对应的相位差值。
  14. 如权利要求10-13任一项所述的时钟信号的相位检测装置，其中，还包括第一标准化模块，设置为在所述相位粗算模块得到所述待检测时钟在当前 采样周期的初相位值大于第一采样周期得到的初相位值加π时，将当前采样周期得到的初相位值减2π后发给所述相位统计模块；在所述相位粗算模块得到所述待检测时钟在当前采样周期的初相位值小于第一采样周期得到的初相位值减π时，将当前采样周期得到的初相位值加2π后发给所述相位统计模块。
  15. 如权利要求10-13任一项所述的时钟信号的相位检测装置，还包括第二标准化模块，设置为在所述相位统计模块得到的终相位值小于0时，将所述终相位值加2π。
  16. 如权利要求10-13任一项所述的时钟信号的相位检测装置，还包括控制模块，设置为在根据所述终相位值确定检测出的相位误差大于预设误差阈值时，更新频率比当前采样时钟的频率大的采样时钟进行采样，以增加采样时钟的频率与待检测时钟的频率的最小公倍数。
  17. 一种通信设备，包括至少一个如权利要求10-16任一项所述的时钟信号的相位检测装置。
PCT/CN2020/100503 2019-07-08 2020-07-06 时钟信号的相位检测方法、装置及通信设备 WO2021004439A1 (zh)

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