WO2020238587A1 - 一种结型势垒肖特基二极管 - Google Patents

一种结型势垒肖特基二极管 Download PDF

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WO2020238587A1
WO2020238587A1 PCT/CN2020/089347 CN2020089347W WO2020238587A1 WO 2020238587 A1 WO2020238587 A1 WO 2020238587A1 CN 2020089347 W CN2020089347 W CN 2020089347W WO 2020238587 A1 WO2020238587 A1 WO 2020238587A1
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Prior art keywords
ion implantation
schottky diode
junction barrier
type ion
metal layer
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PCT/CN2020/089347
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English (en)
French (fr)
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宋庆文
张玉明
汤晓燕
袁昊
何艳静
韩超
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西安电子科技大学
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Priority claimed from CN201910458036.7A external-priority patent/CN110098263A/zh
Priority claimed from CN201910458045.6A external-priority patent/CN110098264A/zh
Application filed by 西安电子科技大学 filed Critical 西安电子科技大学
Priority to US17/263,365 priority Critical patent/US11316052B2/en
Publication of WO2020238587A1 publication Critical patent/WO2020238587A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes

Definitions

  • the invention belongs to the technical field of microelectronics, and specifically relates to a junction barrier Schottky diode.
  • Wide-gap semiconductor materials are the third-generation semiconductor materials developed after the first-generation silicon, germanium, second-generation gallium arsenide, indium phosphide and other materials.
  • silicon carbide SiC
  • SiC silicon carbide
  • JBS Junction Barrier Schottky Diode
  • the present invention provides a junction barrier Schottky diode.
  • the technical problem to be solved by the present invention is realized through the following technical solutions:
  • the present invention provides a junction barrier Schottky diode, which comprises a bottom metal layer, an N+ substrate layer and an N- epitaxial layer which are sequentially arranged from bottom to top, wherein:
  • the upper surface of the N- epitaxial layer is provided with a plurality of P-type ion implantation regions, and the distance between adjacent P-type ion implantation regions increases from the edge to the center of the junction barrier Schottky diode trend;
  • the N- epitaxial layer is provided with an isolation dielectric layer and a top metal layer, the isolation dielectric layer surrounds the periphery of the upper surface of the N- epitaxial layer, and the top metal layer is disposed on the N- epitaxial layer and the top metal layer.
  • the upper surface of the isolation dielectric layer is in contact with the P-type ion implantation area.
  • the contact area between the N+ substrate layer and the bottom metal layer is an ohmic contact area
  • the contact area between the N- epitaxial layer and the top metal layer is an N-type Schottky contact area
  • the first contact area between the P-type ion implantation area and the top metal layer is a P-type Schottky contact or an ohmic contact.
  • the distance between adjacent P-type ion implantation regions continuously increases from the edge to the center of the junction barrier Schottky diode.
  • the distance between adjacent P-type ion implantation regions increases stepwise from the edge to the center of the junction barrier Schottky diode.
  • the top-view shape of the P-type ion implantation region is a ring or a rectangular shape, and the structural size of each P-type ion implantation region is equal, and the depth of the P-type ion implantation region ⁇ 2 ⁇ m, and the distance between adjacent P-type ion implantation regions is ⁇ 2 ⁇ m.
  • each of the P-type ion implantation regions is provided with a groove, and the depth of the groove increases from the edge to the center of the junction barrier Schottky diode,
  • the top metal layer is arranged inside the groove.
  • the second contact area between the bottom of the groove and the top metal layer is a P-type Schottky contact or an ohmic contact.
  • the depth of the groove continuously increases from the edge to the center of the junction barrier Schottky diode.
  • the depth of the groove increases stepwise from the edge to the center of the junction barrier Schottky diode.
  • the distance between adjacent P-type ion implantation regions is ⁇ 3 ⁇ m
  • the sidewall thickness of the P-type ion implantation region is ⁇ 0.8 ⁇ m
  • the width of each P-type ion implantation region Are equal, the difference between the depth of the P-type ion implantation region and the depth of the corresponding groove remains unchanged, the width of the groove is less than or equal to 5 ⁇ m, and the depth is more than or equal to 1 ⁇ m.
  • the present invention has the following beneficial effects:
  • the junction barrier Schottky diode of the present invention increases the area of the N-type Schottky contact area at the center of the device, reduces the area of the N-type Schottky contact area at the edge of the device, and ensures reverse leakage. Under the premise that the current and the forward conduction resistance are not degraded, the temperature difference of the JBS device is reduced, and the occurrence of local electromigration is effectively suppressed, thereby improving the reliability of the device;
  • junction barrier Schottky diode of the present invention a groove is formed in each of the P-type ion implantation regions to form a trench junction barrier Schottky diode (TJBS) ), compared with the JBS diode, due to the reduction of the electric field in the Schottky region, the diode leakage current is significantly reduced, and by increasing the area of the N-type Schottky contact region in the center of the device, the N at the edge of the device is reduced.
  • TJBS trench junction barrier Schottky diode
  • the area of the type Schottky contact area reduces the temperature difference of the TJBS device under the premise of ensuring that the reverse leakage current and the forward conduction resistance are not degraded, and effectively inhibits the occurrence of local electromigration, thereby improving the reliability of the device ;
  • the junction barrier Schottky diode of the present invention increases the depth of the groove at the center of the device and reduces the depth of the groove at the edge of the device, avoiding the increase in the area of the N-type Schottky contact area in the center of the device. This causes the leakage current of the device to increase.
  • FIG. 1 is a schematic structural diagram of a junction barrier Schottky diode according to an embodiment of the present invention
  • FIG. 2 is a dimension drawing of a junction barrier Schottky diode provided by an embodiment of the present invention
  • FIG. 3 is a dimension drawing diagram of another junction barrier Schottky diode provided by an embodiment of the present invention.
  • FIG. 4 is a schematic top view of a P-type ion implantation area provided by an embodiment of the present invention.
  • FIG. 5 is a schematic top view of another P-type ion implantation area provided by an embodiment of the present invention.
  • 6a-6e are schematic diagrams of a manufacturing process of a junction barrier Schottky diode provided by an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of another junction barrier Schottky diode provided by an embodiment of the present invention.
  • Fig. 8 is a dimension drawing of the structure of area a in Fig. 7;
  • FIG. 10 is a dimension drawing diagram of yet another junction barrier Schottky diode provided by an embodiment of the present invention.
  • 11a to 11e are schematic diagrams of the manufacturing process of another junction barrier Schottky diode provided by an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a junction barrier Schottky diode according to an embodiment of the present invention.
  • a junction barrier Schottky diode according to an embodiment of the present invention includes The bottom metal layer 1, the N+ substrate layer 2, and the N- epitaxial layer 3 are sequentially arranged from bottom to top.
  • a number of P-type ion implantation regions 4 are provided on the upper surface of the N-epitaxial layer 3, and the distance between adjacent P-type ion implantation regions 4 increases from the edge to the center of the junction barrier Schottky diode.
  • the N-epitaxial layer 3 is provided with an isolation dielectric layer 6 and a top metal layer 7, the isolation dielectric layer 6 surrounds the upper surface of the N-epitaxial layer 3, and the top metal layer 7 is provided on the N-epitaxial layer 3 and the isolation dielectric layer 6.
  • the upper surface is in contact with the P-type ion implantation area 4.
  • the contact area between the N+ substrate layer 2 and the bottom metal layer 1 is an ohmic contact area 8;
  • the contact area between the N- epitaxial layer 3 and the top metal layer 7 is an N-type Schottky contact area 9; and a P-type ion implantation area 4
  • the first contact area 10 with the top metal layer 7 is a P-type Schottky contact or an ohmic contact.
  • the underlying metal layer 1 includes a Ni metal layer in contact with the N+ substrate layer 2, and a Ti/Ni/Ag metal layer stacked on the lower surface of the Ni metal layer, and the thickness of the Ni metal layer is 50-100 nm
  • the total thickness of the Ti/Ni/Ag metal layers stacked in sequence is 2-5 ⁇ m.
  • the N+ substrate layer 2 is a highly doped N-type silicon carbide substrate
  • the N- epitaxial layer 3 has a thickness of 10-30 ⁇ m
  • the isolation dielectric layer 6 is an SiO 2 isolation dielectric layer with a thickness of 200-500 nm.
  • the top metal layer 7 includes a Ti metal layer in contact with the upper surface of the N- epitaxial layer 3 and the upper surface of the P-type ion implantation region 4, and an Al metal layer or Ag metal layer provided on the Ti metal layer.
  • the thickness of the layer is 50-100 nm, and the thickness of the Al metal layer or the Ag metal layer is 2-5 ⁇ m.
  • the structural size of each P-type ion implantation area 4 is equal, the depth of the P-type ion implantation area 4 is ⁇ 2 ⁇ m, and the distance between adjacent P-type ion implantation areas 4 is ⁇ 2 ⁇ m.
  • the heat dissipation conditions of the different positions of the JBS device are different, because the larger the area of the N-type Schottky contact area 9 is, the higher the current density of the JBS device is. , The greater the power of the JBS device, the more serious the heating of the JBS device.
  • the area of the small-edge N-type Schottky contact region 9 will cause the forward characteristics of the JBS device to be weakened.
  • the junction barrier Schottky diode of this embodiment since the distance between adjacent P-type ion implantation regions 4 increases from the edge to the center of the junction barrier Schottky diode, that is, the N-type The contact area of the Schottky contact area 9 tends to increase from the edge to the center, that is, by increasing the area of the N-type Schottky contact area 9 in the center, the area of the N-type Schottky contact area 9 at the edge is reduced. Under the premise that the reverse leakage current and the forward conduction resistance are not degraded, the temperature difference of the JBS device is reduced, and the occurrence of local electromigration is effectively suppressed, thereby improving the reliability of the device.
  • FIG. 2 is a dimension drawing of a junction barrier Schottky diode provided by an embodiment of the present invention.
  • the width of the N-type Schottky contact region 9 is from Left to right are represented by W S1 , W S2 , W S3 , W S4 , W S5 , W S6 , W S7 , W S8 and W S9 in turn .
  • the width of the N-type Schottky contact area 9 The relationship is W S1 ⁇ W S2 ⁇ W S3 ⁇ W S4 ⁇ W S5 >W S6 >W S7 >W S8 >W S9 , and the width difference between adjacent N-type Schottky contact regions 9 is less than or equal to 10 ⁇ m.
  • the width of the N-type Schottky contact region 9 continuously increases from the edge to the center, that is, the contact area of the N-type Schottky contact region 9 continuously increases from the edge to the center.
  • the distance between adjacent P-type ion implantation regions 4 may increase stepwise from the edge to the center of the junction barrier Schottky diode, that is, the N-type Schottky contact
  • the width of the region 9 increases stepwise from the edge to the center of the junction barrier Schottky diode.
  • FIG. 3 is another junction barrier Schottky diode provided by an embodiment of the present invention.
  • the width of the N-type Schottky contact region 9 increases stepwise from the edge to the center, that is, the contact area of the N-type Schottky contact region 9 is from the edge to the center. The distance gradually increases.
  • the area of the N-type Schottky contact area 9 in the center is reduced to ensure that the reverse leakage current and forward conduction resistance are not degraded.
  • the temperature difference of the JBS device is reduced, the occurrence of local electromigration phenomenon is effectively suppressed, and the reliability of the device is improved.
  • the top view shape of the P-type ion implantation region 4 is a ring shape or a rectangular shape.
  • FIG. 4 is a schematic top view of a P-type ion implantation area provided by an embodiment of the present invention.
  • the top view shape of the P-type ion implantation area 4 is ring. And it surrounds the upper surface of the N- epitaxial layer 3 in parallel.
  • the ring shape can be round or square.
  • the depth of each P-type ion implantation area 4 is ⁇ 2 ⁇ m, and the distance between adjacent P-type ion implantation areas 4 ⁇ 2 ⁇ m, the distance between adjacent P-type ion implantation regions 4 is increasing from the edge to the center.
  • FIG. 5 is a schematic plan view of another P-type ion implantation area provided by an embodiment of the present invention.
  • the plan view shape of the P-type ion implantation area 4 is a rectangular shape.
  • each P-type ion implantation area 4 has the same structural size, and its depth is ⁇ 2 ⁇ m, and the distance between adjacent P-type ion implantation areas 4 is ⁇ 2 ⁇ m, The distance between adjacent P-type ion implantation regions 4 is increasing from the edge to the center.
  • FIGS. 6a-6e are schematic diagrams of a manufacturing process of a junction barrier Schottky diode according to an embodiment of the present invention.
  • the manufacturing method of the junction barrier Schottky diode of this embodiment specifically includes the following steps:
  • Step 1 Epitaxially grow an N- epitaxial layer on the N+ substrate layer.
  • N- epitaxial layer on the N+ substrate layer.
  • Figure 6a Select a highly doped N-type silicon carbide substrate as the N+ substrate layer 2.
  • Step 2 Form a P-type ion implantation area, specifically, referring to FIG. 6b, first deposit 2 ⁇ m SiO 2 as a barrier layer for ion implantation in the P-type ion implantation area 4; secondly, form P-type ion implantation by photolithography and etching In the implantation window of the region 4, the distance between the implantation windows is increasing from the edge to the center of the junction barrier Schottky diode; finally, the P-type ion implantation region 4 is formed by an ion implantation process.
  • Step 3 Form a bottom metal layer.
  • a Ni metal layer is sputtered on the lower surface of the N+ substrate layer 2 by means of magnetron sputtering, and a sequentially stacked Ni metal layer is formed on the lower surface of the Ni metal layer.
  • a Ti/Ni/Ag metal layer is formed to form the underlying metal layer 1, the thickness of the Ni metal layer is 50-100 nm, and the total thickness of the sequentially stacked Ti/Ni/Ag metal layers is 2-5 ⁇ m.
  • the contact area between the N+ substrate layer 2 and the bottom metal layer 1 is an ohmic contact area 8.
  • Step 4 Form an isolation dielectric layer. Specifically, referring to FIG. 6d, a SiO 2 isolation dielectric layer is deposited on the N- epitaxial layer 3 with a thickness of 200-500 nm, and the SiO 2 isolation is etched through a photolithography mask The dielectric layer forms an isolation dielectric layer 6 which surrounds the upper surface of the N-epitaxial layer 3.
  • Step 5 Form the top metal layer. Specifically, referring to FIG. 6e, a Ti metal layer is sputtered on the upper surface of the N-epitaxial layer 3 and the upper surface of the P-type ion implantation region 4 by magnetron sputtering, and then An Al metal layer or Ag metal layer is formed on the Ti metal layer, thereby forming the top metal layer 7, the thickness of the Ti metal layer is 50-100 nm, and the thickness of the Al metal layer or the Ag metal layer is 2-5 ⁇ m.
  • the contact area between the N- epitaxial layer 3 and the top metal layer 7 is an N-type Schottky contact area 9, and the first contact area 10 between the P-type ion implantation area 4 and the top metal layer 7 is a P-type Schottky contact or an ohmic contact .
  • FIG. 7 is a schematic structural diagram of another junction barrier Schottky diode according to an embodiment of the present invention.
  • a junction barrier Schottky diode according to an embodiment of the present invention, It includes a bottom metal layer 1, an N+ substrate layer 2 and an N- epitaxial layer 3 arranged in sequence from bottom to top, wherein the upper surface of the N- epitaxial layer 3 is provided with several P-type ion implantation regions 4, and each P-type ion implantation A groove 5 is provided in the region 4, and the distance between adjacent P-type ion implantation regions 4 increases from the edge to the center of the junction barrier Schottky diode.
  • the depth of the groove 5 is from the junction
  • the shape of the barrier Schottky diode increases from the edge to the center;
  • the N-epitaxial layer 3 is provided with an isolation dielectric layer 6 and a top metal layer 7, and the isolation dielectric layer 6 surrounds the upper surface of the N-epitaxial layer 3.
  • the top metal layer 7 is disposed on the upper surface of the N-epitaxial layer 3 and the isolation dielectric layer 6 and the inside of the groove 5.
  • the contact area between the N+ substrate layer 2 and the bottom metal layer 1 is an ohmic contact area 8
  • the contact area between the N- epitaxial layer 3 and the top metal layer 7 is an N-type Schottky contact area 9
  • the bottom of the groove 5 is
  • the second contact region 11 of the top metal layer 7 is a P-type Schottky contact or an ohmic contact.
  • the underlying metal layer 1 includes a Ni metal layer in contact with the N+ substrate layer 2, and a Ti/Ni/Ag metal layer stacked on the lower surface of the Ni metal layer, and the thickness of the Ni metal layer is 50-100 nm
  • the total thickness of the Ti/Ni/Ag metal layers stacked in sequence is 2-5 ⁇ m.
  • the N+ substrate layer 2 is a highly doped N-type silicon carbide substrate sheet, and the thickness of the N- epitaxial layer 3 is ⁇ 5 ⁇ m.
  • the width of each P-type ion implantation region 4 is the same, and the difference between the depth of the P-type ion implantation region 4 and the depth of the corresponding groove 5 remains unchanged. In this embodiment, referring to FIG.
  • the depth h of the P-type ion implantation region 4 is ⁇ 2.5 ⁇ m
  • the width m is ⁇ 6.2 ⁇ m
  • the sidewall thickness n is ⁇ 0.8 ⁇ m
  • the width c of the groove 5 is ⁇ 5 ⁇ m
  • the depth d is 1 ⁇ m.
  • the width c of the groove 5 is 3 ⁇ m.
  • the isolation dielectric layer 6 is an SiO 2 isolation dielectric layer with a thickness of 200-500 nm.
  • the top metal layer 7 includes a Ti metal layer in contact with the upper surface of the N- epitaxial layer 3 and the inner surface of the groove 5, and an Al metal layer or Ag metal layer provided on the Ti metal layer.
  • the thickness of the Ti metal layer The thickness of the Al metal layer or the Ag metal layer is 2-5 ⁇ m.
  • junction barrier Schottky diode of this embodiment a groove is formed in each P-type ion implantation area to form a trench junction barrier Schottky diode (Trench Junction Barrier Schottky Diode, TJBS for short), Compared with the JBS diode, due to the reduced electric field in the Schottky region, the diode leakage current is significantly reduced. However, due to the different areas of the package contacted by different positions, the heat dissipation conditions at different positions of the TJBS device are different, because the larger the area of the N-type Schottky contact area 9 is, the greater the current density of the TJBS device is, so The greater the power of the TJBS device, the more serious the heating of the TJBS device.
  • TJBS Trench Junction Barrier Schottky Diode
  • the temperature at the edge of the TJBS device can be effectively reduced, but it is only a simple reduction.
  • the area of the small-edge N-type Schottky contact region 9 will cause the forward characteristics of the TJBS device to be weakened.
  • the distance between adjacent P-type ion implantation regions 4 increases from the edge to the center of the junction barrier Schottky diode, that is, the N-type
  • the contact area of the Schottky contact area 9 tends to increase from the edge to the center, that is, by increasing the area of the N-type Schottky contact area 9 in the center, the area of the N-type Schottky contact area 9 at the edge is reduced.
  • the temperature difference of the TJBS device is reduced, and the occurrence of local electromigration is effectively suppressed, thereby improving the reliability of the device.
  • the leakage current of the TJBS device will also increase, and increasing the depth of the groove 5 can reduce the leakage current of the device. Therefore, the For junction barrier Schottky diodes, by increasing the depth of the central groove 5 and reducing the depth of the edge groove 5, the leakage of the device due to the increase in the area of the central N-type Schottky contact region 9 is avoided. The phenomenon of increasing current.
  • FIG. 9 is a dimension drawing of another junction barrier Schottky diode provided by an embodiment of the present invention.
  • the width of the N-type Schottky contact region 9 is from left to right. It is represented by W S1 , W S2 , W S3 , W S4 , W S5 , W S6 , W S7 , W S8 and W S9 , and the depth of the groove 5 is D p1 , D p2 , D p3 , D from left to right.
  • the relationship between the width of the N-type Schottky contact region 9 is W S1 ⁇ W S2 ⁇ W S3 ⁇ W S4 ⁇ W S5 >W S6 >W S7 >W S8 >W S9
  • the width difference between adjacent N-type Schottky contact regions 9 is ⁇ 10 ⁇ m
  • the depth difference between adjacent grooves 5 is ⁇ 10 ⁇ m.
  • the width of the N-type Schottky contact region 9 continuously increases from the edge to the center, that is, the contact area of the N-type Schottky contact region 9 continuously increases from the edge to the center.
  • the distance between adjacent P-type ion implantation regions 4 may increase stepwise from the edge to the center of the junction barrier Schottky diode, that is, the N-type Schottky contact
  • the width of the region 9 increases stepwise from the edge to the center of the junction barrier Schottky diode, and the depth of the groove 5 can increase stepwise from the edge to the center of the junction barrier Schottky diode. Big. Please refer to FIG. 10.
  • FIG. 10 is a dimension drawing of another junction barrier Schottky diode provided by an embodiment of the present invention. As shown in the figure, the width of the N-type Schottky contact region 9 is from left to right.
  • the depth of the groove 5 from left to right is represented by D 1 , D 2 , D 3 , D 4.
  • the width of the N-type Schottky contact region 9 increases stepwise from the edge to the center, that is, the contact area of the N-type Schottky contact region 9 is from the edge to the center.
  • the distance gradually increases, and the depth of the groove 5 increases stepwise from the edge to the center, that is, the depth of the groove 5 gradually increases at a distance from the edge to the center.
  • the temperature difference of the device effectively suppresses the occurrence of local electromigration, thereby improving the reliability of the device.
  • the phenomenon that the leakage current of the device increases due to the increase of the area of the N-type Schottky contact region 9 in the center is avoided.
  • the top view shape of the P-type ion implantation region 4 excluding the groove 5 is a ring shape or a rectangular shape, and it surrounds the upper surface of the N-epitaxial layer 3 in parallel, and the ring shape may be a circle or a square shape.
  • the structure of the P-type ion implantation region 4 in the first embodiment is the same.
  • the depth of each P-type ion implantation region 4 is ⁇ 2.5 ⁇ m and the width is ⁇ 6.2 ⁇ m. The distance between them is ⁇ 3 ⁇ m, and the distance between adjacent P-type ion implantation regions 4 is increasing from the edge to the center.
  • FIGS. 11a to 11e are schematic diagrams of the fabrication process of another junction barrier Schottky diode according to an embodiment of the present invention.
  • the manufacturing method of the junction barrier Schottky diode of this embodiment specifically includes the following steps:
  • Step 1 Epitaxially grow an N- epitaxial layer on the N+ substrate layer.
  • N- epitaxial layer Specifically, please refer to Figure 11a. Select a highly doped N-type silicon carbide substrate as the N+ substrate layer 2, and perform RCA standard cleaning on the N+ substrate layer 2. , And then epitaxially grow an N-epitaxial layer 3 with a thickness of ⁇ 5 ⁇ m on its front surface.
  • Step 2 Form a P-type ion implantation area, specifically, referring to Fig. 11b, first deposit 2 ⁇ m SiO 2 as a barrier layer for ion implantation in the P-type ion implantation area 4; secondly, form P-type ion implantation by photolithography and etching In the implantation window of region 4, the distance between the implantation windows is increasing from the edge to the center of the trench junction barrier Schottky diode; finally, a P-type ion implantation region 4 is formed by an ion implantation process.
  • a groove 5 is provided in the type ion implantation region 4, and the depth of the groove 5 increases from the edge to the center of the groove type junction barrier Schottky diode.
  • Step 3 Form a bottom metal layer.
  • a Ni metal layer is sputtered on the lower surface of the N+ substrate layer 2 by means of magnetron sputtering and sequentially stacked on the lower surface of the Ni metal layer.
  • a Ti/Ni/Ag metal layer is formed to form the underlying metal layer 1, the thickness of the Ni metal layer is 50-100 nm, and the total thickness of the sequentially stacked Ti/Ni/Ag metal layers is 2-5 ⁇ m.
  • the contact area between the N+ substrate layer 2 and the bottom metal layer 1 is an ohmic contact area 8.
  • Step 4 Form an isolation dielectric layer. Specifically, referring to FIG. 11d, a SiO 2 isolation dielectric layer is deposited on the N- epitaxial layer 3 with a thickness of 200-500 nm, and the SiO 2 isolation is etched through a photolithography mask The dielectric layer forms an isolation dielectric layer 6 which surrounds the upper surface of the N-epitaxial layer 3.
  • Step 5 Form a top metal layer. Specifically, referring to FIG. 11e, a Ti metal layer is sputtered on the upper surface of the N- epitaxial layer 3 and the inner surface of the groove 5 by magnetron sputtering, and a Ti metal layer is formed on the Ti An Al metal layer or Ag metal layer is formed on the metal layer to form the top metal layer 7, the Ti metal layer has a thickness of 50-100 nm, and the Al metal layer or Ag metal layer has a thickness of 2-5 ⁇ m.
  • the contact area between the N-epitaxial layer 3 and the top metal layer 7 is an N-type Schottky contact area 9, and the bottom of the groove 5 and the second contact area 11 of the top metal layer 7 are P-type Schottky contact or ohmic contact.

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Abstract

一种结型势垒肖特基二极管，包括从下至上依次设置的底层金属层（1）、N+衬底层（2）和N-外延层（3），其中，N-外延层（3）的上表面设置有若干个P型离子注入区（4），相邻P型离子注入区（4）之间的间距从结型势垒肖特基二极管的边缘到中心呈增大趋势；N-外延层（3）上设置有隔离介质层（6）和顶层金属层（7），隔离介质层（6）环绕在N-外延层（3）上表面的四周，顶层金属层（7）设置在N-外延层（3）和隔离介质层（6）上表面且与P型离子注入区（4）接触。P型离子注入区（4）内可设置有凹槽（5），凹槽（5）的深度从结型势垒肖特基二极管的边缘到中心呈增大趋势。该结型势垒肖特基二极管在保证反向漏电流和正向导通电阻没有退化的前提下，能有效抑制局部电迁移现象的发生，从而提高器件的可靠性。

Description

一种结型势垒肖特基二极管 技术领域
本发明属于微电子技术领域，具体涉及一种结型势垒肖特基二极管。
背景技术
宽禁带半导体材料是继第一代硅、锗和第二代砷化镓、磷化铟等材料之后发展起来的第三代半导体材料。在第三代半导体材料中，碳化硅(SiC)由于具有较大的禁带宽度、较高的临界击穿电场、高的热导率和高的电子饱和漂移速度等优良的物理化学性能，被广泛应用在高温、高压、大功率和抗辐照的半导体器件中。
随着碳化硅工艺的成熟，碳化硅肖特基二极管也逐渐实现了产业化，但是肖特基二极管的过大的反向漏电流依然是制约其在高压领域应用的主要因素，为了降低肖特基二极管过大的反向漏电流这一缺点，结型势垒肖特基二极管(Junction Barrier Schottky Diode，简称JBS)，得到了广泛的研究。JBS二极管具有良好的正向导通特性和反向漏电流小等特点，使其在功率电子领域得到广泛应用。
在目前的生产过程中，由于JBS器件不同位置所接触的封装面积不同，导致JBS器件不同位置的散热条件不同，最终导致JBS器件的中心温度大于边缘温度。这个温度差会导致JBS器件不同位置载流子迁移率不同，温度高的位置，载流子迁移率减小，从而导致电流分布不均匀，芯片会出现局部电迁移的现象，从而影响器件的可靠性。
发明内容
为了解决现有技术中存在的上述问题，本发明提供了一种结型势垒肖特基二极管。本发明要解决的技术问题通过以下技术方案实现：
本发明提供了一种结型势垒肖特基二极管，包括从下至上依次设置的底层金属层、N+衬底层和N-外延层，其中，
所述N-外延层的上表面设置有若干个P型离子注入区，相邻所述P型离子注入区之间的间距从所述结型势垒肖特基二极管的边缘到中心呈增大趋势；
所述N-外延层上设置有隔离介质层和顶层金属层，所述隔离介质层环绕在所述N-外延层上表面的四周，所述顶层金属层设置在所述N-外延层和所述隔离介质层的上表面，与所述P型离子注入区接触。
在本发明的一个实施例中，
所述N+衬底层与所述底层金属层的接触区为欧姆接触区；
所述N-外延层与所述顶层金属层的接触区为N型肖特基接触区；
所述P型离子注入区与所述顶层金属层的第一接触区为P型肖特基接触或欧姆接触。
在本发明的一个实施例中，相邻所述P型离子注入区之间的间距从所述结型势垒肖特基二极管的边缘到中心连续增大。
在本发明的一个实施例中，相邻所述P型离子注入区之间的间距从所述结型势垒肖特基二极管的边缘到中心呈阶梯状增大。
在本发明的一个实施例中，所述P型离子注入区的俯视形状为环状或者矩形形状，每个所述P型离子注入区的结构尺寸均相等，所述P型离子注入区的深度≤2μm，相邻所述P型离子注入区之间的间距≥2μm。
在本发明的一个实施例中，每个所述P型离子注入区内部设置有凹槽，所述凹槽的深度从所述结型势垒肖特基二极管的边缘到中心呈增大趋势，所述凹槽的内部设置有所述顶层金属层。
在本发明的一个实施例中，所述凹槽的底部与所述顶层金属层的第二接触区为P型肖特基接触或欧姆接触。
在本发明的一个实施例中，所述凹槽的深度从所述结型势垒肖特基二极管的边缘到中心连续增大。
在本发明的一个实施例中，所述凹槽的深度从所述结型势垒肖特基二极管的边缘到中心呈阶梯状增大。
在本发明的一个实施例中，相邻所述P型离子注入区之间的间距≥3μm，所述P型离子注入区侧壁厚度≤0.8μm，每个所述P型离子注入区的宽度均相等，所述P型离子注入区的深度与其对应所述凹槽的深度之间的差值不变，所述凹槽的宽度≤5μm，深度≥1μm。
与现有技术相比，本发明的有益效果在于：
1、本发明的结型势垒肖特基二极管，通过增大器件中心的N型肖特基接触区的面积，减小器件边缘的N型肖特基接触区的面积，在保证反向漏电流和正向导通电阻没有退化的前提下，减小了JBS器件的温度差，有效抑制了局部电迁移现象的发生，从而提高器件的可靠性；
2、本发明的结型势垒肖特基二极管，通过在每个所述P型离子注入区内部设置凹槽，形成槽型结型势垒肖特基二极管(Trench Junction Barrier Schottky Diode，简称TJBS)，相比于JBS二极管，由于减小了肖特基区的电场，所以二极管漏电流明显减小，而且通过增大器件中心的N型肖特基接触区的面积，减小器件边缘的N型肖特基接触区的面积，在保证反向漏 电流和正向导通电阻没有退化的前提下，减小了TJBS器件的温度差，有效抑制了局部电迁移现象的发生，从而提高器件的可靠性；
3、本发明的结型势垒肖特基二极管，通过增大器件中心的凹槽深度，减小器件边缘的凹槽深度，避免了由于器件中心的N型肖特基接触区面积增大，而造成器件漏电流增大的现象。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
附图说明
图1是本发明实施例提供的一种结型势垒肖特基二极管的结构示意图；
图2是本发明实施例提供的一种结型势垒肖特基二极管的尺寸标注图；
图3是本发明实施例提供的另一种结型势垒肖特基二极管的尺寸标注图；
图4是本发明实施例提供的一种P型离子注入区的俯视结构示意图；
图5是本发明实施例提供的另一种P型离子注入区的俯视结构示意图；
图6a-图6e是本发明实施例提供的一种结型势垒肖特基二极管的制备过程示意图。
图7是本发明实施例提供的另一种结型势垒肖特基二极管的结构示意图；
图8是图7中区域a结构的尺寸标注图；
图9是本发明实施例提供的另一种结型势垒肖特基二极管的尺寸标注图；
图10是本发明实施例提供的又一种结型势垒肖特基二极管的尺寸标注图；
图11a-图11e是本发明实施例提供的另一种结型势垒肖特基二极管的制备过程示意图。
附图标记说明
1-底层金属层；2-N+衬底层；3-N-外延层；4-P型离子注入区；5-凹槽；6-隔离介质层；7-顶层金属层；8-欧姆接触区；9-N型肖特基接触区；10-第一接触区；11-第二接触区。
具体实施方式
为了进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及具体实施方式，对依据本发明提出的一种结型势垒肖特基二极管进行详细说明。
有关本发明的前述及其他技术内容、特点及功效，在以下配合附图的具体实施方式详细说明中即可清楚地呈现。通过具体实施方式的说明，可对本发明为达成预定目的所采取的技术手段及功效进行更加深入且具体地了解，然而所附附图仅是提供参考与说明之用，并非用来对本发明的技术方案加以限制。
实施例一
请参见图1，图1是本发明实施例提供的一种结型势垒肖特基二极管的结构示意图，如图所示，本发明实施例的一种结型势垒肖特基二极管，包括从下至上依次设置的底层金属层1、N+衬底层2和N-外延层3。N-外延层3的上表面设置有若干个P型离子注入区4，相邻P型离子注入区4之间的间距从结型势垒肖特基二极管的边缘到中心呈增大趋势。N-外延层3上设 置有隔离介质层6和顶层金属层7，隔离介质层6环绕在N-外延层3上表面的四周，顶层金属层7设置在N-外延层3和隔离介质层6的上表面，与P型离子注入区4接触。进一步地，N+衬底层2与底层金属层1的接触区为欧姆接触区8；N-外延层3与顶层金属层7的接触区为N型肖特基接触区9；P型离子注入区4与顶层金属层7的第一接触区10为P型肖特基接触或欧姆接触。
具体地，底层金属层1包括与N+衬底层2接触的Ni金属层，以及在所述Ni金属层下表面依次堆叠的Ti/Ni/Ag金属层，所述Ni金属层的厚度为50-100nm，所述依次堆叠的Ti/Ni/Ag金属层的总厚度为2-5μm。N+衬底层2为高掺杂的N型碳化硅衬底片，N-外延层3的厚度为10-30μm，隔离介质层6为SiO 2隔离介质层，其厚度为200-500nm。顶层金属层7包括与N-外延层3上表面和P型离子注入区4上表面接触的Ti金属层，以及在所述Ti金属层上设置的Al金属层或Ag金属层，所述Ti金属层的厚度为50-100nm，所述Al金属层或Ag金属层的厚度为2-5μm。每个P型离子注入区4的结构尺寸均相等，P型离子注入区4的深度≤2μm，相邻P型离子注入区4之间的间距≥2μm。
在JBS器件中，由于不同位置所接触的封装面积不同，导致所述JBS器件不同位置的散热条件不同，因为N型肖特基接触区9的面积越大，所述JBS器件的电流密度越大，则所述JBS器件的功率越大，所述JBS器件的发热也越严重。通过减小所述JBS器件边缘的N型肖特基接触区9的面积，并且利用所述JBS器件边缘散热特性好的特点，可以有效的降低所述JBS器件边缘的温度，但是只单纯的减小边缘的N型肖特基接触区9的面积会导致所述JBS器件的正向特性削弱。而本实施例的结型势垒肖特基二 极管，由于相邻P型离子注入区4之间的间距从所述结型势垒肖特基二极管的边缘到中心呈增大趋势，即N型肖特基接触区9的接触面积从边缘到中心呈增大趋势，也就是通过增大中心的N型肖特基接触区9的面积，减小边缘的N型肖特基接触区9的面积，在保证反向漏电流和正向导通电阻没有退化的前提下，减小了所述JBS器件的温度差，有效抑制了局部电迁移现象的发生，从而提高了器件的可靠性。
进一步地，相邻P型离子注入区4之间的间距从所述结型势垒肖特基二极管的边缘到中心连续增大，具体地，P型离子注入区4之间为N-外延层3，N-外延层3与顶层金属层7的接触区为N型肖特基接触区9，即N型肖特基接触区9的宽度从所述结型势垒肖特基二极管的边缘到中心连续增大，请参见图2，图2是本发明实施例提供的一种结型势垒肖特基二极管的尺寸标注图，如图所示，N型肖特基接触区9的宽度从左至右依次用W S1、W S2、W S3、W S4、W S5、W S6、W S7、W S8和W S9表示，在本实施例中，N型肖特基接触区9的宽度大小关系为W S1<W S2<W S3<W S4<W S5>W S6>W S7>W S8>W S9，相邻N型肖特基接触区9的宽度差值≤10μm。
本实施例的结型势垒肖特基二极管，N型肖特基接触区9的宽度从边缘到中心连续增大，即N型肖特基接触区9的接触面积从边缘到中心连续增大，通过增大中心的N型肖特基接触区9的面积，减小边缘的N型肖特基接触区9的面积，在保证反向漏电流和正向导通电阻没有退化的前提下，减小了所述JBS器件的温度差，有效抑制了局部电迁移现象的发生，从而提高了器件的可靠性。
进一步地，在其他实施例中，相邻P型离子注入区4之间的间距从所述结型势垒肖特基二极管的边缘到中心可以呈阶梯状增大，即N型肖特基 接触区9的宽度从所述结型势垒肖特基二极管的边缘到中心呈阶梯状增大，请参见图3，图3是本发明实施例提供的另一种结型势垒肖特基二极管的尺寸标注图，如图所示，N型肖特基接触区9的宽度从左至右依次用W 1、W 2、W 3、W 4、W 5、W 6、W 7、W 8和W 9表示，在本实施例中，N型肖特基接触区9的宽度大小关系为W 1＝W 2<W 3＝W 4<W 5>W 6＝W 7>W 8＝W 9。需要理解的是，在本实施例中，不仅限于连续两个N型肖特基接触区9的宽度相等。
本实施例的结型势垒肖特基二极管，N型肖特基接触区9的宽度从边缘到中心呈阶梯状增大，也就是N型肖特基接触区9的接触面积从边缘到中心相隔一段距离逐渐增大，通过增大中心的N型肖特基接触区9的面积，减小边缘的N型肖特基接触区9的面积，在保证反向漏电流和正向导通电阻没有退化的前提下，减小了所述JBS器件的温度差，有效抑制了局部电迁移现象的发生，从而提高了器件的可靠性。
进一步地，P型离子注入区4的俯视形状为环状或者矩形形状。请参见图4，图4是本发明实施例提供的一种P型离子注入区的俯视结构示意图，如图所示，在本实施例中，P型离子注入区4的俯视形状为环状，并且平行环绕在N-外延层3上表面的四周，所述环状可以为圆形或者方形，每个P型离子注入区4的深度≤2μm，相邻P型离子注入区4之间的间距≥2μm，相邻P型离子注入区4之间的间距从边缘到中心呈增大趋势。请参见图5，图5是本发明实施例提供的另一种P型离子注入区的俯视结构示意图，如图所示，在其他实施例中，P型离子注入区4的俯视形状为矩形形状，并且在N-外延层3的上表面分布成矩形阵列，每个P型离子注入区4的结构尺寸均相等，其深度≤2μm，相邻P型离子注入区4之间的间距≥2μm，相邻P型离子注入区4之间的间距从边缘到中心呈增大趋势。
请参见图6a-图6e，图6a-图6e是本发明实施例提供的一种结型势垒肖特基二极管的制备过程示意图。本实施例的结型势垒肖特基二极管的制备方法，具体包括以下步骤：
步骤1：在N+衬底层上外延生长N-外延层，具体地，请参见图6a，选择高掺杂的N型碳化硅衬底片作为N+衬底层2，先对N+衬底层2进行RCA标准清洗，再在其正面上外延生长厚度为10-30μm的N-外延层3。
步骤2：形成P型离子注入区，具体地，请参见图6b，首先淀积2μm的SiO 2作为P型离子注入区4离子注入的阻挡层；其次通过光刻和刻蚀形成P型离子注入区4的注入窗口，所述注入窗口之间的间距从所述结型势垒肖特基二极管的边缘到中心呈增大趋势；最后通过离子注入工艺形成P型离子注入区4。
步骤3：形成底层金属层，具体地，请参见图6c，在N+衬底层2的下表面通过磁控溅射的方式溅射形成Ni金属层以及在所述Ni金属层下表面形成依次堆叠的Ti/Ni/Ag金属层，从而形成底层金属层1，所述Ni金属层的厚度为50-100nm，所述依次堆叠的Ti/Ni/Ag金属层的总厚度为2-5μm。N+衬底层2与底层金属层1的接触区为欧姆接触区8。
步骤4：形成隔离介质层，具体地，请参见图6d，在N-外延层3上淀积一层SiO 2隔离介质层，厚度为200-500nm，通过光刻掩模腐蚀所述SiO 2隔离介质层，形成隔离介质层6，隔离介质层6环绕在N-外延层3上表面的四周。
步骤5：形成顶层金属层，具体地，请参见图6e，通过磁控溅射的方式在N-外延层3上表面和P型离子注入区4上表面溅射形成Ti金属层，并在所述Ti金属层的上形成Al金属层或Ag金属层，从而形成顶层金属层7， 所述Ti金属层的厚度为50-100nm，所述Al金属层或Ag金属层的厚度为2-5μm。N-外延层3与顶层金属层7的接触区为N型肖特基接触区9，P型离子注入区4与顶层金属层7的第一接触区10为P型肖特基接触或欧姆接触。
实施例二
请参见图7，图7是本发明实施例提供的另一种结型势垒肖特基二极管的结构示意图，如图所示，本发明实施例的一种结型势垒肖特基二极管，包括从下至上依次设置的底层金属层1、N+衬底层2和N-外延层3，其中，N-外延层3的上表面设置有若干个P型离子注入区4，每个P型离子注入区4内部设置有凹槽5，相邻P型离子注入区4之间的间距从所述结型势垒肖特基二极管的边缘到中心呈增大趋势，凹槽5的深度从所述结型势垒肖特基二极管的边缘到中心呈增大趋势；N-外延层3上设置有隔离介质层6和顶层金属层7，隔离介质层6环绕在N-外延层3上表面的四周，顶层金属层7设置在N-外延层3和隔离介质层6的上表面以及凹槽5的内部。进一步地，N+衬底层2与底层金属层1的接触区为欧姆接触区8，N-外延层3与顶层金属层7的接触区为N型肖特基接触区9，凹槽5的底部与顶层金属层7的第二接触区11为P型肖特基接触或欧姆接触。
具体地，底层金属层1包括与N+衬底层2接触的Ni金属层，以及在所述Ni金属层下表面依次堆叠的Ti/Ni/Ag金属层，所述Ni金属层的厚度为50-100nm，所述依次堆叠的Ti/Ni/Ag金属层的总厚度为2-5μm。N+衬底层2为高掺杂的N型碳化硅衬底片，N-外延层3的厚度为≥5μm。每个P型离子注入区4的宽度均相等，P型离子注入区4的深度与其对应凹槽5的深度之间的差值不变。在本实施例中，请参见图8，P型离子注入区4的深 度h≥2.5μm，宽度m≤6.2μm，侧壁厚度n≤0.8μm，相邻P型离子注入区4之间的间距≥3μm，凹槽5的宽度c≤5μm，深度d≥1μm，优选地，凹槽5的宽度c为3μm，此时器件的反向漏电流和正向导通电阻两者折中，P型离子注入区4的深度h与其对应凹槽5的深度d之间的差值h-d固定不变。隔离介质层6为SiO 2隔离介质层，其厚度为200-500nm。顶层金属层7包括与N-外延层3上表面和凹槽5内表面接触的Ti金属层，以及在所述Ti金属层上设置的Al金属层或Ag金属层，所述Ti金属层的厚度为50-100nm，所述Al金属层或Ag金属层的厚度为2-5μm。
在本实施例的结型势垒肖特基二极管，通过在每个P型离子注入区内部设置凹槽，形成槽型结型势垒肖特基二极管(Trench Junction Barrier Schottky Diode，简称TJBS)，相比于JBS二极管，由于减小了肖特基区的电场，所以二极管漏电流明显减小。但是，由于不同位置所接触的封装面积不同，导致所述TJBS器件不同位置的散热条件不同，因为N型肖特基接触区9的面积越大，所述TJBS器件的电流密度越大，则所述TJBS器件的功率越大，所述TJBS器件的发热也越严重。通过减小所述TJBS器件边缘的N型肖特基接触区9的面积，并且利用所述TJBS器件边缘散热特性好的特点，可以有效的降低所述TJBS器件边缘的温度，但是只单纯的减小边缘的N型肖特基接触区9的面积会导致所述TJBS器件的正向特性削弱。
而本实施例的结型势垒肖特基二极管，由于相邻P型离子注入区4之间的间距从所述结型势垒肖特基二极管的边缘到中心呈增大趋势，即N型肖特基接触区9的接触面积从边缘到中心呈增大趋势，也就是通过增大中心的N型肖特基接触区9的面积，减小边缘的N型肖特基接触区9的面积，在保证反向漏电流和正向导通电阻没有退化的前提下，减小了所述TJBS 器件的温度差，有效抑制了局部电迁移现象的发生，从而提高了器件的可靠性。由于随着N型肖特基接触区9的面积的增大，所述TJBS器件的漏电流也会增加，而增大凹槽5的深度可以减小器件的漏电流，因此，本实施例的结型势垒肖特基二极管，通过增大中心的凹槽5的深度，减小边缘凹槽5的深度，避免了由于中心的N型肖特基接触区9面积增大，而造成器件漏电流增大的现象。
进一步地，相邻P型离子注入区4之间的间距从所述结型势垒肖特基二极管的边缘到中心连续增大，具体地，P型离子注入区4之间为N-外延层3，N-外延层3与顶层金属层7的接触区为N型肖特基接触区9，即N型肖特基接触区9的宽度从边缘到中心连续增大。凹槽5的深度从所述结型势垒肖特基二极管的边缘到中心连续增大。请参见图9，图9是本发明实施例提供的另一种结型势垒肖特基二极管的尺寸标注图，如图所示，N型肖特基接触区9的宽度从左至右依次用W S1、W S2、W S3、W S4、W S5、W S6、W S7、W S8和W S9表示，凹槽5的深度从左至右依次用D p1、D p2、D p3、D p4、D p5、D p6、D p7、D p8、D p9和D p10表示，在本实施例中，N型肖特基接触区9的宽度大小关系为W S1<W S2<W S3<W S4<W S5>W S6>W S7>W S8>W S9，凹槽5的深度大小关系为D p1<D p2<D p3<D p4<D p5＝D p6<D p7<D p8<D p9<D p10。其中，相邻N型肖特基接触区9的宽度差值≤10μm，相邻凹槽5的深度差值≤10μm。
本实施例的结型势垒肖特基二极管，N型肖特基接触区9的宽度从边缘到中心连续增大，也就是N型肖特基接触区9的接触面积从边缘到中心连续增大，而且凹槽5的深度从边缘到中心连续增大。通过增大中心的N型肖特基接触区9的面积，减小边缘的N型肖特基接触区9的面积，在保证反向漏电流和正向导通电阻没有退化的前提下，减小了器件的温度差，有 效抑制了局部电迁移现象的发生，从而提高了器件的可靠性。同时，通过增大中心的凹槽5的深度，减小边缘凹槽5的深度，避免了由于中心的N型肖特基接触区9面积增大，而造成器件漏电流增大的现象。
进一步地，在其他实施例中，相邻P型离子注入区4之间的间距从所述结型势垒肖特基二极管的边缘到中心可以呈阶梯状增大，即N型肖特基接触区9的宽度从所述结型势垒肖特基二极管的边缘到中心呈阶梯状增大，凹槽5的深度从所述结型势垒肖特基二极管的边缘到中心可以呈阶梯状增大。请参见图10，图10是本发明实施例提供的又一种结型势垒肖特基二极管的尺寸标注图，如图所示，N型肖特基接触区9的宽度从左至右依次用W 1、W 2、W 3、W 4、W 5、W 6、W 7、W 8和W 9表示，凹槽5的深度从左至右依次用D 1、D 2、D 3、D 4、D 5、D 6、D 7、D 8、D 9和D 10表示，在本实施例中，N型肖特基接触区9的宽度大小关系为W 1＝W 2<W 3＝W 4<W 5>W 6＝W 7>W 8＝W 9，凹槽5的深度大小关系为D 1＝D 2<D 3＝D 4<D 5＝D 6<D 7＝D 8<D 9＝D 10。需要理解的是，在本实施例中，不仅限于连续两个N型肖特基接触区9的宽度相等，连续两个凹槽5的深度相等。
本实施例的结型势垒肖特基二极管，N型肖特基接触区9的宽度从边缘到中心呈阶梯状增大，也就是N型肖特基接触区9的接触面积从边缘到中心相隔一段距离逐渐增大，凹槽5的深度从边缘到中心呈阶梯状增大，也就是凹槽5的深度从边缘到中心相隔一段距离逐渐增大。通过增大中心的N型肖特基接触区9的面积，减小边缘的N型肖特基接触区9的面积，在保证反向漏电流和正向导通电阻没有退化的前提下，减小了器件的温度差，有效抑制了局部电迁移现象的发生，从而提高了器件的可靠性。同时，通过增大中心的凹槽5的深度，减小边缘凹槽5的深度，避免了由于中心 的N型肖特基接触区9面积增大，而造成器件漏电流增大的现象。
进一步地，不包括凹槽5的P型离子注入区4的俯视形状为环状或者矩形形状，并且平行环绕在N-外延层3上表面的四周，所述环状可以为圆形或者方形。与实施例一中的P型离子注入区4的结构相同，在本实施例中，每个P型离子注入区4的深度≥2.5μm，宽度≤6.2μm，相邻P型离子注入区4之间的间距≥3μm，相邻P型离子注入区4之间的间距从边缘到中心呈增大趋势。
请参见图11a-图11e，图11a-图11e是本发明实施例提供的另一种结型势垒肖特基二极管的制备过程示意图。本实施例的结型势垒肖特基二极管的制备方法，具体包括以下步骤：
步骤1：在N+衬底层上外延生长N-外延层，具体地，请参见图11a，选择高掺杂的N型碳化硅衬底片作为N+衬底层2，先对N+衬底层2进行RCA标准清洗，再在其正面上外延生长厚度≥5μm的N-外延层3。
步骤2：形成P型离子注入区，具体地，请参见图11b，首先淀积2μm的SiO 2作为P型离子注入区4离子注入的阻挡层；其次通过光刻和刻蚀形成P型离子注入区4的注入窗口，所述注入窗口之间的间距从所述槽型结型势垒肖特基二极管的边缘到中心呈增大趋势；最后通过离子注入工艺形成P型离子注入区4，P型离子注入区4内设置有凹槽5，凹槽5的深度从所述槽型结型势垒肖特基二极管的边缘到中心呈增大趋势。
步骤3：形成底层金属层，具体地，请参见图11c，在N+衬底层2的下表面通过磁控溅射的方式溅射形成Ni金属层以及在所述Ni金属层下表面形成依次堆叠的Ti/Ni/Ag金属层，从而形成底层金属层1，所述Ni金属层的厚度为50-100nm，所述依次堆叠的Ti/Ni/Ag金属层的总厚度为2-5μm。 N+衬底层2与底层金属层1的接触区为欧姆接触区8。
步骤4：形成隔离介质层，具体地，请参见图11d，在N-外延层3上淀积一层SiO 2隔离介质层，厚度为200-500nm，通过光刻掩模腐蚀所述SiO 2隔离介质层，形成隔离介质层6，隔离介质层6环绕在N-外延层3上表面的四周。
步骤5：形成顶层金属层，具体地，请参见图11e，通过磁控溅射的方式在N-外延层3上表面和凹槽5的内表面溅射形成Ti金属层，并在所述Ti金属层的上形成Al金属层或Ag金属层，从而形成顶层金属层7，所述Ti金属层的厚度为50-100nm，所述Al金属层或Ag金属层的厚度为2-5μm。N-外延层3与顶层金属层7的接触区为N型肖特基接触区9，凹槽5的底部与顶层金属层7的第二接触区11为P型肖特基接触或欧姆接触。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

  1. 一种结型势垒肖特基二极管，其特征在于，包括从下至上依次设置的底层金属层(1)、N+衬底层(2)和N-外延层(3)，其中，
    所述N-外延层(3)的上表面设置有若干个P型离子注入区(4)，相邻所述P型离子注入区(4)之间的间距从所述结型势垒肖特基二极管的边缘到中心呈增大趋势；
    所述N-外延层(3)上设置有隔离介质层(6)和顶层金属层(7)，所述隔离介质层(6)环绕在所述N-外延层(3)上表面的四周，所述顶层金属层(7)设置在所述N-外延层(3)和所述隔离介质层(6)的上表面，与所述P型离子注入区(4)接触。
  2. 根据权利要求1所述的结型势垒肖特基二极管，其特征在于，
    所述N+衬底层(2)与所述底层金属层(1)的接触区为欧姆接触区(8)；
    所述N-外延层(3)与所述顶层金属层(7)的接触区为N型肖特基接触区(9)；
    所述P型离子注入区(4)与所述顶层金属层(7)的第一接触区(10)为P型肖特基接触或欧姆接触。
  3. 根据权利要求1所述的结型势垒肖特基二极管，其特征在于，相邻所述P型离子注入区(4)之间的间距从所述结型势垒肖特基二极管的边缘到中心连续增大。
  4. 根据权利要求1所述的结型势垒肖特基二极管，其特征在于，相邻所述P型离子注入区(4)之间的间距从所述结型势垒肖特基二极管的边缘到中心呈阶梯状增大。
  5. 根据权利要求1所述的结型势垒肖特基二极管，其特征在于，所述P型离子注入区(4)的俯视形状为环状或者矩形形状，每个所述P型离子注 入区(4)的结构尺寸均相等，所述P型离子注入区(4)的深度≤2μm，相邻所述P型离子注入区(4)之间的间距≥2μm。
  6. 根据权利要求1所述的结型势垒肖特基二极管，其特征在于，每个所述P型离子注入区(4)内部设置有凹槽(5)，所述凹槽(5)的深度从所述结型势垒肖特基二极管的边缘到中心呈增大趋势，所述凹槽(5)的内部设置有所述顶层金属层(7)。
  7. 根据权利要求6所述的结型势垒肖特基二极管，其特征在于，所述凹槽(5)的底部与所述顶层金属层(7)的第二接触区(11)为P型肖特基接触或欧姆接触。
  8. 根据权利要求6所述的结型势垒肖特基二极管，其特征在于，所述凹槽(5)的深度从所述结型势垒肖特基二极管的边缘到中心连续增大。
  9. 根据权利要求6所述的结型势垒肖特基二极管，其特征在于，所述凹槽(5)的深度从所述结型势垒肖特基二极管的边缘到中心呈阶梯状增大。
  10. 根据权利要求6所述的结型势垒肖特基二极管，其特征在于，相邻所述P型离子注入区(4)之间的间距≥3μm，所述P型离子注入区(4)侧壁厚度≤0.8μm，每个所述P型离子注入区(4)的宽度均相等，所述P型离子注入区(4)的深度与其对应所述凹槽(5)的深度之间的差值不变，所述凹槽(5)的宽度≤5μm，深度≥1μm。
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