WO2020215545A1 - Tft 阵列基板及其制作方法 - Google Patents

Tft 阵列基板及其制作方法 Download PDF

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Publication number
WO2020215545A1
WO2020215545A1 PCT/CN2019/101939 CN2019101939W WO2020215545A1 WO 2020215545 A1 WO2020215545 A1 WO 2020215545A1 CN 2019101939 W CN2019101939 W CN 2019101939W WO 2020215545 A1 WO2020215545 A1 WO 2020215545A1
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Prior art keywords
tft array
array substrate
active layer
protective film
source
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PCT/CN2019/101939
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English (en)
French (fr)
Inventor
李利霞
王勐
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020215545A1 publication Critical patent/WO2020215545A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display technology, in particular to a TFT array substrate and a manufacturing method thereof.
  • LCD Liquid Crystal Display
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules between two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates. The liquid crystal molecules are controlled to change direction by powering on or not, and the light of the backlight module Refraction produces a picture.
  • the LCD panel is composed of a color film (CF, Color Filter) substrate, a thin film transistor (TFT, Thin Film Transistor) substrate, liquid crystal (LC, Liquid Crystal) sandwiched between the color film substrate and the thin film transistor substrate, and a sealant frame (Sealant).
  • the molding process generally includes: the front-end array (Array) process (thin film, yellow light, Etching and peeling), the middle cell process (the TFT substrate is bonded to the CF substrate), and the back module assembly process (the driver IC is pressed against the printed circuit board).
  • Array front-end array
  • Array thin film, yellow light, Etching and peeling
  • the middle cell process the TFT substrate is bonded to the CF substrate
  • the back module assembly process the driver IC is pressed against the printed circuit board.
  • the front Array process is mainly to form TFT substrates to control the movement of liquid crystal molecules;
  • the middle Cell process is mainly to add liquid crystal between the TFT substrate and the CF substrate;
  • the back module assembly process is mainly to drive IC pressing and printed circuits
  • the integration of the panel drives the rotation of the liquid crystal molecules to display images.
  • a-Si amorphous silicon
  • IGZO indium gallium zinc oxide
  • the IGZO type TFT array substrate generally adopts an etching stop (ESL) structure or a back channel etching (BCE) structure.
  • ESL etching stop
  • BCE back channel etching
  • the preparation process of the ESL structure of the IGZO type array substrate is relatively complicated and requires a large number of photomasks, which is not conducive to reducing costs.
  • the manufacturing process of the IGZO type TFT array substrate of the BCE structure is as follows: as shown in FIG. 1, a gate 200 is first fabricated on the substrate 100, and a gate insulating layer 300 is fabricated on the gate 200 and the substrate 100. An active layer 400 made of IGZO is formed on the insulating layer 300 above the gate 200, and then, as shown in FIG.
  • the source electrode 500 and the drain electrode 600 spaced apart are formed on the active layer 400 by etching a metal layer. Therefore, the production of the etching barrier layer can be eliminated, and the purpose of reducing the photomask can be achieved.
  • the existing etching solution will inevitably cause a certain degree of etching on the active layer of IGZO, which will change the surface characteristics of the active layer of IGZO. As a result, the stability of the TFT array substrate deteriorates.
  • the purpose of the present invention is to provide a method for manufacturing a TFT array substrate, which can prevent the source and drain processes from affecting the performance of the active layer and improve product quality.
  • Another object of the present invention is to provide a TFT array substrate, which can prevent the source and drain from affecting the performance of the active layer during production and improve product quality.
  • the present invention first provides a method for manufacturing a TFT array substrate, which includes the following steps:
  • Step S1 providing a substrate, forming a gate on the substrate, forming a gate insulating layer on the gate and the substrate, and forming an active layer above the gate on the gate insulating layer;
  • Step S2 forming a conductive protective film on the gate insulating layer and the active layer;
  • Step S3 forming source and drain electrodes located above the active layer and spaced apart on the conductive protective film;
  • Step S4 removing the part of the conductive protective film that is not blocked by the source electrode and the drain electrode, forming two conductive patterns arranged on the active layer at intervals, and the source electrode and the drain electrode are respectively arranged on the two conductive patterns.
  • the material of the conductive protective film is carbon atoms.
  • the source and drain are used as shields to irradiate the conductive protective film with ultraviolet light to remove the portions of the conductive protective film that are not shielded by the source and drain.
  • the material of the active layer is IGZO.
  • the manufacturing method of the TFT array substrate further includes step S5, forming a passivation layer on the gate insulating layer, the active layer, the source electrode and the drain electrode.
  • the present invention also provides a TFT array substrate, which includes a substrate, a gate provided on the substrate, a gate insulating layer provided on the substrate and the gate, and a gate insulating layer provided on the gate insulating layer and located above the gate.
  • the active layer two conductive patterns arranged on the active layer at intervals, and source and drain electrodes respectively arranged on the two conductive patterns.
  • the material of the conductive pattern is carbon atoms.
  • the material of the active layer is IGZO.
  • the TFT array substrate further includes a passivation layer arranged on the gate insulating layer, the active layer, and the source and drain electrodes.
  • the material of the substrate is glass
  • the material of the gate is at least one of molybdenum, aluminum, and copper;
  • the material of the gate insulating layer is at least one of silicon nitride and silicon oxide;
  • the materials of the source electrode and the drain electrode are at least one of molybdenum, aluminum and copper.
  • the manufacturing method of the TFT array substrate of the present invention first forms a conductive protective film on the gate insulating layer and the active layer, then forms the source and drain on the conductive protective film, and finally removes the conductive protective film.
  • the part that is blocked by the source and drain can avoid the bad influence of the etching solution on the performance of the active layer in the process of making the source and drain by etching the metal layer, thereby ensuring the performance of the TFT device in the TFT array substrate , Improve product stability.
  • the TFT array substrate of the present invention can prevent the source electrode and the drain electrode from affecting the performance of the active layer during production, and improve product quality.
  • 1 and 2 are schematic diagrams of the fabrication of the existing IGZO type TFT array substrate with BCE structure
  • FIG. 3 is a flow chart of the manufacturing method of the TFT array substrate of the present invention.
  • step S1 is a schematic diagram of step S1 of the manufacturing method of the TFT array substrate of the present invention.
  • step S2 is a schematic diagram of step S2 of the manufacturing method of the TFT array substrate of the present invention.
  • step S3 is a schematic diagram of step S3 of the manufacturing method of the TFT array substrate of the present invention.
  • step S5 of the manufacturing method of the TFT array substrate of the present invention is a schematic diagram of step S5 of the manufacturing method of the TFT array substrate of the present invention and a schematic diagram of the structure of the TFT array substrate of the present invention.
  • the present invention provides a manufacturing method of a TFT array substrate, which includes the following steps:
  • Step S1 referring to FIG. 4, a substrate 10 is provided, a gate 20 is formed on the substrate 10, a gate insulating layer 30 is formed on the gate 20 and the substrate 10, and a gate insulating layer 30 is formed on the gate insulating layer 30. 20 above the active layer 40.
  • the material of the substrate 10 is glass.
  • the material of the gate 20 is metal, and further, the material of the gate 20 is at least one of molybdenum (Mo), aluminum (Al), and copper (Cu).
  • the material of the gate insulating layer 30 is at least one of silicon nitride (SiNx) and silicon oxide (SiOx).
  • the material of the active layer 40 is IGZO.
  • Step S2 referring to FIG. 5, a conductive protective film 59 is formed on the gate insulating layer 30 and the active layer 40, and the conductive protective film 59 is used to protect the surface of the active layer 40.
  • the material of the conductive protective film 59 is carbon (C) atoms.
  • the thickness of the conductive protective film 59 may be several atomic layers.
  • Step S3 referring to FIG. 6, a source 61 and a drain 62 located above and spaced apart from the active layer 40 are formed on the conductive protective film 59, so that the gate 20, the active layer 40, the source 61 and the drain 62 Form a TFT device.
  • the material of the source 61 and the drain 62 is metal.
  • a metal material layer and a photoresist layer are first formed on the conductive protective film 59, and then the photoresist layer is subjected to an exposure and development process, and the photoresist layer after the exposure and development process is used as a shield and an etching solution is used to treat the metal
  • the material layer is patterned to obtain the source electrode 61 and the drain electrode 62. Since the conductive protective film 59 is formed on the active layer 40, the metal material layer is etched with an etching solution during the process of making the source electrode 61 and the drain electrode 62. The liquid will not contact the surface of the active layer 40, so the etching liquid will not corrode the active layer 40 made of IGZO material and cause adverse effects.
  • the material of the source 61 and the drain 62 is at least one of molybdenum, aluminum, and copper.
  • Step S4 referring to FIG. 8, remove the part of the conductive protective film 59 that is not blocked by the source 61 and the drain 62, and form two conductive patterns 50 spaced apart on the active layer 40.
  • the source 61 and the drain 62 are respectively Set on two conductive patterns 50.
  • the source 61 and the drain 62 are used to shield the conductive protective film 59 by ultraviolet ( UV) light is irradiated to destroy the part of the conductive protective film 59 that is not blocked by the source 61 and the drain 62 to remove the part of the conductive protective film 59 that is not blocked by the source 61 and the drain 62.
  • UV ultraviolet
  • the manufacturing method of the TFT array substrate of the present invention further includes step S5, forming a passivation layer 70 on the gate insulating layer 30, the active layer 40, the source 61 and the drain 62.
  • the manufacturing method of the TFT array substrate of the present invention adopts the BCE structure, and before the source 61 and the drain 62 are formed, a conductive material made of carbon atoms is formed on the gate insulating layer 30 and the active layer 40.
  • the protective film 59, and then the source 61 and the drain 62 are formed on the conductive protective film 59, and the conductive protective film 59 that is not blocked by the source 61 and the drain 62 is removed by ultraviolet light before the passivation layer 70 is formed
  • the performance of the TFT device in the array substrate improves the stability of the product.
  • the space occupied by the TFT device is reduced, the opening area is increased, and the transmittance is improved.
  • the present invention also provides a TFT array substrate manufactured by the above-mentioned manufacturing method of a TFT array substrate, including a substrate 10, a gate 20 provided on the substrate 10, and The gate insulating layer 30 on the substrate 10 and the gate 20, the active layer 40 disposed on the gate insulating layer 30 and above the gate 20, two conductive patterns 50 disposed on the active layer 40 at intervals, and The source 61 and the drain 62 are respectively provided on the two conductive patterns 50, the passivation layer 70 is provided on the gate insulating layer 30, the active layer 40, and the source 61 and the drain 62.
  • the material of the substrate 10 is glass.
  • the material of the gate 20 is metal, and further, the material of the gate 20 is at least one of molybdenum, aluminum, and copper.
  • the material of the gate insulating layer 30 is at least one of silicon nitride and silicon oxide.
  • the material of the active layer 40 is IGZO.
  • the material of the conductive pattern 50 is carbon atoms.
  • the thickness of the conductive protective film 59 may be several atomic layers.
  • the material of the source 61 and the drain 62 is metal. Further, the material of the source 61 and the drain 62 is at least one of molybdenum, aluminum, and copper.
  • the TFT array substrate of the present invention is made by the above-mentioned manufacturing method of the TFT array substrate and adopts the BCE structure.
  • the TFT array substrate reduces the space occupied by the TFT device and increases the opening area. It is beneficial to improve the transmittance, and at the same time, it can avoid using the etching solution to produce the source 61 and the drain 62 in the process of etching the metal layer to adversely affect the performance of the active layer 40, thereby ensuring the TFT devices in the TFT array substrate The performance improves the stability of the product.
  • the manufacturing method of the TFT array substrate of the present invention first forms a conductive protective film on the gate insulating layer and the active layer, then forms the source and drain on the conductive protective film, and finally removes the conductive protective film.
  • the part shielded by the source and drain can prevent the etching solution from adversely affecting the performance of the active layer in the process of etching the metal layer to make the source and drain, thereby ensuring the performance of the TFT device in the TFT array substrate.
  • the TFT array substrate of the present invention can prevent the source electrode and the drain electrode from affecting the performance of the active layer during production, and improve product quality.

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Abstract

本发明提供一种TFT阵列基板及其制作方法。本发明的TFT阵列基板的制作方法先在栅极绝缘层及有源层上形成导电保护膜，而后在导电保护膜上形成源极及漏极，最后去除导电保护膜未被源极及漏极遮挡的部分，能够避免采用蚀刻金属层的方式制作源极及漏极的过程中蚀刻液对有源层的性能产生不良影响，从而保证了TFT阵列基板中TFT器件的性能，提升产品的稳定性。

Description

TFT阵列基板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT阵列基板及其制作方法。
 背景技术
随着显示技术的发展，液晶显示器（Liquid Crystal Display，LCD）等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组（backlight module）。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜（CF，Color Filter）基板、薄膜晶体管（TFT，Thin Film Transistor）基板、夹于彩膜基板与薄膜晶体管基板之间的液晶（LC，Liquid Crystal）及密封胶框（Sealant）组成，其成型工艺一般包括：前段阵列（Array）制程（薄膜、黄光、蚀刻及剥膜）、中段成盒（Cell）制程（TFT基板与CF基板贴合）及后段模组组装制程（驱动IC与印刷电路板压合）。其中，前段Array制程主要是形成TFT基板，以便于控制液晶分子的运动；中段Cell制程主要是在TFT基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
现有的TFT阵列基板通常采用非晶硅（a-Si）材料来制作半导体层，然而，随着液晶显示装置朝着大尺寸和高分辨率的方向发展，传统的a-Si的迁移率已经无法满足要求，以铟镓锌氧化物（IGZO）为代表的金属氧化物材料的迁移率高，而且相应薄膜晶体管的制备与现有的a-Si为半导体驱动的产线的兼容性好，近年来迅速成为显示领域研发的重点。
目前，IGZO 型TFT阵列基板一般采用刻蚀阻挡（ESL）结构或背沟道蚀刻（BCE）结构， ESL结构的IGZO 型阵列基板的制备过程较为复杂，需要光罩数量多，不利于降低成本。而BCE结构的IGZO型TFT阵列基板的制作过程为：如图1所示，先在衬底100上制作栅极200，在栅极200及衬底100上制作栅极绝缘层300，在栅极绝缘层300上制作位于栅极200上方的采用IGZO制作的有源层400，而后如图2所示，在有源层400上采用蚀刻金属层的方式制作间隔的源极500及漏极600，从而能够取消蚀阻挡层的制作，达到减少光罩的目的，然而现有的蚀刻液不可避免的会对IGZO的有源层造成一定程度的蚀刻，使IGZO的有源层的表面特性发生改变，从而使TFT阵列基板的稳定性变差。
 技术问题
本发明的目的在于提供一种TFT阵列基板的制作方法，能够避免源极及漏极制程对有源层的性能造成影响，提升产品品质。
本发明的另一目的在于提供一种TFT阵列基板，能够避免源极及漏极在制作时对有源层的性能造成影响，提升产品品质。
 技术解决方案
为实现上述目的，本发明首先提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤S1、提供衬底，在衬底上形成栅极，在栅极及衬底上形成栅极绝缘层，在栅极绝缘层上形成位于栅极上方的有源层；
步骤S2、在栅极绝缘层及有源层上形成导电保护膜；
步骤S3、在导电保护膜上形成位于有源层上方且间隔的源极及漏极；
步骤S4、去除导电保护膜未被源极及漏极遮挡的部分，形成间隔设于有源层上的两个导电图案，源极及漏极分别设于两个导电图案上。
所述导电保护膜的材料为碳原子。
所述步骤S4中以源极及漏极为遮挡对导电保护膜进行紫外光照射以去除导电保护膜未被源极及漏极遮挡的部分。
所述有源层的材料为IGZO。
所述TFT阵列基板的制作方法还包括步骤S5、在栅极绝缘层、有源层、源极及漏极上形成钝化层。
本发明还提供一种TFT阵列基板，包括衬底、设于衬底上的栅极、设于衬底及栅极上的栅极绝缘层、设于栅极绝缘层上且位于栅极上方的有源层、间隔设于有源层上的两个导电图案以及分别设于两个导电图案上的源极及漏极。
所述导电图案的材料为碳原子。
所述有源层的材料为IGZO。
所述TFT阵列基板还包括设于栅极绝缘层、有源层及源极及漏极上的钝化层。
所述衬底的材料为玻璃；
所述栅极的材料为钼、铝、铜中的至少一种；
所述栅极绝缘层的材料为氮化硅及氧化硅中的至少一种；
所述源极及漏极的材料均为钼、铝、铜中的至少一种。
 有益效果
本发明的有益效果：本发明的TFT阵列基板的制作方法先在栅极绝缘层及有源层上形成导电保护膜，而后在导电保护膜上形成源极及漏极，最后去除导电保护膜未被源极及漏极遮挡的部分，能够避免采用蚀刻金属层的方式制作源极及漏极的过程中蚀刻液对有源层的性能产生不良影响，从而保证了TFT阵列基板中TFT器件的性能，提升产品的稳定性。本发明的TFT阵列基板能够避免源极及漏极在制作时对有源层的性能造成影响，提升产品品质。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1及图2为现有的BCE结构的IGZO型TFT阵列基板的制作示意图；
图3为本发明的TFT阵列基板的制作方法的流程图；
图4为本发明的TFT阵列基板的制作方法的步骤S1的示意图；
图5为本发明的TFT阵列基板的制作方法的步骤S2的示意图；
图6为本发明的TFT阵列基板的制作方法的步骤S3的示意图；
图7及图8为本发明的TFT阵列基板的制作方法的步骤S4的示意图；
图9为本发明的TFT阵列基板的制作方法的步骤S5的示意图暨本发明的TFT阵列基板的结构示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3，本发明提供一种TFT阵列基板的制作方法，包括如下步骤：
步骤S1、请参阅图4，提供衬底10，在衬底10上形成栅极20，在栅极20及衬底10上形成栅极绝缘层30，在栅极绝缘层30上形成位于栅极20上方的有源层40。
具体地，所述衬底10的材料为玻璃。
具体地，所述栅极20的材料为金属，进一步地，所述栅极20的材料为钼（Mo）、铝（Al）、铜（Cu）中的至少一种。
具体地，所述栅极绝缘层30的材料为氮化硅（SiNx）及氧化硅（SiOx）中的至少一种。
具体地，所述有源层40的材料为IGZO。
步骤S2、请参阅图5，在栅极绝缘层30及有源层40上形成导电保护膜59，利用该导电保护膜59对有源层40的表面进行保护。
具体地，在本发明的优选实施例中，所述导电保护膜59的材料为碳（C）原子。所述导电保护膜59的厚度可以为数个原子层厚度。
步骤S3、请参阅图6，在导电保护膜59上形成位于有源层40上方且间隔的源极61及漏极62，从而由栅极20、有源层40、源极61及漏极62构成TFT器件。
具体地，所述源极61及漏极62的材料为金属。所述步骤S3中，先在导电保护膜59上形成一层金属材料层及光阻层，而后对光阻层进行曝光显影制程，以曝光显影制程后的光阻层为遮挡利用蚀刻液对金属材料层进行图案化而制得源极61及漏极62，由于有源层40上形成有导电保护膜59，利用蚀刻液对金属材料层进行蚀刻制作源极61及漏极62的制程中蚀刻液不会接触有源层40表面，从而蚀刻液不会对采用IGZO材料制作的有源层40进行腐蚀而产生不良影响。
进一步地，所述源极61及漏极62的材料为钼、铝、铜中的至少一种。
步骤S4、请参阅图8，去除导电保护膜59未被源极61及漏极62遮挡的部分，形成间隔设于有源层40上的两个导电图案50，源极61及漏极62分别设于两个导电图案50上。
具体地，请参阅图7，在本发明的优选实施例中，由于导电保护膜59采用碳原子形成，所述步骤S4中以源极61及漏极62为遮挡对导电保护膜59进行紫外（UV）光照射，对导电保护膜59未被源极61及漏极62遮挡的部分进行破坏清除，以去除导电保护膜59未被源极61及漏极62遮挡的部分。
具体地，请参阅图9，本发明的TFT阵列基板的制作方法还包括步骤S5、在栅极绝缘层30、有源层40、源极61及漏极62上形成钝化层70。
需要说明的是，本发明的TFT阵列基板的制作方法采用BCE结构，并在制作源极61及漏极62之前，先在栅极绝缘层30及有源层40上形成材料为碳原子的导电保护膜59，而后在导电保护膜59上形成源极61及漏极62，并在制作钝化层70之前通过紫外光照射的方式去除导电保护膜59未被源极61及漏极62遮挡的部分，能够在节省光罩数量从而节省制作成本的同时，避免采用蚀刻金属层的方式制作源极61及漏极62的过程中蚀刻液对有源层40的性能产生不良影响，从而保证了TFT阵列基板中TFT器件的性能，提升产品的稳定性，同时相比于ESL结构的TFT阵列基板，降低了TFT器件所占空间，增加了开口面积，有利于提升穿透率。
请参阅图9，基于同一发明构思，本发明还提供一种采用上述的TFT阵列基板的制作方法制得的TFT阵列基板，包括衬底10、设于衬底10上的栅极20、设于衬底10及栅极20上的栅极绝缘层30、设于栅极绝缘层30上且位于栅极20上方的有源层40、间隔设于有源层40上的两个导电图案50以及分别设于两个导电图案50上的源极61及漏极62、设于栅极绝缘层30、有源层40及源极61及漏极62上的钝化层70。
具体地，所述衬底10的材料为玻璃。
具体地，所述栅极20的材料为金属，进一步地，所述栅极20的材料为钼、铝、铜中的至少一种。
具体地，所述栅极绝缘层30的材料为氮化硅及氧化硅中的至少一种。
具体地，所述有源层40的材料为IGZO。
具体地，所述导电图案50的材料为碳原子。所述导电保护膜59的厚度可以为数个原子层厚度。
具体地，所述源极61及漏极62的材料为金属。进一步地，所述源极61及漏极62的材料为钼、铝、铜中的至少一种。
需要说明的是，本发明的TFT阵列基板采用上述的TFT阵列基板的制作方法制得，采用BCE结构，相比于ESL结构的TFT阵列基板，降低了TFT器件所占空间，增加了开口面积，有利于提升穿透率，同时，能够避免采用蚀刻金属层的方式制作源极61及漏极62的过程中蚀刻液对有源层40的性能产生不良影响，从而保证了TFT阵列基板中TFT器件的性能，提升产品的稳定性。
综上所述，本发明的TFT阵列基板的制作方法先在栅极绝缘层及有源层上形成导电保护膜，而后在导电保护膜上形成源极及漏极，最后去除导电保护膜未被源极及漏极遮挡的部分，能够避免采用蚀刻金属层的方式制作源极及漏极的过程中蚀刻液对有源层的性能产生不良影响，从而保证了TFT阵列基板中TFT器件的性能，提升产品的稳定性。本发明的TFT阵列基板能够避免源极及漏极在制作时对有源层的性能造成影响，提升产品品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT阵列基板的制作方法，包括如下步骤：
    步骤S1、提供衬底，在衬底上形成栅极，在栅极及衬底上形成栅极绝缘层，在栅极绝缘层上形成位于栅极上方的有源层；
    步骤S2、在栅极绝缘层及有源层上形成导电保护膜；
    步骤S3、在导电保护膜上形成位于有源层上方且间隔的源极及漏极；
    步骤S4、去除导电保护膜未被源极及漏极遮挡的部分，形成间隔设于有源层上的两个导电图案，源极及漏极分别设于两个导电图案上。
  2. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述导电保护膜的材料为碳原子。
  3. 如权利要求2所述的TFT阵列基板的制作方法，其中，所述步骤S4中以源极及漏极为遮挡对导电保护膜进行紫外光照射以去除导电保护膜未被源极及漏极遮挡的部分。
  4. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述有源层的材料为IGZO。
  5. 如权利要求1所述的TFT阵列基板的制作方法，还包括步骤S5、在栅极绝缘层、有源层、源极及漏极上形成钝化层。
  6. 一种TFT阵列基板，包括衬底、设于衬底上的栅极、设于衬底及栅极上的栅极绝缘层、设于栅极绝缘层上且位于栅极上方的有源层、间隔设于有源层上的两个导电图案以及分别设于两个导电图案上的源极及漏极。
  7. 如权利要求6所述的TFT阵列基板，其中，所述导电图案的材料为碳原子。
  8. 如权利要求6所述的TFT阵列基板，其中，所述有源层的材料为IGZO。
  9. 如权利要求6所述的TFT阵列基板，还包括设于栅极绝缘层、有源层及源极及漏极上的钝化层。
  10. 如权利要求6所述的TFT阵列基板，其中，所述衬底的材料为玻璃；
    所述栅极的材料为钼、铝、铜中的至少一种；
    所述栅极绝缘层的材料为氮化硅及氧化硅中的至少一种；
    所述源极及漏极的材料为钼、铝、铜中的至少一种。
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Publication number Priority date Publication date Assignee Title
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CN104409515A (zh) * 2014-11-26 2015-03-11 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板和显示装置
CN110047851A (zh) * 2019-04-22 2019-07-23 深圳市华星光电半导体显示技术有限公司 Tft阵列基板及其制作方法

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US10177199B2 (en) * 2016-05-03 2019-01-08 Tsinghua University Method for making three dimensional complementary metal oxide semiconductor carbon nanotube thin film transistor circuit
CN106098704B (zh) * 2016-07-06 2019-05-03 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板
US10665796B2 (en) * 2017-05-08 2020-05-26 Carbon Nanotube Technologies, Llc Manufacturing of carbon nanotube thin film transistor backplanes and display integration thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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CN104409515A (zh) * 2014-11-26 2015-03-11 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板和显示装置
CN110047851A (zh) * 2019-04-22 2019-07-23 深圳市华星光电半导体显示技术有限公司 Tft阵列基板及其制作方法

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