WO2020093442A1 - 阵列基板的制作方法及阵列基板 - Google Patents

阵列基板的制作方法及阵列基板 Download PDF

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WO2020093442A1
WO2020093442A1 PCT/CN2018/116043 CN2018116043W WO2020093442A1 WO 2020093442 A1 WO2020093442 A1 WO 2020093442A1 CN 2018116043 W CN2018116043 W CN 2018116043W WO 2020093442 A1 WO2020093442 A1 WO 2020093442A1
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array substrate
photoresist
common electrode
transparent conductive
film
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PCT/CN2018/116043
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English (en)
French (fr)
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朱茂霞
徐洪远
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020093442A1 publication Critical patent/WO2020093442A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate manufacturing method and an array substrate.
  • LCD liquid crystal displays
  • other flat display devices have been widely used in mobile phones, TVs, and individuals due to their advantages of high image quality, power saving, thin body, and wide application range.
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become the mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates.
  • the liquid crystal molecules can be controlled to change the direction by turning on or off, and the light of the backlight module Refracted to produce a picture.
  • the liquid crystal display panel is composed of a color filter substrate (CF, Color), an array substrate (TFT, Thin Film Transistor), a liquid crystal (LC, Liquid) and a sealant frame (Sealant) sandwiched between the color filter substrate and the array substrate Composition
  • the molding process generally includes: the front-end array process (thin film, yellow light, etching and stripping), the middle-stage cell process (the TFT substrate is bonded to the CF substrate), and the rear-stage module assembly process ( The driver IC is pressed against the printed circuit board).
  • the front stage Array process is mainly to form a TFT substrate to facilitate the control of the movement of liquid crystal molecules;
  • the middle stage Cell process is mainly to add liquid crystal between the TFT substrate and the CF substrate;
  • the rear stage module assembly process is mainly to drive the IC pressing and printed circuit The integration of the board then drives the liquid crystal molecules to rotate and display images.
  • Existing array substrates generally include: a substrate substrate, a grid electrode arranged on the substrate substrate at intervals and an array substrate common electrode (Array Com, Acom), a common electrode provided on the substrate substrate, the gate electrode and the array substrate A gate insulating layer on the electrode, an active layer provided on the gate insulating layer on the gate, a source provided on the active layer and in contact with both ends of the active layer, and A drain, a passivation layer provided on the gate insulating layer, the active layer, the source and the drain, and a pixel electrode provided on the passivation layer and electrically connected to the drain, wherein
  • the gate and the common electrode of the array substrate are located on the same film layer and are made of opaque metal materials, and the aperture ratio is low.
  • the object of the present invention is to provide a method for manufacturing an array substrate, which can increase the pixel aperture ratio without increasing the number of photomasks.
  • the object of the present invention is also to provide an array substrate which can increase the pixel aperture ratio and improve the display effect.
  • the present invention provides a method for manufacturing an array substrate, including the following steps:
  • Step S1 Provide a base substrate on which a transparent conductive film and a metal film covering the transparent conductive film are formed;
  • Step S2 covering the metal film with a photoresist film
  • Step S3 patterning the photoresist film to remove the photoresist film except for the area where the gate and the common electrode of the array substrate are to be formed, to obtain the first photoresist segment on the area where the gate is to be formed Forming a second photoresist segment on the area of the common electrode of the array substrate, and the thickness of the first photoresist segment is greater than that of the second photoresist segment;
  • Step S4 Using the first photoresist section and the second photoresist section as shields, the transparent conductive film and the metal film are etched to remove the transparent conductive film and metal except for the area where the gate and the common electrode of the array substrate are to be formed film;
  • Step S5 Remove the second photoresist segment while thinning the first photoresist segment, etch the metal film with the remaining first photoresist segment as a shield, remove the metal film on the area where the common electrode of the array substrate is to be formed, to obtain an array substrate Common electrode
  • Step S6 Remove the remaining first photoresist segment to obtain the gate
  • Step S7 forming a gate insulating layer on the base electrode, the gate and the common electrode of the array substrate, forming an active layer on the gate insulating layer on the gate, and forming a separate layer on the active layer
  • a source electrode and a drain electrode located at both ends of the active layer are formed with a passivation layer on the gate insulating layer, the active layer, the source electrode and the drain electrode, and a pixel electrode is formed on the passivation layer.
  • the photoresist film is patterned by a half-tone mask or a gray-scale mask.
  • the process of etching the transparent conductive film and the metal film in step S4 includes:
  • the second etching is performed to remove the transparent conductive film except for the area where the gate and the common electrode of the array substrate are to be formed.
  • the metal film is etched with copper acid; in the second etching, the transparent conductive film is etched with oxalic acid.
  • the metal film is etched by using hydrogen peroxide copper acid to remove the metal film on the area where the common electrode of the array substrate is to be formed while retaining the transparent conductive film on the area where the common electrode of the array substrate is to be formed.
  • the second photoresist segment and the first photoresist segment are ashed through an oxygen plasma process to remove the second photoresist segment and thin the first photoresist segment at the same time.
  • step S6 a photoresist stripping solution is used to remove the remaining first photoresist segment.
  • the material of the transparent conductive film is indium tin oxide.
  • the invention also provides an array substrate, comprising: a base substrate, a grid electrode arranged on the base substrate at intervals and a common electrode of the array substrate, a common electrode arranged on the base substrate, the gate and the array substrate A gate insulating layer on the top, an active layer provided on the gate insulating layer on the gate, a source and a drain provided on the active layer and located at both ends of the active layer, A passivation layer provided on the gate insulating layer, active layer, source and drain, and a pixel electrode provided on the passivation layer;
  • the common electrode of the array substrate is a transparent electrode
  • the gate includes a transparent conductive portion provided on the same layer as the common electrode of the array substrate and a metal conductive portion laminated on the transparent conductive portion.
  • the material of the common electrode and the transparent conductive part of the array substrate is indium tin oxide.
  • the present invention provides a method for manufacturing an array substrate.
  • the method first forms a transparent conductive film and a metal film covering the transparent conductive film on a base substrate, and patterns the transparent through a mask
  • the conductive thin film and the metal thin film form the gate formed by the transparent conductive thin film and the metal thin film and the common electrode of the array substrate formed by the transparent conductive film.
  • the common electrode of the transparent array substrate can improve the pixel aperture ratio.
  • the display effect is improved, and the gate electrode and the common electrode of the array substrate are still made by one mask, without increasing the number of masks, and the manufacturing cost is low.
  • the invention also provides an array substrate, which can increase the pixel aperture ratio and improve the display effect.
  • step S1 is a schematic diagram of step S1 of the method for manufacturing an array substrate of the present invention
  • step S2 is a schematic diagram of step S2 of the method for manufacturing an array substrate of the present invention
  • step S3 is a schematic diagram of step S3 of the method for manufacturing an array substrate of the present invention.
  • step S4 is a schematic diagram of step S4 of the method for manufacturing an array substrate of the present invention.
  • step S5 of the method for manufacturing an array substrate of the present invention are schematic diagrams of step S5 of the method for manufacturing an array substrate of the present invention.
  • step S6 is a schematic diagram of step S6 of the method for manufacturing an array substrate of the present invention.
  • step S7 of the method for manufacturing an array substrate of the present invention are schematic diagrams of step S7 of the method for manufacturing an array substrate of the present invention.
  • FIG. 11 is a flowchart of a method for manufacturing an array substrate of the present invention.
  • the present invention provides a method for manufacturing an array substrate, including the following steps:
  • Step S1 As shown in FIG. 1, a base substrate 1 is provided, on which a transparent conductive film 101 and a metal film 102 covering the transparent conductive film 101 are formed.
  • the base substrate 1 is a transparent substrate, preferably a glass substrate.
  • the step S1 specifically includes first depositing a layer of transparent conductive film 101 on the base substrate 1, and then depositing a layer of metal film 102 on the transparent conductive film 101.
  • the material of the transparent conductive film 101 is indium tin oxide
  • the material of the metal film 102 is one or a combination of molybdenum, aluminum, titanium, and copper.
  • Step S2 As shown in FIG. 2, a photoresist film 103 is covered on the metal film 102.
  • the mask film 103 is formed on the metal film 102 by a coating process.
  • Step S3 pattern the photoresist film 103 to remove the photoresist film 103 except for the area where the gate electrode and the common electrode 3 of the array substrate are to be formed to obtain the area where the gate electrode is to be formed
  • the photoresist film 103 is patterned by a half tone mask (HTM) or a gray tone mask (GTM).
  • HTM half tone mask
  • GTM gray tone mask
  • the first photoresist segment 104 is formed by not exposing or completely exposing the photoresist film 103 on the area where the gate electrode is to be formed, and for the area where the common electrode of the array substrate is to be formed
  • the photoresist film 103 on the top is half-exposed to form a second photoresist segment 105, and the photoresist film 103 in the remaining area is completely exposed or not exposed to remove the photoresist film 103 in the remaining area after development.
  • Step S4 As shown in FIG. 4, using the first photoresist section 104 and the second photoresist section 105 as shields, the transparent conductive film 101 and the metal film 102 are etched, except for removing the common gate electrode and array substrate to be formed The transparent conductive film 101 and the metal film 102 outside the area of the electrode 3.
  • the process of etching the transparent conductive film 101 and the metal film 102 in the step S4 includes: performing the first etching to remove the metal film 102 except for the area where the gate and the common electrode 3 of the array substrate are to be formed ; Perform a second etching to remove the transparent conductive film 101 except for the area where the gate and the common electrode 3 of the array substrate are to be formed.
  • the metal film 102 is etched with copper acid; in the second etching, the transparent conductive film 101 is etched with oxalic acid.
  • Step S5 As shown in FIGS. 5 and 6, the second photoresist segment 105 is removed while the first photoresist segment 104 is thinned, and the metal thin film 102 is etched with the remaining first photoresist segment 104 as a shield to remove the to-be-formed
  • the metal thin film 102 on the area of the common electrode of the array substrate obtains the common electrode 3 of the array substrate.
  • the second photoresist segment 105 and the first photoresist segment 104 are ashed by an oxygen plasma process (O 2 Plasma) to remove the second photoresist segment 105 while thinning the first Photoresist section 104
  • O 2 Plasma oxygen plasma process
  • the metal film 102 is etched by using hydrogen peroxide copper acid to remove the metal film 102 on the area where the common electrode of the array substrate is to be formed while retaining the transparent conductive film 101 on the area where the common electrode of the array substrate is to be formed .
  • etching by the hydrogen peroxide copper acid can avoid etching the transparent conductive film 101 while etching the metal film 102, so as to retain the transparent conductive film 101 on the area where the common electrode of the array substrate is to be formed , For forming the common electrode 3 of the array substrate.
  • Step S6 As shown in FIG. 7, the remaining first photoresist segment 104 is removed to obtain the gate 2.
  • the step S6 uses a photoresist stripping solution to remove the remaining first photoresist segment 104.
  • Step S7 As shown in FIGS. 8 to 10, a gate insulating layer 4 is formed on the base substrate 1, the gate 2 and the common electrode 3 of the array substrate, and the gate insulating layer 4 on the gate 2 An active layer 5 is formed thereon, and a source electrode 6 and a drain electrode 7 located at both ends of the active layer 5 are formed on the active layer 5, and the gate insulating layer 4, the active layer 5, and the source A passivation layer 8 is formed on the electrode 6 and the drain 7, and a pixel electrode 9 is formed on the passivation layer 8.
  • step S7 specifically includes:
  • a gate insulating layer 4 is first deposited on the base substrate 1, the gate 2 and the common electrode 3 of the array substrate;
  • a semiconductor film is deposited on the gate insulating layer 4 and a metal film is deposited on the semiconductor film, and the semiconductor film and the metal film are simultaneously patterned through a mask to obtain Source layer 5, source electrode 6 and drain electrode 7.
  • the photomask patterning the semiconductor film and the metal film is a gray-scale photomask or a half-tone photomask.
  • a passivation layer 8 is then deposited on the gate insulating layer 4, the active layer 5, the source electrode 6 and the drain electrode 7, and the passivation layer 8 is patterned by a mask , A via 91 is formed through the passivation layer 8, the via 91 exposes a portion of the drain 7;
  • a transparent conductive film is finally formed on the passivation layer 8, and the transparent conductive film is patterned by a mask to form a pixel electrode 9, and the pixel electrode 9 passes through the via 91 is electrically connected to the drain 7.
  • the materials of the gate insulating layer 4 and the passivation layer 8 are one or a combination of silicon nitride and silicon oxide, and the material of the active layer 5 may be amorphous silicon or polysilicon Or a metal oxide semiconductor, the material of the source electrode 6 and the drain electrode 7 is a combination of one or more of molybdenum, aluminum, titanium, and copper, and the material of the pixel electrode 9 is indium tin oxide.
  • the manufacturing method of the present invention can make an array substrate through 4 masks, and the array substrate has a transparent array substrate common electrode, which can increase the pixel aperture ratio and improve the display effect, and the number of masks required for manufacturing is small, The production cost is lower.
  • the present invention also provides an array substrate, including: a base substrate 1, spaced-apart gates 2 provided on the base substrate 1 and a common electrode 3 of the array substrate, provided on the substrate The substrate 1, the gate 2 and the gate insulating layer 4 on the common electrode 3 of the array substrate, the active layer 5 provided on the gate insulating layer 4 on the gate 2, and the active layer 5 provided on the active layer 5 And the source electrode 6 and the drain electrode 7 located at both ends of the active layer 5, the passivation layer 8 provided on the gate insulating layer 4, the active layer 5, the source electrode 6 and the drain electrode 7, and the device The pixel electrode 9 on the passivation layer 8;
  • the array substrate common electrode 3 is a transparent electrode
  • the gate 2 includes a transparent conductive portion 21 provided in the same layer as the array substrate common electrode 3 and a metal conductive portion 22 stacked on the transparent conductive portion 21.
  • the materials of the array substrate common electrode 3 and the transparent conductive portion 21 are indium tin oxide.
  • a via hole 91 penetrating the passivation layer 8 and exposing a part of the drain 7 is formed on the passivation layer 8, and the pixel electrode 9 is electrically connected to the drain 7 through the via 91 Sexual connection.
  • the array substrate is made by four photomasks, wherein the array substrate common electrode 3 and the gate electrode 2 are made by a first photomask, and the active layer 5, the source electrode 6 and the drain electrode 7 It is made by a second mask, the via 91 is made by a third mask, and the pixel electrode 9 is made by a fourth mask.
  • the first mask and the second mask are both gray-scale masks or half-tone masks.
  • the materials of the gate insulating layer 4 and the passivation layer 8 are one or a combination of silicon nitride and silicon oxide, and the material of the active layer 5 may be amorphous silicon or polysilicon Or metal oxide semiconductor, the material of the metal conductive portion 22, the source electrode 6 and the drain electrode 7 is one or more combinations of molybdenum, aluminum, titanium and copper, the common electrode 3 of the array substrate, transparent conductive
  • the material of the portion 21 and the pixel electrode 9 is indium tin oxide.
  • the array substrate of the present invention has a transparent array substrate common electrode, which can increase the pixel aperture ratio and improve the display effect, and the number of masks required for manufacturing is small, and the manufacturing cost is low.
  • the present invention provides a method for manufacturing an array substrate.
  • the method first forms a transparent conductive film and a metal film covering the transparent conductive film on a base substrate, and patterns the transparent conductive film through a mask Thin film and metal film, forming the grid formed by the transparent conductive film and the metal film and the common electrode of the array substrate formed by the transparent conductive film.
  • the common electrode of the transparent array substrate can improve the pixel aperture ratio and improve Display effect, and the grid and the common electrode of the array substrate are still made by one mask, without increasing the number of masks, and the manufacturing cost is low.
  • the invention also provides an array substrate, which can increase the pixel aperture ratio and improve the display effect.

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Abstract

一种阵列基板的制作方法及阵列基板，所述阵列基板的制作方法为先在衬底基板（1）上形成透明导电薄膜（101）和覆盖所述透明导电薄膜（101）的金属薄膜（102），并通过一道光罩图案化所述透明导电薄膜（101）和金属薄膜（102），形成由透明导电薄膜（101）和金属薄膜（102）形成的栅极（2）和由透明导电薄膜（101）形成的阵列基板公共电极（3）。所述透明的阵列基板公共电极（3）能够提升像素开口率，改善显示效果，且栅极（2）和阵列基板公共电极（3）仍通过一道光罩制得，无需增加光罩数量，制作成本较低。

Description

阵列基板的制作方法及阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板的制作方法及阵列基板。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜基板(CF，Color Filter)、阵列基板(TFT，Thin Film Transistor)、夹于彩膜基板与阵列基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成TFT基板，以便于控制液晶分子的运动；中段Cell制程主要是在TFT基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
现有的阵列基板一般包括：衬底基板、设于衬底基板上的间隔排列的栅极和阵列基板公共电极(Array Com，Acom)、设于所述衬底基板、栅极和阵列基板公共电极上的栅极绝缘层、设于所述栅极上的栅极绝缘层上的有源层、设于所述有源层上且分别与所述有源层的两端接触的源极和漏极、设于所述栅极绝缘层、有源层、源极和漏极上的钝化层、设于所述钝化层上的且与所述漏极电性连接的像素电极，其中栅极和阵列基板公共电极位于同一膜层且均采用不透光的金属材料制成，开口率较低。
发明内容
本发明的目的在于提供一种阵列基板的制作方法，能够提升像素开口率，且不增加光罩数量。
本发明的目的还在于提供一种阵列基板，能够提升像素开口率，改善显示效果。
为实现上述目的，本发明提供了一种阵列基板的制作方法，包括如下步骤：
步骤S1、提供一衬底基板，在所述衬底基板上形成透明导电薄膜和覆盖所述透明导电薄膜的金属薄膜；
步骤S2、在所述金属薄膜上覆盖光阻薄膜；
步骤S3、对所述光阻薄膜进行图案化，除去除待形成栅极和阵列基板公共电极的区域以外的光阻薄膜，得到位于待形成栅极的区域上的第一光阻段及位于待形成阵列基板公共电极的区域上的第二光阻段，且所述第一光阻段的厚度大于第二光阻段；
步骤S4、以第一光阻段和第二光阻段为遮挡，对所述透明导电薄膜和金属薄膜进行蚀刻，除去除待形成栅极和阵列基板公共电极的区域以外的透明导电薄膜和金属薄膜；
步骤S5、去除第二光阻段同时减薄第一光阻段，以剩余的第一光阻段为遮挡对金属薄膜进行蚀刻，去除待形成阵列基板公共电极的区域上金属薄膜，得到阵列基板公共电极；
步骤S6、去除剩余的第一光阻段，得到栅极；
步骤S7、在所述衬底基板、栅极及阵列基板公共电极上形成栅极绝缘层，在所述栅极上的栅极绝缘层上形成有源层，在所述有源层上形成分别位于所述有源层的两端的源极和漏极，在所述栅极绝缘层、有源层、源极和漏极上形成钝化层，并在所述钝化层上形成像素电极。
所述步骤S3中通过一道半色调光罩或灰阶光罩图案化所述光阻薄膜。
所述步骤S4中对所述透明导电薄膜和金属薄膜进行蚀刻的过程包括：
进行第一次蚀刻，除去除待形成栅极和阵列基板公共电极的区域以外的金属薄膜；
进行第二次蚀刻，除去除待形成栅极和阵列基板公共电极的区域以外的透明导电薄膜。
所述第一次蚀刻中，采用铜酸蚀刻所述金属薄膜；所述第二次蚀刻中，采用草酸蚀刻所述透明导电薄膜。
所述步骤S5中采用双氧水系铜酸蚀刻所述金属薄膜，以去除待形成阵列基板公共电极的区域上金属薄膜同时保留待形成阵列基板公共电极的区 域上的透明导电薄膜。
所述步骤S5中通过氧气等离子工艺对所述第二光阻段和第一光阻段进行灰化，以去除第二光阻段同时减薄第一光阻段。
所述步骤S6采用光阻剥离液去除剩余的第一光阻段。
所述透明导电薄膜的材料为氧化铟锡。
本发明还提供一种阵列基板，包括：衬底基板、设于所述衬底基板上的间隔排列的栅极及阵列基板公共电极、设于所述衬底基板、栅极及阵列基板公共电极上的栅极绝缘层、设于所述栅极上的栅极绝缘层上的有源层、设于所述有源层上且分别位于所述有源层的两端的源极和漏极、设于所述栅极绝缘层、有源层、源极和漏极上的钝化层以及设于所述钝化层上的像素电极；
所述阵列基板公共电极为透明电极，所述栅极包括与所述阵列基板公共电极同层设置的透明导电部及层叠于所述透明导电部上的金属导电部。
所述阵列基板公共电极及透明导电部的材料为氧化铟锡。
本发明的有益效果：本发明提供一种阵列基板的制作方法，该方法先在衬底基板上形成透明导电薄膜和覆盖所述透明导电薄膜的金属薄膜，并通过一道光罩图案化所述透明导电薄膜和金属薄膜，形成由透明导电薄膜和金属薄膜形成的栅极和由透明导电薄膜形成的阵列基板公共电极，相比于现有技术，透明的阵列基板公共电极，能够提升像素开口率，改善显示效果，且栅极和阵列基板公共电极仍通过一道光罩制得，无需增加光罩数量，制作成本较低。本发明还提供一种阵列基板，能够提升像素开口率，改善显示效果。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的阵列基板的制作方法的步骤S1的示意图；
图2为本发明的阵列基板的制作方法的步骤S2的示意图；
图3为本发明的阵列基板的制作方法的步骤S3的示意图；
图4为本发明的阵列基板的制作方法的步骤S4的示意图；
图5至图6为本发明的阵列基板的制作方法的步骤S5的示意图；
图7为本发明的阵列基板的制作方法的步骤S6的示意图；
图8至图10本发明的阵列基板的制作方法的步骤S7的示意图；
图11为本发明的阵列基板的制作方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图11，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤S1、如图1所示，提供一衬底基板1，在所述衬底基板1上形成透明导电薄膜101和覆盖所述透明导电薄膜101的金属薄膜102。
具体地，所述衬底基板1为透明基板，优选为玻璃基板。
具体地，所述步骤S1中具体包括先在所述衬底基板1上沉积一层透明导电薄膜101，随后在所述透明导电薄膜101上沉积一层金属薄膜102。
优选地，所述透明导电薄膜101的材料氧化铟锡，所述金属薄膜102的材料为钼、铝、钛及铜中的一种或多种的组合。
步骤S2、如图2所示，在所述金属薄膜102上覆盖光阻薄膜103。
具体地，所述步骤S2中通过涂布工艺在所述金属薄膜102上形成所述光罩薄膜103。
步骤S3、如图3所示，对所述光阻薄膜103进行图案化，除去除待形成栅极和阵列基板公共电极3的区域以外的光阻薄膜103，得到位于待形成栅极的区域上的第一光阻段104及位于待形成阵列基板公共电极的区域上的第二光阻段105，且所述第一光阻段104的厚度大于第二光阻段105。
具体地，所述步骤S3中通过一道半色调光罩(Half tone mask，HTM)或一道灰阶光罩(Gray tone mask，GTM)图案化所述光阻薄膜103。
具体地，根据光阻薄膜103的正负性质选择对所述待形成栅极的区域上的光阻薄膜103不曝光或完全曝光形成第一光阻段104，对于待形成阵列基板公共电极的区域上的光阻薄膜103进行半曝光形成第二光阻段105，对其余区域的光阻薄膜103完全曝光或不曝光，以在显影后去除所述其余区域的光阻薄膜103。
步骤S4、如图4所示，以第一光阻段104和第二光阻段105为遮挡，对所述透明导电薄膜101和金属薄膜102进行蚀刻，除去除待形成栅极和阵列基板公共电极3的区域以外的透明导电薄膜101和金属薄膜102。
具体地，所述步骤S4中对所述透明导电薄膜101和金属薄膜102进行蚀刻的过程包括：进行第一次蚀刻，除去除待形成栅极和阵列基板公共电极3的区域以外的金属薄膜102；进行第二次蚀刻，除去除待形成栅极和阵 列基板公共电极3的区域以外的透明导电薄膜101。
其中，所述第一次蚀刻中，采用铜酸蚀刻所述金属薄膜102；所述第二次蚀刻中，采用草酸蚀刻所述透明导电薄膜101。
步骤S5、如图5和图6所示，去除第二光阻段105同时减薄第一光阻段104，以剩余的第一光阻段104为遮挡对金属薄膜102进行蚀刻，去除待形成阵列基板公共电极的区域上金属薄膜102，得到阵列基板公共电极3。
具体地，所述步骤S5中通过氧气等离子工艺(O 2Plasma)对所述第二光阻段105和第一光阻段104进行灰化，以去除第二光阻段105同时减薄第一光阻段104
具体地，所述步骤S5中采用双氧水系铜酸蚀刻所述金属薄膜102，以去除待形成阵列基板公共电极的区域上金属薄膜102同时保留待形成阵列基板公共电极的区域上的透明导电薄膜101。
具体地，通过所述双氧水系铜酸进行蚀刻，能够在蚀刻所述金属薄膜102的同时，避免对透明导电薄膜101的蚀刻，以保留下待形成阵列基板公共电极的区域上的透明导电薄膜101，用于形成阵列基板公共电极3。
步骤S6、如图7所示，去除剩余的第一光阻段104，得到栅极2。
具体地，所述步骤S6采用光阻剥离液去除剩余的第一光阻段104。
步骤S7、如图8至图10所示，在所述衬底基板1、栅极2及阵列基板公共电极3上形成栅极绝缘层4，在所述栅极2上的栅极绝缘层4上形成有源层5，在所述有源层5上形成分别位于所述有源层5的两端的源极6和漏极7，在所述栅极绝缘层4、有源层5、源极6和漏极7上形成钝化层8，并在所述钝化层8上形成像素电极9。
具体地，所述步骤S7具体包括：
如图8所示，先在所述衬底基板1、栅极2及阵列基板公共电极3上沉积栅极绝缘层4；
如图9所示，然后在栅极绝缘层4上沉积一层半导体薄膜并在所述半导体薄膜上沉积一层金属薄膜，并通过一道光罩同时图案化所述半导体薄膜和金属薄膜，得到有源层5、源极6和漏极7。所述图案化所述半导体薄膜和金属薄膜的光罩为灰阶光罩或半色调光罩。
如图10所示，接着在所述栅极绝缘层4、有源层5、源极6和漏极7上沉积一层钝化层8，并通过一道光罩图案化所述钝化层8，形成贯穿所述钝化层8的过孔91，所述过孔91暴露出所述漏极7的一部分；
如图10所示，最后在所述钝化层8上形成一层透明导电薄膜，并通过一道光罩图案化所述透明导电薄膜，形成像素电极9，所述像素电极9通过 所述过孔91与所述漏极7电性连接。
优选地，所述栅极绝缘层4和钝化层8的材料均为氮化硅和氧化硅中的一种或二者的组合，所述有源层5的材料可以为非晶硅、多晶硅或金属氧化物半导体，所述源极6和漏极7的材料为钼、铝、钛及铜中的一种或多种的组合，所述像素电极9的材料为氧化铟锡。
具体地，本发明的制作方法可通过4道光罩制成阵列基板，且该阵列基板具有透明的阵列基板公共电极，能够提升像素开口率，改善显示效果，且制作所需的光罩数量少，制作成本较低。
请参阅图10，本发明还提供一种阵列基板，包括：衬底基板1、设于所述衬底基板1上的间隔排列的栅极2及阵列基板公共电极3、设于所述衬底基板1、栅极2及阵列基板公共电极3上的栅极绝缘层4、设于所述栅极2上的栅极绝缘层4上的有源层5、设于所述有源层5上且分别位于所述有源层5的两端的源极6和漏极7、设于所述栅极绝缘层4、有源层5、源极6和漏极7上的钝化层8以及设于所述钝化层8上的像素电极9；
所述阵列基板公共电极3为透明电极，所述栅极2包括与所述阵列基板公共电极3同层设置的透明导电部21及层叠于所述透明导电部21上的金属导电部22。
具体地，所述阵列基板公共电极3及透明导电部21的材料为氧化铟锡。
具体地，所述钝化层8上形成有贯穿所述钝化层8且暴露出漏极7的一部分的过孔91，所述像素电极9通过所述过孔91与所述漏极7电性连接。
具体地，所述阵列基板通过4道光罩制得，其中，所述阵列基板公共电极3和栅极2通过第一道光罩制得，所述有源层5、源极6和漏极7通过第二道光罩制得，所述过孔91通过第三道光罩制得，所述像素电极9通过第四道光罩制得。
具体地，第一道光罩和第二道光罩均为灰阶光罩或半色调光罩。
优选地，所述栅极绝缘层4和钝化层8的材料均为氮化硅和氧化硅中的一种或二者的组合，所述有源层5的材料可以为非晶硅、多晶硅或金属氧化物半导体，所述金属导电部22、源极6和漏极7的材料为钼、铝、钛及铜中的一种或多种的组合，所述阵列基板公共电极3、透明导电部21及像素电极9的材料为氧化铟锡。
具体地，本发明的阵列基板具有透明的阵列基板公共电极，能够提升像素开口率，改善显示效果，且制作所需的光罩数量少，制作成本较低。
综上所述，本发明提供一种阵列基板的制作方法，该方法先在衬底基 板上形成透明导电薄膜和覆盖所述透明导电薄膜的金属薄膜，并通过一道光罩图案化所述透明导电薄膜和金属薄膜，形成由透明导电薄膜和金属薄膜形成的栅极和由透明导电薄膜形成的阵列基板公共电极，相比于现有技术，透明的阵列基板公共电极，能够提升像素开口率，改善显示效果，且栅极和阵列基板公共电极仍通过一道光罩制得，无需增加光罩数量，制作成本较低。本发明还提供一种阵列基板，能够提升像素开口率，改善显示效果。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种阵列基板的制作方法，包括如下步骤：
    步骤S1、提供一衬底基板，在所述衬底基板上形成透明导电薄膜和覆盖所述透明导电薄膜的金属薄膜；
    步骤S2、在所述金属薄膜上覆盖光阻薄膜；
    步骤S3、对所述光阻薄膜进行图案化，除去除待形成栅极和阵列基板公共电极的区域以外的光阻薄膜，得到位于待形成栅极的区域上的第一光阻段及位于待形成阵列基板公共电极的区域上的第二光阻段，且所述第一光阻段的厚度大于第二光阻段；
    步骤S4、以第一光阻段和第二光阻段为遮挡，对所述透明导电薄膜和金属薄膜进行蚀刻，除去除待形成栅极和阵列基板公共电极的区域以外的透明导电薄膜和金属薄膜；
    步骤S5、去除第二光阻段同时减薄第一光阻段，以剩余的第一光阻段为遮挡对金属薄膜进行蚀刻，去除待形成阵列基板公共电极的区域上金属薄膜，得到阵列基板公共电极；
    步骤S6、去除剩余的第一光阻段，得到栅极；
    步骤S7、在所述衬底基板、栅极及阵列基板公共电极上形成栅极绝缘层，在所述栅极上的栅极绝缘层上形成有源层，在所述有源层上形成分别位于所述有源层的两端的源极和漏极，在所述栅极绝缘层、有源层、源极和漏极上形成钝化层，并在所述钝化层上形成像素电极。
  2. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤S3中通过一道半色调光罩或灰阶光罩图案化所述光阻薄膜。
  3. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤S4中对所述透明导电薄膜和金属薄膜进行蚀刻的过程包括：
    进行第一次蚀刻，除去除待形成栅极和阵列基板公共电极的区域以外的金属薄膜；
    进行第二次蚀刻，除去除待形成栅极和阵列基板公共电极的区域以外的透明导电薄膜。
  4. 如权利要求3所述的阵列基板的制作方法，其中，所述第一次蚀刻中，采用铜酸蚀刻所述金属薄膜；所述第二次蚀刻中，采用草酸蚀刻所述透明导电薄膜。
  5. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤S5中 采用双氧水系铜酸蚀刻所述金属薄膜，以去除待形成阵列基板公共电极的区域上金属薄膜同时保留待形成阵列基板公共电极的区域上的透明导电薄膜。
  6. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤S5中通过氧气等离子工艺对所述第二光阻段和第一光阻段进行灰化，以去除第二光阻段同时减薄第一光阻段。
  7. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤S6采用光阻剥离液去除剩余的第一光阻段。
  8. 如权利要求1所述的阵列基板的制作方法，其中，所述透明导电薄膜的材料为氧化铟锡。
  9. 一种阵列基板，包括：衬底基板、设于所述衬底基板上的间隔排列的栅极及阵列基板公共电极、设于所述衬底基板、栅极及阵列基板公共电极上的栅极绝缘层、设于所述栅极上的栅极绝缘层上的有源层、设于所述有源层上且分别位于所述有源层的两端的源极和漏极、设于所述栅极绝缘层、有源层、源极和漏极上的钝化层以及设于所述钝化层上的像素电极；
    所述阵列基板公共电极为透明电极，所述栅极包括与所述阵列基板公共电极同层设置的透明导电部及层叠于所述透明导电部上的金属导电部。
  10. 如权利要求9所述的阵列基板，其中，所述阵列基板公共电极及透明导电部的材料为氧化铟锡。
PCT/CN2018/116043 2018-11-07 2018-11-16 阵列基板的制作方法及阵列基板 WO2020093442A1 (zh)

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CN115280231B (zh) * 2021-02-26 2023-11-03 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板、显示装置
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