WO2017101524A1 - 像素结构及其制作方法、阵列基板及显示装置 - Google Patents
像素结构及其制作方法、阵列基板及显示装置 Download PDFInfo
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- WO2017101524A1 WO2017101524A1 PCT/CN2016/098049 CN2016098049W WO2017101524A1 WO 2017101524 A1 WO2017101524 A1 WO 2017101524A1 CN 2016098049 W CN2016098049 W CN 2016098049W WO 2017101524 A1 WO2017101524 A1 WO 2017101524A1
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Definitions
- the present disclosure relates to the field of display, and in particular, to a pixel structure and a method for fabricating the same, an array substrate, and a display device.
- TFT-LCD Thin Film Transistor Liquid Crystal Display
- the TFT-LCD is mainly composed of an array substrate of a pair of boxes and a color filter substrate, wherein a gate layer (including a gate and a gate line), a source/drain layer (including a source, a drain, and a data line) and a pixel electrode are formed on the array substrate. .
- an aspect of the present disclosure provides a pixel structure including a substrate substrate and a gate layer and a source/drain layer disposed on the substrate. There is an overlap region between the gate layer and the source drain layer, and the gate layer and/or the source drain layer includes a hollow structure located at the overlap region.
- the source drain layer and the gate layer can be effectively reduced by providing a hollow structure at a position overlapping the source/drain layer on the gate layer and/or a position overlapping the gate layer on the source/drain layer.
- the overlap area between them reduces the coupling capacitance of the gate layer and the source and drain layers.
- the inclusion of the hollow structure not only enhances the driving capability of the pixel TFT, but also improves the charge and discharge capability of the pixel.
- the hollow structure includes one or more openings.
- the shape of the opening of the hollow structure is any one of the following: a triangle, a rectangle, a circle.
- the gate layer comprises a gate of the thin film transistor
- the source drain layer comprises a thin The source and drain of the membrane transistor
- the overlap region includes an overlap region between the source and the gate.
- the overlap region includes an overlap region between the drain and the gate.
- the source drain layer further includes a data line connected to the source, wherein the width of the source is less than the width of the data line.
- the channel length of the thin film transistor is from 2 micrometers to 8 micrometers, and in particular, the channel length of the thin film transistor may be 5 micrometers.
- the advantage of such a channel length is that the area of the gate can be reduced, thereby not only reducing the overlap region of the source/drain layer and the gate layer, but also avoiding an increase in leakage current of the thin film transistor due to a decrease in the source width.
- the source drain layer further includes an intermediate electrode disposed between the source and the drain and separated from the source and the drain.
- the intermediate electrode may constitute a thin film transistor with the source and the drain, respectively, thereby avoiding increasing the leakage current of the thin film transistor by reducing the source width.
- the base substrate further includes a gate insulating layer, an active layer, a protective layer, and a pixel electrode.
- the active layer is made of amorphous silicon, polysilicon or an oxide semiconductor material.
- Another aspect of the present disclosure also provides an array substrate including the above-described pixel structure.
- a further aspect of the present disclosure also provides a display device comprising the above array substrate.
- Another aspect of the present disclosure provides a method of fabricating a pixel structure, including forming a gate layer on a base substrate, forming a gate insulating layer, an active layer, and a source/drain layer on the gate layer; forming a source/drain layer a protective layer; a pixel electrode is formed on the protective layer.
- a method of fabricating a pixel structure including forming a gate layer on a base substrate, forming a gate insulating layer, an active layer, and a source/drain layer on the gate layer; forming a source/drain layer a protective layer; a pixel electrode is formed on the protective layer.
- the method further includes forming a hollow structure at the overlap region on the gate layer and/or the source drain layer.
- FIG. 1 is a top plan view of a pixel structure in accordance with an embodiment of the present disclosure
- Figure 2 is a schematic cross-sectional view taken along line AA' of Figure 1;
- Figure 3 is a schematic cross-sectional view taken along line BB' of Figure 1;
- FIG. 4 is a schematic diagram of another pixel structure in accordance with an embodiment of the present disclosure.
- FIG. 5 is a schematic diagram of still another pixel structure in accordance with an embodiment of the present disclosure.
- FIG. 6 is a flow chart of a method of fabricating a pixel structure in accordance with an embodiment of the present disclosure.
- Embodiments of the present disclosure provide a pixel structure including a substrate substrate and a gate layer and a source/drain layer disposed on the substrate. There is an overlap region between the gate layer and the source drain layer, and the gate layer and/or the source drain layer includes a hollow structure located in the overlap region.
- the source and drain layers can be effectively reduced by providing a hollow structure at a position overlapping the source/drain layer on the gate layer and/or a position overlapping the gate layer on the source/drain layer.
- the overlap area between the gate layers thereby reducing the coupling capacitance of the gate layer and the source and drain layers.
- the inclusion of the hollow region not only enhances the driving ability of the pixel TFT, but also improves the charge and discharge capability of the pixel.
- the hollow structure may be located on the gate layer, or may be located on the source and drain layers, or a hollow structure may be disposed on both the gate layer and the source and drain layers.
- the hollow structure on the gate layer and/or the hollow structure on the source and drain layers may include one or more openings.
- the shape of the opening may be a triangle, a rectangle (such as a rectangle, a square), a circle, or other irregular shape.
- FIG. 1 is a top view of a pixel structure in accordance with an embodiment of the present disclosure.
- the pixel structure generally includes a base substrate on which a gate layer, a gate insulating layer (GI layer), an active layer, a source/drain layer, a protective layer (PL layer), a pixel electrode, and the like are provided.
- the gate layer 10 includes a gate electrode 12 and a gate line 11 connected to the gate electrode.
- the source drain layer 20 includes a source 22 of the thin film transistor, a drain 23, and a data line 21 connected to the source 22.
- the pixel electrode 30 is connected to the drain 23 through a via hole (a region in the dashed frame 1) on the protective layer.
- the active layer is located in the area within the dashed box 2.
- the source 22 is provided with a hollow structure at a position overlapping the gate electrode 12, the hollow structure including a plurality of openings 24. As shown, the opening 24 exposes the gate 12.
- the hollow structure in the source 22 may be disposed at any one of the gate 12, the source 22, and the drain 23 or Multiple on.
- Figure 2 is a schematic cross-sectional view taken along line AA' of Figure 1.
- the gate layer 10 the gate insulating layer (GI layer) 40, the active layer 50, the source/drain layer 20, and the protective layer (PL layer) 60
- the substrate 100 is sequentially disposed.
- the opening 24 at a position where the source drain layer 20 overlaps the gate layer 10, the overlapping area of the source/drain layer 20 and the gate layer 10 can be effectively reduced, thereby reducing the coupling capacitance of the gate layer and the source/drain layer.
- Figure 3 is a schematic cross-sectional view taken along line BB' of Figure 1. As shown in FIG. 3, the pixel electrode 30 is connected to the drain 23 in the source/drain layer 20 through a via hole on the protective layer 60.
- the material of the gate layer 10 may be molybdenum (Mo) or aluminum (Al), and the material of the active layer 50 may be amorphous silicon, polysilicon or an oxide semiconductor material.
- the manufacturing method thereof may include the steps as shown in FIG. 6.
- a gate layer is formed on the base substrate.
- one or more metal thin films may be deposited on the base substrate (which may be a glass substrate), and the material of the metal thin film may be Mo, Al or an alloy thereof or the like.
- the gate layer is formed by subjecting the metal thin film to a mask exposure, development, etching, or the like.
- the gate layer may include a gate line (gate metal trace) and a gate pattern of the thin film transistor.
- a gate insulating layer, an active layer and a source/drain layer are formed on the gate layer.
- a gate insulating layer GI
- a semiconductor thin film is formed using a material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor.
- An active layer of the thin film transistor is formed by subjecting the semiconductor film to a mask exposure, development, etching, or the like.
- one or more metal thin films are deposited, and the material of the metal thin film may be Mo, Al or an alloy thereof or the like.
- the source/drain layer is formed by subjecting the metal thin film to a process such as exposure, development, etching, or the like.
- a gate insulating layer (GI layer), an active layer, and a source/drain layer are sequentially disposed on the gate layer.
- the source and drain layers include a source, a drain, and a data line of the thin film transistor.
- a protective layer is formed on the source/drain layer.
- a protective layer is formed on the source/drain layer using a resin material or other inorganic material.
- a via hole may be formed thereon by a process such as exposure, development, or the like as needed.
- a pixel electrode is formed on the protective layer.
- a transparent conductive film such as an ITO material
- a transparent conductive pattern such as a pixel electrode or a common electrode is formed by a process such as exposure, development, etching, or the like.
- a hollow structure located in the overlap region is formed on the gate layer and/or the source/drain layer.
- the hollow structure can be formed by processes such as exposure, development, etching, and the like.
- the width of the source may also be appropriately reduced.
- the width D of the source 22 may be smaller than that of the source drain layer.
- the thin film transistor has a channel length L of from 2 microns to 8 microns, such as 5 microns.
- the advantage of such a channel length is that the area of the gate can be reduced, thereby not only reducing the overlap region of the source/drain layer and the gate layer, but also avoiding an increase in leakage current of the thin film transistor due to a decrease in the source width.
- an intermediate electrode may be disposed between the source and the drain of the thin film transistor, thereby forming two thin film transistors connected in series.
- the source/drain layer 20 includes not only the source 22, the drain 23, and the data line 21 connected to the source 22 of the thin film transistor, but also the source 22 and the drain 23.
- the intermediate electrode 25 is separated from the source 22 and the drain 23. The presence of the intermediate electrode 25 enables two thin film transistors in series (i.e., the source 22 and the intermediate electrode 25 form a thin film transistor, and the intermediate electrode 25 and the drain 23 form another thin film transistor), thereby reducing leakage current.
- the above-mentioned pixel structure may be a pixel structure in a TN mode display device, or may be a pixel structure in a VA, IPS or ADS mode display device, which is not specifically limited in the present disclosure.
- the source and drain layers can be effectively reduced by providing a hollow structure at a position overlapping the source/drain layer on the gate layer and/or a position overlapping the gate layer on the source/drain layer.
- the overlapping area of the gate layers thereby reducing the coupling capacitance of the gate layer and the source and drain layers.
- the inclusion of the hollow structure not only avoids a large amount of change ( ⁇ Vp) of the pixel voltage, but also does not cause the gray scale displayed at the end of the pixel to seriously deviate from the gray scale desired by the originally written voltage, and also avoids data line writing.
- the symmetrical voltage of the positive and negative polarity is shifted downward to generate DC residual.
- an embodiment of the present disclosure further provides an array substrate including the above pixel structure.
- Embodiments of the present disclosure also provide a display device including the above array substrate.
- the display device may be any product or component having a display function such as a notebook computer display, a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, a tablet computer, or the like.
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Abstract
Description
Claims (15)
- 一种像素结构,包括衬底基板以及设置在所述衬底基板上的栅层和源漏层,所述栅层与所述源漏层之间存在交叠区域,并且所述栅层和/或所述源漏层包括位于所述交叠区域的镂空结构。
- 根据权利要求1所述的像素结构,其中,所述镂空结构包括一个或多个开口。
- 根据权利要求2所述的像素结构,其中,所述镂空结构中开口的形状为以下的任意一种:三角形、矩形、圆形。
- 根据权利要求1所述的像素结构,其中,所述栅层包括薄膜晶体管的栅极,所述源漏层包括所述薄膜晶体管的源极和漏极。
- 根据权利要求4所述的像素结构,其中,所述交叠区域包括所述源极与所述栅极之间的交叠区域。
- 根据权利要求4所述的像素结构,其中,所述交叠区域包括所述漏极与所述栅极之间的交叠区域。
- 根据权利要求4所述的像素结构,其中,所述源漏层还包括与所述源极相连的数据线,所述源极的宽度小于所述数据线的宽度。
- 根据权利要求7所述的像素结构,其中,所述薄膜晶体管的沟道长度为2微米~8微米。
- 根据权利要求8所述的像素结构,其中,所述薄膜晶体管的沟道长度为5微米。
- 根据权利要求7所述的像素结构,其中,所述源漏层还包括设置在所述源极与所述漏极之间且与所述源极和所述漏极分离的中间电极。
- 根据权利要求1-10任一所述的像素结构,其中,所述衬底基板还包括栅极绝缘层、有源层、保护层和像素电极。
- 根据权利要求11所述的像素结构,其中有源层由非晶硅、多晶硅或氧化物半导体材料制成。
- 一种阵列基板,包括权利要求1-12任一所述的像素结构。
- 一种显示装置,包括权利要求13所述的阵列基板。
- 一种制作权利要求1-12任一项所述的像素结构的方法,包括:在衬底基板上形成栅层;在所述栅层上形成栅极绝缘层、有源层和源漏层;在所述源漏层上形成保护层;在所述保护层上形成像素电极,其中,所述栅层与所述源漏层之间存在交叠区域,并且所述方法还包括在所述栅层和/或所述源漏层上形成位于所述交叠区域的镂空结构。
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CN106252418B (zh) * | 2016-09-22 | 2018-05-15 | 南京华东电子信息科技股份有限公司 | 一种薄膜晶体管 |
CN108398839A (zh) | 2018-03-26 | 2018-08-14 | 京东方科技集团股份有限公司 | 一种显示面板及其制作方法、显示装置 |
CN108598155A (zh) * | 2018-04-18 | 2018-09-28 | 昆山龙腾光电有限公司 | 薄膜晶体管、阵列基板及显示装置 |
CN109116198B (zh) * | 2018-08-29 | 2021-01-08 | 京东方科技集团股份有限公司 | 一种击穿测试结构、显示面板和击穿测试方法 |
CN110047853B (zh) * | 2019-05-06 | 2021-04-13 | 合肥鑫晟光电科技有限公司 | 一种阵列基板、显示面板和显示装置 |
CN110931504A (zh) * | 2019-09-17 | 2020-03-27 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板及显示面板 |
CN111025724A (zh) * | 2019-12-24 | 2020-04-17 | 福建华佳彩有限公司 | 一种液晶显示面板 |
CN112129278B (zh) * | 2020-09-15 | 2022-08-19 | 浙江大学 | 可减小由电容边缘效应导致的电容-位移之间的非线性的栅结构 |
CN113675222B (zh) * | 2021-08-24 | 2024-05-17 | 京东方科技集团股份有限公司 | 一种tft基板、电子纸显示屏、显示设备及其制备方法 |
CN114236932B (zh) * | 2022-01-21 | 2023-12-15 | 厦门天马微电子有限公司 | 显示面板及显示装置 |
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