WO2020192121A1 - 显示基板及其制备方法 - Google Patents

显示基板及其制备方法 Download PDF

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Publication number
WO2020192121A1
WO2020192121A1 PCT/CN2019/115059 CN2019115059W WO2020192121A1 WO 2020192121 A1 WO2020192121 A1 WO 2020192121A1 CN 2019115059 W CN2019115059 W CN 2019115059W WO 2020192121 A1 WO2020192121 A1 WO 2020192121A1
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WIPO (PCT)
Prior art keywords
layer
insulating layer
barrier
area
wall
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PCT/CN2019/115059
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English (en)
French (fr)
Inventor
张跳梅
霍宇飞
姜尚勋
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to JP2020562581A priority Critical patent/JP7386811B2/ja
Priority to CN201980002261.8A priority patent/CN112005378B/zh
Priority to US16/768,283 priority patent/US11575103B2/en
Priority to EP19921020.4A priority patent/EP3955305A4/en
Publication of WO2020192121A1 publication Critical patent/WO2020192121A1/zh
Priority to JP2023190826A priority patent/JP2024020320A/ja

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H10K50/822—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/842—Containers
    • H10K50/8426—Peripheral sealing arrangements, e.g. adhesives, sealants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0264—Details of the structure or mounting of specific components for a camera module assembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0266—Details of the structure or mounting of specific components for a display module assembly
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the embodiment of the present disclosure relates to a display substrate and a preparation method thereof.
  • the display screen of the display device is developing in the direction of large screen and full screen.
  • a display device such as a mobile phone, a tablet computer, etc.
  • the camera device is usually arranged on a side outside the display area of the display screen.
  • the camera device can be combined with the display area of the display screen to reserve a place for the camera device in the display area to maximize the display area of the display screen.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a display area, a barrier area, and an opening area.
  • the display area and the barrier area surround the opening area, and the barrier area is located in the display area.
  • the barrier area includes a first barrier wall, a first barrier wall, and a second barrier wall that are arranged in sequence from the display area to the opening area.
  • a barrier wall, a first barrier wall, and a second barrier wall surround the opening area;
  • the first barrier wall includes a first metal layer structure, and at least one of the first metal layer structure surrounds the opening area
  • the side has a notch;
  • the first blocking wall includes a first insulating layer structure;
  • the second blocking wall includes a second metal layer structure and a first stacked layer structure, and the second metal layer structure is located in the first stacked layer structure.
  • at least one side surface of the second metal layer structure surrounding the opening area has a notch, and the first layered structure includes a layered layer with a metal layer and an insulating layer.
  • the second metal layer structure and the first metal layer structure have the same structure and include the same material.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a base substrate, wherein the display area includes a thin film transistor and a storage capacitor, and the thin film transistor includes a gate and a gate sequentially disposed on the base substrate.
  • the storage capacitor includes a first electrode plate and a second electrode plate, the first electrode plate and the gate electrode are arranged in the same layer, and the second electrode plate is located at the Between the gate insulating layer and the interlayer insulating layer; the first metal layer structure, the second metal layer structure and the source and drain electrodes are arranged in the same layer.
  • the stack of the first stacked structure includes a first metal sublayer, a first insulating sublayer, and a second metal sublayer that are sequentially disposed on the base substrate.
  • Layer and a second insulating sub-layer, the first metal sub-layer and the gate are provided in the same layer
  • the first insulating sub-layer and the gate insulating layer are provided in the same layer
  • the second metal sub-layer and the first The two-electrode plates are arranged in the same layer
  • the second insulating sub-layer and the interlayer insulating layer are arranged in the same layer.
  • the first barrier wall further includes a second insulating layer structure, the first metal layer structure is located on the second insulating layer structure, and the second insulating layer structure The layer structure is arranged at least in the same layer as the gate insulating layer and the interlayer insulating layer.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a barrier layer and a buffer layer disposed on the base substrate, wherein the second insulating layer structure includes a first part and a second part that are stacked, The first part is arranged at least in the same layer as the gate insulating layer and the interlayer insulating layer, and the second part is arranged at least in the same layer as the barrier layer and the buffer layer.
  • the overall longitudinal section of the second insulating layer structure is stepped.
  • the display area further includes: a planarization layer for planarizing the thin film transistor, and pixels on the side of the planarization layer away from the thin film transistor are defined Layer, the pixel defining layer is used to define a plurality of pixel units and spacers on the side of the pixel defining layer away from the flat layer; the first insulating layer structure of the first blocking wall and the At least one of the planarization layer, the pixel defining layer, and the spacer are arranged in the same layer.
  • the display substrate provided by at least one embodiment of the present disclosure further includes an encapsulation layer, wherein the encapsulation layer at least encapsulates the first barrier wall.
  • the encapsulation layer includes a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer that are sequentially stacked on the first barrier wall.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a first organic insulating layer, wherein the first organic insulating layer at least covers the second barrier wall.
  • the blocking area further includes a second blocking wall adjacent to the first blocking wall and on the side of the first blocking wall away from the display area,
  • the second interception wall is higher than the first interception wall.
  • the second blocking wall is provided in the same layer as the planarization layer, the pixel defining layer, and the spacer.
  • the barrier region further includes a third barrier wall and a second organic insulating layer, and the third barrier wall is located on the second barrier wall away from the display area.
  • the second organic insulating layer is between the second barrier wall and the third barrier wall and covers the second barrier wall.
  • the third blocking wall and the second blocking wall have the same structure and include the same material.
  • the blocking area further includes signal line leads, the signal line leads are electrically connected to the signal lines of the display area, and the signal line leads are connected to the first blocking area.
  • the side of the wall close to the display area.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: an image sensor and/or an infrared sensor, wherein the image sensor and/or the infrared sensor are combined with the base substrate and are on the base substrate
  • At least one embodiment of the present disclosure further provides a method for preparing a display substrate, including: forming a display area, a barrier area, and an opening area, wherein the display area and the barrier area surround the opening area, and the barrier The area is located between the display area and the opening area; wherein forming the barrier area includes forming a first barrier wall, a first barrier wall, and a first barrier wall that are sequentially arranged from the display area to the opening area.
  • first barrier wall includes a first metal layer structure, and the first metal layer structure surrounds the At least one side surface of the opening area has a notch;
  • first barrier wall includes a first insulating layer structure;
  • second barrier wall includes a second metal layer structure and a first laminated structure, and the first laminated layer The structure is located on the first stacked structure, at least one side surface of the second metal layer structure surrounding the opening area has a notch, and the first stacked structure includes a stacked layer of a metal layer and an insulating layer.
  • the second metal layer structure and the first metal layer structure are formed of the same material and formed by the same patterning process.
  • the method for preparing a display substrate further includes: providing a base substrate; wherein forming the display area includes forming a thin film transistor and a storage capacitor on the base substrate, and forming the thin film transistor It includes forming a gate electrode, a gate insulating layer, an interlayer insulating layer and a source and drain electrode on the base substrate in sequence; forming the storage capacitor includes forming a first electrode plate and a second electrode plate, the first electrode plate and The gate electrode is formed in the same layer, and the second electrode plate is formed between the gate insulating layer and the interlayer insulating layer; the first metal layer structure, the second metal layer structure and the source The drain electrode is formed in the same layer.
  • forming the first laminated structure includes sequentially forming a first metal sublayer, a first insulating sublayer, and a second metal sublayer on the base substrate. Layer and a second insulating sublayer to obtain a stack of the first stacked structure, wherein the first metal sublayer and the gate are formed in the same layer, and the first insulating sublayer and the gate insulating layer The same layer is formed, the second metal sublayer and the second electrode plate are formed in the same layer, and the second insulating sublayer and the interlayer insulating layer are formed in the same layer.
  • the first barrier wall further includes a second insulating layer structure, and the first metal layer structure is formed on the second insulating layer structure, so The second insulating layer structure is formed at least in the same layer as the gate insulating layer and the interlayer insulating layer.
  • the method for preparing a display substrate further includes: forming a barrier layer and a buffer layer on the base substrate, and the second insulating layer structure includes a first part and a second part that are stacked The first part is formed at least in the same layer as the gate insulating layer and the interlayer insulating layer, and the second part is formed at least in the same layer as the barrier layer and the buffer layer.
  • the method for preparing a display substrate further includes forming a bending area on one side of the display area, wherein forming the bending area includes etching an insulating layer located in the bending area To form a groove, the groove and the second insulating layer structure are formed by the same etching process.
  • the insulating layer located in the bending area includes a barrier layer, a buffer layer, a gate insulating layer, and a barrier layer extending from the display area to the bending area.
  • the interlayer insulating layer when the second insulating layer structure includes the first part and the second part arranged in a stack, the gates located in the bending area and the blocking area are simultaneously etched through the first etching process The insulating layer and the interlayer insulating layer are simultaneously etched through the second etching process to etch the barrier layer and the buffer layer located in the bending area and the barrier area to form the groove and the buffer layer.
  • the second insulating layer structure when the second insulating layer structure includes the first part and the second part arranged in a stack, the gates located in the bending area and the blocking area are simultaneously etched through the first etching process.
  • the insulating layer and the interlayer insulating layer are simultaneously etched through the second etching process to etch the barrier layer and the buffer layer located in the bending area and
  • forming the display area further includes: forming a planarization layer for planarizing the thin film transistor, and the planarization layer is away from the thin film transistor.
  • a pixel defining layer is formed on one side of the pixel defining layer, the pixel defining layer is used to define a plurality of pixel units, and a spacer is formed on the side of the pixel defining layer away from the flat layer, wherein the first blocking wall
  • the first insulating layer structure is formed in the same layer as at least one of the planarization layer, the pixel defining layer, and the spacer.
  • the method for preparing a display substrate further includes forming an encapsulation layer that encapsulates at least the first barrier wall, and forming the encapsulation layer includes sequentially forming first inorganic encapsulation on the first barrier wall.
  • the method for preparing a display substrate provided by at least one embodiment of the present disclosure further includes forming a first organic insulating layer on the second barrier wall, and the first organic insulating layer at least covers the second barrier wall.
  • forming the barrier area further includes forming a barrier adjacent to the first barrier wall and on the side of the first barrier wall away from the display area.
  • the second interception wall is higher than the first interception wall.
  • the second blocking wall is formed in the same layer as the planarization layer, the pixel defining layer, and the spacer.
  • forming the barrier region further includes forming a third barrier wall and a second organic insulating layer, and the third barrier wall is formed on the second barrier wall.
  • the second organic insulating layer is formed between the second barrier wall and the third barrier wall and covers the second barrier wall.
  • the second organic insulating layer is formed by inkjet printing.
  • the second organic insulating layer and the first organic encapsulation layer covering the first barrier wall are formed in the same inkjet printing process.
  • Figure 1A is a schematic plan view of a display substrate
  • FIG. 1B is a schematic cross-sectional view of the display substrate in FIG. 1A along line A-A;
  • FIG. 2A is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 2B is a schematic cross-sectional view of the display substrate in FIG. 2A along the line B-B;
  • FIG. 2C is a schematic cross-sectional view of the display substrate in FIG. 2A along the line C-C;
  • 3A is a schematic cross-sectional view of a first barrier wall in a display substrate provided by at least one embodiment of the present disclosure
  • 3B is a schematic cross-sectional view of a first interception wall in a display substrate provided by at least one embodiment of the present disclosure
  • 3C is a schematic cross-sectional view of a second barrier wall in a display substrate provided by at least one embodiment of the present disclosure
  • 3D is a schematic cross-sectional view of a second interception wall in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 4A is a schematic partial cross-sectional view of a display substrate provided by at least one embodiment of the present disclosure
  • 4B is another schematic cross-sectional view of a second barrier wall in a display substrate provided by at least one embodiment of the present disclosure
  • 5A is a schematic partial cross-sectional view of a display substrate provided by at least one embodiment of the present disclosure
  • 5B is another schematic cross-sectional view of a first barrier wall in a display substrate provided by at least one embodiment of the present disclosure
  • 5C is another schematic cross-sectional view of a second barrier wall in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 6 is another schematic cross-sectional view of the display substrate in FIG. 2A along the line B-B;
  • FIG. 7 is a schematic plan view of a barrier area in a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8A is a schematic cross-sectional view of a bending area in a display substrate provided by at least one embodiment of the present disclosure
  • 8B is another schematic cross-sectional view of a bending area in a display substrate provided by at least one embodiment of the present disclosure
  • FIG. 8C is a schematic cross-sectional view of a bent area in a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 9A-FIG. 9C, FIG. 10A-FIG. 10C, FIG. 11A-FIG. 11B, FIG. 12A-FIG. 12B, FIG. 13A-FIG. 13B, and FIG. 14A-FIG. 14C are a display substrate provided by at least one embodiment of the present disclosure in preparation Schematic cross-section of the process.
  • the camera device (imaging device) of the display device can be integrated with the display area, and the camera device can be arranged in the display area.
  • FIG. 1A shows a schematic plan view of a display substrate for a display device
  • FIG. 1B is a schematic cross-sectional view of the display substrate in FIG. 1A along the line A-A.
  • the display substrate 10 includes a display area 12, the display area 12 includes a pixel array and has an opening 11 in the pixel array.
  • the opening 11 is a reserved position for a camera device (not shown).
  • the camera device may It is arranged on the back side of the display substrate 10 opposite to the display side, so that the imaging device can acquire images through the opening 11.
  • the imaging device and the display area 12 of the display substrate 10 are integrated.
  • the display area 12 has a light-emitting device for display.
  • the light-emitting device is an organic light-emitting diode.
  • the organic material layer 13 and the electrode layer 14 of the multiple light-emitting devices in all or part of the display area 12 are usually formed in the display area 12 It is a whole surface. Therefore, when the packaging layer 15 is used for packaging, the area near the opening 11 is often difficult to be packaged, or even if it is packaged, it is difficult to ensure the packaging effect of the area. At this time, as shown in FIG.
  • impurities such as water and oxygen can enter the display area 12 from the organic functional layer 13 and the electrode layer 14 formed along the entire surface of the opening 11, contaminating the functional materials in the display area 12, resulting in The performance of these functional materials is degraded, thereby affecting the display effect of the display area 12.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a display area, a barrier area, and an opening area.
  • the display area and the barrier area surround the opening area, and the barrier area is located between the display area and the opening area;
  • the barrier area It includes a first barrier wall, a first barrier wall, and a second barrier wall arranged in order from the display area to the opening area.
  • the first barrier wall, the first barrier wall, and the second barrier wall surround the opening area;
  • the first barrier wall It includes a first metal layer structure, at least one side surface of the first metal layer structure surrounding the opening area has a notch;
  • the first barrier wall includes a first insulating layer structure;
  • the second barrier wall includes a second metal layer structure and a first stack
  • the second metal layer structure is located on the first stacked layer structure. At least one side surface of the second metal layer structure surrounding the opening area has a notch.
  • the first stacked layer structure includes a stacked layer with a metal layer and an insulating layer.
  • the display substrate can effectively prevent impurities such as water and oxygen from entering the display area of the display substrate from the opening area, thereby improving the reliability of the display substrate.
  • FIG. 2A shows a schematic plan view of the display substrate 100.
  • FIG. 2B is a schematic cross-sectional view of the display substrate in FIG. 2A along line BB, that is, the barrier area 201 of the display substrate 100 Schematic cross section.
  • the display substrate 100 includes a display area 101, a barrier area 201, and an opening area 301.
  • the display area 101 and the barrier area 201 surround the opening area 301, and the barrier area 201 is located in the display area 101 and the opening. Between area 301.
  • the display area 101 includes a pixel array to realize display.
  • the opening area 301 allows light from the display side of the display substrate 100 to pass through the display substrate 100 to reach the back side of the display substrate 100.
  • the barrier area 201 includes a first barrier wall 202, a first barrier wall 203, and a second barrier wall 204 arranged in sequence from the display area 101 to the opening area 301 (that is, the direction from right to left in FIG. 2B).
  • the barrier wall 202, the first barrier wall 203 and the second barrier wall 204 all surround the opening area 301.
  • the barrier area 201 can isolate the display area 101 from the opening area 301, so as to protect the display area 101.
  • FIG. 3A shows a schematic cross-sectional view of a first barrier wall 202
  • FIG. 3B shows a schematic cross-sectional view of a first barrier wall 203
  • FIG. 3C shows a schematic cross-sectional view of a second barrier wall 204.
  • the first barrier wall 202 includes a first metal layer structure 202B, and at least one side surface of the first metal layer structure 202B surrounding the opening area 301 has a notch.
  • the side of the first metal layer structure 202B facing the opening area 301 and the side facing away from the opening area 301 have notches, that is, the situation shown in FIGS. 2B and 3A.
  • the first metal One side of the layer structure 202B has a notch.
  • the first barrier wall 202 can disconnect the functional layers formed on the entire surface of the display substrate, such as the organic material layer and the cathode layer of the light-emitting device (detailed later).
  • the first blocking wall 203 includes a first insulating layer structure.
  • the first insulating layer structure includes, for example, a stack of multiple sub-insulating layers.
  • FIGS. 2B and 3B show two sub-insulating layers 2031. And 2032 stack.
  • the first blocking wall 203 can block some functional layers formed in the display area 101 (for example, an organic encapsulation layer, which will be described later) to prevent materials of these functional layers from approaching or entering the opening area 301.
  • the second barrier wall 204 includes a second metal layer structure 204B and a first laminate structure 204A.
  • the second metal layer structure 204B is located on the first laminate structure 204A, and the second metal layer structure 204B At least one side surface surrounding the opening area 301 has a notch.
  • the side of the second metal layer structure 204B facing the hole region 301 and the side facing away from the hole region 301 both have notches, that is, the situation shown in FIGS. 2B and 3C.
  • the One side of the metal layer structure 204B has a notch.
  • the first stacked structure 204A includes a stacked layer having a metal layer and an insulating layer.
  • the second barrier wall 204 can also disconnect the functional layer formed on the entire surface of the display substrate, thereby achieving a dual barrier effect together with the first barrier wall 202. At this time, even if one of the first barrier wall 202 and the second barrier wall 204 is If it fails, the other of the first barrier wall 202 and the second barrier wall 204 will also achieve a barrier effect; in addition, the second barrier wall 204 is close to the opening area 301, when the opening area 301 is formed, for example, by stamping or cutting. The second barrier wall 204 can also prevent the cracks that may be generated when the opening area 301 is formed from expanding, thereby preventing the cracks from extending to the display area 101.
  • the number of the first barrier wall 202, the first barrier wall 203, and the second barrier wall 204 may be one or more.
  • two first barrier walls 202, one first barrier wall 203, and one The second barrier wall 204 is taken as an example, but this does not constitute a limitation to the embodiment of the present disclosure.
  • the second metal layer structure 204B of the second barrier wall 204 and the first metal layer structure 202B of the first barrier wall 202 have the same structure and include the same material. Therefore, in the preparation process of the display substrate, the second metal layer structure 204B of the second barrier wall 204 and the first metal layer structure 202B of the first barrier wall 202 can be formed through the same material layer through the same patterning process to Simplify the preparation process of the display substrate.
  • FIG. 2C is a schematic cross-sectional view of the display substrate in FIG. 2A along the line C-C, that is, a schematic partial cross-sectional view of the display area 101 of the display substrate 100.
  • the display substrate 100 further includes a base substrate 1011.
  • the display area 101 includes a pixel array for performing display operations.
  • the pixel array includes a plurality of pixel units arranged in an array, and each pixel unit includes a driving circuit, a light emitting device, and the like.
  • the driving circuit includes a thin film transistor 102 and a storage capacitor 103 and other structures.
  • the thin film transistor 102 includes an active layer 1021, a gate 1022, a gate insulating layer 1014 (for example, a first gate insulating layer 1014A and a second gate insulating layer 1014B), an interlayer insulating layer 1015, and a gate insulating layer 1014 sequentially disposed on a base substrate 1011.
  • Source and drain electrodes (including source 1023 and drain 1024).
  • the storage capacitor 103 includes a first plate 1031 and a second plate 1032.
  • the first electrode plate 1031 and the gate electrode 1022 are arranged in the same layer, and the second electrode plate 1032 is between the gate insulating layer 1014 and the interlayer insulating layer 1015.
  • the first metal layer structure 202B of the first barrier wall 202 and the second metal layer structure 204B of the second barrier wall 204 are arranged in the same layer as the source and drain electrodes 1023 and 1024.
  • the arrangement of two or more functional layers in the same layer means that these functional layers arranged in the same layer can be formed using the same material layer and the same preparation process (such as patterning process, etc.), thereby simplifying The preparation process of the display substrate.
  • the source and drain electrodes 1023 and 1024 each have a three-layer metal layer structure, such as titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, titanium/copper/titanium, or molybdenum/copper/molybdenum, etc.
  • Three-layer metal layer structure At this time, the three metal sub-layers 2023/2024/2025 of the first metal layer structure 202B and the three metal sub-layers 2045/2046/2047 of the second metal layer structure 204B are respectively connected to the source and drain electrodes 1023 It has a one-to-one correspondence with 1024's three-layer metal layer and has the same material.
  • the first metal layer structure 202B, the second metal layer structure 204B, and the source and drain electrodes 1023 and 1024 can be formed by using the same three metal material layers and using the same patterning process.
  • the stack of the first stacked structure 204A of the second barrier wall 204 includes a first metal sub-layer 2041 and a first insulating sub-layer sequentially disposed on the base substrate 1011 2042, a second metal sublayer 2043, and a second insulating sublayer 2044.
  • the first metal sublayer 2041 and the gate electrode 1022 are provided in the same layer
  • the first insulating sublayer 2042 and the gate insulating layer 1014 are provided in the same layer
  • the second metal sublayer 2043 and the second electrode plate 1032 are provided in the same layer
  • the second insulating sublayer 2044 is provided on the same layer as the interlayer insulating layer 1015. Therefore, the functional layers arranged in the same layer can be formed by using the same material layer and using the same patterning process to simplify the preparation process of the display substrate.
  • the second barrier wall 204 may have various forms.
  • the first insulating sublayer 2042 and the second insulating sublayer 2044 of the second barrier wall 204 may have the same characteristics as the first metal sublayer 2041 and the second metal sublayer 2043.
  • the pattern is thus embodied in Figure 4B as having the same width.
  • the first insulating sub-layer 2042 and the second insulating sub-layer 2044 may be further etched to form corresponding patterns.
  • the first barrier wall 202 may further include a second insulating layer structure 202A, the first metal layer structure 202B is located on the second insulating layer structure 202A, and the second insulating layer structure 202A It is provided at least in the same layer as the gate insulating layer 1014 and the interlayer insulating layer 1015.
  • the second insulating layer structure 202A includes a plurality of insulating sublayers, for example, as shown in FIG. 3A as including insulating sublayers 2021 and 2022.
  • the insulating sub-layer 2021 and the gate insulating layer 1014 are arranged in the same layer, and the insulating sub-layer 2022 and the interlayer insulating layer 1015 are arranged in the same layer, so that the functional layers arranged in the same layer can be made of the same material layer and pass the same patterning during the preparation process.
  • the arrangement of the second insulating layer structure 202A can enhance the barrier effect of the first barrier wall 202, and is beneficial to the first inorganic encapsulation layer 1051 (described later) formed on the first barrier wall 202 later, for example, by deposition. It is well formed along the surface topography of the first barrier wall 202.
  • the width W1 of the first barrier wall 202 may be 2 ⁇ m-4 ⁇ m, such as 3 ⁇ m or 3.5 ⁇ m.
  • the width of the second barrier wall 204 may also be 2 ⁇ m-4 ⁇ m, such as 3 ⁇ m or 3.5 ⁇ m, etc.
  • the embodiment of the present disclosure does not specifically limit the size of each structure, as long as the corresponding function can be realized.
  • the display area 101 of the display substrate 100 further includes a planarization layer 1016, a pixel defining layer 1017, and spacers 1018.
  • the planarization layer 1016 is used to planarize the thin film transistor 102
  • the pixel defining layer 1017 is on the side of the planarizing layer 1016 away from the thin film transistor 102
  • the pixel defining layer 1017 is used to define a plurality of pixel units.
  • the spacer 1018 is on the side of the pixel defining layer 1017 away from the flat layer 1016.
  • the first insulating layer structure of the first blocking wall 203 is arranged in the same layer as at least one of the planarization layer 1016, the pixel defining layer 1017, and the spacer 1018.
  • the first blocking wall 203 includes a plurality of insulating sub-layers, which is shown in FIG. 3B as including insulating sub-layers 2031 and 2032.
  • the insulating sub-layers 2031 and 2032 correspond to two of the planarization layer 1016, the pixel defining layer 1017, and the spacer 1018 in one-to-one correspondence and are arranged in the same layer.
  • the insulating sublayer 2031 and the planarization layer 1016 are provided in the same layer, and the insulating sublayer 2032 and the pixel defining layer 1017 are provided in the same layer; or, the insulating sublayer 2031 and the planarization layer 1016 are provided in the same layer, and the insulating sublayer 2032 and the spacer 1018 are provided in the same layer. Or, the insulating sub-layer 2031 and the pixel defining layer 1017 are provided in the same layer, and the insulating sub-layer 2032 and the spacer 1018 are provided in the same layer. Therefore, in the preparation process, these functional layers arranged in the same layer can be formed by the same material layer and the same patterning process.
  • the blocking area 201 may also include a second blocking wall 205 adjacent to the first blocking wall 203 and on the side of the first blocking wall 203 away from the display area 101.
  • the second blocking wall 205 is higher than the first blocking wall 205.
  • the second blocking wall 205 includes a plurality of insulating sub-layers, which is shown in FIG. 3D as including insulating sub-layers 2051, 2052, and 2053.
  • the insulating sub-layer 2051 is the same as the planarization layer 1016.
  • the insulating sub-layer 2052 and the pixel defining layer 1017 are arranged in the same layer, and the insulating sub-layer 2053 and the spacer 1018 are arranged in the same layer. Therefore, in the preparation process, these functional layers arranged in the same layer can be formed by the same material layer and the same patterning process.
  • the second interception wall 205 is higher than the first interception wall 203, which can achieve a sufficient interception function, and the second interception wall 205 and the first interception wall 203 together can achieve a double interception effect.
  • the display substrate 100 may further include a barrier layer 1012 and a buffer layer 1013 disposed on a base substrate 1011.
  • the barrier layer 1012 can prevent impurities such as water and oxygen from penetrating from the base substrate 1011 to the thin film transistor 102, etc.
  • the buffer layer 1013 can provide a flat surface to facilitate the arrangement of other functional layers of the display substrate.
  • the barrier layer 1012 and the buffer layer 1013 can jointly protect other functional structures on the base substrate 1011.
  • the structure of the first barrier wall 202 and the second barrier wall 204 may also include a structure arranged in the same layer as the barrier layer 1012 and the buffer layer 1013.
  • the second insulating layer structure 202A of the first barrier wall 202 includes a first part (including insulating sublayers 2021 and 2022) and a second part (including insulator Layers 2026 and 2027), the first part is at least arranged in the same layer as the gate insulating layer 1014 and the interlayer insulating layer 1015, and the second part is arranged at least in the same layer as the barrier layer 1012 and the buffer layer 1013. Therefore, in the preparation process, these functional layers arranged in the same layer can be formed by the same material layer and the same patterning process.
  • the widths of the first part and the second part of the second insulating layer structure 202A are different, for example, the second part is wider than the first part, so that the overall longitudinal section of the second insulating layer structure 202A is stepped, as shown in FIG. 5B.
  • the number of barrier layers and buffer layers included on the base substrate may be more.
  • the second part of the second insulating layer structure 202A may be combined with more barrier layers and buffer layers. Same layer settings.
  • the gate insulating layer 1014 in the barrier region 201 (and the bending region 401 described later) is only shown as one layer in the drawings.
  • the first laminated structure 204A of the second barrier wall 204 may also include two parts, called the third part (including the first metal sublayer 2041, the first insulating sublayer 2042, The second metal sublayer 2043 and the second insulating sublayer 2044) and the fourth part (including the insulating sublayers 2048 and 2049), for example, the fourth part and the second part of the second insulating layer structure 202A of the first barrier wall and the barrier layer 1012 and the buffer layer 1013 are arranged in the same layer. Therefore, in the preparation process, these functional layers arranged in the same layer can be formed by the same material layer and the same patterning process.
  • the third part and the fourth part have different widths, for example, the fourth part is wider than the third part, so that the longitudinal section of the first laminated structure 204A is stepped as a whole.
  • the first inorganic encapsulation layer is formed thereon, for example, by deposition. 1051 (introduced later) can be better formed along the surface topography of the first barrier wall 202 and the second barrier wall 204 without side fractures and other undesirable conditions, so that the first inorganic encapsulation layer 1051 has better Integrity, and provide better packaging effect.
  • FIGS. 4A and 5A only show the first barrier wall 202, the first barrier wall 203, the second barrier wall 204, and the second barrier wall 205 on the base substrate 1011.
  • the display substrate may also include other structures as shown in FIG. 2B.
  • FIG. 2B please refer to FIG. 2B, which will not be repeated here.
  • the light emitting device 104 included in each pixel unit in the display area 101 includes an anode layer 1041, a light emitting layer 1042, and a cathode layer 1043.
  • the anode layer 1041 is connected to the source electrode 1023 of the thin film transistor through a via hole in the flat layer 1016.
  • the cathode layer 1043 is formed on the entire surface of the base substrate 1011 and is disconnected at the first barrier wall 202 and the second barrier wall 204.
  • an auxiliary light-emitting layer (not shown in the figure) that helps the light-emitting layer 1042 emit light may also be included, such as an electron transport layer, One or more of injection layer, hole transport layer, and hole injection layer.
  • the auxiliary light-emitting layer is, for example, an organic material layer.
  • the auxiliary light-emitting layer may also be formed on the entire surface of the base substrate 1011 and be disconnected at the first barrier wall 202 and the second barrier wall 204.
  • the auxiliary light-emitting layer and the cathode layer 1043 on the side close to the opening area 301 are contaminated by impurities such as water and oxygen, the auxiliary light-emitting layer and the cathode layer 1043 are broken by the first barrier wall 202 and the second barrier wall 204. Open, so that these contaminant impurities will not extend to the auxiliary light-emitting layer and the cathode layer 1043 for the light-emitting device to emit light.
  • part of the auxiliary light-emitting layer and the cathode layer 1043 are also formed on the top of the first barrier wall 202 and the second barrier wall 204, but these parts are separated from other parts.
  • the display substrate 100 may further include an encapsulation layer 105, which encapsulates at least the first barrier wall 202.
  • the encapsulation layer 105 simultaneously encapsulates the display area 101 and the first barrier rib 202. Blocking wall 202.
  • the encapsulation layer 105 includes a first inorganic encapsulation layer 1051, a first organic encapsulation layer 1052, and a second inorganic encapsulation layer 1053 that are sequentially stacked on the first barrier wall 202.
  • the first inorganic encapsulation layer 1051 is formed on the entire surface of the display substrate. Due to the interception effect of the first interception wall 203, the first organic encapsulation layer 1052 and the second inorganic encapsulation layer 1053 terminate at the first interception wall 203.
  • the display substrate 100 may further include a first organic insulating layer 206, and the first organic insulating layer 206 covers at least the second barrier wall 204.
  • the first organic insulating layer 206 is disposed between the second blocking wall 205 and the opening area 301.
  • the first organic insulating layer 206 can protect the second barrier wall 204, and can also prevent impurities such as water and oxygen from entering the display area 101 from the opening area 301; in addition, the first organic insulating layer 206 has a certain height.
  • the first organic insulating layer 206 can support structures such as the polarizer and the cover plate around the opening area 301 to prevent the structure of the polarizer and cover plate from being damaged.
  • the hole area 301 has undesirable phenomena such as collapse.
  • the barrier region 201 may further include a third barrier wall 207 and a second organic insulating layer 208.
  • the third blocking wall 207 is on the side of the second blocking wall 205 away from the display area 101, and the second organic insulating layer 208 is between the second blocking wall 205 and the third blocking wall 207 and covers the second blocking wall 204. Therefore, the third blocking wall 207 and the second organic insulating layer 208 provide a further barrier effect, so that the barrier region 201 can fully isolate the opening region 301 and the display region 101, and prevent impurities such as water and oxygen from entering the display region from the opening region 301. Area 101, and prevent cracks that may be formed when the opening area 301 is formed from extending to the display area 101.
  • the third blocking wall 207 and the second blocking wall 205 have the same structure and include the same material.
  • the third interception wall 207 and the second interception wall 205 can be formed using the same material layer and through the same patterning process.
  • the second organic insulating layer 208 has the same material as the first organic encapsulation layer 1052 of the encapsulation layer 1015, and may be formed by the same inkjet printing process, for example.
  • the barrier area 201 further includes a signal line lead 210, which is electrically connected to the signal line of the display area 101, and the signal line lead 210 is close to 101 of the first barrier wall 202.
  • the blocking area 201 includes a plurality of signal line leads 210 to be electrically connected with signal lines such as data lines, scan lines, or power lines in the display area 101 to implement wiring around the opening area 301.
  • the display substrate 100 may further include: an image sensor and/or an infrared sensor 501, which is combined with the non-display side of the display substrate 100, and The orthographic projection on the base substrate 1011 and the opening area 301 at least partially overlap.
  • the image sensor and/or the infrared sensor 501 can realize multiple functions such as photographing, facial recognition, infrared sensing, etc. through the opening area 301.
  • the display substrate 100 may be a flexible display substrate.
  • the base substrate 1011 may be a flexible insulating material such as polyimide (PI).
  • the display substrate 100 may further include a bending area 401 located on one side of the display area 101.
  • FIG. 8A shows a schematic cross-sectional view when the bending area 401 is not bent
  • FIG. 8B shows another schematic cross-sectional view when the bending area 401 is not bent
  • FIG. 8C shows the bending area 401
  • the folded schematic cross-sectional view which is obtained by cutting along line DD in FIG. 2A, for example.
  • the bending area 401 includes an insulating layer 4011 disposed on the base substrate 1011, and the insulating layer 4011 includes a barrier layer 1012, a buffer layer 1013, and a gate insulating layer 1014 extending from the display area to the bending area 401, respectively.
  • the insulating layer 4011 has, for example, wiring (not shown) and a protective layer 4013 and the like.
  • the non-display side of the display substrate 100 has a driving structure such as a driving chip and a circuit board, and the driving circuit of the display area 101 can be electrically connected to the driving structure on the non-display side of the display substrate 100 through the wiring of the bending area 401, so that the The driving structure can realize the display control of the display area 101 of the display substrate 100.
  • a driving structure such as a driving chip and a circuit board
  • the driving circuit of the display area 101 can be electrically connected to the driving structure on the non-display side of the display substrate 100 through the wiring of the bending area 401, so that the The driving structure can realize the display control of the display area 101 of the display substrate 100.
  • the insulating layer 4011 has a groove 4012, and the groove 4012 is filled with a stress relaxation material.
  • the stress relaxation material includes a flexible organic material, which can alleviate the stress generated in the bending area 401 during bending, as shown in FIG. 8C .
  • the groove 4012 in the insulating layer 4011 may penetrate one or more insulating sub-layers in the insulating layer 4011.
  • the groove 4012 penetrates the gate insulating layer 1014 and the interlayer insulating layer 1015, which can be etched The gate insulating layer 1014 and the interlayer insulating layer 1015 are formed. In FIG.
  • the groove 4012 penetrates the barrier layer 1012, the buffer layer 1013, the gate insulating layer 1014, and the interlayer insulating layer 1015, so that the barrier layer 1012, the buffer layer 1013, the gate insulating layer 1014, and the interlayer insulating layer 1015 can be etched. form.
  • the groove 4012 may be formed by the same etching process as the second insulating layer structure 202A of the first barrier wall 202 and the insulating sub-layer of the first stacked structure 204A of the second barrier wall 204.
  • the etching process may be One etching process or two etching processes.
  • two etching processes may be used to etch different functional layers respectively, so as to improve the accuracy of the etching process and obtain the required etching topography.
  • the barrier region 201 can fully isolate the display region 101 from the opening region 301, effectively preventing impurities such as water and oxygen from entering the display region 101 from the opening region 301, and can also prevent the formation of the opening region.
  • the cracks that may occur at 301 extend to the display area 101, which improves the reliability of the display substrate.
  • At least one embodiment of the present disclosure also provides a method for preparing a display substrate, which can prepare the above-mentioned display substrate 100.
  • the preparation method includes: forming a display area, a barrier area and an opening area.
  • the display area and the barrier area surround the opening area, and the barrier area is located between the display area and the opening area.
  • Forming the barrier area includes forming a first barrier wall, a first barrier wall, and a second barrier wall that are sequentially arranged from the display area to the opening area, and the first barrier wall, the first barrier wall, and the second barrier wall surround the opening area.
  • the first barrier wall includes a first metal layer structure, and at least one side surface of the first metal layer structure surrounding the opening area has a notch.
  • the first blocking wall includes a first insulating layer structure.
  • the second barrier wall includes a second metal layer structure and a first laminate structure.
  • the first laminate structure is located on the first laminate structure. At least one side surface of the second metal layer structure surrounding the opening area has a notch.
  • the laminated structure includes a laminated layer of a metal layer and an insulating layer.
  • a base substrate 1011 is provided.
  • the provided base substrate 1011 may be a flexible substrate such as polyimide (PI).
  • the substrate 1011 may be a rigid substrate such as glass or quartz.
  • the present embodiment takes the formation of a flexible display substrate as an example for introduction. At this time, the flexible display substrate has a bending area 401, for example.
  • a functional layer for the display area 101, the barrier area 201, and the bending area 401 is formed on the base substrate 1011, and positions are reserved for the opening area 301 to facilitate the display area 101
  • the opening area 301 is formed by means such as punching or cutting.
  • the barrier layer 1012 and the buffer layer 1013 may be sequentially formed on the base substrate 1011 by a method such as deposition.
  • the barrier layer 1012 and the buffer layer 1013 may be formed on the base substrate 1011 over the entire surface.
  • the barrier layer 1012 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride
  • the buffer layer 1013 can also be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the first laminated structure 204A has a bending region insulating layer 4011 formed in the bending region 401.
  • an active layer 1021 is formed on a base substrate 1011 by a patterning process; a first gate insulating layer 1014A is formed on the active layer 1021 by deposition or the like; on the first gate insulating layer A patterning process is used to simultaneously form a gate 1022, a first electrode plate 1031, and a first metal sublayer 2041 on the 1014A; a second gate is formed on the gate 1022, the first electrode plate 1031 and the first metal sublayer 2041 by deposition or other methods Insulating layer 1014B; using a patterning process to simultaneously form the second electrode plate 1032 and the second metal sub 2043; on the second electrode 1032 and the second metal sub 2043 to form an interlayer insulating layer 1015 by means of deposition, etc.; then, etching the gate
  • the insulating layer 1014 and the interlayer insulating layer 1015 form via holes exposing the active layer 1021.
  • a patterning process includes photoresist formation, exposure, development
  • the first metal sublayer 2041 of the second barrier wall 204 is formed in the same layer as the gate electrode 1022
  • the first insulating sublayer 2042 is formed in the same layer as the gate insulating layer 1014
  • the second metal sublayer 2043 is formed in the same layer as the second electrode plate 1032.
  • Layer formation, the second insulating sub-layer 2044 and the interlayer insulating layer 1015 are formed in the same layer. This simplifies the preparation process of the display substrate.
  • the materials of the gate 211, the first electrode plate 1031, and the first metal sublayer 2041 include metals or alloy materials such as aluminum, titanium, and cobalt.
  • the formation of other structures formed in the same layer is similar to this, so it will not be repeated here.
  • the active layer 1021 can be made of materials such as polysilicon and metal oxide
  • the gate insulating layer 1014 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride
  • the second electrode plate 1032 and the second metal sublayer 2043 can be Metal or alloy materials such as aluminum, titanium, and cobalt are used
  • the interlayer insulating layer 1015 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the embodiments of the present disclosure do not limit the material of each functional layer, and the material of each functional layer is not limited to the above examples.
  • a single etching process can be used to etch the gate insulating layer 1014 and the interlayer insulating layer 1015 in the barrier region 201 and the bending region 401, thereby forming the first barrier wall 202.
  • the second insulating layer structure 202A includes a sub-insulating layer 2021 formed in the same layer as the gate insulating layer 1014 and a sub-insulating layer 2022 formed in the same layer as the interlayer insulating layer 1015.
  • the groove 4012 may be filled with a stress-relieving material, such as organic insulating materials such as polyimide and epoxy.
  • the second insulating layer structure 202A is formed in the same layer as the gate insulating layer 1014 and the interlayer insulating layer 1015, and the second insulating layer structure 202A is also formed by the same etching process as the insulating layer 4011 in the bending region 401. This simplifies the preparation process of the display substrate.
  • the method for preparing the display substrate can also form the first barrier wall 202 as shown in FIG. 5B and the second barrier wall 204 as shown in FIG. 5C.
  • the gate insulating layer 1014 and the interlayer insulating layer 1015 in the bending region 401 and the barrier region 201 can be simultaneously etched by the first etching process, and the second etching process can be simultaneously etched in the bending region 401 and
  • the barrier layer 1012 and the buffer layer 1013 of the barrier region 201 are formed to form a groove 4012 penetrating the barrier layer 1012, the buffer layer 1013, the gate insulating layer 1014, and the interlayer insulating layer 1015 (for example, the case shown in FIG.
  • the second insulating layer structure 202A including the first part (including the insulating sublayers 2021 and 2022) and the second part (including the insulating sublayers 2026 and 2027) and the third part (including the first metal sublayer 2041, the first insulating sublayer 2042) The second metal sublayer 2043 and the second insulating sublayer 2044) and the fourth part (including the insulating sublayers 2048 and 2049) of the first stacked structure 204A.
  • the insulating sub-layer in the first part of the second insulating layer structure 202A and the third part of the first stacked structure 204A is formed in the same layer as the gate insulating layer 1014 and the interlayer insulating layer 1015, and is formed with the concave portion of the bending region 401
  • a part of the trench 4012 is formed by etching through the same etching process (first etching process); the second part of the second insulating layer structure 202A, the fourth part of the first stacked structure 204A, and the barrier layer 1012 and the buffer layer 1013 It is formed in the same layer, and is formed by etching with the same etching process (second etching process) as another part of the groove 4012 of the bending area 401.
  • the overall thickness of the barrier layer 1012, the buffer layer 1013, the gate insulating layer 1014, and the interlayer insulating layer 1015 is relatively thick, etching a part of them through the two etching processes is beneficial to the smooth progress of the etching process and is beneficial to ensure The final etch topography.
  • the barrier layer 1012, the buffer layer 1013, the gate insulating layer 1014 and the part of the interlayer insulating layer 1015 close to the opening area 301 can also be etched at the same time, (that is, the part in FIG. 10A The dashed box on the left shows the part). Since part or all of the barrier layer 1012, the buffer layer 1013, the gate insulating layer 1014, and the interlayer insulating layer 1015 are made of inorganic insulating materials, due to the brittleness of the inorganic insulating materials, the opening areas are formed by means such as punching or cutting. Cracks are likely to form at 301. Therefore, removing the barrier layer 1012, buffer layer 1013, gate insulating layer 1014 and interlayer insulating layer 1015 near the opening region 301 can avoid cracks in these layers when forming the opening region 301.
  • the source electrode 1023 and the drain electrode 1024 and the first metal layer structure 202B of the first barrier wall 202 and the second barrier wall 204 are formed.
  • the second metal layer structure 204B is formed.
  • the source electrode 1023 and the drain electrode 1024 may be formed in a multilayer metal structure, such as a three-layer metal layer structure.
  • a titanium material layer, an aluminum material layer, and a titanium material layer may be sequentially formed by sputtering or evaporation, and then the three material layers may be patterned using the same patterning process to form the source electrode 1023.
  • a three-layer metal structure of titanium/aluminum/titanium 3 and the drain 1024 forms an initial first metal layer structure and an initial second metal layer structure with flush sides.
  • the initial first metal layer structure and the initial second metal layer structure with flush sides are etched by one etching process to form the first metal layer structure 202B and the second metal layer structure 204B with notches on the side surface.
  • the etching solution used in the etching process only has an etching effect on the intermediate layer of the first metal layer structure 202B and the second metal layer structure 204B, or the etching rate of the intermediate layer is greater than the etching rate of other layers, Therefore, the etching process can form the recesses of the first metal layer structure 202B and the second metal layer structure 204B.
  • the source electrode 1023 and the drain electrode 1024, the first metal layer structure 202B of the first barrier wall 202 and the second metal layer structure 204B of the second barrier wall 204 are formed in the same layer, which simplifies the manufacturing process of the display substrate.
  • the planarization layer 1016, the anode layer 1041, the pixel defining layer 1017, and the spacer 1018 are sequentially formed, and the first One interception wall 203 and second interception wall 205.
  • the planarization layer 1016, the insulating sublayer 2031 of the first blocking wall 203, and the insulating sublayer 2051 of the second blocking wall 205 are formed in the same layer through a patterning process.
  • the planarization layer 1016, the insulating sub-layer 2031 of the first blocking wall 203, and the insulating sub-layer 2051 of the second blocking wall 205 can be made of organic insulating materials such as polyimide and epoxy resin.
  • the formed planarization layer 1016 has a via hole, so that the anode layer 1041 formed later is electrically connected to the source electrode 1023 through the via hole.
  • a patterning process is used to form the anode layer 1041 on the planarization layer 1016 of the display area 101, and the anode layer 1041 is electrically connected to the source electrode 1023 through the via hole in the planarization layer 1016.
  • the material of the anode layer 1041 includes metal oxides such as ITO, IZO, or metals such as Ag, Al, Mo, or alloys thereof.
  • the pixel defining layer 1017, the insulating sub-layer 2032 of the first blocking wall 203 and the insulating sub-layer 2052 of the second blocking wall 205 are formed in the same layer by a patterning process.
  • the pixel defining layer 1017 has an opening exposing the anode layer 1041 so as to form the light emitting layer 1042 and the cathode layer 1043 of the light emitting device later.
  • the material of the pixel defining layer 1017, the insulating sub-layer 2032 of the first blocking wall 203, and the insulating sub-layer 2052 of the second blocking wall 205 may include organic insulating materials such as polyimide and epoxy resin.
  • the spacer 1018 and the insulating sublayer 2053 of the second blocking wall 205 are formed in the same layer by a patterning process.
  • the materials of the spacer 1018 and the insulating sublayer 2053 of the second blocking wall 205 include organic insulating materials such as polyimide and epoxy resin.
  • the number of sub-insulation layers of the second interception wall 205 is more than the number of sub-insulation layers of the first interception wall 203, so the second interception wall 205 is higher than the first interception wall 203.
  • the first blocking wall 203 is formed in the same layer as the planarization layer 1016 and the pixel defining layer 1017
  • the second blocking wall 205 is formed in the same layer as the planarizing layer 1016, the pixel defining layer 1017, and the spacer 108, which simplifies The preparation process of the display substrate.
  • the second blocking wall 205 can also be formed in the same layer as the planarization layer 1016 and the spacer 108, or formed in the same layer as the pixel defining layer 1017 and the spacer 108. This is the case in the embodiment of the present disclosure. Not limited.
  • the light-emitting layer 1042 can be formed in the opening of the pixel defining layer 1017 by inkjet printing or evaporation, and then the cathode layer 1043 is formed.
  • an auxiliary light-emitting layer (not shown) may be formed between the light-emitting layer 1042 and the anode layer 1041 or between the light-emitting layer 1042 and the cathode layer 1043.
  • the auxiliary light-emitting layer includes, for example, an electron injection layer, an electron transport layer, and a hole injection layer. And one or more of the hole transport layers.
  • the cathode layer 1043 and the auxiliary light-emitting layer are formed on the entire surface of the display substrate, for example, and are disconnected at the first barrier wall 202 and the second barrier wall 204.
  • the material of the light-emitting layer 1042 and the auxiliary light-emitting layer are organic materials, and the material of the light-emitting layer 1042 can be selected according to requirements that can emit light of a certain color (such as red light, blue light, or green light).
  • the material of the cathode layer 1043 may include metals such as Mg, Ca, Li, or Al or their alloys, or metal oxides such as IZO, ZTO, or PEDOT/PSS (poly 3,4-ethylenedioxythiophene/polystyrene sulfonic acid Salt) and other organic materials with conductive properties.
  • an encapsulation layer 105 can be formed on the display area 201 and the first barrier wall 202.
  • forming the encapsulation layer 105 includes sequentially forming a first inorganic encapsulation layer 1051, a first organic encapsulation layer 1052, and a second inorganic encapsulation layer 1053 on the first barrier wall 202 and in the display area 201.
  • the first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 are formed by deposition or the like.
  • the first organic encapsulation layer 1052 is formed by inkjet printing. As shown in FIG. 14B, due to the interception effect of the first interception wall 203, the first organic encapsulation layer 1052 terminates at the first interception wall 203.
  • the ink may flow to the outside of the first blocking wall 203 when the first organic encapsulation layer 1052 is formed by inkjet printing. , Even flow to the outside of the second interception wall 205, so that the first organic encapsulation layer 1052 extends to the opening area 301, which becomes a channel for water and oxygen transmission, making the display area 101 contaminated.
  • the first organic encapsulation layer 1052 may be formed by printing indentation control and edge supplement printing.
  • the inkjet printing boundary can be retracted to point D.
  • Point D is on the side of the first blocking wall 203 close to the display area 101.
  • the distance between point D and the first blocking wall 203 is selected as 50 ⁇ m-70 ⁇ m, for example 60 ⁇ m, in this case, first use dot D as the printing boundary for inkjet printing.
  • supplementary edge printing is performed on the range between D point and the first blocking wall 203. Therefore, the inkjet printing process is easier to control, and the ideal first organic encapsulation layer 1052 is easily formed.
  • the first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 may be formed of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc.
  • the first organic encapsulation layer 1052 may be formed of polyimide (PI), epoxy Made of organic materials such as resin.
  • PI polyimide
  • the first inorganic encapsulation layer 1051, the first organic encapsulation layer 1052, and the second inorganic encapsulation layer 1053 are formed as a composite encapsulation layer, which can form the functional structure of the display area 201 and the first barrier wall 202. Multiple protection, with better packaging effect.
  • a first organic insulating layer 206 can also be formed on the second barrier wall 204 by coating or the like, and the first organic insulating layer 206 covers at least the second barrier wall 204.
  • the first organic insulating layer 206 is formed between the second blocking wall 205 and the opening region 301.
  • the first organic insulating layer 206 can protect the second barrier wall 204, and the first organic insulating layer 20 can also prevent impurities such as water and oxygen from entering the display area 101 from the opening area 301; in addition, the first organic insulating layer 206 Having a certain height can support structures such as the polarizer and cover plate formed on the display substrate 100 later, and prevent the structure such as the polarizer and cover plate from collapsing in the opening area 301.
  • a protective layer 4013 is also formed on the insulating layer 4011 of the bending region 401.
  • the protective layer 4013 may be formed in the same layer as the first organic insulating layer 206 to simplify the manufacturing process.
  • other necessary functional film layers may be formed in the display area 101, the barrier area 201, and the bending area 401 according to needs, and these film layers may be formed by conventional methods, which will not be repeated here.
  • the opening area 301 can be formed by laser cutting or mechanical punching.
  • the opening area 301 penetrates the base substrate 1011, and the opening area 301 can be equipped with an image sensor, an infrared sensor, and other structures, and is connected to a central processing unit.
  • the image sensor or infrared sensor can be arranged on the side of the base substrate 1011 away from the light-emitting device (that is, the non-display side of the display substrate), and photography, facial recognition, infrared sensing, etc. can be realized through the opening area 301 A variety of functions.
  • structures such as a polarizer and a cover plate may also be formed on the display substrate, which is not limited in the embodiment of the present disclosure.
  • the first barrier wall 202, the first barrier wall 203, the second barrier wall 204, the second barrier wall 205, etc. may be formed in multiples, so that the barrier area 201 has a better barrier effect.
  • the embodiment of the present disclosure does not limit the number of structures such as the first barrier wall 202, the first barrier wall 203, the second barrier wall 204, and the second barrier wall 205.
  • the method for preparing the display substrate can also form the display substrate as shown in FIG. 6.
  • forming the barrier region 201 also includes forming the third barrier wall 207 and the second organic insulating layer 208.
  • the third blocking wall 207 is formed on the side of the second blocking wall 205 away from the display area 101, and the second organic insulating layer 208 is formed between the second blocking wall 205 and the third blocking wall 207 and covers the second blocking wall 204.
  • the third interception wall 207 and the second interception wall 205 are formed on the same layer and have the same structure.
  • the specific formation method of the third interception wall 207 please refer to the formation method of the second interception wall 205 described in the above embodiment. No longer.
  • the second organic insulating layer 208 may be formed by inkjet printing.
  • the second organic insulating layer 208 and the first organic encapsulation layer 1052 are formed in the same inkjet printing process to simplify the preparation process of the display substrate.
  • the display substrate formed by the preparation method provided by the embodiment of the present disclosure includes a barrier region, the barrier region includes a plurality of barrier walls and barrier walls, which can sufficiently isolate the display region from the opening region and avoid crack propagation that may be formed when the opening region is formed To the display area, thereby improving the reliability of the display substrate.
  • the display substrate provided by the embodiment of the present disclosure or the display substrate obtained by the preparation method provided by the embodiment of the present disclosure may be used in a display device, and the display device may be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, Any product or component with a display function, such as a navigator, is not limited in the embodiment of the present disclosure.

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Abstract

一种显示基板及其制备方法。该显示基板(100)包括显示区(101)、阻隔区(201)和开孔区(301)，阻隔区(201)位于显示区(101)和开孔区(301)之间。阻隔区(201)包括从显示区(101)到开孔区(301)方向依次排列的第一阻隔墙(202)、第一拦截墙(203)以及第二阻隔墙(204)。第一阻隔墙(202)包括第一金属层结构(202B)，第一金属层结构(202B)的围绕开孔区(301)的至少一个侧面具有凹口；第一拦截墙(203)包括第一绝缘层结构；第二阻隔墙(204)包括第二金属层结构(204B)和第一叠层结构(204A)，第二金属层结构(204B)的围绕开孔区(301)的至少一个侧面具有凹口，第一叠层结构(204A)包括具有金属层和绝缘层的叠层。该显示基板(100)将摄像装置与显示基板(100)的显示区(101)结合在一起，并且具有更好的封装效果。

Description

显示基板及其制备方法 技术领域
本公开的实施例涉及一种显示基板及其制备方法。
背景技术
目前，显示器件的显示屏正往大屏化、全屏化方向发展。通常，显示器件(例如手机、平板电脑等)具有摄像装置(或成像装置)，该摄像装置通常设置在显示屏显示区域外的一侧。但是，由于摄像装置的安装需要一定的位置，因此不利于显示屏的全屏化、窄边框设计。例如，可以将摄像装置与显示屏的显示区域结合在一起，在显示区域中为摄像装置预留位置，以获得显示屏显示区域的最大化。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板包括显示区、阻隔区和开孔区，所述显示区和所述阻隔区围绕所述开孔区，所述阻隔区位于所述显示区和所述开孔区之间，其中，所述阻隔区包括从所述显示区到所述开孔区方向依次排列的第一阻隔墙、第一拦截墙以及第二阻隔墙，所述第一阻隔墙、第一拦截墙以及第二阻隔墙围绕所述开孔区；所述第一阻隔墙包括第一金属层结构，所述第一金属层结构的围绕所述开孔区的至少一个侧面具有凹口；所述第一拦截墙包括第一绝缘层结构；所述第二阻隔墙包括第二金属层结构和第一叠层结构，所述第二金属层结构位于所述第一叠层结构上，所述第二金属层结构的围绕所述开孔区的至少一个侧面具有凹口，所述第一叠层结构包括具有金属层和绝缘层的叠层。
例如，本公开至少一实施例提供的显示基板中，所述第二金属层结构与所述第一金属层结构具有相同的结构，并且包括相同的材料。
例如，本公开至少一实施例提供的显示基板还包括衬底基板，其中，所述显示区包括薄膜晶体管和存储电容，所述薄膜晶体管包括依次设置在所述衬底基板上的栅极、栅绝缘层，层间绝缘层和源漏电极；所述存储电容包括第一极板和第二极板，所述第一极板与所述栅极同层设置，所述第二极板在 所述栅绝缘层和所述层间绝缘层之间；所述第一金属层结构、所述第二金属层结构与所述源漏电极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第一叠层结构的叠层包括依次设置在所述衬底基板上的第一金属子层、第一绝缘子层、第二金属子层以及第二绝缘子层，所述第一金属子层与所述栅极同层设置，所述第一绝缘子层与所述栅绝缘层同层设置，所述第二金属子层与所述第二极板同层设置，所述第二绝缘子层与所述层间绝缘层同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第一阻隔墙还包括第二绝缘层结构，所述第一金属层结构位于所述第二绝缘层结构上，所述第二绝缘层结构至少与所述栅绝缘层和所述层间绝缘层同层设置。
例如，本公开至少一实施例提供的显示基板还包括设置在所述衬底基板上的阻挡层和缓冲层，其中，所述第二绝缘层结构包括叠层设置的第一部分和第二部分，所述第一部分至少与所述栅绝缘层和所述层间绝缘层同层设置，所述第二部分至少与所述阻挡层和所述缓冲层同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第二绝缘层结构的纵截面整体呈阶梯状。
例如，本公开至少一实施例提供的显示基板中，所述显示区还包括：用于平坦化所述薄膜晶体管的平坦化层，在所述平坦化层远离所述薄膜晶体管一侧的像素界定层，所述像素界定层用于界定多个像素单元，以及在所述像素界定层远离所述平坦层一侧的隔垫物；所述第一拦截墙的所述第一绝缘层结构与所述平坦化层、所述像素界定层和所述隔垫物中的至少一种同层设置。
例如，本公开至少一实施例提供的显示基板还包括封装层，其中，所述封装层至少封装所述第一阻隔墙。
例如，本公开至少一实施例提供的显示基板中，所述封装层包括在所述第一阻隔墙上依次叠层设置的第一无机封装层，第一有机封装层以及第二无机封装层。
例如，本公开至少一实施例提供的显示基板还包括第一有机绝缘层，其中，所述第一有机绝缘层至少覆盖所述第二阻隔墙。
例如，本公开至少一实施例提供的显示基板中，所述阻隔区还包括与所述第一拦截墙相邻且在所述第一拦截墙远离所述显示区一侧的第二拦截墙, 所述第二拦截墙高于所述第一拦截墙。
例如，本公开至少一实施例提供的显示基板中，所述第二拦截墙与所述平坦化层、所述像素界定层和所述隔垫物同层设置。
例如，本公开至少一实施例提供的显示基板中，所述阻隔区还包括第三拦截墙和第二有机绝缘层，所述第三拦截墙在所述第二拦截墙远离所述显示区的一侧，所述第二有机绝缘层在所述第二拦截墙与所述第三拦截墙之间且覆盖所述第二阻隔墙。
例如，本公开至少一实施例提供的显示基板中，所述第三拦截墙和所述第二拦截墙具有相同的结构，并且包括相同的材料。
例如，本公开至少一实施例提供的显示基板中，所述阻隔区还包括信号线引线，所述信号线引线电连接所述显示区的信号线，所述信号线引线在所述第一阻隔墙的靠近所述显示区的一侧。
例如，本公开至少一实施例提供的显示基板还包括：图像传感器和/或红外传感器，其中，所述图像传感器和/或红外传感器结合于所述衬底基板，并且在所述衬底基板上的正投影与所述开孔区至少部分重叠。
本公开至少一实施例还提供一种显示基板的制备方法，包括：形成显示区、阻隔区和开孔区，其中，所述显示区和所述阻隔区围绕所述开孔区，所述阻隔区位于所述显示区和所述开孔区之间；其中，形成所述阻隔区包括形成从所述显示区到所述开孔区方向依次排列的第一阻隔墙、第一拦截墙以及第二阻隔墙，所述第一阻隔墙、第一拦截墙以及第二阻隔墙围绕所述开孔区；所述第一阻隔墙包括第一金属层结构，所述第一金属层结构的围绕所述开孔区的至少一个侧面具有凹口；所述第一拦截墙包括第一绝缘层结构；所述第二阻隔墙包括第二金属层结构和第一叠层结构，所述第一叠层结构位于所述第一叠层结构上，所述第二金属层结构的围绕所述开孔区的至少一个侧面具有凹口，所述第一叠层结构包括金属层和绝缘层的叠层。
例如，本公开至少一实施例提供的显示基板的制备方法中，所述第二金属层结构与所述第一金属层结构采用相同的材料并通过相同的构图工艺形成。
例如，本公开至少一实施例提供的显示基板的制备方法还包括：提供衬底基板；其中，形成所述显示区包括在所述衬底基板上形成薄膜晶体管和存储电容，形成所述薄膜晶体管包括在所述衬底基板上依次形成栅极、栅绝缘 层，层间绝缘层和源漏电极；形成所述存储电容包括形成第一极板和第二极板，所述第一极板与所述栅极同层形成，所述第二极板形成在所述栅绝缘层和所述层间绝缘层之间；所述第一金属层结构、所述第二金属层结构与所述源漏电极同层形成。
例如，本公开至少一实施例提供的显示基板的制备方法中，形成所述第一叠层结构包括在所述衬底基板上依次形成第一金属子层、第一绝缘子层、第二金属子层以及第二绝缘子层，以得到所述第一叠层结构的叠层，其中，所述第一金属子层与所述栅极同层形成，所述第一绝缘子层与所述栅绝缘层同层形成，所述第二金属子层与所述第二极板同层形成，所述第二绝缘子层与所述层间绝缘层同层形成。
例如，本公开至少一实施例提供的显示基板的制备方法中，所述第一阻隔墙还包括第二绝缘层结构，所述第一金属层结构形成在所述第二绝缘层结构上，所述第二绝缘层结构至少与所述栅绝缘层和所述层间绝缘层同层形成。
例如，本公开至少一实施例提供的显示基板的制备方法还包括：在所述衬底基板上形成阻挡层和缓冲层，所述第二绝缘层结构包括叠层设置的第一部分和第二部分，所述第一部分至少与所述栅绝缘层和所述层间绝缘层同层形成，所述第二部分至少与所述阻挡层和所述缓冲层同层形成。
例如，本公开至少一实施例提供的显示基板的制备方法还包括形成位于所述显示区一侧的弯折区，其中，形成所述弯折区包括刻蚀位于所述弯折区的绝缘层以形成凹槽，所述凹槽与所述第二绝缘层结构通过相同的刻蚀工艺形成。
例如，本公开至少一实施例提供的显示基板的制备方法中，位于所述弯折区的绝缘层包括从所述显示区延伸到所述弯折区的阻挡层、缓冲层、栅绝缘层和层间绝缘层，当所述第二绝缘层结构包括叠层设置的第一部分和第二部分时，通过第一刻蚀工艺同时刻蚀位于所述弯折区和所述阻隔区的所述栅绝缘层和所述层间绝缘层，并通过第二刻蚀工艺同时刻蚀位于所述弯折区和所述阻隔区的所述阻挡层和所述缓冲层，以形成所述凹槽和所述第二绝缘层结构。
例如，本公开至少一实施例提供的显示基板的制备方法中，形成所述显示区还包括：形成用于平坦化所述薄膜晶体管的平坦化层，在所述平坦化层 远离所述薄膜晶体管的一侧形成像素界定层，所述像素界定层用于界定多个像素单元，以及在所述像素界定层远离所述平坦层的一侧形成隔垫物，其中，所述第一拦截墙的所述第一绝缘层结构与所述平坦化层、所述像素界定层和所述隔垫物中的至少一种同层形成。
例如，本公开至少一实施例提供的显示基板的制备方法还包括形成至少封装所述第一阻隔墙的封装层，形成所述封装层包括在所述第一阻隔墙上依次形成第一无机封装层，第一有机封装层以及第二无机封装层；其中，所述第一有机封装层采用喷墨打印的方式形成。
例如，本公开至少一实施例提供的显示基板的制备方法还包括在所述第二阻隔墙上形成第一有机绝缘层，所述第一有机绝缘层至少覆盖所述第二阻隔墙。
例如，本公开至少一实施例提供的显示基板的制备方法中，形成所述阻隔区还包括形成与所述第一拦截墙相邻且在所述第一拦截墙远离所述显示区一侧的第二拦截墙,所述第二拦截墙高于所述第一拦截墙。
例如，本公开至少一实施例提供的显示基板的制备方法中，所述第二拦截墙与所述平坦化层、所述像素界定层和所述隔垫物同层形成。
例如，本公开至少一实施例提供的显示基板的制备方法中，形成所述阻隔区还包括形成第三拦截墙和第二有机绝缘层，所述第三拦截墙形成在所述第二拦截墙远离所述显示区的一侧，所述第二有机绝缘层形成在所述第二拦截墙与所述第三拦截墙之间且覆盖所述第二阻隔墙。
例如，本公开至少一实施例提供的显示基板的制备方法中，通过喷墨打印的方式形成所述第二有机绝缘层。
例如，本公开至少一实施例提供的显示基板的制备方法中，所述第二有机绝缘层与覆盖所述第一阻隔墙的第一有机封装层在相同的喷墨打印工艺中形成。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种显示基板的平面示意图；
图1B为图1A中的显示基板沿A-A线的截面示意图；
图2A为本公开至少一实施例提供的一种显示基板的平面示意图；
图2B为图2A中的显示基板沿B-B线的截面示意图；
图2C为图2A中的显示基板沿C-C线的截面示意图；
图3A为本公开至少一实施例提供的一种显示基板中第一阻隔墙的截面示意图；
图3B为本公开至少一实施例提供的一种显示基板中第一拦截墙的截面示意图；
图3C为本公开至少一实施例提供的一种显示基板中第二阻隔墙的截面示意图；
图3D为本公开至少一实施例提供的一种显示基板中第二拦截墙的截面示意图；
图4A为本公开至少一实施例提供的一种显示基板的部分截面示意图；
图4B为本公开至少一实施例提供的一种显示基板中第二阻隔墙的另一截面示意图；
图5A为本公开至少一实施例提供的一种显示基板的部分截面示意图；
图5B为本公开至少一实施例提供的一种显示基板中第一阻隔墙的另一截面示意图；
图5C为本公开至少一实施例提供的一种显示基板中第二阻隔墙的另一截面示意图；
图6为图2A中的显示基板沿B-B线的另一截面示意图；
图7为本公开至少一实施例提供的一种显示基板中阻隔区的平面示意图；
图8A为本公开至少一实施例提供的一种显示基板中弯折区的截面示意图；
图8B为本公开至少一实施例提供的一种显示基板中弯折区的另一截面示意图；
图8C为本公开至少一实施例提供的一种显示基板中弯折区弯折后的截面示意图；以及
图9A-图9C、图10A-图10C、图11A-图11B、图12A-图12B、图13A-图13B以及图14A-图14C为本公开至少一实施例提供的一种显示基板在制 备过程中的截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为实现显示装置的显示区域的最大化，可以将显示装置所具有的摄像装置(成像装置)与显示区域整合在一起，将摄像装置布置在显示区域之中。
例如，图1A示出了一种用于显示装置的显示基板的平面示意图，图1B为图1A中的显示基板沿A-A线的截面示意图。如图1A所示，显示基板10包括显示区域12，显示区域12包括像素阵列且具有在像素阵列中的开孔11，该开孔11为摄像装置(未示出)预留位置，摄像装置可以设置在该显示基板10的与显示侧相对的背侧，从而摄像装置可以通过开孔11获取图像。由此，将摄像装置与显示基板10的显示区域12整合在一起。
显示区域12具有用于显示的发光器件，例如该发光器件为有机发光二极管，显示区域12的全部或部分中的多个发光器件具有的有机材料层13和电极层14通常在显示区域12中形成为一整面，因此采用封装层15进行封装时，位于开孔11附近的区域往往难以被封装，或者即使被封装，也难以保证该区域的封装效果。此时，如图1B所示，例如水、氧等杂质可以从开孔11沿整面形成的有机功能层13和电极层14进入到显示区域12内部，污 染显示区域12中的功能材料，导致这些功能材料的性能退化，进而影响显示区域12的显示效果。
本公开至少一实施例提供一种显示基板，该显示基板包括显示区、阻隔区和开孔区，显示区和阻隔区围绕开孔区，阻隔区位于显示区和开孔区之间；阻隔区包括从显示区到开孔区方向依次排列的第一阻隔墙、第一拦截墙以及第二阻隔墙，第一阻隔墙、第一拦截墙以及第二阻隔墙围绕开孔区；第一阻隔墙包括第一金属层结构，第一金属层结构的围绕开孔区的至少一个侧面具有凹口；第一拦截墙包括第一绝缘层结构；第二阻隔墙包括第二金属层结构和第一叠层结构，第二金属层结构位于第一叠层结构上，第二金属层结构的围绕开孔区的至少一个侧面具有凹口，第一叠层结构包括具有金属层和绝缘层的叠层。该显示基板可以有效地防止水氧等杂质从开孔区进入到显示基板的显示区，从而可以提高显示基板的信赖性。
下面通过几个具体的实施例对本公开一些实施例的显示基板及其制备方法进行说明。
本公开至少一实施例提供一种显示基板，图2A示出了该显示基板100的平面示意图，图2B为图2A中的显示基板沿B-B线的截面示意图，即显示基板100的阻隔区201的截面示意图。
如图2A和图2B所示，该显示基板100包括显示区101、阻隔区201和开孔区301，显示区101和阻隔区201围绕开孔区301，阻隔区201位于显示区101和开孔区301之间。显示区101包括像素阵列，以实现显示。开孔区301允许来自显示基板100的显示侧的光传输通过显示基板100，从而到达显示基板100的背侧。阻隔区201包括从显示区101到开孔区301方向(即图2B中的从右至左的方向)依次排列的第一阻隔墙202、第一拦截墙203以及第二阻隔墙204，第一阻隔墙202、第一拦截墙203以及第二阻隔墙204均围绕开孔区301。阻隔区201可以隔离显示区101与开孔区301，从而达到保护显示区101的作用。
例如，图3A示出了一种第一阻隔墙202的截面示意图；图3B示出了一种第一拦截墙203的截面示意图；图3C示出了一种第二阻隔墙204的截面示意图。
如图2B和图3A所示，第一阻隔墙202包括第一金属层结构202B，第一金属层结构202B的围绕开孔区301的至少一个侧面具有凹口。例如，第 一金属层结构202B面向开孔区301的侧面和背离开孔区301的侧面均具有凹口，即图2B和图3A示出的情况，在其他示例中，也可以在第一金属层结构202B的一个侧面具有凹口。第一阻隔墙202可以断开显示基板上整面形成的功能层，例如发光器件的有机材料层以及阴极层等(稍后详述)。
如图2B和图3B所示，第一拦截墙203包括第一绝缘层结构，第一绝缘层结构例如包括多个子绝缘层的叠层，图2B和图3B示出为包括两个子绝缘层2031和2032的叠层。第一拦截墙203可以拦截显示区101中形成的一些功能层(例如有机封装层，稍后详述)，防止这些功能层的材料靠近或进入开孔区301。
如图2B和图3C所示，第二阻隔墙204包括第二金属层结构204B和第一叠层结构204A，第二金属层结构204B位于第一叠层结构204A上，第二金属层结构204B的围绕开孔区301的至少一个侧面具有凹口。例如，第二金属层结构204B的面向开孔区301的侧面和背离开孔区301的侧面均具有凹口，即图2B和图3C示出的情况，在其他示例中，也可以在第二金属层结构204B的一个侧面具有凹口。例如，第一叠层结构204A包括具有金属层和绝缘层的叠层。第二阻隔墙204也可以断开显示基板上整面形成的功能层，从而与第一阻隔墙202一起达到双重阻隔效果，此时，即使第一阻隔墙202和第二阻隔墙204中的一个失效，第一阻隔墙202和第二阻隔墙204中的另一个也会实现阻隔效果；另外，第二阻隔墙204靠近开孔区301，在例如通过冲压或者切割等方式形成开孔区301时，第二阻隔墙204还可以防止形成开孔区301时可能产生的裂纹进行扩展，从而避免裂纹延伸至显示区101。
例如，第一阻隔墙202、第一拦截墙203以及第二阻隔墙204的个数可以为一个或者多个，图2B中示出两个第一阻隔墙202、一个第一拦截墙203以及一个第二阻隔墙204作为示例，但这并不构成对本公开实施例的限制。
例如，在一些示例中，第二阻隔墙204的第二金属层结构204B与第一阻隔墙202的第一金属层结构202B具有相同的结构，并且包括相同的材料。由此，在显示基板的制备工艺中，第二阻隔墙204的第二金属层结构204B与第一阻隔墙202的第一金属层结构202B可以通过相同的材料层通过相同的构图工艺形成，以简化显示基板的制备工艺。
图2C为图2A中的显示基板沿C-C线的截面示意图，即显示基板100 的显示区101的部分截面示意图。如图2C所示，显示基板100还包括衬底基板1011。显示区101包括用于进行显示操作的像素阵列，该像素阵列包括阵列排布的多个像素单元，每个像素单元包括驱动电路和发光器件等。驱动电路包括薄膜晶体管102和存储电容103等结构。薄膜晶体管102包括依次设置在衬底基板1011上的有源层1021、栅极1022、栅绝缘层1014(例如包括第一栅绝缘层1014A和第二栅绝缘层1014B)，层间绝缘层1015和源漏电极(包括源极1023和漏极1024)。存储电容103包括第一极板1031和第二极板1032。例如，第一极板1031与栅极1022同层设置，第二极板1032在栅绝缘层1014和层间绝缘层1015之间。例如，第一阻隔墙202的第一金属层结构202B、第二阻隔墙204的第二金属层结构204B与源漏电极1023和1024同层设置。
本公开的实施例中，两个或更多个功能层同层设置指的是这些同层设置的功能层可以采用相同的材料层并利用相同制备工艺(例如构图工艺等)形成，从而可以简化显示基板的制备工艺。
例如，在图2C示出的示例中，源漏电极1023和1024均具有三层金属层结构，例如钛/铝/钛、钼/铝/钼、钛/铜/钛或者钼/铜/钼等三层金属层结构，此时，第一金属层结构202B的三个金属子层2023/2024/2025以及第二金属层结构204B的三个金属子层2045/2046/2047分别与源漏电极1023和1024的三层金属层一一对应且材料相同。由此，第一金属层结构202B、第二金属层结构204B与源漏电极1023和1024可以采用相同的三层金属材料层并利用相同的构图工艺形成。
例如，在一些实施例中，如图3C所示，第二阻隔墙204的第一叠层结构204A的叠层包括依次设置在衬底基板1011上的第一金属子层2041、第一绝缘子层2042、第二金属子层2043以及第二绝缘子层2044。例如，第一金属子层2041与栅极1022同层设置，第一绝缘子层2042与栅绝缘层1014同层设置，第二金属子层2043与第二极板1032同层设置，第二绝缘子层2044与层间绝缘层1015同层设置。由此，这些同层设置的功能层可以采用相同的材料层并通过相同的构图工艺形成，以简化显示基板的制备工艺。
例如，第二阻隔墙204的形式可以为多种。例如，在一些示例中，如图4A和图4B所示，第二阻隔墙204的第一绝缘子层2042和第二绝缘子层2044可以与第一金属子层2041和第二金属子层2043具有相同的图案，从而在图 4B中体现为具有相同的宽度。此时，在制备工艺中，第一绝缘子层2042和第二绝缘子层2044可以通过进一步的刻蚀工艺以形成相应的图案。
例如，在一些实施例中，如图3A所述，第一阻隔墙202还可以包括第二绝缘层结构202A，第一金属层结构202B位于第二绝缘层结构202A上，第二绝缘层结构202A至少与栅绝缘层1014和层间绝缘层1015同层设置。例如，第二绝缘层结构202A包括多个绝缘子层，例如图3A中示出为包括绝缘子层2021和2022。例如，绝缘子层2021与栅绝缘层1014同层设置，绝缘子层2022与层间绝缘层1015同层设置，从而在制备工艺中这些同层设置的功能层可以采用相同的材料层并通过相同的构图工艺形成。第二绝缘层结构202A的设置可增强第一阻隔墙202的阻隔效果，并有利于之后在第一阻隔墙202上例如通过沉积等方式形成的第一无机封装层1051(稍后介绍)可以更好地沿第一阻隔墙202的表面形貌形成。
例如，如图3A所示，第一阻隔墙202的宽度W1可以为2μm-4μm，例如3μm或者3.5μm等。类似地，第二阻隔墙204的宽度也可以为2μm-4μm，例如3μm或者3.5μm等，本公开的实施例对各结构的尺寸不做具体限定，只要可以实现相应的功能即可。
例如，如图2C所示，显示基板100的显示区101还包括平坦化层1016、像素界定层1017以及隔垫物1018。平坦化层1016用于平坦化薄膜晶体管102，像素界定层1017在平坦化层1016远离薄膜晶体管102的一侧，像素界定层1017用于界定多个像素单元。隔垫物1018在像素界定层1017远离平坦层1016的一侧。例如，第一拦截墙203的第一绝缘层结构与平坦化层1016、像素界定层1017和隔垫物1018中的至少一种同层设置。
例如，如图3B所示，第一拦截墙203包括多个绝缘子层，图3B中示出为包括绝缘子层2031和2032。例如，绝缘子层2031和2032与平坦化层1016、像素界定层1017和隔垫物1018中的两种一一对应且同层设置。例如，绝缘子层2031与平坦化层1016同层设置，绝缘子层2032与像素界定层1017同层设置；或者，绝缘子层2031与平坦化层1016同层设置，绝缘子层2032与隔垫物1018同层设置；或者，绝缘子层2031与像素界定层1017同层设置，绝缘子层2032与隔垫物1018同层设置。由此，在制备工艺中这些同层设置的功能层可以采用相同的材料层并通过相同的构图工艺形成。
例如，在一些实施例中，阻隔区201还可以包括与第一拦截墙203相邻 且在第一拦截墙203远离显示区101一侧的第二拦截墙205,第二拦截墙205高于第一拦截墙203。由此，第二拦截墙205与第一拦截墙203一起可以达到双重拦截效果。
例如，在一些示例中，如图3D所示，第二拦截墙205包括多个绝缘子层，图3D中示出为包括绝缘子层2051、2052和2053，例如，绝缘子层2051与平坦化层1016同层设置，绝缘子层2052和像素界定层1017同层设置，绝缘子层2053与隔垫物1018同层设置。由此，在制备工艺中，这些同层设置的功能层可以采用相同的材料层并通过相同的构图工艺形成。在上述设置中，第二拦截墙205高于第一拦截墙203，可以起到充分的拦截功能，并且第二拦截墙205与第一拦截墙203一起可以达到双重拦截效果。
例如，如图2C所示，显示基板100还可以包括设置在衬底基板1011上的阻挡层1012和缓冲层1013，阻挡层1012可以防止水氧等杂质从衬底基板1011渗入到薄膜晶体管102等功能结构中，缓冲层1013可以提供平坦的表面，以便于显示基板其他功能层的设置。阻挡层1012和缓冲层1013可以共同对衬底基板1011上的其他功能结构起到保护作用。
例如，第一阻隔墙202和第二阻隔墙204的结构还可以包括与阻挡层1012和缓冲层1013同层设置的结构。
例如，在一些示例中，如图5A和图5B所示，第一阻隔墙202的第二绝缘层结构202A包括叠层设置的第一部分(包括绝缘子层2021和2022)和第二部分(包括绝缘子层2026和2027)，第一部分至少与栅绝缘层1014和层间绝缘层1015同层设置，第二部分至少与阻挡层1012和缓冲层1013同层设置。由此，在制备工艺中，这些同层设置的功能层可以采用相同的材料层并通过相同的构图工艺形成。
例如，第二绝缘层结构202A的第一部分和第二部分的宽度不同，例如第二部分宽于第一部分，从而第二绝缘层结构202A的纵截面整体呈阶梯状，如图5B所示。
例如，在一些示例中，衬底基板上包括的阻挡层和缓冲层的个数可以为更多个，此时，第二绝缘层结构202A的第二部分可以与更多个阻挡层和缓冲层同层设置。另外，为示出清楚以及简明，阻隔区201(以及后面介绍的弯折区401)中栅绝缘层1014在附图只示出为一层。
例如，如图5A和图5C所示，第二阻隔墙204的第一叠层结构204A也 可以包括两个部分，称为第三部分(包括第一金属子层2041、第一绝缘子层2042、第二金属子层2043以及第二绝缘子层2044)和第四部分(包括绝缘子层2048和2049)，例如，第四部分与第一阻隔墙的第二绝缘层结构202A的第二部分以及阻挡层1012和缓冲层1013同层设置。由此，在制备工艺中，这些同层设置的功能层可以采用相同的材料层并通过相同的构图工艺形成。
例如，第三部分和第四部分的宽度不同，例如第四部分宽于第三部分，从而第一叠层结构204A的纵截面整体呈阶梯状。
当第一阻隔墙202的第二绝缘层结构202A和第二阻隔墙204的第一叠层结构204A的纵截面整体呈阶梯状时，在其上例如通过沉积等方式形成的第一无机封装层1051(稍后介绍)可以更好地沿第一阻隔墙202和第二阻隔墙204的表面形貌形成，而不会出现侧面断裂等不良情况，从而使第一无机封装层1051具有更好的完整性，进而提供更好的封装效果。
需要注意的是，为清楚且简明起见，图4A和图5A仅示出了衬底基板1011上的第一阻隔墙202、第一拦截墙203、第二阻隔墙204以及第二拦截墙205的结构，但是，该显示基板还可以包括如图2B示出的其他结构，具体可参照图2B，在此不再赘述。
例如，如图2C所示，显示区101中每个像素单元包括的发光器件104包括阳极层1041，发光层1042以及阴极层1043。阳极层1041通过平坦层1016中的过孔连接到薄膜晶体管的源极1023。例如，阴极层1043在衬底基板1011上整面形成，并在第一阻隔墙202和第二阻隔墙204处断开。例如，阳极层1041与发光层1042之间以及阴极层1043与发光层1042之间还可以包括有助于发光层1042发光的辅助发光层(图中未示出)，例如包括电子传输层、电子注入层、空穴传输层以及空穴注入层中的一种或多种。辅助发光层例如为有机材料层。例如，辅助发光层也可以在衬底基板1011上整面形成，并在第一阻隔墙202和第二阻隔墙204处断开。
由此，当位于靠近开孔区301一侧的辅助发光层和阴极层1043被水、氧等杂质污染时，由于辅助发光层和阴极层1043被第一阻隔墙202和第二阻隔墙204断开，使得这些污染杂质不会延伸至辅助发光层和阴极层1043的用于发光器件进行发光的部分中。例如，第一阻隔墙202和第二阻隔墙204的顶部上也形成有部分的辅助发光层和阴极层1043，但是这些部分与其他部分相分离。
例如，如图2B和图2C所示，显示基板100还可以包括封装层105，封装层105至少封装第一阻隔墙202，例如，在一些示例中，封装层105同时封装显示区101以及第一阻隔墙202。
例如，封装层105包括在第一阻隔墙202上依次叠层设置的第一无机封装层1051，第一有机封装层1052以及第二无机封装层1053。例如，第一无机封装层1051在显示基板上整面形成，由于第一拦截墙203的拦截作用，第一有机封装层1052以及第二无机封装层1053终止于第一拦截墙203。
例如，在一些实施例中，显示基板100还可以包括第一有机绝缘层206，第一有机绝缘层206至少覆盖第二阻隔墙204。例如，第一有机绝缘层206设置在第二拦截墙205与开孔区301之间。第一有机绝缘层206可以保护第二阻隔墙204，并且也可以起到防止水氧等杂质从开孔区301进入显示区101的功能；另外，第一有机绝缘层206具有一定的高度，当显示基板100上覆盖了偏光片以及盖板等结构后，第一有机绝缘层206可以在开孔区301周围对偏光片以及盖板等结构起到支撑作用，防止偏光片以及盖板等结构在开孔区301产生塌陷等不良现象。
例如，在一些实施例中，为了进一步增强阻隔区201的阻隔效果，如图6所示，阻隔区201还可以包括第三拦截墙207和第二有机绝缘层208。第三拦截墙207在第二拦截墙205远离显示区101的一侧，第二有机绝缘层208在第二拦截墙205与第三拦截墙207之间且覆盖第二阻隔墙204。由此，第三拦截墙207和第二有机绝缘层208提供了进一步的阻隔效果，使得阻隔区201可以充分隔离开孔区301和显示区101，防止水氧等杂质从开孔区301进入显示区101，并防止形成开孔区301时可能形成的裂纹扩展至显示区101。
例如，第三拦截墙207和第二拦截墙205具有相同的结构，并且包括相同的材料。由此，第三拦截墙207和第二拦截墙205可以采用相同的材料层并通过相同的构图工艺形成。例如，第二有机绝缘层208与封装层1015的第一有机封装层1052的材料相同，例如可以通过相同的喷墨打印工艺形成。
例如，在一些实施例中，如图7所示，阻隔区201还包括信号线引线210，信号线引线210电连接显示区101的信号线，信号线引线210在第一阻隔墙202的靠近101显示区的一侧。例如，阻隔区201包括多条信号线引线210，以分别与显示区101中的数据线、扫描线或者电源线等信号线电连接，以实 现开孔区301周围的布线。
例如，在一些实施例中，如图2B所示，显示基板100还可以包括：图像传感器和/或红外传感器501，图像传感器和/或红外传感器501结合于显示基板100的非显示侧，并且在衬底基板1011上的正投影与开孔区301至少部分重叠。由此，图像传感器和/或红外传感器501可以通过开孔区301实现拍照、面部识别、红外感应等多种功能。
例如，在一些示例中，显示基板100可以为柔性显示基板，此时，衬底基板1011可以为聚酰亚胺(PI)等柔性绝缘材料。例如，如图2A所示，显示基板100还可以包括位于显示区101一侧的弯折区401。
例如，图8A示出了一种弯折区401未弯折时的截面示意图，图8B示出了弯折区401未弯折时的另一截面示意图；图8C示出了弯折区401弯折后的截面示意图，该截面示意图例如通过沿图2A中的D-D线剖切得到。
如图8A所示，弯折区401包括设置在衬底基板1011上的绝缘层4011，绝缘层4011包括分别从显示区延伸到弯折区401的阻挡层1012、缓冲层1013、栅绝缘层1014以及层间绝缘层1015等，绝缘层4011上例如具有走线(未示出)以及保护层4013等。例如，显示基板100的非显示侧具有驱动芯片以及电路板等驱动结构，显示区101的驱动电路可通过弯折区401的走线电连接到位于显示基板100非显示侧的驱动结构，从而该驱动结构可以实现对显示基板100显示区101的显示控制。
例如，绝缘层4011中具有凹槽4012，凹槽4012中填充有应力缓和材料，例如，应力缓和材料包括柔性有机材料，可缓和弯折区401在弯折时产生的应力，如图8C所示。例如，绝缘层4011中的凹槽4012可以贯穿绝缘层4011中的一个或者多个绝缘子层，例如图8A中示出凹槽4012贯穿栅绝缘层1014以及层间绝缘层1015，从而可以通过刻蚀栅绝缘层1014以及层间绝缘层1015形成。在图8B中，凹槽4012贯穿阻挡层1012、缓冲层1013、栅绝缘层1014以及层间绝缘层1015，从而可以通过刻蚀阻挡层1012、缓冲层1013栅绝缘层1014以及层间绝缘层1015形成。
例如，凹槽4012可以与第一阻隔墙202的第二绝缘层结构202A以及第二阻隔墙204的第一叠层结构204A中的绝缘子层通过相同的刻蚀工艺形成，该刻蚀工艺可以为一次刻蚀工艺或者两次刻蚀工艺。例如，当绝缘层4011的厚度较厚时，可以采用两次刻蚀工艺分别刻蚀不同的功能层，以提高刻蚀 工艺的精度，并获得所需的刻蚀形貌。
本公开实施例提供的显示基板中，阻隔区201可以充分隔离显示区101与开孔区301，有效防止水氧等杂质从开孔区301进入到显示区101，并且还可以防止形成开孔区301时可能产生的裂纹扩展至显示区101，提高了显示基板的信赖性。
本公开至少一实施例还提供一种显示基板的制备方法，该制备方法可以制备上述显示基板100。该制备方法包括：形成显示区、阻隔区和开孔区。显示区和阻隔区围绕开孔区，阻隔区位于显示区和开孔区之间。形成阻隔区包括形成从显示区到开孔区方向依次排列的第一阻隔墙、第一拦截墙以及第二阻隔墙，第一阻隔墙、第一拦截墙以及第二阻隔墙围绕开孔区。第一阻隔墙包括第一金属层结构，第一金属层结构的围绕开孔区的至少一个侧面具有凹口。第一拦截墙包括第一绝缘层结构。第二阻隔墙包括第二金属层结构和第一叠层结构，第一叠层结构位于第一叠层结构上，第二金属层结构的围绕开孔区的至少一个侧面具有凹口，第一叠层结构包括金属层和绝缘层的叠层。
下面，以形成图2A-图2C所示的显示基板100为例，对本公开实施例提供的显示基板的制备方法进行介绍。
首先，提供衬底基板1011，例如，当显示基板100为柔性显示基板时，所提供的衬底基板1011可以为聚酰亚胺(PI)等柔性基板，当显示基板为刚性基板时，衬底基板1011可以为玻璃、石英等刚性基板。本实施例以形成柔性显示基板为例进行介绍，此时，该柔性显示基板例如具有弯折区401。
如图9A-图9C所示，首先在衬底基板1011上形成用于显示区101、阻隔区201以及弯折区401的功能层，并为开孔区301预留位置，以便于显示区101、阻隔区201以及弯折区401的功能层形成完成后，通过例如冲压或者切割等方式形成开孔区301。
例如，可以通过沉积等方法在衬底基板1011上依次形成阻挡层1012和缓冲层1013。例如，阻挡层1012和缓冲层1013可以整面形成在衬底基板1011上。例如，阻挡层1012可以采用氧化硅、氮化硅、或者氮氧化硅等无机绝缘材料，缓冲层1013也可以采用氧化硅、氮化硅、或者氮氧化硅等无机绝缘材料。
例如，在阻挡层1012和缓冲层1013形成之后，如图9A所示，在显示 区101形成薄膜晶体管102以及存储电容103等结构，如图9B所示，在阻隔区201形成第二阻隔墙204的第一叠层结构204A，如图9C所示，在弯折区401形成弯折区绝缘层4011。
例如，如图9A-图9C所示，采用构图工艺在衬底基板1011上形成有源层1021；在有源层1021上通过沉积等方式形成第一栅绝缘层1014A；在第一栅绝缘层1014A上采用构图工艺同时形成栅极1022、第一极板1031以及第一金属子层2041；在栅极1022、第一极板1031以及第一金属子层2041上通过沉积等方式形成第二栅绝缘层1014B；采用构图工艺同时形成第二极板1032以及第二金属子2043；在第二极板1032以及第二金属子2043上采用沉积等方式形成层间绝缘层1015；然后，刻蚀栅绝缘层1014以及层间绝缘层1015以形成暴露有源层1021的过孔。例如，一次构图工艺包括光刻胶的形成、曝光、显影以及刻蚀等工艺。
此时，第二阻隔墙204的第一金属子层2041与栅极1022同层形成，第一绝缘子层2042与栅绝缘层1014同层形成，第二金属子层2043与第二极板1032同层形成，第二绝缘子层2044与层间绝缘层1015同层形成。由此简化了显示基板的制备工艺。
例如，栅极211、第一极板1031以及第一金属子层2041的材料包括铝、钛、钴等金属或者合金材料。在制备时，首先采用溅射或者蒸镀等方式形成一层栅极材料层，然后对栅极材料层进行构图工艺，以形成图案化的栅极211、第一极板1031以及第一金属子层2041。同层形成的其他结构的形成方式与此类似，因此不再赘述。
例如，有源层1021可以采用多晶硅和金属氧化物等材料，栅绝缘层1014可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，第二极板1032以及第二金属子层2043可以采用铝、钛、钴等金属或者合金材料，层间绝缘层1015可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。本公开的实施例对各功能层的材料不做限定，各功能层的材料并不局限于上述示例。
例如，如图10A和图10B所示，可以采用一次刻蚀工艺刻蚀位于阻隔区201以及位于弯折区401的栅绝缘层1014和层间绝缘层1015，从而形成第一阻隔墙202的第二绝缘层结构202A，并同时形成位于弯折区401的凹槽4012。由此，第二绝缘层结构202A包括与栅绝缘层1014同层形成的子绝缘层2021和与层间绝缘层1015同层形成的子绝缘层2022。例如，弯折区 401的凹槽4012形成后，可以在凹槽4012中填充应力缓和材料，例如聚酰亚胺、环氧树脂等有机绝缘材料。
此时，第二绝缘层结构202A与栅绝缘层1014和层间绝缘层1015同层形成，并且第二绝缘层结构202A还与位于弯折区401的绝缘层4011通过相同的刻蚀工艺形成。由此简化了显示基板的制备工艺。
例如，在另一实施例中，显示基板的制备方法还可以形成如图5B示出的第一阻隔墙202和如图5C示出的第二阻隔墙204。此时，可以通过第一刻蚀工艺同时刻蚀位于弯折区401和阻隔区201的栅绝缘层1014和层间绝缘层1015，并通过第二刻蚀工艺同时刻蚀位于弯折区401和阻隔区201的阻挡层1012和缓冲层1013，以形成贯穿阻挡层1012、缓冲层1013、栅绝缘层1014和层间绝缘层1015的凹槽4012(例如图10C示出的情形)，并同时形成包括第一部分(包括绝缘子层2021和2022)和第二部分(包括绝缘子层2026和2027)的第二绝缘层结构202A以及包括第三部分(包括第一金属子层2041、第一绝缘子层2042、第二金属子层2043以及第二绝缘子层2044)和第四部分(包括绝缘子层2048和2049)的第一叠层结构204A。
由此，第二绝缘层结构202A的第一部分、第一叠层结构204A的第三部分中的绝缘子层与栅绝缘层1014和层间绝缘层1015同层形成，并与弯折区401的凹槽4012的一部分通过相同的刻蚀工艺(第一刻蚀工艺)刻蚀形成；第二绝缘层结构202A的第二部分、第一叠层结构204A的第四部分与阻挡层1012和缓冲层1013同层形成，并与弯折区401的凹槽4012的另一部分通过相同的刻蚀工艺(第二刻蚀工艺)刻蚀形成。由于阻挡层1012、缓冲层1013、栅绝缘层1014和层间绝缘层1015的总体厚度较厚，通过两次刻蚀工艺分别刻蚀其中的一部分有利于刻蚀工艺的顺利进行，并有利于保证最终的刻蚀形貌。
如图10A所示，在上述刻蚀工艺中，还可以同时刻蚀阻挡层1012、缓冲层1013、栅绝缘层1014和层间绝缘层1015靠近开孔区301的部分，(即图10A中的左侧虚线框示出的部分)。由于阻挡层1012、缓冲层1013、栅绝缘层1014和层间绝缘层1015中的部分或者全部采用无机绝缘材料制成，由于无机绝缘材料具有脆性，在通过例如冲压或者切割等方式形成开孔区301时容易形成裂纹，因此将阻挡层1012、缓冲层1013、栅绝缘层1014和层间绝缘层1015靠近开孔区301的部分去除，可以避免形成开孔区301时在这 些层中产生裂纹。
如图11A和图11B所示，在层间绝缘层1015中的过孔形成后，形成源极1023和漏极1024以及第一阻隔墙202的第一金属层结构202B和第二阻隔墙204的第二金属层结构204B。
例如，源极1023和漏极1024可以形成为多层金属结构，例如三层金属层结构。例如，在一个示例中，可以采用溅射或者蒸镀等方式依次形成钛材料层、铝材料层以及钛材料层，然后采用同一次构图工艺对三个材料层进行构图，从而形成构成源极1023和漏极1024的钛/铝/钛3三层金属结构，同时形成侧面齐平的初始第一金属层结构和初始第二金属层结构。然后，通过一次刻蚀工艺刻蚀侧面齐平的初始第一金属层结构和初始第二金属层结构，以形成侧面具有凹口的第一金属层结构202B和第二金属层结构204B。例如，该刻蚀工艺使用的刻蚀液仅对第一金属层结构202B和第二金属层结构204B的中间层具有刻蚀效果或者对中间层的刻蚀速率大于对其他层的刻蚀速率，从而该刻蚀工艺可以形成第一金属层结构202B和第二金属层结构204B的凹口。
由此，源极1023和漏极1024以及第一阻隔墙202的第一金属层结构202B和第二阻隔墙204的第二金属层结构204B同层形成，简化了显示基板的制备工艺。
如图12A和图12B所示，在薄膜晶体管102以及存储电容103的各膜层形成完成后，依次形成平坦化层1016、阳极层1041、像素界定层1017和隔垫物1018，并同时形成第一拦截墙203和第二拦截墙205。
例如，通过构图工艺同层形成平坦化层1016、第一拦截墙203的绝缘子层2031和第二拦截墙205绝缘子层2051。例如，平坦化层1016、第一拦截墙203的绝缘子层2031和第二拦截墙205绝缘子层2051材料的可以采用聚酰亚胺、环氧树脂等有机绝缘材料。形成的平坦化层1016中具有过孔，以便之后形成的阳极层1041通过该过孔与源极1023电连接。
例如，在显示区101的平坦化层1016上采用构图工艺形成阳极层1041，阳极层1041通过平坦化层1016中的过孔与源极1023电连接。例如，阳极层1041的材料包括ITO、IZO等金属氧化物或者Ag、Al、Mo等金属或其合金。
例如，通过构图工艺同层形成像素界定层1017、第一拦截墙203的绝缘 子层2032和第二拦截墙205的绝缘子层2052。像素界定层1017中具有暴露阳极层1041的开口，以便之后形成发光器件的发光层1042以及阴极层1043等结构。例如，像素界定层1017、第一拦截墙203的绝缘子层2032和第二拦截墙205的绝缘子层2052的材料可以包括聚酰亚胺、环氧树脂等有机绝缘材料。
例如，通过构图工艺同层形成隔垫物1018和第二拦截墙205的绝缘子层2053。隔垫物1018和第二拦截墙205的绝缘子层2053的材料包括聚酰亚胺、环氧树脂等有机绝缘材料。此时，第二拦截墙205的子绝缘层数量多于第一拦截墙203的子绝缘层数量，因此第二拦截墙205高于第一拦截墙203。
在上述示例中，第一拦截墙203与平坦化层1016、像素界定层1017同层形成，第二拦截墙205与平坦化层1016、像素界定层1017和隔垫物108同层形成，简化了显示基板的制备工艺。例如，在其他示例中，第二拦截墙205也可以与平坦化层1016和隔垫物108同层形成，或者与像素界定层1017和隔垫物108同层形成，本公开的实施例对此不做限定。
例如，如图13A和图13B所示，可以通过喷墨打印或者蒸镀等方式在像素界定层1017的开口中形成发光层1042，然后形成阴极层1043。例如，发光层1042与阳极层1041之间或者发光层1042与阴极层1043之间还可以形成辅助发光层(未示出)，辅助发光层例如包括电子注入层、电子传输层、空穴注入层以及空穴传输层中的一种或多种。阴极层1043和辅助发光层例如在显示基板上整面形成，并且在第一阻隔墙202以及第二阻隔墙204处断开。
例如，发光层1042的材料和辅助发光层的材料为有机材料，发光层1042的材料可根据需求选择可发出某一颜色光(例如红光、蓝光或者绿光等)的发光材料。阴极层1043的材料可以包括Mg、Ca、Li或Al等金属或其合金，或者IZO、ZTO等金属氧化物，又或者PEDOT/PSS(聚3，4-乙烯二氧噻吩/聚苯乙烯磺酸盐)等具有导电性能有机材料。
此时，当阴极层1043和辅助发光层的靠近开孔区301的部分被污染时，由于阴极层1043和辅助发光层被第一阻隔墙202以及第二阻隔墙204断开，水、氧等杂质不会扩散、延伸至阴极层1043和辅助发光层的用于发光的部分。
如图14A-图14B所示，发光器件104形成后，可以在显示区201以及 第一阻隔墙202上形成封装层105。例如，形成封装层105包括在第一阻隔墙202上以及显示区201中依次形成第一无机封装层1051，第一有机封装层1052以及第二无机封装层1053。例如，第一无机封装层1051和第二无机封装层1053采用沉积等方式形成。第一有机封装层1052采用喷墨打印的方式形成。如图14B所示，由于第一拦截墙203的拦截作用，第一有机封装层1052终止于第一拦截墙203。
例如，在一些实施例中，由于喷墨打印工艺中，喷墨打印的范围难以控制等原因，在喷墨打印形成第一有机封装层1052时可能会使打印墨水流到第一拦截墙203外侧，甚至还流到第二拦截墙205外侧，使得第一有机封装层1052延伸至开孔区301，成为水氧传输的通道，使得显示区101被污染。此时，可以采用打印内缩控制并边缘补充打印的方式形成第一有机封装层1052。
例如，如图14B所示，可以将喷墨打印的边界内缩到D点，D点在第一拦截墙203靠近显示区101的一侧，例如D点与第一拦截墙203的距离选择为50μm-70μm，例如60μm，此时，先以D点为打印边界进行喷墨打印。然后，再对D点与第一拦截墙203之间的范围进行边缘补充打印。由此喷墨打印过程更容易控制，并容易形成理想的第一有机封装层1052。
例如，第一无机封装层1051和第二无机封装层1053可以采用氮化硅、氧化硅、氮氧化硅等无机材料形成，第一有机封装层1052可以采用聚酰亚胺(PI)、环氧树脂等有机材料形成。由此，第一无机封装层1051，第一有机封装层1052以及第二无机封装层1053形成为复合封装层，该复合封装层可以对显示区201的功能结构以及第一阻隔墙202等结构形成多重保护，具有更好的封装效果。
例如，如图14B所示，还可以在第二阻隔墙204上通过涂覆等方式形成第一有机绝缘层206，第一有机绝缘层206至少覆盖第二阻隔墙204。例如，第一有机绝缘层206形成在第二拦截墙205与开孔区301之间。第一有机绝缘层206可以保护第二阻隔墙204，并且第一有机绝缘层20也可以起到防止水氧等杂质从开孔区301进入显示区101的功能；另外，第一有机绝缘层206具有一定的高度，可以对之后形成在显示基板100上的偏光片以及盖板等结构起到支撑作用，防止偏光片以及盖板等结构在开孔区301产生塌陷等不良现象。
例如，如图14C所示，弯折区401的绝缘层4011上也形成有保护层4013，该保护层4013例如可以与第一有机绝缘层206同层形成，以简化制备工艺。
本公开的一些实施例中，根据需要，显示区101、阻隔区201以及弯折区401中还可以形成其他必要的功能膜层，这些膜层可采用常规方法形成，在此不再赘述。
例如，在显示区101形成完成后，可以采用激光切割或者机械冲压的方式对形成开孔区301。开孔区301贯穿衬底基板1011，开孔区301处可以安装图像传感器、红外传感器等结构，并与例如中央处理器等信号连接。例如，该图像传感器或者红外传感器等结构可以设置在衬底基板1011的远离发光器件的一侧(即显示基板的非显示侧)，并可通过开孔区301实现拍照、面部识别、红外感应等多种功能。
例如，在开孔区301形成后，还可以在显示基板上形成偏光片、盖板等结构，本公开的实施例对此不做限定。
例如，在一些实施例中，第一阻隔墙202、第一拦截墙203、第二阻隔墙204、第二拦截墙205等可以形成为多个，从而使阻隔区201具有更好的阻隔效果。本公开的实施例对第一阻隔墙202、第一拦截墙203、第二阻隔墙204、第二拦截墙205等结构的个数不做限定。
例如，本公开实施例提供的显示基板的制备方法还可以形成如图6所示的显示基板，此时，形成阻隔区201还包括形成第三拦截墙207和第二有机绝缘层208。第三拦截墙207形成在第二拦截墙205远离显示区101的一侧，第二有机绝缘层208形成在第二拦截墙205与第三拦截墙207之间且覆盖第二阻隔墙204。
例如，第三拦截墙207与第二拦截墙205同层形成，并且具有相同的结构，第三拦截墙207的具体形成方式可参见上述实施例描述的第二拦截墙205的形成方式，在此不再赘述。
例如。可以通过喷墨打印的方式形成第二有机绝缘层208，例如，第二有机绝缘层208与第一有机封装层1052在相同的喷墨打印工艺中形成，以简化显示基板的制备工艺。
本公开实施例提供的制备方法形成的显示基板包括阻隔区，该阻隔区包括多个阻隔墙以及阻挡墙，可以充分隔离显示区与开孔区，并且避免形成开孔区时可能形成的裂纹扩展至显示区，由此提高了显示基板的信赖性。
本公开实施例提供的显示基板或者利用本公开实施例提供的制备方法得到的显示基板可以用于显示装置中，该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不做限定。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (33)

  1. 一种显示基板，包括显示区、阻隔区和开孔区，所述显示区和所述阻隔区围绕所述开孔区，所述阻隔区位于所述显示区和所述开孔区之间，其中，所述阻隔区包括从所述显示区到所述开孔区方向依次排列的第一阻隔墙、第一拦截墙以及第二阻隔墙，所述第一阻隔墙、第一拦截墙以及第二阻隔墙围绕所述开孔区；
    所述第一阻隔墙包括第一金属层结构，所述第一金属层结构的围绕所述开孔区的至少一个侧面具有凹口；
    所述第一拦截墙包括第一绝缘层结构；
    所述第二阻隔墙包括第二金属层结构和第一叠层结构，所述第二金属层结构位于所述第一叠层结构上，所述第二金属层结构的围绕所述开孔区的至少一个侧面具有凹口，所述第一叠层结构包括具有金属层和绝缘层的叠层。
  2. 根据权利要求1所述的显示基板，其中，所述第二金属层结构与所述第一金属层结构具有相同的结构，并且包括相同的材料。
  3. 根据权利要求1或2所述的显示基板，还包括衬底基板，其中，所述显示区包括薄膜晶体管和存储电容，所述薄膜晶体管包括依次设置在所述衬底基板上的栅极、栅绝缘层，层间绝缘层和源漏电极；所述存储电容包括第一极板和第二极板，所述第一极板与所述栅极同层设置，所述第二极板在所述栅绝缘层和所述层间绝缘层之间；
    所述第一金属层结构、所述第二金属层结构与所述源漏电极同层设置。
  4. 根据权利要求3所述的显示基板，其中，所述第一叠层结构的叠层包括依次设置在所述衬底基板上的第一金属子层、第一绝缘子层、第二金属子层以及第二绝缘子层，
    所述第一金属子层与所述栅极同层设置，所述第一绝缘子层与所述栅绝缘层同层设置，所述第二金属子层与所述第二极板同层设置，所述第二绝缘子层与所述层间绝缘层同层设置。
  5. 根据权利要求3或4所述的显示基板，其中，所述第一阻隔墙还包括第二绝缘层结构，所述第一金属层结构位于所述第二绝缘层结构上，
    所述第二绝缘层结构至少与所述栅绝缘层和所述层间绝缘层同层设置。
  6. 根据权利要求5所述的显示基板，还包括设置在所述衬底基板上的 阻挡层和缓冲层，
    其中，所述第二绝缘层结构包括叠层设置的第一部分和第二部分，所述第一部分至少与所述栅绝缘层和所述层间绝缘层同层设置，所述第二部分至少与所述阻挡层和所述缓冲层同层设置。
  7. 根据权利要求6所述的显示基板，其中，所述第二绝缘层结构的纵截面整体呈阶梯状。
  8. 根据权利要求3-7任一所述的显示基板，其中，所述显示区还包括：
    用于平坦化所述薄膜晶体管的平坦化层，
    在所述平坦化层远离所述薄膜晶体管一侧的像素界定层，所述像素界定层用于界定多个像素单元，以及
    在所述像素界定层远离所述平坦层一侧的隔垫物，
    所述第一拦截墙的所述第一绝缘层结构与所述平坦化层、所述像素界定层和所述隔垫物中的至少一种同层设置。
  9. 根据权利要求1-8任一所述的显示基板，还包括封装层，其中，所述封装层至少封装所述第一阻隔墙。
  10. 根据权利要求9所述的显示基板，其中，所述封装层包括在所述第一阻隔墙上依次叠层设置的第一无机封装层，第一有机封装层以及第二无机封装层。
  11. 根据权利要求1-10任一所述的显示基板，还包括第一有机绝缘层，其中，所述第一有机绝缘层至少覆盖所述第二阻隔墙。
  12. 根据权利要求8所述的显示基板，其中，所述阻隔区还包括与所述第一拦截墙相邻且在所述第一拦截墙远离所述显示区一侧的第二拦截墙,
    所述第二拦截墙高于所述第一拦截墙。
  13. 根据权利要求12所述的显示基板，其中，所述第二拦截墙与所述平坦化层、所述像素界定层和所述隔垫物同层设置。
  14. 根据权利要求12或13所述的显示基板，其中，所述阻隔区还包括第三拦截墙和第二有机绝缘层，所述第三拦截墙在所述第二拦截墙远离所述显示区的一侧，所述第二有机绝缘层在所述第二拦截墙与所述第三拦截墙之间且覆盖所述第二阻隔墙。
  15. 根据权利要求13所述的显示基板，其中，所述第三拦截墙和所述第二拦截墙具有相同的结构，并且包括相同的材料。
  16. 根据权利要求1-15任一所述的显示基板，其中，所述阻隔区还包括信号线引线，所述信号线引线电连接所述显示区的信号线，
    所述信号线引线在所述第一阻隔墙的靠近所述显示区的一侧。
  17. 根据权利要求1-16任一所述的显示基板，还包括：图像传感器和/或红外传感器，
    其中，所述图像传感器和/或红外传感器结合于所述衬底基板，并且在所述衬底基板上的正投影与所述开孔区至少部分重叠。
  18. 一种显示基板的制备方法，包括：
    形成显示区、阻隔区和开孔区，其中，所述显示区和所述阻隔区围绕所述开孔区，所述阻隔区位于所述显示区和所述开孔区之间；
    其中，形成所述阻隔区包括形成从所述显示区到所述开孔区方向依次排列的第一阻隔墙、第一拦截墙以及第二阻隔墙，所述第一阻隔墙、第一拦截墙以及第二阻隔墙围绕所述开孔区；
    所述第一阻隔墙包括第一金属层结构，所述第一金属层结构的围绕所述开孔区的至少一个侧面具有凹口；
    所述第一拦截墙包括第一绝缘层结构；
    所述第二阻隔墙包括第二金属层结构和第一叠层结构，所述第一叠层结构位于所述第一叠层结构上，所述第二金属层结构的围绕所述开孔区的至少一个侧面具有凹口，所述第一叠层结构包括金属层和绝缘层的叠层。
  19. 根据权利要求18所述的显示基板的制备方法，其中，所述第二金属层结构与所述第一金属层结构采用相同的材料并通过相同的构图工艺形成。
  20. 根据权利要求18或19所述的显示基板的制备方法，还包括：提供衬底基板；
    其中，形成所述显示区包括在所述衬底基板上形成薄膜晶体管和存储电容，形成所述薄膜晶体管包括在所述衬底基板上依次形成栅极、栅绝缘层，层间绝缘层和源漏电极；形成所述存储电容包括形成第一极板和第二极板，所述第一极板与所述栅极同层形成，所述第二极板形成在所述栅绝缘层和所述层间绝缘层之间；
    所述第一金属层结构、所述第二金属层结构与所述源漏电极同层形成。
  21. 根据权利要求20所述的显示基板的制备方法，其中，形成所述第 一叠层结构包括在所述衬底基板上依次形成第一金属子层、第一绝缘子层、第二金属子层以及第二绝缘子层，以得到所述第一叠层结构的叠层，
    其中，所述第一金属子层与所述栅极同层形成，所述第一绝缘子层与所述栅绝缘层同层形成，所述第二金属子层与所述第二极板同层形成，所述第二绝缘子层与所述层间绝缘层同层形成。
  22. 根据权利要求20或21所述的显示基板的制备方法，其中，所述第一阻隔墙还包括第二绝缘层结构，所述第一金属层结构形成在所述第二绝缘层结构上，
    所述第二绝缘层结构至少与所述栅绝缘层和所述层间绝缘层同层形成。
  23. 根据权利要求22所述的显示基板的制备方法，还包括：在所述衬底基板上形成阻挡层和缓冲层，
    所述第二绝缘层结构包括叠层设置的第一部分和第二部分，所述第一部分至少与所述栅绝缘层和所述层间绝缘层同层形成，所述第二部分至少与所述阻挡层和所述缓冲层同层形成。
  24. 根据权利要求22或23所述的显示基板的制备方法，还包括形成位于所述显示区一侧的弯折区，其中，形成所述弯折区包括刻蚀位于所述弯折区的绝缘层以形成凹槽，
    所述凹槽与所述第二绝缘层结构通过相同的刻蚀工艺形成。
  25. 根据权利要求24所述的显示基板的制备方法，其中，位于所述弯折区的绝缘层包括从所述显示区延伸到所述弯折区的阻挡层、缓冲层、栅绝缘层和层间绝缘层，
    当所述第二绝缘层结构包括叠层设置的第一部分和第二部分时，通过第一刻蚀工艺同时刻蚀位于所述弯折区和所述阻隔区的所述栅绝缘层和所述层间绝缘层，并通过第二刻蚀工艺同时刻蚀位于所述弯折区和所述阻隔区的所述阻挡层和所述缓冲层，以形成所述凹槽和所述第二绝缘层结构。
  26. 根据权利要求20-25任一所述的显示基板的制备方法，其中，形成所述显示区还包括：
    形成用于平坦化所述薄膜晶体管的平坦化层，
    在所述平坦化层远离所述薄膜晶体管的一侧形成像素界定层，所述像素界定层用于界定多个像素单元，以及
    在所述像素界定层远离所述平坦层的一侧形成隔垫物，
    其中，所述第一拦截墙的所述第一绝缘层结构与所述平坦化层、所述像素界定层和所述隔垫物中的至少一种同层形成。
  27. 根据权利要求18-26任一所述的显示基板的制备方法，还包括形成至少封装所述第一阻隔墙的封装层，形成所述封装层包括在所述第一阻隔墙上依次形成第一无机封装层，第一有机封装层以及第二无机封装层；
    其中，所述第一有机封装层采用喷墨打印的方式形成。
  28. 根据权利要求18-27任一所述的显示基板的制备方法，还包括在所述第二阻隔墙上形成第一有机绝缘层，所述第一有机绝缘层至少覆盖所述第二阻隔墙。
  29. 根据权利要求26所述的显示基板的制备方法，其中，形成所述阻隔区还包括形成与所述第一拦截墙相邻且在所述第一拦截墙远离所述显示区一侧的第二拦截墙,
    所述第二拦截墙高于所述第一拦截墙。
  30. 根据权利要求29所述的显示基板的制备方法，其中，所述第二拦截墙与所述平坦化层、所述像素界定层和所述隔垫物同层形成。
  31. 根据权利要求29或30所述的显示基板的制备方法，其中，形成所述阻隔区还包括形成第三拦截墙和第二有机绝缘层，
    所述第三拦截墙形成在所述第二拦截墙远离所述显示区的一侧，所述第二有机绝缘层形成在所述第二拦截墙与所述第三拦截墙之间且覆盖所述第二阻隔墙。
  32. 根据权利要求31所述的显示基板的制备方法，其中，通过喷墨打印的方式形成所述第二有机绝缘层。
  33. 根据权利要求32所述的显示基板的制备方法，其中，所述第二有机绝缘层与覆盖所述第一阻隔墙的第一有机封装层在相同的喷墨打印工艺中形成。
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WO2023093252A1 (zh) * 2021-11-25 2023-06-01 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置

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