WO2022057508A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022057508A1
WO2022057508A1 PCT/CN2021/111224 CN2021111224W WO2022057508A1 WO 2022057508 A1 WO2022057508 A1 WO 2022057508A1 CN 2021111224 W CN2021111224 W CN 2021111224W WO 2022057508 A1 WO2022057508 A1 WO 2022057508A1
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Prior art keywords
layer
sub
display
crack detection
display substrate
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PCT/CN2021/111224
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English (en)
French (fr)
Inventor
韩林宏
张毅
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/795,066 priority Critical patent/US20230146897A1/en
Publication of WO2022057508A1 publication Critical patent/WO2022057508A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and more particularly, to a display substrate and a display device.
  • the display screen of the display device is developing in the direction of large screen and full screen.
  • a display device such as a mobile phone, a tablet computer, etc.
  • the camera device can be combined with the display area of the display screen, and a hole is drilled in the display area to reserve a position for the camera device. to maximize the display area of the display.
  • cracks are likely to occur at the punched positions, which may cause signal breakage of the display panel, package failure, etc., and finally cause abnormal display.
  • PCD Panel Crack Detection
  • At least one embodiment of the present disclosure provides a display substrate, including:
  • a base substrate comprising a display area, a peripheral area and a blocking area, the peripheral area surrounding the display area, and the display area surrounding the blocking area;
  • a through hole located in the blocking area, the center of the display substrate and the center of the through hole do not overlap; a plurality of sub-pixels located in the display area;
  • a plurality of signal lines located in the display area, the peripheral area and the blocking area, and electrically connected to the plurality of sub-pixels, the plurality of signal lines including a first signal line;
  • a shift register circuit located in the peripheral area and electrically connected to the plurality of signal lines;
  • At least one loop of crack detection lines is located in the blocking area and surrounds the through holes, the at least one loop of crack detection lines is electrically connected to the first signal line, and the first signal line is connected to the plurality of sub-pixels At least one of the sub-pixels is electrically connected.
  • the shift register circuit includes a plurality of shift register units, and the first signal line is connected to the plurality of shift register units. one of the electrical connections.
  • the shift register circuit is a gate shift register circuit, and the first signal line is a scan signal line;
  • the shift register circuit is a light emission control shift register circuit, and the first signal line is a light emission control signal line.
  • the display substrate provided by at least one embodiment of the present disclosure further includes at least one first overlapping structure, wherein the first signal line and the at least one loop of crack detection lines pass through the at least one first overlapping structure.
  • a first lap structure is electrically connected, and the at least one first lap structure and the at least one ring of crack detection lines are located at different layers and are electrically connected through via holes.
  • the number of the at least one first overlapping structure is two
  • the first signal line includes a first sub-line and a second Two sub-wires
  • the two first overlapping structures are respectively electrically connected to the first sub-wire and the first ends of the at least one loop of crack detection wires, and the second sub-wire and the at least one loop of the crack detection wire respectively.
  • the second end of a loop of crack detection wire is the first end of a loop of crack detection wire.
  • the number of the at least one loop of crack detection lines is multiple loops, and the multiple loops of crack detection lines are continuous lines and surround the through hole.
  • the display substrate provided by at least one embodiment of the present disclosure further includes at least one second overlapping structure, wherein the at least one second overlapping structure is passed between two adjacent crack detection lines.
  • the at least one second overlapping structure and the two adjacent loops of crack detection lines are located at different layers and are electrically connected through via holes.
  • the number of the at least one circle of crack detection lines is four circles, and along the radial direction close to the center of the through hole, each of A detection sub-line, a second detection sub-line, a third detection sub-line and a fourth detection sub-line, the first detection sub-line and the second detection sub-line are connected by a second lap
  • the structure is electrically connected, and any two of the second detection sub-wire, the third detection sub-wire and the fourth detection sub-wire are electrically connected through the two second overlapping structures.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a first multilayer insulating layer located on one side of the base substrate, wherein the at least one loop of crack detection lines is located on the The first multi-layer insulating layer is away from the side of the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a first organic functional layer located on a side of the at least one crack detection line away from the base substrate, and a first organic functional layer located on the first crack detection line.
  • a second organic functional layer on the side of the multi-layer insulating layer away from the substrate, the first organic functional layer and the second organic functional layer are intermittently arranged, and the first organic functional layer is on the substrate.
  • the orthographic projection of the base substrate and the orthographic projection of the second organic functional layer on the base substrate do not overlap.
  • the at least one loop of crack detection lines includes first sub-substrates sequentially located on a side of the multilayer insulating layer away from the base substrate. layer, a second sublayer and a third sublayer, the orthographic projection of the second sublayer on the base substrate is located in the orthographic projection of the first sublayer and the third sublayer on the base substrate Inside.
  • At least one embodiment of the present disclosure provides a display substrate, wherein the at least one ring of crack detection lines has a notch around at least one side surface of the through hole.
  • At least one embodiment of the present disclosure provides a display substrate, wherein at least one of the plurality of sub-pixels includes:
  • Thin film transistors including:
  • a source electrode and a drain electrode located on the side of the second insulating layer away from the base substrate and electrically connected to the active layer
  • Storage capacitors including:
  • Light-emitting devices including:
  • an anode layer located on the side of the source electrode and the drain electrode away from the base substrate
  • an organic functional layer located on the side of the anode away from the base substrate, and
  • the cathode layer is located on the side of the organic functional layer away from the base substrate.
  • the at least one crack detection line is located in the same layer as the source electrode or the drain electrode;
  • the first multi-layer insulating layer includes at least the first insulating layer and the second insulating layer;
  • the second overlapping structure and the first overlapping structure are located on the same layer as the second electrode plate.
  • the organic functional layer is made of the same material as the first organic functional layer and the second organic functional layer.
  • the display substrate provided in at least one embodiment of the present disclosure further includes at least one groove, the at least one groove penetrating the first insulating layer and at least part of the second insulating layer , the orthographic projection of the groove on the base substrate does not overlap with the orthographic projection of the at least one circle of crack detection lines on the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes at least one circle of intercepting walls located in a direction in which the at least one circle of crack detection lines is close to the through holes, the at least one circle of interception walls An organic encapsulation layer that is configured to block the encapsulation of the plurality of sub-pixels.
  • the at least one circle of intercepting walls includes a first intercepting wall and a second intercepting wall, and the first intercepting wall is located at the second intercepting wall.
  • One side of the intercepting wall far away from the through hole, and the maximum height of the first intercepting wall in the direction perpendicular to the base substrate is smaller than the maximum height of the second intercepting wall in the direction perpendicular to the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes at least one ring of crack blocking walls on one side of the at least one ring of blocking walls close to the through holes.
  • the display substrate provided by at least one embodiment of the present disclosure further includes an encapsulation layer, wherein the encapsulation layer at least encapsulates the barrier wall, and the encapsulation layer includes crack detection in the at least one circle
  • a first inorganic encapsulation layer, a first organic encapsulation layer and a second inorganic encapsulation layer are stacked in sequence on the line.
  • the display substrate provided by at least one embodiment of the present disclosure further includes an image sensor and/or an infrared sensor, wherein the image sensor and/or the infrared sensor are combined with the base substrate, and are The orthographic projection on the base substrate at least partially overlaps the through hole.
  • An embodiment of the present disclosure also provides a display device, including the display substrate of the above-mentioned embodiment.
  • Embodiments of the present disclosure further provide a method for manufacturing a display substrate, including: forming a base substrate, including a display area, a peripheral area, and a blocking area, the peripheral area surrounding the display area, and the display area surrounding the blocking area a through hole, located in the blocking area, the center of the display substrate and the center of the through hole do not overlap; a plurality of sub-pixels, located in the display area; a plurality of signal lines, located in the display area, the peripheral area and a blocking area, and electrically connected to the plurality of sub-pixels, the plurality of signal lines including a first signal line; a shift register circuit located in the peripheral area and electrically connected to the plurality of signal lines; at least one loop of crack detection a line located in the blocking region and surrounding the through hole, the at least one ring of crack detection lines is electrically connected to the first signal line, and the first signal line is connected to at least one sub-pixel in the plurality of sub-pixels Pixel electrical connections.
  • 1A is a schematic plan view of a display substrate
  • 1B is a schematic plan view of a display substrate
  • FIG. 2A is an enlarged schematic view of the display substrate isolation region 201 in FIG. 1B ;
  • FIG. 2B is a schematic cross-sectional view of the display substrate in FIG. 1B and FIG. 2A along line A-A;
  • FIG. 2C is a schematic cross-sectional view of the display substrate in FIG. 1B along line B-B;
  • FIG. 3A is an enlarged schematic view of the display substrate blocking region 201 in FIG. 1B according to at least one embodiment of the present disclosure
  • FIG. 3B is a schematic cross-sectional view of the display substrate in FIG. 3A along line C-C;
  • FIG. 4A is an enlarged schematic view of the display substrate blocking region 201 in FIG. 1B according to at least one embodiment of the present disclosure
  • FIG. 4B is a schematic cross-sectional view of the display substrate in FIG. 4A along line D-D;
  • FIG. 4C is a schematic cross-sectional view of the display substrate in FIG. 4A along line D-D according to at least one embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a connection method of a crack detection line of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a connection method of a crack detection line of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 7A is a schematic cross-sectional view of a barrier wall in a display substrate according to at least one embodiment of the present disclosure
  • FIG. 7B is a schematic cross-sectional view of a first intercepting wall in a display substrate according to at least one embodiment of the present disclosure
  • FIG. 7C is a schematic cross-sectional view of a crack blocking wall in a display substrate according to at least one embodiment of the present disclosure
  • 7D is a schematic cross-sectional view of a second intercepting wall in a display substrate according to at least one embodiment of the present disclosure
  • FIG. 8A is a partial cross-sectional schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8B is another schematic cross-sectional view of a crack blocking wall in a display substrate according to at least one embodiment of the present disclosure
  • 9A is a partial cross-sectional schematic diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • 9B is another schematic cross-sectional view of a barrier wall in a display substrate according to at least one embodiment of the present disclosure.
  • 9C is another schematic cross-sectional view of a crack blocking wall in a display substrate according to at least one embodiment of the present disclosure.
  • 10A-10C, 11A-11B, 12A-12B, 13A-13B, and 14A-14B are schematic cross-sectional views of a display substrate in a manufacturing process according to at least one embodiment of the present disclosure.
  • the terms “installed”, “connected” and “connected” should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed should be construed in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • the camera device (imaging device) of the display device can be integrated with the display area, and the camera device can be arranged in the display area.
  • Device reserved location For example, FIG. 1A shows a schematic plan view of a display substrate for a display device, the display substrate 10 includes a display area 12, the display area 12 includes a pixel array and has through holes 11 in the pixel array, the through holes 11 are The camera device (not shown) has a reserved position, and the camera device can be arranged on the side of the through hole 11 away from the display surface of the display substrate, so that the camera device can acquire images through the through hole 11 . Thereby, the imaging device is integrated with the display area 12 of the display substrate 10 .
  • the display area 12 has a light-emitting device for display, for example, the light-emitting device is an organic light-emitting diode (OLED), and the organic material layers and driving structure layers of the multiple light-emitting devices in all or part of the display area 12 are usually in the display area 12 Therefore, when the encapsulation layer is used for encapsulation, it is often difficult to encapsulate the area near the through hole 11 , or even if encapsulated, it is difficult to ensure the encapsulation effect of this area. Secondly, due to through-hole cutting process fluctuations, laser thermal effects, handling, etc., some display substrates have cracks during the production process, resulting in package failure. At this time, impurities such as water and oxygen can enter into the display area 12 from the through holes 11 to contaminate the functional layers in the display area 12 , resulting in performance degradation of these functional layers, thereby affecting the display effect of the display area 12 .
  • OLED organic light-emitting diode
  • a panel crack detection (Panel Crack Detection, PCD) technology has been widely used in display panel crack detection.
  • the crack detection line is usually arranged in the peripheral area 13 of the display area 12 , wherein the peripheral area is arranged around the display area 12 .
  • the crack detection technology usually utilizes the resistance value change of the metal detection line (the resistance value change caused by the crack or even disconnection of the metal detection line) to realize the crack detection in the peripheral area of the display panel.
  • At least one embodiment of the present disclosure provides a display substrate, the display substrate includes: a base substrate including a display area, a peripheral area and a blocking area, the peripheral area surrounding the display area, the display area surrounding the blocking area; a through hole located in the blocking area, The center of the display substrate and the center of the through hole do not overlap; a plurality of sub-pixels are located in the display area; a plurality of signal lines are located in the display area, the peripheral area and the blocking area, and are electrically connected to the plurality of sub-pixels, and the plurality of signal lines include the first a signal line; a shift register circuit, located in the peripheral area and electrically connected to a plurality of signal lines; at least one crack detection line located in the blocking region and surrounding the through hole, at least one crack detection line electrically connected to the first signal line, and The first signal line is electrically connected to at least one subpixel of the plurality of subpixels.
  • the display substrate utilizes at least part of the organic functional layer of the display region 12 and the driving structure layer to form a height difference to form a blocking region, so that the organic functional layer is separated from the through hole, which can effectively prevent impurities such as water and oxygen from entering the through hole.
  • the display area of the display substrate By reusing at least part of the driving structure layer of the blocking region as crack detection lines, the increase in the area of the non-display area caused by the provision of crack detection lines is not increased, and the maximization of the display area of the display substrate is ensured.
  • the shift register circuit to be electrically connected with the first signal line and at least one loop of crack detection lines located in the blocking area, the crack detection of the through hole is realized.
  • FIG. 1B shows a schematic plan view of a display substrate 100 .
  • the display substrate 100 includes a display area 101 , a peripheral area 401 , a blocking area 201 and a through hole 301 , and the center of the display substrate and the center of the through hole do not coincide.
  • the through holes 301 allow light from the display side of the display substrate 100 to transmit through the display substrate 100 to reach the back side of the display substrate 100 .
  • the display area 101 and the blocking area 201 surround the through hole 301 , and the blocking area 201 is located between the display area 101 and the through hole 301 .
  • the display substrate includes a display area, a binding area on one side of the display area, and a peripheral area on the other side of the display area, the display area includes a plurality of regularly arranged sub-pixels, and each sub-pixel is connected to at least one
  • the gate lines and at least one data line are collectively referred to as driving signal lines
  • the binding area and the edge area are provided with driving circuits
  • the driving circuits are configured to provide display signals to the display area.
  • the driving circuit may include: a gate driver on array (GOA) circuit disposed on both sides of the display area, configured to provide a scan signal to the display area; a source disposed in the binding area A driver circuit (Driver IC) configured to provide a data signal (Data) to the display area.
  • the shift register circuit is composed of cascaded multi-stage (in the accompanying drawings, n represents the cascade relationship, n ⁇ 2, n is a natural number) shift register unit.
  • the shift register circuit includes a gate shift register drive circuit (Gate GOA) and an emission control shift register circuit (EM GOA).
  • the gate shift register driving circuit outputs two types of signals: reset signal (Reset) and gate scan signal (Gate).
  • the light emission control shift register circuit outputs a light emission control signal (EM).
  • EM light emission control signal
  • the light-emitting control signal prohibits the sub-pixels from emitting light during initialization and data signal writing, turns on the sub-pixels to emit light after the data signals are correctly read in, and controls the light-emitting time.
  • FIG. 2A is a partially enlarged schematic view of the blocking region 201 in FIG. 1B .
  • the blocking area 201 includes a plurality of signal lines 210, and the plurality of signal lines 210 are electrically connected to the driving signal lines (not shown in the figure) of the display area 101, and the plurality of signal lines 210 are on the side of the blocking wall 202 close to the display area 101 .
  • the multiple signal lines can transmit the same signal or at least partially different signals.
  • the multiple signal lines may include gate scanning signal lines, light-emitting control signal lines, and data signal lines.
  • the plurality of signal lines located in the blocking region are electrically connected to the driving signal lines in the display region 101 in a one-to-one correspondence, so as to realize the wiring of the through holes 301 .
  • the blocking area 201 further includes a blocking wall 202 , an intercepting wall 203 and a crack blocking wall 204 arranged in order from the display area 101 to the through hole 301 (ie, the direction from right to left in FIG. 2B ).
  • the blocking wall 202 , the blocking wall 203 and the crack blocking wall 204 all surround the through hole 301 .
  • the blocking area 201 can isolate the display area 101 from the through hole 301 , so as to protect the display area 101 .
  • the blocking wall 203 is not shown in FIG. 2A , and the blocking wall 203 is located between the blocking wall 202 and the crack blocking wall 204 .
  • the number of blocking walls 202, blocking walls 203 and crack blocking walls 204 may be one or more.
  • FIG. 2B two blocking walls 202, one blocking wall 203 and two crack blocking walls 204 are shown as examples, but This does not constitute a limitation to the embodiments of the present disclosure.
  • the display substrate 100 includes a base substrate 1011 .
  • the display substrate 100 may be a flexible display substrate, and in this case, the base substrate 1011 may be a flexible insulating material such as polyimide (PI).
  • the base substrate 1011 may also be a rigid display substrate such as glass.
  • the display substrate 100 may further include a barrier layer 1012 and a buffer layer 1013 disposed on the base substrate 1011.
  • the barrier layer 1012 can prevent impurities such as water and oxygen from infiltrating into functional structures such as the thin film transistor 102 from the base substrate 1011, and the buffer layer 1013 may Provide a flat surface to facilitate the placement of other functional layers of the display substrate.
  • the blocking layer 1012 and the buffer layer 1013 can jointly protect other functional structures on the base substrate 1011 .
  • the driving structure layer of the display substrate 100 includes structures such as thin film transistors 102 and storage capacitors 103 .
  • the thin film transistor 102 includes an active layer 1021, a gate electrode 1022, a first insulating layer 1014 (for example, including a first insulating sublayer 1014A and a first insulating sublayer 1014B), a second insulating layer 1015 and a source Drain electrode (including source electrode 1024 and drain electrode 1023).
  • both the source and drain electrodes have a three-layer metal layer structure, such as titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, titanium/copper/titanium, or molybdenum/copper/molybdenum three-layer metal layer structure.
  • the storage capacitor 103 includes a first electrode plate 1031 and a second electrode plate 1032 .
  • the first electrode plate 1031 and the gate electrode 1022 are disposed in the same layer, and the second electrode plate 1032 is between the first insulating layer 1014 and the second insulating layer 1015 .
  • the plurality of signal lines 210 in the blocking region are disposed at least partially in the same layer as the second electrode plate 1032 , the first electrode plate 1031 , and the source-drain electrodes 1023 / 1024 .
  • two or more functional layers are disposed in the same layer, which means that these functional layers disposed in the same layer can be formed by using the same material layer and using the same preparation process (such as patterning process, etc.), so that the simplification can be achieved.
  • the preparation process of the display substrate Therefore, these functional layers disposed in the same layer can be formed by using the same material layer and through the same patterning process, so as to simplify the preparation process of the display substrate.
  • the display area 101 of the display substrate 100 further includes a planarization layer 1016 , a pixel definition layer 1017 and a spacer 1018 .
  • the planarization layer 1016 is used to planarize the thin film transistor 102
  • the pixel definition layer 1017 is on the side of the planarization layer 1016 away from the thin film transistor 102
  • the pixel definition layer 1017 is used to define a plurality of sub-pixels.
  • the spacer 1018 is on the side of the pixel defining layer 1017 away from the flat layer 1016 .
  • the display area 101 includes a plurality of sub-pixels, wherein the sub-pixels include a driving structure layer and a light emitting device 104, wherein the driving structure layer includes a plurality of driving signal lines, and the driving signal lines drive the light emitting device 104 to emit light.
  • the light-emitting device 104 can be, for example, an organic light-emitting diode (OLED for short) or a quantum dot electroluminescent display (QLED for short).
  • the light emitting device 104 includes an anode layer 1041 , an organic functional layer 1042 and a cathode layer 1043 .
  • the organic functional layer 1042 is located between the anode layer 1041 and the cathode layer 1043 .
  • the anode layer 1041 is connected to the drain electrode 1023 of the thin film transistor through a via hole in the planarization layer 1016 .
  • the organic functional layer 1042 may further include an auxiliary light-emitting layer (not shown in the figure), for example, including one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.
  • the auxiliary light-emitting layer is, for example, an organic material layer.
  • the organic functional layer 1042 may also be formed on the entire surface of the base substrate 1011 and be disconnected at the barrier wall 202 and the crack barrier wall 204 .
  • the cathode layer 1043 is formed on the entire surface of the base substrate 1011 , and is disconnected at the barrier wall 202 and the crack barrier wall 204 .
  • parts of the organic functional layer 1042 and the cathode layer 1043 are also formed on tops of the barrier walls 202 and the crack barrier walls 204, but these parts are separated from other parts.
  • the blocking region 201 includes a first organic functional layer 10421 and a second organic functional layer 10422 which are provided with the same layer and the same material as the organic functional layer 1042 .
  • the first organic functional layer 10421 is located on the side of at least one crack detection line away from the substrate, and the second organic functional layer is located on the side of the first multilayer insulating layer 202A away from the substrate.
  • the first organic functional layer 10421 and the second organic functional layer 10422 are arranged intermittently, and the orthographic projection of the first organic functional layer 10421 on the base substrate and the orthographic projection of the second organic functional layer 10422 on the base substrate do not overlap.
  • the organic functional layer on the side close to the through hole 301 is contaminated with impurities such as water and oxygen, since the organic functional layer is disconnected by the barrier wall 202 and the crack barrier wall 204, these contaminated impurities will not extend to the organic function.
  • the layer is used in the portion of the light emitting device that emits light.
  • the blocking area further includes at least one loop of crack detection lines 202B, and is disposed around the through hole.
  • the crack detection line 202B constitutes at least part of the barrier wall 202 , that is, at least a part of the first barrier wall 202 is multiplexed into the crack detection line 202B.
  • the crack detection line 202B is provided in the same layer as the source-drain electrodes 1023/1024. Because the driving structure layer of the display substrate includes the source and drain electrodes 1023/1024, that is, at least part of the driving structure layer of the display substrate is multiplexed into at least one loop of crack detection lines 202B.
  • the crack detection line 202B is disposed on the barrier wall on the side close to the display area.
  • the blocking region 201 includes a plurality of blocking walls 202, and at least one circle of crack detection lines 202B is disposed on any circle of the blocking walls.
  • At least one loop of the crack detection wire 202B has a three-layer metal layer structure, such as a three-layer metal layer structure such as titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, titanium/copper/titanium, or molybdenum/copper/molybdenum.
  • a three-layer metal layer structure such as titanium/aluminum/titanium, molybdenum/aluminum/molybdenum, titanium/copper/titanium, or molybdenum/copper/molybdenum.
  • At least one loop of crack detection lines 202B includes a first sub-layer sequentially located on the side of the first multilayer insulating layer 202A away from the base substrate 2045, the second sublayer 2046 and the third sublayer 2047, the orthographic projection of the second sublayer 2046 on the base substrate is located on the first sublayer 2045 and the third sublayer 2046 on the base substrate in the orthographic projection.
  • the barrier wall 202 may further include a first multilayer insulating layer 202A, and the crack detection line 202B is located on the first multilayer insulating layer 202A.
  • the first multi-layer insulating layer 202A includes a plurality of insulating sub-layers, eg, shown in FIG. 7A as including insulating sub-layers 2021 and 2022 .
  • the insulating sub-layer 2021 and the first insulating layer 1014 are provided in the same layer, and the insulating sub-layer 2022 and the second insulating layer 1015 are provided in the same layer.
  • the width W1 of the barrier wall 202 may be 2 ⁇ m-4 ⁇ m, for example, 3 ⁇ m or 3.5 ⁇ m.
  • the number of barrier layers and buffer layers included on the base substrate may be more, and in this case, the second portion of the first multilayer insulating layer 202A may be combined with more barrier layers and buffer layers. Layer-to-layer settings.
  • the first multilayer insulating layer 202A of the barrier wall 202 includes a first portion (including insulating sublayers 2021 and 2022 ) and a second portion (including insulating sublayers 2026 and 2027 ) arranged in a stack ), the first part is disposed at least in the same layer as the first insulating layer 1014 and the second insulating layer 1015 , and the second part is disposed in at least the same layer as the blocking layer 1012 and the buffer layer 1013 .
  • the first insulating layer 1014 in the blocking region 201 is only shown as one layer in the drawings.
  • the widths of the first portion and the second portion of the first multi-layer insulating layer 202A are different, for example, the second portion is wider than the first portion, so that the overall longitudinal section of the first multi-layer insulating layer 202A is stepped, as shown in FIG. 9B . .
  • the plurality of signal lines 210 includes a first signal line 211 .
  • the first signal line 211 is one of the plurality of signal lines 210 electrically connected to the crack detection line 202B.
  • At least one loop of crack detection line 202B includes at least one first overlapping structure 220A. It is used to electrically connect at least one loop of crack detection lines to the first signal line 211 .
  • the number of the first overlapping structures 220A is two 2201 and 2202 , and the two first overlapping structures 2201 and 2202 are respectively electrically connected to the first sub-wire 2111 of the first signal line and at least one The first end of the loop of crack detection line 202B, and the second end of at least one loop of crack detection line 202B and the second sub-trace 2112.
  • the first sub-line 2111 and the second sub-line 2112 belong to the part of the first signal line 211 .
  • the two first overlapping structures 220A may be located on opposite sides in the radial direction of the through hole 301 , may also be located on the same side in the radial direction of the through hole 301 , or may be located on any side in the radial direction of the through hole 301 . limit.
  • the first signal line 211 , the first overlapping structure 220A and the second electrode plate 1032 are disposed on the same layer.
  • the first lap structure 220A is electrically connected to at least one loop of crack detection lines 202B of the barrier wall through a via hole, and the via hole penetrates the second insulating layer 1015 to expose the first lap structure 220A.
  • the first signal line 211 , the first overlapping structure 220A and the first electrode plate 1031 are disposed on the same layer.
  • the first lap structure 220A is electrically connected with at least one loop of crack detection lines 202B through via holes, which penetrate through the first insulating layer 1014 and the second insulating layer 1015 to expose the first lap structure 220A. Providing the first overlapping structure can eliminate the static electricity accumulation benefit on the crack detection line.
  • the first signal line 211 , the first bonding structure 220A and the source-drain electrodes 1023 / 1024 are disposed in the same layer.
  • the first signal line 211 , the first overlapping structure 220A, and the at least one loop of the crack detection line 202B can be electrically connected to each other without the need to provide a via hole.
  • the first overlapping structure 220A may not be provided at this time.
  • the first lap structure 220A may be multi-layered, for example, at least part of the same layer as the first electrode plate 1031, and at least part of the same layer as the second electrode plate 1032, the first lap structure 220A
  • the multi-layer structures are electrically connected to each other and are electrically connected to at least one loop of crack detection lines 202B through via holes.
  • the first overlapping structure arranged in multiple layers can eliminate the electrostatic accumulation benefit on the crack detection lines.
  • the number of crack detection lines 202B is multiple turns, and the multiple turns of crack detection lines are continuous traces and surround the through holes.
  • FIG. 4B is a partial cross-sectional schematic diagram of FIG. 4A along line DD, at least one loop of crack detection line 202B includes at least one second overlapping structure 220B, wherein, The at least one second lap structure 220B is electrically connected between two adjacent loops of crack detection lines, wherein the at least one second lap structure and the two adjacent loops of crack detection lines are located at different layers and are electrically connected through vias. connect.
  • the number of at least one circle of crack detection lines 202B is four circles, and along the radial direction close to the center of the through hole 301 , the first detection sub-lines 2021 are respectively included , the second detection sub-line 2022, the third detection sub-line 2023 and the fourth detection sub-line 2024, the first detection sub-line 2021 and the second detection sub-line 2022 pass through at least one second lap structure 220B
  • the via holes are electrically connected, and any two of the second detection sub-line 2022 , the third detection sub-line 2023 and the fourth detection sub-line 2024 are electrically connected through the via holes through at least two second overlapping structures 220B.
  • multiple loops of crack detection wires 202B are arranged around the through hole 301 , and the multiple loops of crack detection wires 202B are connected to form a continuous and unbroken annular metal wire through a plurality of second overlapping structures 220B.
  • the plurality of second lap structures 220B can be distributed at radial intervals of the through holes 301 .
  • the number and distribution position of the plurality of second lap structures 220B are not limited here, but in order to realize the barrier wall and the crack barrier wall 204 In order to achieve a double barrier effect together, the plurality of second overlapping structures 220B are distributed in the radial direction of the through holes 301 without overlapping. Similarly, providing a plurality of second overlapping structures can eliminate the electrostatic accumulation benefit on the crack detection line.
  • the lap joint structure 220 can be arranged on the same layer as the second pole plate, as shown in Figure 4B; it can also be arranged on the same layer as the first pole plate, as shown in Figure 4C; it can also be partly arranged on the same layer as the first pole plate And part of it is arranged on the same layer as the second electrode plate, which is not shown in the figure.
  • the second lap structure 220B may be multi-layered, for example, at least part of the same layer as the first electrode plate 1031 , and at least part of the same layer as the second electrode plate 1032 , the second lap structure 220B has multiple layers.
  • the layer structures are electrically connected to each other and to at least one loop of crack detection lines 202B through vias.
  • Both the first lap structure 220A and the second lap structure 220B belong to the lap structure 220, and can be formed by using the same material layer and through the same patterning process, so as to simplify the preparation process of the display substrate.
  • the display substrate 100 includes the shift register circuit 19 located in the peripheral region and electrically connected to the plurality of signal lines 210 .
  • the shift register circuit 19 includes a plurality of cascaded shift register units 193 .
  • the shift register circuit 19 may include a gate shift register circuit 191 (Gate GOA), or an emission control shift register circuit 192 (EM GOA).
  • the gate shift register circuit 191 includes a plurality of cascaded shift register units 193
  • the light emission control shift register circuit 192 includes a plurality of cascaded shift register units 193 .
  • the settings of the gate shift register circuit 191 and the light emission control shift register circuit 192 in the drawings are only examples.
  • the gate shift register circuit 191 and the light emission control shift register circuit 192 are arranged on opposite sides of the display substrate 100 .
  • the shift register circuit of the actual substrate can be arranged in different ways, which is not limited here. .
  • the driving structure layer of the display substrate 100 includes a shift register circuit 19, which is electrically connected to a plurality of sub-pixels 18 in the display area, and drives the plurality of sub-pixels 18 row by row to realize display.
  • the display substrate 100 further includes a binding area 17 on at least one side of the display panel.
  • the binding area 17 is electrically connected to the shift register circuit 19 .
  • at least one of the plurality of driving signal lines 221 is electrically connected to the first signal line 211 .
  • the driving signal line electrically connected to the first signal line 211 is electrically connected to at least one of the plurality of sub-pixels 18 .
  • the first signal line 211 is electrically connected to at least one sub-pixel 18 .
  • the driving signal line electrically connected to the first signal line 211 is one of the gate scanning signal lines.
  • the driving signal line electrically connected to the first signal line 211 is one of the light-emitting control signal lines.
  • the resistance value of the at least one loop of the crack detection line 202B increases.
  • the resistance value of the row where the first signal line 211 is electrically connected to the crack detection line is increased, and the resistance value of the row where at least one sub-pixel electrically connected thereto is located is changed (for example, increased), causing the driving structure layer to drive the sub-pixel.
  • the light emission luminance of the light emitting device 104 of the pixel 18 is changed, that is, the display is abnormal, thereby realizing the detection of cracks in the through hole 301 .
  • the shift register circuit is electrically connected with the first signal line and at least one loop of crack detection lines located in the blocking area, so as to realize the crack detection of the through hole and improve the reliability of the display substrate.
  • the display substrate 100 includes crack detection lines 16 located in the peripheral region.
  • the crack detection line 16 realizes crack detection of the peripheral region of the display substrate.
  • the crack detection line is connected to the binding area 17, and the crack detection of the display substrate 100 is realized through the signal control structure located in the binding area.
  • a detection signal is applied to one end of the crack detection line 16 through the signal control structure in the binding area, and received through the other end of the crack detection line 16 also located in the binding area According to the state of the received signal, it can be determined whether the display panel has cracks. Since the crack detection line is an integral loop, when a crack occurs at any position in the peripheral area of the display panel, it can be determined that the crack occurs according to the received signal exceeding the preset range. In some embodiments, the crack detection line is partially cracked (or disconnected) due to the through hole 301, and its resistance value increases (or exceeds a preset range value), and the receiving signal end located in the binding area determines that a crack has occurred , to achieve crack detection.
  • the crack detection line 16 of the display substrate can be used to realize the crack detection of the through hole 301, which improves the reliability of the display substrate.
  • the barrier wall 202 includes at least one loop of crack detection lines 202B, and the at least one loop of crack detection lines 202B has a notch around at least one side of the through hole 301 .
  • at least one loop of the crack detection line 202B has a notch on both the side facing the through hole 301 and the side facing away from the through hole 301 .
  • the barrier wall 202 can disconnect the functional layers formed on the entire surface of the display substrate, such as the organic functional layer 1042 and the cathode layer 1043 of the light emitting device.
  • the blocking region further includes at least one groove 206 , the groove 206 is located between the blocking wall 203 and the blocking wall 202 and penetrates through the first insulating layer 1014 and at least part of the For the second insulating layer 1015, the orthographic projection of the groove on the base substrate does not overlap with the orthographic projection of the at least one circle of crack detection lines on the base substrate.
  • the grooves 206 may be formed simultaneously with the first insulating layer and/or the second insulating layer through a patterning process when the first insulating layer 1014 and the second insulating layer 1015 are formed, or may be formed when the first insulating layer 1014 and the second insulating layer are formed.
  • the number of grooves may be one, that is, between the blocking wall 203 and the blocking wall 202 . In other embodiments, the number of grooves may be multiple, such as between multiple blocking walls. The number and position of the grooves do not limit the present disclosure. Of course, in other embodiments, grooves may not be provided.
  • the arrangement of the first multi-layer insulating layer 202A and the at least one groove 206 can enhance the barrier effect of the barrier wall 202, and is beneficial to the first inorganic encapsulation layer 1051 (described later) formed on the barrier wall 202 later, for example, by deposition or the like. ) can be better formed along the surface topography of the barrier wall 202 .
  • the blocking area 201 includes the blocking walls 202 , the blocking walls 202 , the blocking walls 202 , the blocking walls 202 , the blocking walls 202 , the blocking walls 202 , the blocking walls 202 , the blocking The wall 203 and the crack blocking wall 204 , the blocking wall 202 , the first intercepting wall 203 and the crack blocking wall 204 all surround the through hole 301 .
  • the number of intercepting walls 203 is at least one circle, and is arranged around the through holes. At least one circle of blocking walls 203 is configured to block the organic encapsulation layer encapsulating the plurality of sub-pixels.
  • the blocking wall 203 includes a second multilayer insulating layer, eg, a stack including a plurality of sub-insulating layers, such as a stack including two sub-insulating layers 20311 and 20312 .
  • the blocking wall 203 can block some functional layers (eg, organic encapsulation layers) formed in the display area 101 to prevent the materials of these functional layers from approaching or entering the through holes 301 .
  • the blocking wall 203 is configured to block the organic encapsulation layer material encapsulating the plurality of sub-pixels.
  • the insulating sublayers 20311 and 20312 correspond to two of the planarization layer 1016 , the pixel defining layer 1017 and the spacer 1018 in one-to-one correspondence and are disposed in the same layer.
  • the second multi-layer insulating layer of the blocking wall 203 is disposed in the same layer as at least one of the planarization layer 1016 , the pixel defining layer 1017 and the spacer 1018 .
  • the insulating sub-layer 20311 and the planarization layer 1016 are placed on the same layer, and the insulating sub-layer 20312 and the pixel defining layer 1017 are placed on the same layer; or, the insulating sub-layer 20311 and the planarizing layer 1016 are placed on the same layer, and the insulating sub-layer 20312 and the spacer 1018 are placed on the same layer.
  • the insulating sub-layer 20311 and the pixel defining layer 1017 are arranged at the same layer, and the insulating sub-layer 20312 and the spacer 1018 are arranged at the same layer. Therefore, in the preparation process, these functional layers disposed on the same layer can be formed by using the same material layer and through the same patterning process.
  • the at least one ring of intercepting walls includes a first intercepting wall 2031 and a second intercepting wall 2032.
  • the second intercepting wall 2032 is adjacent to the first intercepting wall 2031 and on the side of the first intercepting wall 2031 away from the display area 101, and the maximum height of the first intercepting wall 2031 in the direction perpendicular to the substrate is smaller than that of the second intercepting wall 2031 The maximum height of the wall 2032 in the direction perpendicular to the base substrate.
  • the second intercepting wall 2032 and the first intercepting wall 2031 can achieve a double interception effect.
  • the second blocking wall 2032 includes a plurality of insulating sublayers, which are shown in FIG. 7D as including insulating sublayers 20321 , 20322 and 20323 , for example, the insulating sublayer 20321 is the same as the planarization layer 1016 Layer arrangement, the insulating sub-layer 20322 and the pixel defining layer 1017 are arranged in the same layer, and the insulating sub-layer 20323 and the spacer 1018 are arranged in the same layer. Therefore, in the preparation process, these functional layers provided in the same layer can be formed by using the same material layer and through the same patterning process.
  • the second intercepting wall 2032 is higher than the first intercepting wall 2031, which can play a sufficient intercepting function, and the second intercepting wall 2032 and the first intercepting wall 2031 together can achieve a double intercepting effect.
  • the crack barrier wall 204 includes a metal layer structure 204B and a stack structure 204A, the metal layer structure 204B is located on the stack structure 204A, and the metal layer structure 204B is located on the stack structure 204A.
  • At least one side around the through hole 301 has a notch.
  • both the side facing the through hole 301 and the side facing away from the through hole 301 of the metal layer structure 204B have notches, that is, as shown in FIG. 3B and FIG. 7C .
  • the sides have notches.
  • the three metal sub-layers 2023/2024/2025 of at least one loop of the crack detection line 202B and the three metal sub-layers 2045/2046/2047 of the crack blocking wall 204B are respectively connected with the source-drain current
  • the three metal layers of the poles 1023 and 1024 are in one-to-one correspondence and have the same material. Therefore, at least one loop of the crack detection line 202B, the crack blocking wall 204B, and the source-drain electrodes 1023 and 1024 can be formed by using the same three-layer metal material layer and using the same patterning process.
  • the metal layer structure 204B of the crack barrier wall 204 has the same structure and includes the same material as at least one loop of crack detection lines 202B of the barrier wall 202 . Therefore, in the preparation process of the display substrate, the metal layer structure 204B of the crack blocking wall 204 and at least one crack detection line 202B of the blocking wall 202 can be formed by the same material layer and the same patterning process, so as to simplify the process of the display substrate. Preparation Process.
  • the metal layer structure 204B of the crack barrier wall 204 and the at least one loop of crack detection lines 202B of the barrier wall 202 have the same structure and include the same material. Similar to the foregoing, the metal layer structure 204B of the crack blocking wall 204 can also be electrically connected to the first signal line 211 to realize crack detection of the through hole 301 . That is, the crack blocking wall 204 configured to detect the crack of the through hole 301 is also included in the inventive concept of the present disclosure.
  • the crack blocking wall 204 and the blocking wall 202 are jointly configured to detect the crack of the through hole 301 , which is also included in the inventive concept of the present disclosure.
  • the stack of the stacked structure 204A of the crack barrier wall 204 includes a first metal sublayer 2041 , a first insulating sublayer 2042 , a first metal sublayer 2041 , a first insulating sublayer 2042 , a Two metal sublayers 2043 and a second insulating sublayer 2044 .
  • the first metal sub-layer 2041 and the gate electrode 1022 are arranged on the same layer
  • the first insulating sub-layer 2042 and the first insulating layer 1014 are arranged on the same layer
  • the second metal sub-layer 2043 and the second electrode plate 1032 are arranged on the same layer
  • the second insulator The layer 2044 is disposed in the same layer as the second insulating layer 1015 .
  • the structures of the barrier wall 202 and the crack barrier wall 204 may also include structures provided in the same layer as the barrier layer 1012 and the buffer layer 1013 . Therefore, these functional layers disposed in the same layer can be formed by using the same material layer and through the same patterning process, so as to simplify the preparation process of the display substrate.
  • the crack barrier wall 204 may take a variety of forms.
  • the first insulating sublayer 2042 and the second insulating sublayer 2044 of the crack barrier wall 204 may have the same characteristics as the first metal sublayer 2041 and the second metal sublayer 2043
  • the pattern, thus embodied in Figure 8B, has the same width.
  • the first insulating sub-layer 2042 and the second insulating sub-layer 2044 may undergo a further etching process to form corresponding patterns.
  • the stack structure 204A includes a stack having metal layers and insulating layers.
  • the crack barrier wall 204 can also disconnect the functional layer formed on the entire surface of the display substrate, thereby achieving a double barrier effect together with the barrier wall 202. At this time, even if the barrier wall 202 fails, the crack barrier wall 204 includes a metal layer and an insulating layer.
  • the vertical distance from the base substrate 1011 is greater than the vertical distance from the barrier wall 202 to the base substrate 1011, and the barrier effect will be achieved in the crack barrier wall 204; Or when the through hole 301 is formed by cutting or other methods, the crack blocking wall 204 can also prevent the cracks that may be generated when the through hole 301 is formed from expanding, and the crack blocking wall 204 has a good crack because it includes a stack with a metal layer and an insulating layer. The blocking effect is thereby prevented from extending to the display area 101 .
  • the stacked structure 204A of the crack barrier wall 204 may also include two parts, called a third part (including the first metal sublayer 2041 , the first insulating sublayer 2042 , the second part Metal sublayer 2043 and second insulating sublayer 2044) and fourth portion (including insulating sublayers 2048 and 2049), eg, fourth portion and second portion of first multilayer insulating layer 202A of barrier wall and barrier layer 1012 and buffer Layer 1013 is set on the same layer. Therefore, in the preparation process, these functional layers provided in the same layer can be formed by using the same material layer and through the same patterning process. For example, the widths of the third portion and the fourth portion are different, for example, the fourth portion is wider than the third portion, so that the longitudinal section of the laminated structure 204A is stepped as a whole.
  • the first inorganic encapsulation layer 1051 (later) formed thereon, for example, by deposition or the like. Introduction) can be better formed along the surface topography of the barrier wall 202 and the crack barrier wall 204 without the occurrence of side fractures and other undesirable situations, so that the first inorganic encapsulation layer 1051 has better integrity, thereby providing better packaging effect.
  • the width of the crack barrier wall 204 can also be 2 ⁇ m-4 ⁇ m, such as 3 ⁇ m or 3.5 ⁇ m, etc.
  • the embodiments of the present disclosure do not specifically limit the size of each structure, as long as the corresponding function can be achieved.
  • FIGS. 8A and 9A only show the structures and parts of the barrier wall 202 , the first barrier wall 2031 , the crack barrier wall 204 and the second barrier wall 2032 on the base substrate 1011
  • the signal line 210 may also include other structures as shown in FIG. 2B.
  • FIG. 2B please refer to FIG. 2B, which will not be repeated here.
  • the display substrate 100 may further include an encapsulation layer 105 that encapsulates at least the barrier walls 202 .
  • the encapsulation layer 105 encapsulates the display area 101 (including a plurality of sub-pixels) at the same time. ) and the barrier wall 202.
  • the encapsulation layer 105 includes a first inorganic encapsulation layer 1051 , a first organic encapsulation layer 1052 and a second inorganic encapsulation layer 1053 , which are sequentially stacked on the barrier wall 202 .
  • the first inorganic encapsulation layer 1051 is formed on the entire surface of the display substrate. Due to the interception effect of the first intercepting wall 2031 , the first organic encapsulating layer 1052 and the second inorganic encapsulating layer 1053 terminate at the first intercepting wall 2031 .
  • the display substrate 100 may further include: an image sensor and/or an infrared sensor 501 , and the image sensor and/or the infrared sensor 501 is combined with the non-display side of the display substrate 100 , And the orthographic projection on the base substrate 1011 at least partially overlaps with the through hole 301 .
  • the image sensor and/or the infrared sensor 501 can realize various functions such as photographing, face recognition, infrared sensing, etc. through the through hole 301 .
  • the blocking region 201 can sufficiently isolate the display region 101 from the through hole 301 , effectively prevent impurities such as water and oxygen from entering the display region 101 from the through hole 301 , and can also prevent the possibility of forming the through hole 301 from entering the display region 101 .
  • the generated cracks extend to the display area 101, which can effectively prevent impurities such as water and oxygen from entering the display area of the display substrate from the through holes.
  • At least one embodiment of the present disclosure further provides a method for fabricating a display substrate.
  • the display substrate 100 shown in FIGS. 4A-4B is taken as an example, wherein only two barrier walls 202 are exemplarily shown, one The crack blocking wall 204 will be introduced to the manufacturing method of the display substrate provided by the embodiment of the present disclosure.
  • a base substrate 1011 is provided.
  • the provided base substrate 1011 can be a flexible substrate such as polyimide (PI), and when the display substrate is a rigid substrate, the substrate The substrate 1011 may be a rigid substrate such as glass or quartz.
  • a functional layer for the display area 101 and the blocking area 201 is firstly formed on the base substrate 1011 , and positions are reserved for the through holes 301 to facilitate the functions of the display area 101 and the blocking area 201 After the layers are formed, the through holes 301 are formed by punching or cutting, for example.
  • the barrier layer 1012 and the buffer layer 1013 can be sequentially formed on the base substrate 1011 by methods such as deposition.
  • the barrier layer 1012 and the buffer layer 1013 may be formed on the entire surface of the base substrate 1011 .
  • the barrier layer 1012 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride
  • the buffer layer 1013 can also be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the crack barrier 204 is formed in the barrier area 201 .
  • an active layer 1021 is formed on the base substrate 1011 by a patterning process; a first insulating layer 1014A is formed on the active layer 1021 by deposition or the like; on the first insulating layer 1014A
  • the gate 1022, the first electrode plate 1031 and the first metal sub-layer 2041 are simultaneously formed by a patterning process; the second insulating layer 1014B is formed on the gate 1022, the first electrode plate 1031 and the first metal sub-layer 2041 by means of deposition or the like.
  • Adopt patterning process to simultaneously form the second pole plate 1032, the second metal sublayer 2043 and at least part of the overlapping structure 220, a plurality of signal lines 210 of the same material in the same layer; in the second pole plate 1032 and the second metal sublayer A second insulating layer 1015 is formed on 2043 by deposition or the like; then, the first insulating layer 1014 and the second insulating layer 1015 are etched to form via holes exposing the active layer 1024, and to form an exposed lap structure 220 on the second metal Via 2204 of sublayer 2043.
  • one patterning process includes photoresist formation, exposure, development, and etching.
  • the first metal sub-layer 2041 of the crack barrier 204 is formed in the same layer as the gate electrode 1022
  • the first insulating sub-layer 2042 is formed in the same layer as the first insulating layer 1014
  • the second metal sub-layer 2043 is formed in the same layer.
  • the signal line 210 and the second electrode plate 1032 are formed in the same layer
  • the second insulating sub-layer 2044 and the second insulating layer 1015 are formed in the same layer.
  • the materials of the gate electrode 1022, the first electrode plate 1031 and the first metal sub-layer 2041 include metal or alloy materials such as aluminum, titanium, and cobalt.
  • a gate material layer is first formed by sputtering or evaporation, and then a patterning process is performed on the gate material layer to form the patterned gate 1022 , the first electrode plate 1031 and the first metal sub-layer Layer 2041.
  • the formation methods of other structures formed in the same layer are similar to this, and thus are not repeated here.
  • the active layer 1021 can be made of materials such as polysilicon and metal oxide
  • the first insulating layer 1014 can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride
  • the second electrode plate 1032 and the second metal sub-layer 2043 The lap structure 220 and the signal line 210 can be made of metal or alloy materials such as aluminum, titanium, and cobalt
  • the second insulating layer 1015 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the embodiments of the present disclosure do not limit the material of each functional layer, and the material of each functional layer is not limited to the above examples.
  • the first insulating layer 1014 and the second insulating layer 1015 located in the blocking region 201 may be etched by one etching process, thereby forming the first multi-layer insulating layer 202A of the blocking wall 202 , and at the overlapping A via hole is formed at the bonding structure 220 to form a via hole 2204 exposing the bonding structure 220 .
  • the first multilayer insulating layer 202A includes a sub-insulating layer 2021 formed on the same layer as the first insulating layer 1014 and a sub-insulating layer 2022 formed on the same layer as the second insulating layer 1015 .
  • the first multi-layer insulating layer 202A, the via hole 2204 for forming the exposed overlapping structure 220 and the first insulating layer 1014 and the second insulating layer 1015 are formed in the same layer, thereby simplifying the manufacturing process of the display substrate.
  • the manufacturing method of the display substrate may further form the barrier wall 202 as shown in FIG. 9B and the crack barrier wall 204 as shown in FIG. 9C .
  • the first insulating layer 1014 and the second insulating layer 1015 of the blocking region 201 may be etched through the first etching process, and the blocking layer 1012 and the buffer layer 1013 of the blocking region 201 may be etched through the second etching process to form a structure including The first multi-layer insulating layer 202A of the first part (including insulating sublayers 2021 and 2022 ) and the second part (including insulating sublayers 2026 and 2027 ) and the third part (including the first metal sublayer 2041 , the first insulating sublayer 2042 , The stack structure 204A of the second metal sublayer 2043 and the second insulating sublayer 2044) and the fourth part (including the insulating sublayers 2048 and 2049).
  • the first part of the first multilayer insulating layer 202A and the insulating sublayer in the third part of the laminated structure 204A are formed in the same layer as the first insulating layer 1014 and the second insulating layer 1015;
  • the second portion, the fourth portion of the stacked structure 204A is formed in the same layer as the barrier layer 1012 and the buffer layer 1013 . Since the overall thickness of the barrier layer 1012, the buffer layer 1013, the first insulating layer 1014 and the second insulating layer 1015 is relatively thick, etching a part of them through the two etching processes is conducive to the smooth progress of the etching process, and is beneficial to The final etched topography is guaranteed.
  • the barrier layer 1012 , the buffer layer 1013 , the first insulating layer 1014 and the second insulating layer 1015 can also be etched at the same time near the through hole 301 , (ie, the portion in FIG. 10C . The part shown by the dotted box on the left). Since some or all of the barrier layer 1012 , the buffer layer 1013 , the first insulating layer 1014 and the second insulating layer 1015 are made of inorganic insulating materials, due to the brittleness of the inorganic insulating materials, the through holes are formed by punching or cutting. 301 is easy to form cracks. Therefore, parts of the barrier layer 1012 , buffer layer 1013 , first insulating layer 1014 and second insulating layer 1015 close to the through hole 301 are removed to avoid cracks in these layers when the through hole 301 is formed.
  • the source electrode 1023 and the drain electrode 1024 and at least one circle of crack detection lines 202B of the barrier wall 202 and the metal layer of the crack barrier wall 204 are formed Structure 204B. At least part of the source electrode 1024 and the drain electrode 1023 located on the barrier wall 202 are electrically connected to the part of the overlap structure located on the second electrode plate at the via hole 2204 of the overlap structure 220 to realize overlap.
  • the bonding structure 220 (including the first bonding structure 220A and the second bonding structure 220B) includes the second metal sub-layer 2043 (the second electrode plate 1032 is of the same layer and the same material), the source and drain layers (including The source electrode 1024 and the drain electrode 1023) are electrically connected through the via hole.
  • the overlapping structure may also include the first metal sub-layer 2041 (the first electrode plate 1031 ) and the source and drain layers, which are electrically connected through via holes.
  • the source electrode 1023 and the drain electrode 1024 may be formed in a multi-layer metal structure, such as a three-layer metal layer structure.
  • a titanium material layer, an aluminum material layer, and a titanium material layer may be sequentially formed by means of sputtering or evaporation, and then the three material layers are patterned by the same patterning process, thereby forming the source electrode 1023 and the titanium/aluminum/titanium 3 three-layer metal structure of the drain electrode 1024, at the same time, an initial at least one circle of crack detection lines and an initial metal layer structure with flush sides are formed.
  • the initial at least one ring of crack detection lines and the initial metal layer structure with flush sides are etched through one etching process to form at least one ring of crack detection lines 202B and metal layer structures 204B with notches on the sides.
  • the etching solution used in the etching process only has an etching effect on at least one ring of the crack detection line 202B and the intermediate layer of the metal layer structure 204B, or the etching rate for the intermediate layer is higher than the etching rate for other layers, thereby
  • the etching process may form at least one loop of crack detection line 202B and a notch of metal layer structure 204B.
  • the source electrode 1023 and the drain electrode 1024 and at least one crack detection line 202B of the barrier wall 202 are formed in the same layer as the metal layer structure 204B and the overlapping structure 220 of the crack barrier wall 204, which simplifies the preparation process of the display substrate.
  • the planarization layer 1016 , the anode layer 1041 , the pixel defining layer 1017 and the spacer 1018 are sequentially formed, and the first An intercepting wall 2031 and a second intercepting wall 2032.
  • the planarization layer 1016 , the insulating sub-layer 20311 of the first intercepting wall 2031 and the insulating sub-layer 20321 of the second intercepting wall 2032 are formed in the same layer through a patterning process.
  • the planarization layer 1016, the insulating sub-layer 20311 of the first intercepting wall 203 and the insulating sub-layer 20321 of the second intercepting wall 2032 can be made of organic insulating materials such as polyimide and epoxy resin.
  • the formed planarization layer 1016 has a via hole, so that the anode layer 1041 to be formed later is electrically connected to the source electrode 1023 through the via hole.
  • an anode layer 1041 is formed on the planarization layer 1016 of the display area 101 by a patterning process, and the anode layer 1041 is electrically connected to the source electrode 1023 through via holes in the planarization layer 1016 .
  • the material of the anode layer 1041 includes metal oxides such as ITO, IZO, or metals such as Ag, Al, Mo, or alloys thereof.
  • the pixel defining layer 1017 , the insulating sub-layer 20312 of the first intercepting wall 2031 and the insulating sub-layer 20322 of the second intercepting wall 2032 are formed in the same layer through a patterning process.
  • the pixel defining layer 1017 has 32 openings exposing the anode layer 1041, so that structures such as the organic functional layer 1042 and the cathode layer 1043 of the light emitting device are formed later.
  • the materials of the pixel defining layer 1017 , the insulating sub-layer 20312 of the first intercepting wall 2031 and the insulating sub-layer 20322 of the second intercepting wall 2032 may include organic insulating materials such as polyimide and epoxy resin.
  • the spacer 1018 and the insulating sub-layer 20323 of the second blocking wall 2032 are formed in the same layer through a patterning process.
  • the materials of the spacer 1018 and the insulating sub-layer 20323 of the second intercepting wall 2032 include organic insulating materials such as polyimide and epoxy resin.
  • the number of sub-insulating layers of the second intercepting wall 2032 is greater than the number of sub-insulating layers of the first intercepting wall 2031 , so the second intercepting wall 2032 is higher than the first intercepting wall 203 .
  • the first blocking wall 2031 is formed on the same layer as the planarization layer 1016 and the pixel defining layer 1017
  • the second blocking wall 2032 is formed on the same layer as the planarizing layer 1016, the pixel defining layer 1017 and the spacer 108, which simplifies the The preparation process of the display substrate.
  • the second blocking wall 2032 can also be formed in the same layer as the planarization layer 1016 and the spacer 108 , or formed in the same layer as the pixel defining layer 1017 and the spacer 108 , which is the embodiment of the present disclosure. Not limited.
  • the organic functional layer 1042 may be formed in the opening of the pixel defining layer 1017 by inkjet printing or evaporation, and then the cathode layer 1043 may be formed.
  • an auxiliary light-emitting layer (not shown) can also be formed between the organic functional layer 1042 and the anode layer 1041 or between the organic functional layer 1042 and the cathode layer 1043, and the auxiliary light-emitting layer includes, for example, an electron injection layer, an electron transport layer, a hole One or more of an injection layer and a hole transport layer.
  • the cathode layer 1043 and the auxiliary light emitting layer are formed on the entire surface of the display substrate, for example, and are disconnected at the barrier walls 202 and the crack barrier walls 204 .
  • the material of the organic functional layer 1042 and the material of the auxiliary light-emitting layer are organic materials, and the material of the organic functional layer 1042 can be selected from a light-emitting material that can emit light of a certain color (eg, red light, blue light, or green light, etc.) according to requirements.
  • the material of the cathode layer 1043 may include metals such as Mg, Ca, Li or Al or their alloys, or metal oxides such as IZO, ZTO, or PEDOT/PSS (poly3,4-ethylenedioxythiophene/polystyrenesulfonic acid). salt) and other organic materials with conductive properties.
  • an encapsulation layer 105 may be formed on the display area 201 and the barrier wall 202 .
  • forming the encapsulation layer 105 includes sequentially forming a first inorganic encapsulation layer 1051 , a first organic encapsulation layer 1052 and a second inorganic encapsulation layer 1053 on the barrier wall 202 and in the display area 201 .
  • the first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 are formed by deposition or the like.
  • the first organic encapsulation layer 1052 is formed by inkjet printing. As shown in FIG. 14B , due to the intercepting effect of the first intercepting wall 2031 , the first organic encapsulation layer 1052 is terminated at the first intercepting wall 2031 .
  • the first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 may be formed of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc.
  • the first organic encapsulation layer 1052 may be formed of polyimide (PI), epoxy Resin and other organic materials.
  • PI polyimide
  • the first inorganic encapsulation layer 1051 , the first organic encapsulation layer 1052 and the second inorganic encapsulation layer 1053 are formed as a composite encapsulation layer, and the composite encapsulation layer can form multiple protections for the functional structure of the display area 201 and the structure such as the barrier wall 202 . , with better encapsulation effect.
  • other necessary functional film layers may also be formed in the display area 101 and the blocking area 201 as required, and these film layers may be formed by conventional methods, which will not be repeated here.
  • the through holes 301 may be formed by means of laser cutting or mechanical punching.
  • the through hole 301 penetrates through the base substrate 1011, and structures such as an image sensor, an infrared sensor, etc. can be installed in the through hole 301, and the through hole 301 can be connected to a signal such as a central processing unit.
  • the image sensor or infrared sensor and other structures can be arranged on the side of the base substrate 1011 away from the light-emitting device (ie, the non-display side of the display substrate), and the through holes 301 can be used to realize photographing, facial recognition, infrared sensing, etc. a function.
  • structures such as a polarizer and a cover plate may also be formed on the display substrate, which is not limited in the embodiment of the present disclosure.
  • the display substrate formed by the preparation method provided by the embodiment of the present disclosure combines the imaging device with the display area of the display substrate, and utilizes at least part of the organic functional layer and the driving structure layer in the display area to form a height difference to form a blocking area, so that the organic The functional layer is separated from the through hole, which can effectively prevent impurities such as water and oxygen from entering the display area of the display substrate from the through hole, thereby improving the reliability of the display substrate.
  • the shift register circuit to be electrically connected with the first signal line and at least one loop of crack detection lines located in the blocking region, crack detection of the through hole can be realized.
  • the driving structure layers By multiplexing at least part of the driving structure layers as crack detection lines, the area of the non-display area is not increased due to the provision of crack detection lines, which ensures the maximization of the display area of the display substrate.
  • the display substrate provided by the embodiment of the present disclosure or the display substrate obtained by using the preparation method provided by the embodiment of the present disclosure can be used in a display device, and the display device can be a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, Any product or component with a display function, such as a navigator, is not limited in the embodiments of the present disclosure.

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Abstract

一种显示基板及显示装置，包括：衬底基板，包括显示区、周边区和阻隔区，周边区围绕显示区，显示区围绕阻隔区；通孔，位于阻隔区，显示基板的中心和通孔的中心不重合；多个子像素，位于显示区；多条信号线，位于显示区、周边区和阻隔区，且电连接多个子像素，多条信号线包括第一信号线；移位寄存电路，位于周边区且电连接多条信号线；至少一圈裂纹检测线，位于阻隔区且围绕通孔，至少一圈裂纹检测线与第一信号线电连接，且第一信号线与多个子像素中的至少一个子像素电连接。

Description

显示基板及显示装置
本申请要求于2020年09月16日提交中国专利局、申请号为202010976764.X、发明名称为显示基板及其制备方法、显示装置的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
目前，显示器件的显示屏正往大屏化、全屏化方向发展。通常，显示器件(例如手机、平板电脑等)具有摄像装置(或成像装置)，例如，可以将摄像装置与显示屏的显示区域结合在一起，在显示区域中通过打孔为摄像装置预留位置，以获得显示屏显示区域的最大化。然而，在显示面板的生产过程中，打孔位置处容易产生裂纹，造成显示面板信号断裂、封装失效等，最终造成显示异常。
基板裂纹检测(Panel Crack Detection，PCD)技术已经广泛应用于显示面板检测中。现有的裂纹检测技术需要在显示屏切割边缘占据一定位置，影响了显示屏显示区域的最大化。
发明内容
本公开至少一实施例提供一种显示基板，包括：
衬底基板，包括显示区、周边区和阻隔区，所述周边区围绕所述显示区，所述显示区围绕所述阻隔区；
通孔，位于所述阻隔区，所述显示基板的中心和所述通孔的中心不重合；多个子像素，位于所述显示区；
多条信号线，位于所述显示区、周边区和阻隔区，且电连接所述多个子像素，所述多条信号线包括第一信号线；
移位寄存电路，位于所述周边区且电连接所述多条信号线；
至少一圈裂纹检测线，位于所述阻隔区且围绕所述通孔，所述至少一圈裂纹 检测线与所述第一信号线电连接，且所述第一信号线与所述多个子像素中的至少一个子像素电连接。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中，所述移位寄存电路包括多个移位寄存单元，所述第一信号线与所述多个移位寄存单元中的一个电连接。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中，所述移位寄存电路为栅极移位寄存电路，所述第一信号线为扫描信号线；或
所述移位寄存电路为发光控制移位寄存电路，且所述第一信号线为发光控制信号线。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，还包括至少一个第一搭接结构，其中，所述第一信号线与所述至少一圈裂纹检测线通过所述至少一个第一搭接结构电连接，所述至少一个第一搭接结构与所述至少一圈裂纹检测线位于不同层，且通过过孔电连接。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中，所述至少一个第一搭接结构的数量为两个，所述第一信号线包括第一子走线和第二子走线，所述两个第一搭接结构分别电连接所述第一子走线和所述至少一圈裂纹检测线的第一端，以及所述第二子走线和所述至少一圈裂纹检测线的第二端。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中，所述至少一圈裂纹检测线的数量为多圈，所述多圈裂纹检测线为连续走线且围绕所述通孔。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，还包括至少一个第二搭接结构，其中，相邻两圈裂纹检测线之间通过所述至少一个第二搭接结构电连接，所述至少一个第二搭接结构与所述相邻两圈裂纹检测线位于不同层且通过过孔电连接。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中，所述至少一圈裂纹检测线的数量为四圈，沿靠近所述通孔中心的径向方向，分别包括第一检测子走线、第二检测子走线、第三检测子走线和第四检测子走线，所述第一检测子走线和所述第二检测子走线通过一个第二搭接结构电连接，所述第二检测子走线、所述第三检测子走线和所述第四检测子走线中的任意两者通过两个所述第二搭接结构电连接。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，还包括位于所述衬底基板一侧的第一多层绝缘层，其中，所述至少一圈裂纹检测线位于所述第一多层绝缘层远离所述衬底基板的一侧。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，还包括位于所述至少一圈裂纹检测线远离所述衬底基板一侧的第一有机功能层，和位于所述第一多层绝缘层远离所述衬底基板一侧的第二有机功能层，所述第一有机功能层和所述第二有机功能层间断设置，且所述第一有机功能层在所述衬底基板的正投影和所述第二有机功能层在所述衬底基板的正投影不交叠。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中，所述至少一圈裂纹检测线包括依次位于所述多层绝缘层远离所述衬底基板一侧的第一子层、第二子层和第三子层，所述第二子层在所述衬底基板的正投影位于所述第一子层和所述第三子层在所述衬底基板的正投影内。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中，所述至少一圈裂纹检测线围绕所述通孔的至少一个侧面具有凹口。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中，所述多个子像素中的至少一个包括：
薄膜晶体管，包括：
位于所述衬底基板上的有源层，
位于所述有源层远离所述衬底基板一侧的栅极，
位于所述栅极远离所述衬底基板一侧的第一绝缘层，
位于所述第一绝缘层远离所述衬底基板一侧的第二绝缘层，和
位于所述第二绝缘层远离所述衬底基板一侧、且电连接至所述有源层的源极和漏极；和
存储电容，包括：
第一极板，与所述第一栅极位于同一层，和
第二极板，位于所述第一绝缘层和所述第二绝缘层之间；和
发光器件，包括：
阳极层，位于所述源极和所述漏极远离所述衬底基板的一侧，
有机功能层，位于所述阳极远离所述衬底基板的一侧，和
阴极层，位于所述有机功能层远离所述衬底基板的一侧。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中， 所述至少一圈裂纹检测线与所述源极或所述漏极位于同一层；
所述第一多层绝缘层至少包括所述第一绝缘层和所述第二绝缘层；
所述第二搭接结构和所述第一搭接结构与所述第二极板位于同一层。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中，所述有机功能层与所述第一有机功能层、所述第二有机功能层的材料相同。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中，还包括至少一个凹槽，所述至少一个凹槽贯穿所述第一绝缘层和至少部分所述第二绝缘层，所述凹槽在所述衬底基板上的正投影与所述至少一圈裂纹检测线在所述衬底基板上的正投影不交叠。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，还包括位于所述至少一圈裂纹检测线靠近所述通孔方向的至少一圈拦截墙，所述至少一圈拦截墙被配置为阻挡封装所述多个子像素的有机封装层。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，其中，所述至少一圈拦截墙包括第一拦截墙和第二拦截墙，所述第一拦截墙位于所述第二拦截墙远离所述通孔的一侧，且所述第一拦截墙在垂直于所述衬底基板方向的最大高度小于所述第二拦截墙在垂直于所述衬底基板方向的最大高度。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，还包括位于所述至少一圈拦截墙靠近所述通孔一侧的至少一圈裂纹阻挡墙。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板，还包括封装层，其中，所述封装层至少封装所述阻隔墙，所述封装层包括在所述至少一圈裂纹检测线上依次叠层设置的第一无机封装层，第一有机封装层以及第二无机封装层。
在一些示例性实施方式中，本公开至少一实施例提供的显示基板还包括图像传感器和/或红外传感器，其中，所述图像传感器和/或红外传感器结合于所述衬底基板，并且在所述衬底基板上的正投影与所述通孔至少部分交叠。
本公开实施例还提供了一种显示装置，包括上述实施例的显示基板。
本公开实施例还提供了一种显示基板的制备方法，包括：形成衬底基板，包括显示区、周边区和阻隔区，所述周边区围绕所述显示区，所述显示区围绕所述阻隔区；通孔，位于所述阻隔区，所述显示基板的中心和所述通孔的中心不重合；多个子像素，位于所述显示区；多条信号线，位于所述显示区、 周边区和阻隔区，且电连接所述多个子像素，所述多条信号线包括第一信号线；移位寄存电路，位于所述周边区且电连接所述多条信号线；至少一圈裂纹检测线，位于所述阻隔区且围绕所述通孔，所述至少一圈裂纹检测线与所述第一信号线电连接，且所述第一信号线与所述多个子像素中的至少一个子像素电连接。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1A为一种显示基板的平面示意图；
图1B为一种显示基板的平面示意图；
图2A为图1B中的显示基板隔离区201的放大示意图；
图2B为图1B、图2A中的显示基板沿A-A线的截面示意图；
图2C为图1B中的显示基板沿B-B线的截面示意图；
图3A为本公开至少一实施例提供的图1B中的显示基板阻隔区201的放大示意图；
图3B为图3A中的显示基板沿C-C线的截面示意图；
图4A为本公开至少一实施例提供的图1B中的显示基板阻隔区201的放大示意图；
图4B为图4A中的显示基板沿D-D线的截面示意图；
图4C为本公开至少一实施例提供的图4A中的显示基板沿D-D线的截面示意图；
图5为本公开至少一实施例提供的一种显示基板的裂纹检测线连接方式的示意图；
图6为本公开至少一实施例提供的一种显示基板的裂纹检测线连接方式的示意图；
图7A为本公开至少一实施例提供的一种显示基板中阻隔墙的截面示意图；
图7B为本公开至少一实施例提供的一种显示基板中第一拦截墙的截面示意图；
图7C为本公开至少一实施例提供的一种显示基板中裂纹阻挡墙的截面示意图；
图7D为本公开至少一实施例提供的一种显示基板中第二拦截墙的截面示意图；
图8A为本公开至少一实施例提供的一种显示基板的部分截面示意图；
图8B为本公开至少一实施例提供的一种显示基板中裂纹阻挡墙的另一截面示意图；
图9A为本公开至少一实施例提供的一种显示基板的部分截面示意图；
图9B为本公开至少一实施例提供的一种显示基板中阻隔墙的另一截面示意图；
图9C为本公开至少一实施例提供的一种显示基板中裂纹阻挡墙的另一截面示意图；
图10A-图10C、图11A-图11B、图12A-图12B、图13A-图13B以及图14A-图14B为本公开至少一实施例提供的一种显示基板在制备过程中的截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右” 等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
为实现显示装置的显示区域的最大化，可以将显示装置所具有的摄像装置(成像装置)与显示区域整合在一起，将摄像装置布置在显示区域之中，通过打孔在显示区域中为摄像装置预留位置。例如，图1A示出了一种用于显示装置的显示基板的平面示意图，显示基板10包括显示区域12，显示区域12包括像素阵列且具有在像素阵列中的通孔11，该通孔11为摄像装置(未示出)预留位置，摄像装置可以设置在通孔11的背离显示基板显示面的一侧，从而摄像装置可以通过通孔11获取图像。由此，将摄像装置与显示基板10的显示区域12整合在一起。
显示区域12具有用于显示的发光器件，例如该发光器件为有机发光二极管(OLED)，显示区域12的全部或部分中的多个发光器件具有的有机材料层和驱动结构层通常在显示区域12中形成为一整面，因此采用封装层进行封装时，位于通孔11附近的区域往往难以被封装，或者即使被封装，也难以保证该区域的封装效果。其次，由于通孔切割工艺波动、激光热效应、搬运等影响，部分显示基板在生产过程中产生裂纹，导致封装失效。此时，例如水、氧等杂质可以从通孔11进入到显示区域12内部，污染显示区域12中的功能层，导致这些功能层的性能退化，进而影响显示区域12的显示效果。
一方面，要提升通孔11附近的封装效果；另一方面，需要在生产阶段筛选出这些封装失效的显示面板，以避免流入后续工艺过程中造成浪费，或是流入到客户端对产品带来不良影响。
相关技术中，基板裂纹检测(Panel Crack Detection，PCD)技术已经广泛应用于显示面板裂纹检测中。裂纹检测技术通常将裂纹检测线设置在显示区域12的周边区域13，其中，周边区环绕显示区域12设置。裂纹检测技术通常利用金属检测线的阻值改变(因金属检测线产生裂纹甚至断开导致的阻值改变)实现显示面板周边区的裂纹检测。由于通孔区域驱动结构层复杂，在 通孔11设置裂纹检测线会增加工艺成本和制造难度、降低良率，且设置裂纹检测线会占据一定的显示面积，导致显示区域面积减小，所以相关技术中在通孔11区域不设置裂纹检测线。
本公开至少一实施例提供一种显示基板，该显示基板包括：衬底基板，包括显示区、周边区和阻隔区，周边区围绕显示区，显示区围绕阻隔区；通孔，位于阻隔区，显示基板的中心和通孔的中心不重合；多个子像素，位于显示区；多条信号线，位于显示区、周边区和阻隔区，且电连接所述多个子像素，多条信号线包括第一信号线；移位寄存电路，位于周边区且电连接多条信号线；至少一圈裂纹检测线，位于阻隔区且围绕通孔，至少一圈裂纹检测线与第一信号线电连接，且第一信号线与多个子像素中的至少一个子像素电连接。
该显示基板利用显示区域12的有机功能层和驱动结构层的至少部分形成高度差，以形成阻隔区，使得有机功能层与通孔隔开，可以有效地防止水氧等杂质从通孔进入到显示基板的显示区。通过复用阻隔区的至少部分驱动结构层为裂纹检测线，不增加因设置裂纹检测线而导致的非显示区域面积增加，保证了显示基板显示区域的最大化。利用移位寄存电路和第一信号线、位于阻隔区的至少一圈裂纹检测线电连接，实现通孔的裂纹检测。
下面通过几个具体的实施例对本公开一些实施例的显示基板及其制备方法进行说明。
图1B示出了一种显示基板100的平面示意图。该显示基板100包括显示区101、周边区401、阻隔区201和通孔301，显示基板的中心和所述通孔的中心不重合。通孔301允许来自显示基板100的显示侧的光传输通过显示基板100，从而到达显示基板100的背侧。显示区101和阻隔区201围绕通孔301，阻隔区201位于显示区101和通孔301之间。
在示例性实施方式中，显示基板包括显示区域、位于显示区域一侧的绑定区域和位于显示区域其它侧的周边区域，显示区包括规则排布的多个子像素，每个子像素连接到至少一条栅线和至少一条数据线(栅线和数据线统称为驱动信号线)，绑定区域和边缘区域设置有驱动电路，驱动电路配置为向显示区域提供显示信号。在示例性实施方式中，驱动电路可以包括：设置在显示区域两侧的移位寄存电路(Gate Driver On Array，简称GOA)电路，配置为向显示区域提供扫描信号；设置在绑定区域的源驱动电路(Driver IC)，配置为 向显示区域提供数据信号(Data)。移位寄存电路由级联的多级(说明书附图中用n表示级联关系，n≥2，n为自然数)移位寄存单元构成。移位寄存电路包括栅极移位寄存驱动电路(Gate GOA)和发光控制移位寄存电路(EM GOA)。相关技术中，栅极移位寄存驱动电路输出两类信号：复位信号(Reset)和栅极扫描信号(Gate)，当像素电路接收到复位信号低电位脉冲时，则显示区域12的至少一行子像素被初始化，并在随后而来的栅极扫描信号作用下，写入新的数据信号。发光控制移位寄存电路输出发光控制信号(EM)。发光控制信号在初始化、数据信号写入过程中禁止子像素发光，在数据信号正确读入后开启子像素发光，并控制发光时间。
如图2A所示，其中，图2A为图1B中的阻隔区201的局部放大示意图。阻隔区201包括多条信号线210，多条信号线210与显示区101的驱动信号线(图中未示出)电连接，多条信号线210在阻隔墙202的靠近101显示区的一侧。多条信号线可以传输相同的信号，也可以传输至少部分不同的信号。例如，多条信号线传输不同的信号时，多条信号线可以包括栅极扫描信号线，发光控制信号线，以及数据信号线等。位于阻隔区的多条信号线与显示区101中的驱动信号线一一对应电连接，从而实现通孔301绕线。
如图2B所示，阻隔区201还包括从显示区101到通孔301方向(即图2B中的从右至左的方向)依次排列的阻隔墙202、拦截墙203以及裂纹阻挡墙204。阻隔墙202、拦截墙203以及裂纹阻挡墙204均围绕通孔301。阻隔区201可以隔离显示区101与通孔301，从而达到保护显示区101的作用。为清楚显示，图2A中未示出拦截墙203，拦截墙203位于阻隔墙202和裂纹阻挡墙204之间。例如，阻隔墙202、拦截墙203以及裂纹阻挡墙204的个数可以为一个或者多个，图2B中示出两个阻隔墙202、一个拦截墙203以及两个裂纹阻挡墙204作为示例，但这并不构成对本公开实施例的限制。
在示例性实施方式中，如图2B和2C所示，显示基板100包括衬底基板1011。在一些示例中，显示基板100可以为柔性显示基板，此时，衬底基板1011可以为聚酰亚胺(PI)等柔性绝缘材料。在另一些示例中，衬底基板1011也可以为玻璃等刚性显示基板。
显示基板100还可以包括设置在衬底基板1011上的阻挡层1012和缓冲层1013，阻挡层1012可以防止水氧等杂质从衬底基板1011渗入到薄膜晶体管102等功能结构中，缓冲层1013可以提供平坦的表面，以便于显示基板其他 功能层的设置。阻挡层1012和缓冲层1013可以共同对衬底基板1011上的其他功能结构起到保护作用。
在示例性实施方式中，如图2C所示，显示基板100的驱动结构层包括薄膜晶体管102和存储电容103等结构。薄膜晶体管102包括依次设置在衬底基板1011上的有源层1021、栅极1022、第一绝缘层1014(例如包括第一绝缘子层1014A和第一绝缘子层1014B)，第二绝缘层1015和源漏电极(包括源极1024和漏极1023)。例如，源漏电极均具有三层金属层结构，例如钛/铝/钛、钼/铝/钼、钛/铜/钛或者钼/铜/钼等三层金属层结构。存储电容103包括第一极板1031和第二极板1032。例如，第一极板1031与栅极1022同层设置，第二极板1032在第一绝缘层1014和第二绝缘层1015之间。
例如，在一些实施例中，位于阻隔区的多条信号线210与第二极板1032、第一极板1031、源漏电极1023/1024至少部分同层设置。
本公开的实施例中，两个或更多个功能层同层设置指的是这些同层设置的功能层可以采用相同的材料层并利用相同制备工艺(例如构图工艺等)形成，从而可以简化显示基板的制备工艺。由此，这些同层设置的功能层可以采用相同的材料层并通过相同的构图工艺形成，以简化显示基板的制备工艺。
在示例性实施方式中，显示基板100的显示区101还包括平坦化层1016、像素界定层1017以及隔垫物1018。平坦化层1016用于平坦化薄膜晶体管102，像素界定层1017在平坦化层1016远离薄膜晶体管102的一侧，像素界定层1017用于界定多个子像素。隔垫物1018在像素界定层1017远离平坦层1016的一侧。
在示例性实施方式中，显示区101包括多个子像素，其中，子像素包括驱动结构层和发光器件104，其中，驱动结构层包括多条驱动信号线，驱动信号线驱动发光器件104实现发光。这里，发光器件104例如可以为有机电致发光显示装置(organic light-emitting diode，简称OLED)或量子点电致发光显示装置(quantum dot light emitting diode，简称QLED)。
在一些实施例中，发光器件104包括阳极层1041，有机功能层1042以及阴极层1043。有机功能层1042位于阳极层1041和阴极层1043之间。阳极层1041通过平坦层1016中的过孔连接到薄膜晶体管的漏极1023。有机功能层1042还可以包括辅助发光层(图中未示出)，例如包括电子传输层、电子注入层、空穴传输层以及空穴注入层中的一种或多种。辅助发光层例如为有 机材料层。例如，有机功能层1042也可以在衬底基板1011上整面形成，并在阻隔墙202和裂纹阻挡墙204处断开。例如，阴极层1043在衬底基板1011上整面形成，并在阻隔墙202和裂纹阻挡墙204处断开。例如，阻隔墙202和裂纹阻挡墙204的顶部上也形成有部分的有机功能层1042和阴极层1043，但是这些部分与其他部分相分离。
例如，本公开示例性实施例中，如图3B所示，阻隔区201包括与有机功能层1042同层同材料设置的第一有机功能层10421与第二有机功能层10422。第一有机功能层10421位于至少一圈裂纹检测线远离衬底基板一侧，第二有机功能层位于第一多层绝缘层202A远离所述衬底基板一侧。第一有机功能层10421和第二有机功能层10422间断设置，且第一有机功能层10421在衬底基板的正投影和第二有机功能层10422在衬底基板的正投影不交叠。
由此，当位于靠近通孔301一侧的有机功能层被水、氧等杂质污染时，由于有机功能层被阻隔墙202和裂纹阻挡墙204断开，使得这些污染杂质不会延伸至有机功能层用于发光器件进行发光的部分中。
例如，本公开示例性实施例中，如图3A和图3B所示，阻隔区还包括至少一圈裂纹检测线202B，且围绕通孔设置。其中，裂纹检测线202B构成阻隔墙202的至少部分，也即，第一阻隔墙202的至少部分复用为裂纹检测线202B。例如，裂纹检测线202B与源漏电极1023/1024同层设置。因显示基板的驱动结构层包括源漏电极1023/1024，也即，显示基板的至少部分驱动结构层的复用为至少一圈裂纹检测线202B。
例如，如图3A所示，裂纹检测线202B设置于靠近显示区的一侧的阻隔墙上。在另一些实施例中，阻隔区201包含多个阻隔墙202，至少一圈裂纹检测线202B设置于任意一圈阻隔墙上。
例如，至少一圈裂纹检测线202B具有三层金属层结构，例如钛/铝/钛、钼/铝/钼、钛/铜/钛或者钼/铜/钼等三层金属层结构。例如，如图7A所示，图7A示出了一种阻隔墙202的截面示意图，至少一圈裂纹检测线202B包括依次位于第一多层绝缘层202A远离衬底基板一侧的第一子层2045、第二子层2046和第三子层2047，第二子层2046在所述衬底基板的正投影位于所述第一子层2045和所述第三子层2046在所述衬底基板的正投影内。
例如，在一些实施例中，阻隔墙202还可以包括第一多层绝缘层202A，裂纹检测线202B位于第一多层绝缘层202A上。例如，第一多层绝缘层202A 包括多个绝缘子层，例如图7A中示出为包括绝缘子层2021和2022。例如，绝缘子层2021与第一绝缘层1014同层设置，绝缘子层2022与第二绝缘层1015同层设置。
例如，如图7A所示，阻隔墙202的宽度W1可以为2μm-4μm，例如3μm或者3.5μm等。
例如，在一些示例中，衬底基板上包括的阻挡层和缓冲层的个数可以为更多个，此时，第一多层绝缘层202A的第二部分可以与更多个阻挡层和缓冲层同层设置。
例如，在一些示例中，如图9B所示，阻隔墙202的第一多层绝缘层202A包括叠层设置的第一部分(包括绝缘子层2021和2022)和第二部分(包括绝缘子层2026和2027)，第一部分至少与第一绝缘层1014和第二绝缘层1015同层设置，第二部分至少与阻挡层1012和缓冲层1013同层设置。另外，为示出清楚以及简明，阻隔区201中第一绝缘层1014在附图只示出为一层。
例如，第一多层绝缘层202A的第一部分和第二部分的宽度不同，例如第二部分宽于第一部分，从而第一多层绝缘层202A的纵截面整体呈阶梯状，如图9B所示。
在一些实施例中，多条信号线210中包括第一信号线211。其中，第一信号线211为与裂纹检测线202B电连接的多条信号线210中的一条。
例如，请再次参见图3A，至少一圈裂纹检测线202B包括至少一个第一搭接结构220A。用于将至少一圈裂纹检测线与第一信号线211电连接。
例如，如图3A所示，第一搭接结构220A的数量为两个2201和2202，两个第一搭接结构2201和2202分别电连接第一信号线的第一子走线2111和至少一圈裂纹检测线202B的第一端，以及至少一圈裂纹检测线202B的第二端和第二子走线2112。其中，第一子走线2111和第二子走线2112属于第一信号线211的部分。两个第一搭接结构220A可以位于通孔301的径向的相对侧，也可以位于通孔301的径向的同一侧，或是位于通孔301的径向的任意侧，此处不做限制。
例如，第一信号线211、第一搭接结构220A与第二极板1032同层设置。第一搭接结构220A与阻隔墙的至少一圈裂纹检测线202B通过过孔电连接，过孔贯穿第二绝缘层1015以暴露出第一搭接结构220A。在另外一些实施例中，第一信号线211、第一搭接结构220A与第一极板1031同层设置。第一 搭接结构220A与至少一圈裂纹检测线202B通过过孔电连接，过孔贯穿第一绝缘层1014和第二绝缘层1015以暴露出第一搭接结构220A。设置第一搭接结构可以消除裂纹检测线上的静电累积效益。
例如，在另外一些实施例中，第一信号线211、第一搭接结构220A与源漏电极1023/1024同层设置。此时不需要设置过孔同样可实现第一信号线211、第一搭接结构220A、至少一圈裂纹检测线202B电连接。换言之，此时也可以不设置第一搭接结构220A。
例如，在一些实施例中，第一搭接结构220A可以为多层，比如至少部分与第一极板1031同层，且至少部分与第二极板1032同层，第一搭接结构220A的多层结构互相电连接，并通过过孔与至少一圈裂纹检测线202B电连接，多层设置的第一搭接结构可以消除裂纹检测线上的静电累积效益。
例如，在一些实施例中，裂纹检测线202B的数量为多圈，多圈裂纹检测线为连续走线且围绕所述通孔。
例如，如图4A、图4B和图4C示出的示例中，图4B为图4A沿着D-D线的部分截面示意图，至少一圈裂纹检测线202B包括至少一个第二搭接结构220B，其中，相邻两圈裂纹检测线之间通过所述至少一个第二搭接结构220B电连接，其中，至少一个第二搭接结构与所述相邻两圈裂纹检测线位于不同层且通过过孔电连接。
例如，如图4A、图4B和图4C示出的示例中，至少一圈裂纹检测线202B的数量为四圈，沿靠近通孔301中心的径向方向，分别包括第一检测子走线2021、第二检测子走线2022、第三检测子走线2023和第四检测子走线2024，第一检测子走线2021和第二检测子走线2022通过至少一个第二搭接结构220B通过过孔电连接，第二检测子走线2022、第三检测子走线2023和第四检测子走线2024中的任意两者通过至少两个第二搭接结构220B通过过孔电连接。从而，实现多圈裂纹检测线202B环绕通孔301设置，多圈裂纹检测线202B通过多个第二搭接结构220B连接成一条连续不断裂的环形金属线。多个第二搭接结构220B可以在通孔301的径向间隔分布，此处对多个第二搭接结构220B的个数和分布位置不做限制，但为了实现阻隔墙与裂纹阻挡墙204一起达到双重阻隔效果，多个第二搭接结构220B在通孔301的径向上分布不交叠。类似的，设置多个第二搭接结构可以消除裂纹检测线上的静电累积效益。
例如，搭接结构220可以与第二极板同层设置，如图4B所示；也可以与第一极板同层设置，如图4C所示；也可以部分与第一极板同层设置且部分与第二极板同层设置，图中未示出。在又一些实施例中，第二搭接结构220B可以为多层，比如至少部分与第一极板1031同层，且至少部分与第二极板1032同层，第二搭接结构220B的多层结构互相电连接，并通过过孔与至少一圈裂纹检测线202B电连接。
第一搭接结构220A和第二搭接结构220B均属于搭接结构220，可以采用相同的材料层并通过相同的构图工艺形成，以简化显示基板的制备工艺。
例如，在一些实施例中，如图5所示，显示基板100包括位于周边区且电连接所述多条信号线210的移位寄存电路19。移位寄存电路19包括多个级联的移位寄存单元193。移位寄存电路19可以包括栅极移位寄存电路191(Gate GOA)，或者发光控制移位寄存电路192(EM GOA)。栅极移位寄存电路191包括多个级联的移位寄存单元193，发光控制移位寄存电路192包括多个级联的移位寄存单元193。其中，附图中栅极移位寄存电路191和发光控制移位寄存电路192的设置仅作为示例。如图5所示，栅极移位寄存电路191和发光控制移位寄存电路192设置于显示基板100的相对侧，当然现实基板的移位寄存电路可以有不同的设置方式，此处不做限制。
例如，显示基板100的驱动结构层包含移位寄存电路19，移位寄存电路19与显示区的多个子像素18电连接，并逐行驱动多个子像素18，实现显示。显示基板100还包括位于显示面板至少一侧的绑定区17。绑定区17与移位寄存电路19电连接。其中，多条驱动信号线221中的至少一条与第一信号线211电连接。其中，与第一信号线211电连接的驱动信号线与多个子像素18中的至少一个电连接。换言之，第一信号线211与至少一个子像素18电连接。
例如，第一信号线211与多个栅极移位寄存电路191的一个移位寄存单元电连接，则与第一信号线211电连接的驱动信号线即栅极扫描信号线中的一条。例如，第一信号线211与多个发光控制移位寄存电路192的一个移位寄存单元电连接，则与第一信号线211电连接的驱动信号线即发光控制信号线中的一条。
在一种示例性的实施例中，如通孔301产生裂纹，阻隔墙202的至少一圈裂纹检测线202B产生裂纹(或者断开)，则该至少一圈裂纹检测线202B的电阻值增加。由此，与该裂纹检测线电连接的第一信号线211所在行的电阻 值增加，与其电连接的至少一个子像素所在行的电阻值发生改变(比如增加)，造成驱动结构层驱动该子像素18的发光器件104的发光亮度发生改变，也即，显示异常，从而实现通孔301裂纹检出。
本公开实施例提供的显示基板中，通过复用阻隔区的至少部分驱动结构层为裂纹检测线，不增加因设置裂纹检测线而导致的非显示区域面积增加，保证了显示基板显示区域的最大化。利用移位寄存电路和第一信号线、位于阻隔区的至少一圈裂纹检测线电连接，实现通孔的裂纹检测，提高了显示基板的信赖性。
例如，在一些实施例中，如图6所示，显示基板100包括位于周边区的裂纹检测线16。裂纹检测线16实现对显示基板的周边区的裂纹检测。裂纹检测线搭接到绑定区17，通过位于绑定区的信号控制结构实现显示基板100的裂纹检测。
在一种示例性的实施例中，在进行裂纹检测时，通过绑定区的信号控制结构向裂纹检测线16一端施加检测信号，通过同样位于绑定区的裂纹检测线16的另一端点接收信号，根据接收信号的状态可以判断显示面板是否产生裂纹。由于裂纹检测线为一个整体回路，当显示面板的周边区任意位置产生裂纹时，可根据接收信号超过预设范围而判断出裂纹产生。在一些实施例中，裂纹检检测线因为通孔301产生部***纹(或者断开)，其电阻值变大(或者超过预设范围值)，则位于绑定区的接收信号端判断出裂纹产生，实现裂纹检测。
本公开实施例提供的显示基板中，能够利用显示基板的裂纹检测线16实现对通孔301的裂纹检测，提高了显示基板的信赖性。
在一种示例性的实施例中，请再次参见图3B和图7A，阻隔墙202包括至少一圈裂纹检测线202B，至少一圈裂纹检测线202B围绕通孔301的至少一个侧面具有凹口。在另一种示例性的实施例中，至少一圈裂纹检测线202B面向通孔301的侧面和背离通孔301的侧面均具有凹口。阻隔墙202可以断开显示基板上整面形成的功能层，例如发光器件的有机功能层1042以及阴极层1043等。
在一种示例性的实施例中，请再次参见图3B，阻隔区还包括至少一个凹槽206，凹槽206位于拦截墙203与阻隔墙202之间，且贯穿第一绝缘层1014和至少部分第二绝缘层1015，所述凹槽在所述衬底基板上的正投影与所述至 少一圈裂纹检测线在所述衬底基板上的正投影不交叠。凹槽206可以在生成第一绝缘层1014和第二绝缘层1015时通过构图工艺与第一绝缘层和/或第二绝缘层同时生成，也可以在生成第一绝缘层1014和第二绝缘层1015之后，通过比如曝光、显影、刻蚀等工艺再生成。凹槽的个数可以为一个，即在拦截墙203与阻隔墙202之间。在另一些实施例中，凹槽的个数可以为多个，比如在多个阻隔墙之间。凹槽的个数和位置不对本公开构成限制。当然，在另一些实施例中，也可以不设置凹槽。第一多层绝缘层202A以及至少一个凹槽206的设置可增强阻隔墙202的阻隔效果，并有利于之后在阻隔墙202上例如通过沉积等方式形成的第一无机封装层1051(稍后介绍)可以更好地沿阻隔墙202的表面形貌形成。
在一种示例性的实施例中，请再次参见图3B，阻隔区201包括从显示区101到通孔301方向(即图3B中的从右至左的方向)依次排列的阻隔墙202、拦截墙203以及裂纹阻挡墙204，阻隔墙202、第一拦截墙203以及裂纹阻挡墙204均围绕通孔301。其中，拦截墙203的数量为至少一圈，且围绕通孔设置。至少一圈拦截墙203被配置为阻挡封装多个子像素的有机封装层。
例如，例如图7B示出，拦截墙203包括第二多层绝缘层，第二多层绝缘层例如包括多个子绝缘层的叠层，例如包括两个子绝缘层20311和20312的叠层。拦截墙203可以拦截显示区101中形成的一些功能层(例如有机封装层)，防止这些功能层的材料靠近或进入通孔301。拦截墙203被配置为阻挡封装所述多个子像素的有机封装层材料。
例如，绝缘子层20311和20312与平坦化层1016、像素界定层1017和隔垫物1018中的两种一一对应且同层设置。例如，拦截墙203的第二多层绝缘层与平坦化层1016、像素界定层1017和隔垫物1018中的至少一种同层设置。例如，绝缘子层20311与平坦化层1016同层设置，绝缘子层20312与像素界定层1017同层设置；或者，绝缘子层20311与平坦化层1016同层设置，绝缘子层20312与隔垫物1018同层设置；或者，绝缘子层20311与像素界定层1017同层设置，绝缘子层20312与隔垫物1018同层设置。由此，在制备工艺中这些同层设置的功能层可以采用相同的材料层并通过相同的构图工艺形成。
例如，在一些实施例中，如图3B和7D所示，至少一圈拦截墙包括第一拦截墙2031和第二拦截墙2032。第二拦截墙2032与第一拦截墙2031相邻且在第一拦截墙2031远离显示区101的一侧,且第一拦截墙2031在垂直于所述衬 底基板方向的最大高度小于第二拦截墙2032在垂直于所述衬底基板方向的最大高度。由此，第二拦截墙2032与第一拦截墙2031一起可以达到双重拦截效果。
例如，在一些示例中，如图7D所示，第二拦截墙2032包括多个绝缘子层，图7D中示出为包括绝缘子层20321、20322和20323，例如，绝缘子层20321与平坦化层1016同层设置，绝缘子层20322和像素界定层1017同层设置，绝缘子层20323与隔垫物1018同层设置。由此，在制备工艺中，这些同层设置的功能层可以采用相同的材料层并通过相同的构图工艺形成。在上述设置中，第二拦截墙2032高于第一拦截墙2031，可以起到充分的拦截功能，并且第二拦截墙2032与第一拦截墙2031一起可以达到双重拦截效果。
在一种示例性的实施例中，请再次参见图3B和图7C，裂纹阻挡墙204包括金属层结构204B和叠层结构204A，金属层结构204B位于叠层结构204A上，金属层结构204B的围绕通孔301的至少一个侧面具有凹口。例如，金属层结构204B的面向通孔301的侧面和背离通孔301的侧面均具有凹口，即图3B和图7C示出的情况，在其他示例中，也可以在金属层结构204B的一个侧面具有凹口。
例如，请再次参见图7A和7C所示，至少一圈裂纹检测线202B的三个金属子层2023/2024/2025以及裂纹阻挡墙204B的三个金属子层2045/2046/2047分别与源漏电极1023和1024的三层金属层一一对应且材料相同。由此，至少一圈裂纹检测线202B、裂纹阻挡墙204B与源漏电极1023和1024可以采用相同的三层金属材料层并利用相同的构图工艺形成。
例如，在一些示例中，裂纹阻挡墙204的金属层结构204B与阻隔墙202的至少一圈裂纹检测线202B具有相同的结构，并且包括相同的材料。由此，在显示基板的制备工艺中，裂纹阻挡墙204的金属层结构204B与阻隔墙202的至少一圈裂纹检测线202B可以通过相同的材料层通过相同的构图工艺形成，以简化显示基板的制备工艺。
例如，在另外一些实施例中，裂纹阻挡墙204的金属层结构204B与阻隔墙202的至少一圈裂纹检测线202B具有相同的结构，并且包括相同的材料。与前文类似，裂纹阻挡墙204的金属层结构204B同样可以与第一信号线211电连接，实现对通孔301的裂纹检测。即，裂纹阻挡墙204被配置为检测通孔301的裂纹，同样包含在本公开的发明构思内。
例如，在另外一些实施例中，裂纹阻挡墙204、阻隔墙202共同被配置为检测通孔301的裂纹，同样包含在本公开的发明构思内。
例如，在一些实施例中，如图7C所示，裂纹阻挡墙204的叠层结构204A的叠层包括依次设置在衬底基板1011上的第一金属子层2041、第一绝缘子层2042、第二金属子层2043以及第二绝缘子层2044。例如，第一金属子层2041与栅极1022同层设置，第一绝缘子层2042与第一绝缘层1014同层设置，第二金属子层2043与第二极板1032同层设置，第二绝缘子层2044与第二绝缘层1015同层设置。例如，阻隔墙202和裂纹阻挡墙204的结构还可以包括与阻挡层1012和缓冲层1013同层设置的结构。由此，这些同层设置的功能层可以采用相同的材料层并通过相同的构图工艺形成，以简化显示基板的制备工艺。
例如，裂纹阻挡墙204的形式可以为多种。例如，在一些示例中，如图8A和图8B所示，裂纹阻挡墙204的第一绝缘子层2042和第二绝缘子层2044可以与第一金属子层2041和第二金属子层2043具有相同的图案，从而在图8B中体现为具有相同的宽度。此时，在制备工艺中，第一绝缘子层2042和第二绝缘子层2044可以通过进一步的刻蚀工艺以形成相应的图案。
例如，叠层结构204A包括具有金属层和绝缘层的叠层。裂纹阻挡墙204也可以断开显示基板上整面形成的功能层，从而与阻隔墙202一起达到双重阻隔效果，此时，即使阻隔墙202失效，裂纹阻挡墙204由于包括具有金属层和绝缘层的叠层，距离衬底基板1011的垂直距离大于阻隔墙202距离衬底基板1011的垂直距离，裂纹阻挡墙204中会实现阻隔效果；另外，裂纹阻挡墙204靠近通孔301，在例如通过冲压或者切割等方式形成通孔301时，裂纹阻挡墙204还可以防止形成通孔301时可能产生的裂纹进行扩展，且裂纹阻挡墙204由于包括具有金属层和绝缘层的叠层，具有良好的裂纹阻隔效果，从而避免裂纹延伸至显示区101。
又例如，如图9A和图9C所示，裂纹阻挡墙204的叠层结构204A也可以包括两个部分，称为第三部分(包括第一金属子层2041、第一绝缘子层2042、第二金属子层2043以及第二绝缘子层2044)和第四部分(包括绝缘子层2048和2049)，例如，第四部分与阻隔墙的第一多层绝缘层202A的第二部分以及阻挡层1012和缓冲层1013同层设置。由此，在制备工艺中，这些同层设置的功能层可以采用相同的材料层并通过相同的构图工艺形成。例如，第三部 分和第四部分的宽度不同，例如第四部分宽于第三部分，从而叠层结构204A的纵截面整体呈阶梯状。
当阻隔墙202的第一多层绝缘层202A和裂纹阻挡墙204的叠层结构204A的纵截面整体呈阶梯状时，在其上例如通过沉积等方式形成的第一无机封装层1051(稍后介绍)可以更好地沿阻隔墙202和裂纹阻挡墙204的表面形貌形成，而不会出现侧面断裂等不良情况，从而使第一无机封装层1051具有更好的完整性，进而提供更好的封装效果。
类似地，裂纹阻挡墙204的宽度也可以为2μm-4μm，例如3μm或者3.5μm等，本公开的实施例对各结构的尺寸不做具体限定，只要可以实现相应的功能即可。
需要注意的是，为清楚且简明起见，图8A和图9A仅示出了衬底基板1011上的阻隔墙202、第一拦截墙2031、裂纹阻挡墙204、第二拦截墙2032的结构以及部分信号线210，但是，该显示基板还可以包括如图2B示出的其他结构，具体可参照图2B，在此不再赘述。
例如，如图2B和图2C所示，显示基板100还可以包括封装层105，封装层105至少封装阻隔墙202，例如，在一些示例中，封装层105同时封装显示区101(包括多个子像素)以及阻隔墙202。
例如，封装层105包括在阻隔墙202上依次叠层设置的第一无机封装层1051，第一有机封装层1052以及第二无机封装层1053。例如，第一无机封装层1051在显示基板上整面形成，由于第一拦截墙2031的拦截作用，第一有机封装层1052以及第二无机封装层1053终止于第一拦截墙2031。
例如，在一些实施例中，如图2A和2B所示，显示基板100还可以包括：图像传感器和/或红外传感器501，图像传感器和/或红外传感器501结合于显示基板100的非显示侧，并且在衬底基板1011上的正投影与通孔301至少部分重叠。由此，图像传感器和/或红外传感器501可以通过通孔301实现拍照、面部识别、红外感应等多种功能。
本公开实施例提供的显示基板中，阻隔区201可以充分隔离显示区101与通孔301，有效防止水氧等杂质从通孔301进入到显示区101，并且还可以防止形成通孔301时可能产生的裂纹扩展至显示区101，可以有效地防止水氧等杂质从通孔进入到显示基板的显示区。通过复用阻隔区的至少部分驱动结构层为裂纹检测线，不增加因设置裂纹检测线而导致的非显示区域面积增加， 保证了显示基板显示区域的最大化。利用移位寄存电路和第一信号线、位于阻隔区的至少一圈裂纹检测线电连接，实现通孔的裂纹检测。
本公开至少一实施例还提供一种显示基板的制备方法，下面，以形成图4A-图4B所示的显示基板100为例，其中，只示例性的示出了两个阻隔墙202，一个裂纹阻挡墙204以对本公开实施例提供的显示基板的制备方法进行介绍。
首先，提供衬底基板1011，例如，当显示基板100为柔性显示基板时，所提供的衬底基板1011可以为聚酰亚胺(PI)等柔性基板，当显示基板为刚性基板时，衬底基板1011可以为玻璃、石英等刚性基板。
如图10A-图10B所示，首先在衬底基板1011上形成用于显示区101、阻隔区201的功能层，并为通孔301预留位置，以便于显示区101、阻隔区201的功能层形成完成后，通过例如冲压或者切割等方式形成通孔301。
例如，可以通过沉积等方法在衬底基板1011上依次形成阻挡层1012和缓冲层1013。例如，阻挡层1012和缓冲层1013可以整面形成在衬底基板1011上。例如，阻挡层1012可以采用氧化硅、氮化硅、或者氮氧化硅等无机绝缘材料，缓冲层1013也可以采用氧化硅、氮化硅、或者氮氧化硅等无机绝缘材料。
例如，在阻挡层1012和缓冲层1013形成之后，如图10A所示，在显示区101形成薄膜晶体管102以及存储电容103等结构；如图10B所示，在阻隔区201形成裂纹阻挡墙204的叠层结构204A，以及至少部分搭接结构220和多条信号线210。
例如，如图10A-图10C所示，采用构图工艺在衬底基板1011上形成有源层1021；在有源层1021上通过沉积等方式形成第一绝缘层1014A；在第一绝缘层1014A上采用构图工艺同时形成栅极1022、第一极板1031以及第一金属子层2041；在栅极1022、第一极板1031以及第一金属子层2041上通过沉积等方式形成第二绝缘层1014B；采用构图工艺同时形成第二极板1032、第二金属子层2043、以及同层同材料的至少部分搭接结构220、多条信号线210；在第二极板1032以及第二金属子层2043上采用沉积等方式形成第二绝缘层1015；然后，刻蚀第一绝缘层1014以及第二绝缘层1015以形成暴露有源层1024的过孔、以及形成暴露搭接结构220位于第二金属子层2043的过孔2204。例如，一次构图工艺包括光刻胶的形成、曝光、显影以及刻蚀等工艺。
此时，裂纹阻挡墙204的第一金属子层2041与栅极1022同层形成，第一绝缘子层2042与第一绝缘层1014同层形成，第二金属子层2043、以及至搭接结构220和信号线210与第二极板1032同层形成，第二绝缘子层2044与第二绝缘层1015同层形成。由此简化了显示基板的制备工艺。
例如，栅极1022、第一极板1031以及第一金属子层2041的材料包括铝、钛、钴等金属或者合金材料。在制备时，首先采用溅射或者蒸镀等方式形成一层栅极材料层，然后对栅极材料层进行构图工艺，以形成图案化的栅极1022、第一极板1031以及第一金属子层2041。同层形成的其他结构的形成方式与此类似，因此不再赘述。
例如，有源层1021可以采用多晶硅和金属氧化物等材料，第一绝缘层1014可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，第二极板1032以及第二金属子层2043、搭接结构220和信号线210可以采用铝、钛、钴等金属或者合金材料，第二绝缘层1015可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。本公开的实施例对各功能层的材料不做限定，各功能层的材料并不局限于上述示例。
例如，如图10C所示，可以采用一次刻蚀工艺刻蚀位于阻隔区201的第一绝缘层1014和第二绝缘层1015，从而形成阻隔墙202的第一多层绝缘层202A，以及在搭接结构220处生成过孔，形成暴露搭接结构220的过孔2204。由此，第一多层绝缘层202A包括与第一绝缘层1014同层形成的子绝缘层2021和与第二绝缘层1015同层形成的子绝缘层2022。
此时，第一多层绝缘层202A、形成暴露搭接结构220的过孔2204与第一绝缘层1014和第二绝缘层1015同层形成，由此简化了显示基板的制备工艺。
例如，在另一实施例中，显示基板的制备方法还可以形成如图9B示出的阻隔墙202和如图9C示出的裂纹阻挡墙204。此时，可以通过第一刻蚀工艺刻蚀阻隔区201的第一绝缘层1014和第二绝缘层1015，并通过第二刻蚀工艺阻隔区201的阻挡层1012和缓冲层1013，以形成包括第一部分(包括绝缘子层2021和2022)和第二部分(包括绝缘子层2026和2027)的第一多层绝缘层202A以及包括第三部分(包括第一金属子层2041、第一绝缘子层2042、第二金属子层2043以及第二绝缘子层2044)和第四部分(包括绝缘子层2048和2049)的叠层结构204A。
由此，第一多层绝缘层202A的第一部分、叠层结构204A的第三部分中 的绝缘子层与第一绝缘层1014和第二绝缘层1015同层形成；第一多层绝缘层202A的第二部分、叠层结构204A的第四部分与阻挡层1012和缓冲层1013同层形成。由于阻挡层1012、缓冲层1013、第一绝缘层1014和第二绝缘层1015的总体厚度较厚，通过两次刻蚀工艺分别刻蚀其中的一部分有利于刻蚀工艺的顺利进行，并有利于保证最终的刻蚀形貌。
如图10C所示，在上述刻蚀工艺中，还可以同时刻蚀阻挡层1012、缓冲层1013、第一绝缘层1014和第二绝缘层1015靠近通孔301的部分，(即图10C中的左侧虚线框示出的部分)。由于阻挡层1012、缓冲层1013、第一绝缘层1014和第二绝缘层1015中的部分或者全部采用无机绝缘材料制成，由于无机绝缘材料具有脆性，在通过例如冲压或者切割等方式形成通孔301时容易形成裂纹，因此将阻挡层1012、缓冲层1013、第一绝缘层1014和第二绝缘层1015靠近通孔301的部分去除，可以避免形成通孔301时在这些层中产生裂纹。
如图11A和图11B所示，在第二绝缘层1015中的过孔形成后，形成源极1023和漏极1024以及阻隔墙202的至少一圈裂纹检测线202B和裂纹阻挡墙204的金属层结构204B。位于阻隔墙202的至少部分源极1024和漏极1023在搭接结构220的过孔2204处与搭接结构位于第二极板的部分形成电连接，实现搭接。也就是说，搭接结构220(包括第一搭接结构220A和第二搭接结构220B)包括位于第二金属子层2043(第二极板1032同层同材料)、源漏极层(包括源极1024和漏极1023)，两者通过过孔实现电连接。类似的，搭接结构也可以包括第一金属子层2041(第一极板1031)、源漏极层，两者通过过孔实现电连接。
例如，源极1023和漏极1024可以形成为多层金属结构，例如三层金属层结构。例如，在一个示例中，可以采用溅射或者蒸镀等方式依次形成钛材料层、铝材料层以及钛材料层，然后采用同一次构图工艺对三个材料层进行构图，从而形成构成源极1023和漏极1024的钛/铝/钛3三层金属结构，同时形成侧面齐平的初始至少一圈裂纹检测线和初始金属层结构。然后，通过一次刻蚀工艺刻蚀侧面齐平的初始至少一圈裂纹检测线和初始金属层结构，以形成侧面具有凹口的至少一圈裂纹检测线202B和金属层结构204B。例如，该刻蚀工艺使用的刻蚀液仅对至少一圈裂纹检测线202B和金属层结构204B的中间层具有刻蚀效果或者对中间层的刻蚀速率大于对其他层的刻蚀速率， 从而该刻蚀工艺可以形成至少一圈裂纹检测线202B和金属层结构204B的凹口。
由此，源极1023和漏极1024以及阻隔墙202的至少一圈裂纹检测线202B和裂纹阻挡墙204的金属层结构204B、搭接结构220同层形成，简化了显示基板的制备工艺。
如图12A和图12B所示，在薄膜晶体管102以及存储电容103的各膜层形成完成后，依次形成平坦化层1016、阳极层1041、像素界定层1017和隔垫物1018，并同时形成第一拦截墙2031和第二拦截墙2032。
例如，通过构图工艺同层形成平坦化层1016、第一拦截墙2031的绝缘子层20311和第二拦截墙2032绝缘子层20321。例如，平坦化层1016、第一拦截墙203的绝缘子层20311和第二拦截墙2032绝缘子层20321材料的可以采用聚酰亚胺、环氧树脂等有机绝缘材料。形成的平坦化层1016中具有过孔，以便之后形成的阳极层1041通过该过孔与源极1023电连接。
例如，在显示区101的平坦化层1016上采用构图工艺形成阳极层1041，阳极层1041通过平坦化层1016中的过孔与源极1023电连接。例如，阳极层1041的材料包括ITO、IZO等金属氧化物或者Ag、Al、Mo等金属或其合金。
例如，通过构图工艺同层形成像素界定层1017、第一拦截墙2031的绝缘子层20312和第二拦截墙2032的绝缘子层20322。像素界定层1017中具有32暴露阳极层1041的开口，以便之后形成发光器件的有机功能层1042以及阴极层1043等结构。例如，像素界定层1017、第一拦截墙2031的绝缘子层20312和第二拦截墙2032的绝缘子层20322的材料可以包括聚酰亚胺、环氧树脂等有机绝缘材料。
例如，通过构图工艺同层形成隔垫物1018和第二拦截墙2032的绝缘子层20323。隔垫物1018和第二拦截墙2032的绝缘子层20323的材料包括聚酰亚胺、环氧树脂等有机绝缘材料。此时，第二拦截墙2032的子绝缘层数量多于第一拦截墙2031的子绝缘层数量，因此第二拦截墙2032高于第一拦截墙203。
在上述示例中，第一拦截墙2031与平坦化层1016、像素界定层1017同层形成，第二拦截墙2032与平坦化层1016、像素界定层1017和隔垫物108同层形成，简化了显示基板的制备工艺。例如，在其他示例中，第二拦截墙2032也可以与平坦化层1016和隔垫物108同层形成，或者与像素界定层1017 和隔垫物108同层形成，本公开的实施例对此不做限定。
例如，如图13A和图13B所示，可以通过喷墨打印或者蒸镀等方式在像素界定层1017的开口中形成有机功能层1042，然后形成阴极层1043。例如，有机功能层1042与阳极层1041之间或者有机功能层1042与阴极层1043之间还可以形成辅助发光层(未示出)，辅助发光层例如包括电子注入层、电子传输层、空穴注入层以及空穴传输层中的一种或多种。阴极层1043和辅助发光层例如在显示基板上整面形成，并且在阻隔墙202以及裂纹阻挡墙204处断开。
例如，有机功能层1042的材料和辅助发光层的材料为有机材料，有机功能层1042的材料可根据需求选择可发出某一颜色光(例如红光、蓝光或者绿光等)的发光材料。阴极层1043的材料可以包括Mg、Ca、Li或Al等金属或其合金，或者IZO、ZTO等金属氧化物，又或者PEDOT/PSS(聚3，4-乙烯二氧噻吩/聚苯乙烯磺酸盐)等具有导电性能有机材料。
此时，当阴极层1043和有机功能层1042的靠近通孔301的部分被污染时，由于阴极层1043和有机功能层被阻隔墙202以及裂纹阻挡墙204断开，水、氧等杂质不会扩散、延伸至阴极层1043和有机功能层的用于发光的部分。
如图14A-图14B所示，发光器件104形成后，可以在显示区201以及阻隔墙202上形成封装层105。例如，形成封装层105包括在阻隔墙202上以及显示区201中依次形成第一无机封装层1051，第一有机封装层1052以及第二无机封装层1053。例如，第一无机封装层1051和第二无机封装层1053采用沉积等方式形成。第一有机封装层1052采用喷墨打印的方式形成。如图14B所示，由于第一拦截墙2031的拦截作用，第一有机封装层1052终止于第一拦截墙2031。
例如，第一无机封装层1051和第二无机封装层1053可以采用氮化硅、氧化硅、氮氧化硅等无机材料形成，第一有机封装层1052可以采用聚酰亚胺(PI)、环氧树脂等有机材料形成。由此，第一无机封装层1051，第一有机封装层1052以及第二无机封装层1053形成为复合封装层，该复合封装层可以对显示区201的功能结构以及阻隔墙202等结构形成多重保护，具有更好的封装效果。
本公开的一些实施例中，根据需要，显示区101、阻隔区201中还可以形成其他必要的功能膜层，这些膜层可采用常规方法形成，在此不再赘述。
例如，在显示区101形成完成后，可以采用激光切割或者机械冲压的方式对形成通孔301。通孔301贯穿衬底基板1011，通孔301处可以安装图像传感器、红外传感器等结构，并与例如中央处理器等信号连接。例如，该图像传感器或者红外传感器等结构可以设置在衬底基板1011的远离发光器件的一侧(即显示基板的非显示侧)，并可通过通孔301实现拍照、面部识别、红外感应等多种功能。
例如，在通孔301形成后，还可以在显示基板上形成偏光片、盖板等结构，本公开的实施例对此不做限定。
本公开实施例提供的制备方法形成的显示基板将摄像装置与显示基板的显示区结合在一起，利用显示区域的有机功能层和驱动结构层的至少部分形成高度差，以形成阻隔区，使得有机功能层与通孔隔开，可以有效地防止水氧等杂质从通孔进入到显示基板的显示区，从而可以提高显示基板的信赖性。利用移位寄存电路和第一信号线、位于阻隔区的至少一圈裂纹检测线电连接，可实现通孔的裂纹检测。通过复用至少部分驱动结构层为裂纹检测线，不增加因设置裂纹检测线导致非显示区域面积增加，保证了显示基板显示区域的最大化。
本公开实施例提供的显示基板或者利用本公开实施例提供的制备方法得到的显示基板可以用于显示装置中，该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不做限定。
还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易 想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (21)

  1. 一种显示基板，包括：
    衬底基板，包括显示区、周边区和阻隔区，所述周边区围绕所述显示区，所述显示区围绕所述阻隔区；
    通孔，位于所述阻隔区，所述显示基板的中心和所述通孔的中心不重合；
    多个子像素，位于所述显示区；
    多条信号线，位于所述显示区、周边区和阻隔区，且电连接所述多个子像素，所述多条信号线包括第一信号线；
    移位寄存电路，位于所述周边区且电连接所述多条信号线；
    至少一圈裂纹检测线，位于所述阻隔区且围绕所述通孔，所述至少一圈裂纹检测线与所述第一信号线电连接，且所述第一信号线与所述多个子像素中的至少一个子像素电连接。
  2. 根据权利要求1所述的显示基板，其中，所述移位寄存电路包括多个移位寄存单元，所述第一信号线与所述多个移位寄存单元中的一个电连接。
  3. 根据权利要求2所述的显示基板，其中，所述移位寄存电路为栅极移位寄存电路，所述第一信号线为扫描信号线；或
    所述移位寄存电路为发光控制移位寄存电路，且所述第一信号线为发光控制信号线。
  4. 根据权利要求1所述的显示基板，还包括至少一个第一搭接结构，其中，所述第一信号线与所述至少一圈裂纹检测线通过所述至少一个第一搭接结构电连接，所述至少一个第一搭接结构与所述至少一圈裂纹检测线位于不同层，且通过过孔电连接。
  5. 根据权利要求4所述的显示基板，其中，所述至少一个第一搭接结构的数量为两个，所述第一信号线包括第一子走线和第二子走线，所述两个第一搭接结构分别电连接所述第一子走线和所述至少一圈裂纹检测线的第一端，以及所述第二子走线和所述至少一圈裂纹检测线的第二端。
  6. 根据权利要求1所述的显示基板，其中，所述至少一圈裂纹检测线的数量为多圈，所述多圈裂纹检测线为连续走线且围绕所述通孔。
  7. 根据权利要求6所述的显示基板，还包括至少一个第二搭接结构，其中，相邻两圈裂纹检测线之间通过所述至少一个第二搭接结构电连接，所述 至少一个第二搭接结构与所述相邻两圈裂纹检测线位于不同层且通过过孔电连接。
  8. 根据权利要求7所述的显示基板，其中，所述至少一圈裂纹检测线的数量为四圈，沿靠近所述通孔中心的径向方向，分别包括第一检测子走线、第二检测子走线、第三检测子走线和第四检测子走线，所述第一检测子走线和所述第二检测子走线通过一个第二搭接结构电连接，所述第二检测子走线、所述第三检测子走线和所述第四检测子走线中的任意两者通过两个所述第二搭接结构电连接。
  9. 根据权利要求1-8任一项所述的显示基板，还包括位于所述衬底基板一侧的第一多层绝缘层，其中，所述至少一圈裂纹检测线位于所述第一多层绝缘层远离所述衬底基板的一侧。
  10. 根据权利要求9所述的显示基板，还包括位于所述至少一圈裂纹检测线远离所述衬底基板一侧的第一有机功能层，和位于所述第一多层绝缘层远离所述衬底基板一侧的第二有机功能层，其中，所述第一有机功能层和所述第二有机功能层间断设置，且所述第一有机功能层所述衬底基板的正投影和所述第二有机功能层在所述衬底基板的正投影不交叠。
  11. 根据权利要求9任一项所述的显示基板，其中，所述至少一圈裂纹检测线包括依次位于所述多层绝缘层远离所述衬底基板一侧的第一子层、第二子层和第三子层，所述第二子层在所述衬底基板的正投影位于所述第一子层和所述第三子层在所述衬底基板的正投影内。
  12. 根据权利要求9所述的显示基板，其中，所述至少一圈裂纹检测线围绕所述通孔的至少一个侧面具有凹口。
  13. 根据权利要求10所述的显示基板，其中，所述多个子像素中的至少一个包括：
    薄膜晶体管，包括：
    位于所述衬底基板上的有源层，
    位于所述有源层远离所述衬底基板一侧的栅极，
    位于所述栅极远离所述衬底基板一侧的第一绝缘层，
    位于所述第一绝缘层远离所述衬底基板一侧的第二绝缘层，和
    位于所述第二绝缘层远离所述衬底基板一侧、且电连接至所述有源层的源极和漏极；和
    存储电容，包括：
    第一极板，与所述第一栅极位于同一层，和
    第二极板，位于所述第一绝缘层和所述第二绝缘层之间；和
    发光器件，包括：
    阳极层，位于所述源极和所述漏极远离所述衬底基板的一侧，
    有机功能层，位于所述阳极远离所述衬底基板的一侧，和
    阴极层，位于所述有机功能层远离所述衬底基板的一侧。
  14. 根据权利要求13所述的显示基板，其中，所述至少一圈裂纹检测线与所述源极或所述漏极位于同一层；
    所述第一多层绝缘层至少包括所述第一绝缘层和所述第二绝缘层；
    所述第二搭接结构和所述第一搭接结构与所述第二极板位于同一层。
  15. 根据权利要求14所述的显示基板，其中，所述有机功能层与所述第一有机功能层、所述第二有机功能层的材料相同。
  16. 根据权利要求13所述的显示基板，其中，还包括至少一个凹槽，所述至少一个凹槽贯穿所述第一绝缘层和至少部分所述第二绝缘层，所述凹槽在所述衬底基板上的正投影与所述至少一圈裂纹检测线在所述衬底基板上的正投影不交叠。
  17. 根据权利要求9所述的显示基板，其中，还包括位于所述至少一圈裂纹检测线靠近所述通孔方向的至少一圈拦截墙，所述至少一圈拦截墙被配置为阻挡封装所述多个子像素的有机封装层。
  18. 根据权利要求17所述的显示基板，其中，所述至少一圈拦截墙包括第一拦截墙和第二拦截墙，所述第一拦截墙位于所述第二拦截墙远离所述通孔的一侧，且所述第一拦截墙在垂直于所述衬底基板方向的最大高度小于所述第二拦截墙在垂直于所述衬底基板方向的最大高度。
  19. 根据权利要求9所述的显示基板，其中，还包括位于所述至少一圈拦截墙靠近所述通孔一侧的至少一圈裂纹阻挡墙。
  20. 根据权利要求9所述的显示基板，还包括封装层，其中，所述封装层至少封装所述阻隔墙，所述封装层包括在所述至少一圈裂纹检测线上依次叠层设置的第一无机封装层，第一有机封装层以及第二无机封装层。
  21. 一种显示装置,还包括：图像传感器和/或红外传感器，其中，所述图像传感器和/或红外传感器结合于所述衬底基板，并且在所述衬底基板上的正 投影与所述通孔至少部分交叠。
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