WO2018223739A1 - 显示驱动电路及其控制方法、显示装置 - Google Patents

显示驱动电路及其控制方法、显示装置 Download PDF

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Publication number
WO2018223739A1
WO2018223739A1 PCT/CN2018/078420 CN2018078420W WO2018223739A1 WO 2018223739 A1 WO2018223739 A1 WO 2018223739A1 CN 2018078420 W CN2018078420 W CN 2018078420W WO 2018223739 A1 WO2018223739 A1 WO 2018223739A1
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Prior art keywords
signal
circuit
data transmission
terminal
sub
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PCT/CN2018/078420
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English (en)
French (fr)
Inventor
丛乐乐
孙建
秦文文
张寒
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/320,070 priority Critical patent/US10692460B2/en
Publication of WO2018223739A1 publication Critical patent/WO2018223739A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display driving circuit, a control method thereof, and a display device.
  • a display driving circuit includes: a plurality of function multiplexing circuits, each of the plurality of function multiplexing circuits being connected to at least one data line via a data transmission end;
  • the function multiplexing circuit has an enable signal end, a first signal end, and a second signal end, and is configured to be under the control of the signal of the enable signal end, the first signal end, and the second signal end, A detection signal is supplied to the data line, and static electricity on the data transmission end is released via the first signal terminal or the second signal terminal.
  • the function multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; the first multiplexing sub-circuit is connected to the enabling signal end, the first signal end, and the data transmission End, configured to input a signal of the first signal end to the data transmission end and static electricity on the data transmission end under control of a signal of the enable signal end and the first signal end The first signal end is released;
  • the second multiplex sub-circuit is connected to the second signal end and the data transmission end, and configured to stabilize the voltage of the data transmission end under the control of the signal of the second signal end and the data transmission end The static electricity on the data transmission end is released via the second signal terminal.
  • the first multiplex sub-circuit includes a first transistor; a gate of the first transistor is connected to the enable signal terminal, a first pole is connected to the data transmission end, and a second pole is connected to the first signal end.
  • the second multiplex sub-circuit includes a second transistor; a gate and a first pole of the second transistor are connected to the data transmission end, and a second pole is connected to the second signal end.
  • the display driving circuit further includes a multiplexer; the multiplexer is connected to the gate control terminal, the data line, and the data transmission end of the function multiplexing circuit; the multiplexer And configured to output the signal of the data transmission end to a data line matching the strobe signal under the control of the strobe signal output by the strobe control terminal.
  • the multiplexer includes a plurality of strobe subcircuits, each of the strobe subcircuits being coupled to two adjacent function multiplex circuits; each strobe subcircuit includes L strobes, wherein The odd-numbered gates are connected to the odd-bit function multiplexing circuit and the odd-numbered data lines, and the even-numbered gates are connected to the even-numbered function multiplexing circuit and the even-numbered data lines; where L is a positive integer.
  • the display driver circuit further includes a source driver coupled to the data transfer terminal of the function multiplexing circuit, the source driver configured to provide a data signal to the data transfer terminal.
  • a display device comprising any of the display driving circuits as described above.
  • the function multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit
  • the method includes: after the signal of the enable signal end and the signal of the first signal end, the first multiplexing sub-circuit inputs a signal of the first signal end to the data transmission end, to a data line connected to the data transmission end provides a detection signal; under the control of the signal of the second signal end and the data transmission end, the second multiplexing sub-circuit stabilizes the voltage of the data transmission end; at the enable signal Controlling, by the terminal and the signal of the first signal end, the first multiplex sub-circuit releases static electricity on the data transmission end via the first signal end; at the second signal end and the data The second multiplex sub-circuit releases the static electricity on the data transmission end via the second signal terminal under the control of the signal at the transmitting end.
  • the first multiplex sub-circuit includes a first transistor, and the first multiplex sub-circuit releases the static electricity on the data transmission end via the first signal end, including: to the enable signal end and The first signal terminal applies the same voltage signal such that the first transistor is in a diode conducting state.
  • the two adjacent first multiplex sub-circuits respectively providing the detection signal to the data line include: for the first image frame, the first signal connected to the odd-numbered first multiplex sub-circuit Inputting a high level, inputting a low level to a first signal end connected to the even-numbered first multiplex sub-circuit; and connecting to the first multiplex sub-circuit of the odd-numbered bit for the second image frame
  • the first signal terminal inputs a low level, and inputs a high level to the first signal end connected to the even-numbered first multiplex sub-circuit; wherein the first image frame and the second image frame are Adjacent two image frames.
  • FIG. 1 is a schematic structural diagram of a display driving circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a function multiplexing circuit in the display driving circuit shown in FIG. 1;
  • FIG. 3 is a schematic diagram showing a specific structure of the function multiplexing circuit shown in FIG. 2;
  • 4a-4b are equivalent circuit diagrams of the function multiplexing circuit shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of another display driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural view showing a case where a multiplex sub-circuit is a transistor in the display driving circuit shown in FIG. 5;
  • FIG. 7 is a control timing chart of the display driving circuit shown in FIG. 6;
  • FIG. 8 illustrates a schematic diagram of a display device in accordance with an embodiment of the present disclosure
  • FIG. 9 illustrates a flow chart of a control method of a display driving circuit according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a display driving circuit.
  • the display driving circuit 01 includes a plurality of (at least two) function multiplexing circuits 10, and the function multiplexing circuit 10 is connected to at least one data line data in the display panel through the data transmission end 101 to detect The signal is input to the data line data.
  • the function multiplexing circuit 10 further has an enable signal terminal SW, a first signal terminal 102 and a second signal terminal 103. Only the connection lines of the two function multiplexing circuits 10 are shown in Fig. 1, and the connection lines for the other function multiplexing circuits 10 can be referred to.
  • the display driving circuit 01 can multiplex the display performance detection and the static electricity protection function of the display panel.
  • the detection signal input to the display panel can be transmitted to the data line data of the display panel through the function multiplexing circuit 10.
  • the function multiplexing circuit 10 supplies a detection signal to the data line data under the control of the signals of the enable signal terminal SW, the first signal terminal 102, and the second signal terminal 103.
  • the function multiplexing circuit 10 performs static electricity on the data transmission end 101 by the first signal terminal 102 or the second signal terminal 103. freed.
  • the data transmission terminal 101 may be a signal terminal for transmitting a data signal to the data line.
  • the source driver may be connected to the data transmission terminal 101 to input a data signal to the data line data, however, static electricity in the data signal may be released through the function multiplexing circuit 10.
  • the detection signal is used to drive pixels in the display panel to display before the display panel does not form a driving circuit (source driver, or source driver IC) for transmitting signals to the data lines, thereby The display performance of the pixel is detected.
  • the detection signal can be provided by an external controller.
  • the display driving circuit 01 further includes a source driver connected to the data transmission terminal 101.
  • the source driver is used to provide a data signal to the data transmission end 101 during the display phase. Since the data transmission end 101 is connected to the data line data in the display panel, the source driver can transmit the above data signal to the data line data.
  • the static electricity may be released through the first signal terminal 102 or the second signal terminal 103. The example release process is described during the operation of the subsequent function multiplexing circuit 10.
  • the first signal terminal is The signal of 102 is input to the data transmission terminal 101 to provide a detection signal to the data line connected to the data transmission terminal 101, thereby detecting the display performance of the pixels in the display panel.
  • the electrostatic protection phase under the control of the enable signal terminal SW, the first signal terminal 102 or the second signal terminal 103, the static electricity of the data transmission end 101 is released through the first signal terminal 102 or the second signal terminal 103.
  • the related wiring and layout of the static elimination and the display performance detection can be simultaneously completed, thereby effectively solving the layout design of the small-sized display panel, and the layout can be difficult due to the small space, and the static elimination cannot be designed.
  • the problem with the circuit is described.
  • the detecting unit is idle.
  • the display driving circuit 01 having the function multiplexing circuit 10 is designed to detect the display performance of the display panel during the display performance test phase, and the static electricity on the data transmission end 101 can be performed in the electrostatic protection phase. freed. Thereby, the idleness of the display driving circuit 01 can be avoided.
  • the function multiplexing circuit 10 may include a first multiplex sub-circuit 11 and a second multiplex sub-circuit 12.
  • the first multiplex sub-circuit 11 is connected to the enable signal terminal SW, the first signal terminal 102, and the data transmission terminal 101.
  • the first multiplex sub-circuit 11 is configured to input the signal of the first signal end 102 to the data transmission end 101 and the static electricity on the data transmission end 101 under the control of the signals of the enable signal terminal SW and the first signal terminal 102. Release is performed via the first signal terminal 101.
  • the second multiplex sub-circuit 12 is connected to the second signal terminal 103 and the data transmission terminal 101.
  • the second multiplex sub-circuit 12 is configured to stabilize the voltage of the data transmission terminal 101 and release the static electricity on the data transmission terminal 101 via the second signal terminal 103 under the control of the signals of the second signal terminal 103 and the data transmission terminal 101. .
  • the first multiplex sub-circuit 11 may include a first transistor T1, the gate of the first transistor T1 is connected to the enable signal terminal SW, the first pole is connected to the data transmission terminal 101, and the second pole is coupled to the first signal.
  • the ends 102 are connected.
  • the second multiplex sub-circuit 12 may include a second transistor T2 having a gate and a first pole connected to the data transmission terminal 101 and a second pole connected to the second signal terminal 103.
  • the transistors are all N-type transistors
  • the first source is the first source and the second electrode is the drain.
  • a constant high level is applied to the second signal terminal 103.
  • the above transistors are all P-type transistors, their first extreme drain and the second extreme source.
  • a constant low level is applied to the second signal terminal 103.
  • the data transmission end 101 is connected to the data line through the data lead. If a data transmission end 101 is only connected to one data line, for a small-sized high-PPI display panel, the data lead traces in the display panel are dense, so Short-circuit phenomenon is prone to occur. Therefore, as shown in FIG. 5, the display driving circuit 01 may further include a multiplexer 20.
  • the multiplexer 20 is connected to the gate control terminal MUX n , the data line data, and the data transfer terminal 101 of the function multiplexing circuit 10.
  • the multiplexer 20 is configured to output the signal of the function multiplexing circuit 10 to the data line data corresponding to the strobe signal under the control of the strobe signal of the strobe control terminal MUX n , thereby reducing data.
  • the setting of the lead wire reduces the probability of the wire being dense and causing a short circuit phenomenon.
  • the multiplexer 20 may include a plurality of strobe sub-circuits 201, each of which is connected to two adjacent functional multiplex circuits 10.
  • each of the strobe sub-circuits 201 may include L gates 2011, wherein the odd-numbered gates 2011 connect the odd-numbered functional multiplexing circuits 10 and the odd-numbered data lines data, the even-numbered gates 2011 is an even-numbered functional multiplexing circuit 10 and an even-numbered data line data; where L is a positive integer.
  • one data transmission terminal 101 can provide data signals for six data lines.
  • each of the strobe sub-circuits 201 includes six transistors, and the gates of the transistors are respectively connected to the gate control terminals MUX 1 -MUX 6 , the first poles are connected to the data lines data, and the second poles are connected.
  • a gate device 2011 includes a transistor, the first transistor is connected to the first functional multiplexing circuit 10 and the first data line, and the second transistor is connected to the second functional multiplexing circuit 10 and the second data line. analogy.
  • one data transmission end 101 can provide data signals for three data lines.
  • the enable signal terminal SW is at a high level.
  • the first transistor T1 is turned on, and the detection signals CTDO and CTDE input by the first signal terminal 102 are input to the multiplexer 20 through the data transmission terminal 101. in.
  • the gate control terminal MUX 1 When the gate control terminal MUX 1 is at a high level, the first and fourth transistors in the multiplexer 20 are turned on. Since the first transistor is different from the data transmission terminal 101 connected to the fourth transistor, the detection signal in the first functional multiplexing circuit 10 is transmitted to the data line data1 connected to the first transistor, and the second The detection signal in the function multiplexing circuit 10 is transmitted to the data line data4 connected to the fourth transistor.
  • the gate control terminal MUX 1 When the gate control terminal MUX 1 is at a low level, the first and fourth transistors are turned off, and at this time, writing of signals to the data lines data1 and data4 is stopped.
  • the column inversion driving can be realized by controlling the high and low level transitions of the adjacent detection signals CTDO and CTDE in the adjacent two image frames, thereby reducing the rotation angle of the liquid crystal in the display panel for a long time or the rotation angle is small, resulting in a small rotation angle.
  • the probability of liquid crystal aging For example, in the first image frame, the detection signal CTDO is at a high level, and the detection signal CTDE is at a low level; in the second image frame, the detection signal CTDO is at a low level, and the detection signal CTDE is at a high level.
  • the first image frame and the second image frame are adjacent two image frames.
  • the levels of the data signals written by the adjacent two columns of data lines are opposite.
  • the data signal is continuously inverted between the high and low levels. Even if the gray scale change of the screen is small, the rotation angle of the liquid crystal will constantly change, so that the liquid crystal aging caused by the rotation angle of the liquid crystal is not changed for a long time. The phenomenon is relieved.
  • FIG. 3 the equivalent circuit diagram of FIG. 3 is as shown in FIGS. 4a and 4b, in which the first transistor T1 and the second transistor T2 operate as a diode D1 and a diode D2, respectively.
  • the anode of diode D1 is connected to a low level; the cathode of diode D2 is connected to a high level.
  • the source driver When the source driver provides a large forward static (eg, +30V) in the data signal of the data line data, the static current flows to the diode D2, and the direction of the static current is directed by the solid arrow in FIG. 4a.
  • the anode of the diode D2 is connected to +30V, and the cathode is connected to +5V, so the diode D2 is in an on state, at which time a large forward static electricity is conducted to the diode D2, and is released through the second signal terminal 103.
  • the source driver When the source driver provides a large negative electrostatic charge (for example, -30V) in the data signal of the data line data, the static electricity flows to the diode D1, and the direction of the electrostatic current is directed by the arrow in FIG. 4b.
  • the anode of the diode D1 is connected to -5V, and the cathode of the diode is connected to -30V, so the diode D1 is in a reverse breakdown state.
  • the diode D1 is turned off, a large forward static electricity is conducted to the diode D2, and passes through the first signal end 102. Release.
  • an embodiment of the present disclosure provides a display device including a display driving circuit according to an embodiment of the present disclosure.
  • the display device may further include a gate drive circuit (GOA), a circuit detection terminal (ET), a fast discharge circuit (Rapid), a ground terminal (GND), and the like located in the non-display area.
  • GAA gate drive circuit
  • ET circuit detection terminal
  • Rapid fast discharge circuit
  • GND ground terminal
  • the signals of the detection signals CTDO, CTDE and the enable signal terminal SW can be input through the circuit detection terminal ET.
  • the embodiment of the present disclosure provides a method for driving the display driving circuit 01 according to an embodiment of the present disclosure, wherein the function multiplexing circuit 10 includes a first multiplexing sub-circuit 11 and a second multiplexing sub-circuit 12.
  • the function multiplexing circuit 10 includes a first multiplexing sub-circuit 11 and a second multiplexing sub-circuit 12.
  • the transistors are all N-type transistors, with a high level of +5V and a low level of -5V.
  • the method can include the following steps.
  • step S91 under the control of the enable signal terminal SW and the first signal terminal 102, the first multiplexing sub-circuit 11 inputs the signal of the first signal terminal 102 to the data transmission terminal 101 to be associated with the data transmission terminal 101.
  • the connected data line provides a detection signal. This phase can be referred to as the "detection phase.”
  • the second multiplex sub-circuit 12 stabilizes the voltage of the data transmission terminal 101.
  • the enable control terminal SW is always kept at a high level, so that the first transistor T1 is turned on.
  • the second signal terminal 103 outputs a high level.
  • the detection signal is input to the first signal terminal 102. Since the first transistor T1 is turned on, the detection signal can be transmitted to the data line data of the display panel through the data transmission terminal 101.
  • the data transmission terminal 101 is at a high level at this time.
  • the potential of the gate of the second transistor T2 is the same as the potential of the second electrode, the gate-source voltage Vgs of the second transistor T2 is 0, and the second transistor T2 is turned off.
  • the signal input from the first signal terminal 102 has a higher static electricity
  • the signal output through the data transmission terminal 101 also has a higher static electricity
  • the gate potential of the second transistor T2 rises.
  • the second transistor T2 is turned on.
  • the static electricity is conducted to the second signal terminal 103 through the second transistor T2, thereby causing the data transmission terminal 101 to maintain the above-described high level. Therefore, the second transistor T2 can stabilize the voltage of the data transfer terminal 101.
  • the data transmission terminal 101 is at a low level, and at this time, the second transistor T2 is turned off.
  • step S82 under the control of the enable signal terminal SW and the first signal terminal 102, the first multiplex sub-circuit 11 releases the static electricity on the data transmission terminal 101 through the first signal terminal 102. Under the control of the second signal terminal 103 and the data transmission terminal 101, the second multiplex sub-circuit 12 releases the static electricity on the data transmission terminal 101 through the second signal terminal 103. Therefore, this stage can be referred to as an "electrostatic protection stage.”
  • the data signal supplied from the source driver is transmitted to the data line data of the display panel through the data transmission terminal 101.
  • the control terminal SW is enabled, the first signal terminal 102 is at a low level, and the third signal terminal 103 is at a high level.
  • the equivalent circuit diagram of FIG. 3 is as shown in FIGS. 4a and 4b, in which the first transistor T1 and the second transistor T2 operate as a diode D1 and a diode D2, respectively.
  • the anode of diode D1 is connected to a low level; the cathode of diode D2 is connected to a high level.
  • the source driver When the source driver provides a large forward static (eg, +30V) in the data signal of the data line data, the static current flows to the diode D2, and the direction of the static current is directed by the solid arrow in FIG. 4a.
  • the anode of the diode D2 is connected to +30V, and the cathode is connected to +5V, so the diode D2 is in an on state, at which time a large forward static electricity is conducted to the diode D2, and is released through the second signal terminal 103.
  • the source driver When the source driver provides a large negative electrostatic charge (for example, -30V) in the data signal of the data line data, the static electricity flows to the diode D1, and the direction of the electrostatic current is directed by the arrow in FIG. 4b.
  • the anode of the diode D1 is connected to -5V, and the cathode of the diode is connected to -30V, so the diode D1 is in a reverse breakdown state.
  • the diode D1 is turned off, and the static electricity is conducted to the diode D2 and is released through the first signal terminal 102.
  • the first signal terminal is used.
  • the signal of 102 is input to the data transmission terminal 101 to provide a detection signal to the data line connected to the data transmission terminal 101, thereby detecting the display performance of the pixels in the display panel.
  • the static protection phase the static electricity of the data transmission end 101 is released through the first signal terminal 102 or the second signal terminal 103 under the control of the enable signal terminal SW, the first signal terminal 102 or the second signal terminal 103.
  • the relevant wiring and layout of the unit for static elimination and the unit for detecting display performance can be simultaneously completed, thereby effectively solving the small size display panel due to small space, place and route. Difficult to design a static elimination circuit.
  • the first multiplex sub-circuit 11 includes the first transistor T1, and the first multiplex sub-circuit 11 releases the static electricity on the data transmission end 101 via the first signal terminal 102.
  • a signal of the same voltage is input to the enable signal terminal SW and the first signal terminal 102 such that the first transistor T1 is in a diode off state.
  • the first transistor T1 is an N-type transistor
  • a low level is input to the enable signal terminal SW and the first signal terminal 102 such that the first transistor T1 is in a diode-off state.
  • the signal of the data transmission terminal 101 has a large negative static electricity
  • the first transistor T1 is reversely reversed, so that the larger negative static electricity is released through the first signal terminal 102.
  • the display driving circuit In order to avoid the problem that the liquid crystal ages due to the long-term rotation angle of the liquid crystal in the display panel or the rotation angle is small, the display driving circuit generally adopts a column inversion driving method.
  • the providing, by the first multiplex sub-circuit 11 to the data line connected to the data transmission end 101, the detection signal may include:
  • a high level is input to the first signal terminal 102 connected to the odd-numbered first multiplex sub-circuit 11; and input to the first signal terminal 102 connected to the even-numbered first multiplex sub-circuit 11 Low level.
  • a low level is input to the first signal terminal 102 connected to the odd-numbered first multiplex sub-circuit 11; and input to the first signal terminal 102 connected to the even-numbered first multiplex sub-circuit 11 High level.
  • the first image frame and the second image frame are adjacent two image frames.
  • the data signals of the adjacent two columns of data lines have opposite levels.
  • the data signal is continuously inverted between the high and low levels, and even if the gray scale change of the screen is small, the rotation angle of the liquid crystal is constantly changed, so that the rotation angle of the liquid crystal is long.
  • the phenomenon of liquid crystal aging caused by constant changes is alleviated.

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Abstract

一种显示驱动电路（01）及其控制方法、显示装置。该显示驱动电路（01）包括多个功能复用电路（10），每个功能复用电路（10）通过数据传输端（101）与至少一条数据线（data）相连接。功能复用电路（10）还连接使能信号端（SW）、第一信号端（102）和第二信号端（103），配置为在使能信号端（SW）、第一信号端（102）以及第二信号端（103）的作用下，向数据线（data）提供检测信号，还用于将数据传输端（101）上的静电由第一信号端（102）或第二信号端（103）进行释放。

Description

显示驱动电路及其控制方法、显示装置
本申请要求于2017年6月5日提交的、申请号为201710414835.5的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示驱动电路及其控制方法、显示装置。
背景技术
在显示面板的制作过程中，受空间和制作工艺限制，对于小尺寸显示面板，无法设置针对数据线的静电消除单元，这将对显示面板的正常工作产生影响。
发明内容
根据本公开实施例的一方面，提供了一种显示驱动电路，包括：多个功能复用电路，所述多个功能复用电路中的每一个经由数据传输端与至少一条数据线相连接；所述功能复用电路具有使能信号端、第一信号端和第二信号端，被配置为在所述使能信号端、所述第一信号端以及所述第二信号端的信号控制下，向所述数据线提供检测信号，并将所述数据传输端上的静电经由第一信号端或第二信号端释放。
例如，所述功能复用电路包括第一复用子电路和第二复用子电路；所述第一复用子电路连接所述使能信号端、所述第一信号端以及所述数据传输端，被配置为在所述使能信号端和所述第一信号端的信号的控制下，将所述第一信号端的信号输入至所述数据传输端以及将所述数据传输端上的静电经由所述第一信号端释放；
所述第二复用子电路连接所述第二信号端和所述数据传输端，配置为在所述第二信号端和所述数据传输端的信号的控制下，稳定所述数据传输端的电压并将所述数据传输端上的静电经由所述第二信号端释放。
例如，所述第一复用子电路包括第一晶体管；所述第一晶体管的栅极连接所 述使能信号端，第一极连接所述数据传输端，第二极连接所述第一信号端。
例如，所述第二复用子电路包括第二晶体管；所述第二晶体管的栅极和第一极连接所述数据传输端，第二极连接所述第二信号端。
例如，所述显示驱动电路还包括多路选择器；所述多路选择器与选通控制端、所述数据线以及所述功能复用电路的数据传输端相连接；所述多路选择器配置为在所述选通控制端输出的选通信号的控制下，将所述数据传输端的信号输出至与所述选通信号相匹配的数据线上。所述多路选择器包括多个选通子电路，每个所述选通子电路与相邻的两个功能复用电路相连接；每个选通子电路包括L个选通器，其中，奇数位选通器连接奇数位功能复用电路和奇数位数据线，偶数位选通器连接偶数位功能复用电路和偶数位数据线；其中L为正整数。
例如，所述显示驱动电路还包括与所述功能复用电路的数据传输端相连接的源极驱动器，所述源极驱动器配置为向所述数据传输端提供数据信号。
本公开实施例的另一方面，提供一种显示装置，包括如上所述的任一种显示驱动电路。
本公开实施例的又一方面，提供一种用于控制如上所述的任一种显示驱动电路的方法，在功能复用电路包括第一复用子电路和第二复用子电路的情况下，所述方法包括：在使能信号端和第一信号端的信号的控制下，所述第一复用子电路将所述第一信号端的信号输入至所述数据传输端，以向与所述数据传输端相连接的数据线提供检测信号；在第二信号端和所述数据传输端的信号的控制下，所述第二复用子电路稳定所述数据传输端的电压；在所述使能信号端和所述第一信号端的信号的控制下，所述第一复用子电路将所述数据传输端上的静电经由所述第一信号端释放；在所述第二信号端和所述数据传输端的信号的控制下，所述第二复用子电路将所述数据传输端上的静电经由所述第二信号端释放。
例如，所述第一复用子电路包括第一晶体管，所述第一复用子电路将所述数据传输端上的静电经由所述第一信号端释放包括：向所述使能信号端和所述第一信号端施加相同的电压信号，以使得所述第一晶体管处于二极管导通状态。
例如，相邻两个所述第一复用子电路分别向与所述数据线提供检测信号包括：针对第一图像帧，向与奇数位所述第一复用子电路相连接的第一信号端输入高电平，向与偶数位所述第一复用子电路相连接的第一信号端输入低电平；针对 第二图像帧，向与奇数位所述第一复用子电路相连接的第一信号端输入低电平，向与偶数位所述第一复用子电路相连接的第一信号端输入高电平；其中，所述第一图像帧和所述第二图像帧为相邻的两图像帧。
附图说明
为了更清楚地说明本公开实施例或传统的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种显示驱动电路的结构示意图；
图2为图1所示的显示驱动电路中功能复用电路的一种结构示意图；
图3为图2所示的功能复用电路的一种具体结构示意图；
图4a-4b为图3所示的功能复用电路的等效电路图；
图5为本公开实施例提供的另一种显示驱动电路的结构示意图；
图6为图5所示的显示驱动电路中复用子电路为晶体管时的结构示意图；
图7为图6所示的显示驱动电路的控制时序图；
图8示出了根据本公开实施例的显示装置的示意图；以及
图9示出了根据本公开实施例的显示驱动电路的控制方法的流程图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供了一种显示驱动电路。如图1所示，显示驱动电路01包括多个(至少两个)功能复用电路10，功能复用电路10通过数据传输端101与显示面板内的至少一条数据线data相连接，以将检测信号输入至数据线data。功能复用电路10还具有使能信号端SW、第一信号端102和第二信号端103。图1中仅绘制了其中两个功能复用电路10的连接线路，对于其他功能复用电路10的 连接线路可以参考该连接线路。
显示驱动电路01可以复用显示面板的显示性能检测和静电防护功能。其中，在面板检测阶段，向显示面板输入的检测信号可以通过功能复用电路10传输至显示面板的数据线data。例如功能复用电路10在使能信号端SW、第一信号端102以及第二信号端103的信号的控制下，向数据线data提供检测信号。另外，在显示阶段(由于在此阶段需静电防护，因此也可称为静电防护阶段)，功能复用电路10将数据传输端101上的静电由第一信号端102或第二信号端103进行释放。数据传输端101可以是用于向数据线传输数据信号的信号端。通常可以源极驱动器连接数据传输端101，以向数据线data输入数据信号，然而数据信号中的静电可通过功能复用电路10释放。
需要说明的是，上述检测信号用于在显示面板未形成用于向数据线传输信号的驱动电路(源极驱动器，或称为源极驱动IC)之前，驱动显示面板中的像素进行显示，从而对像素的显示性能进行检测。其中，检测信号可以通过外部控制器提供。
此外，显示驱动电路01还包括与数据传输端101相连接的源极驱动器。源极驱动器用于在显示阶段向数据传输端101提供数据信号。由于数据传输端101与显示面板中的数据线data相连接，因此源极驱动器可以将上述数据信号传输至数据线data中。当源极驱动器提供的数据信号中具有较高静电，即数据传输端101上具有较高静电时，上述静电可以通过第一信号端102或第二信号端103进行释放。示例释放过程在后续功能复用电路10的工作过程中进行说明。
基于此，通过对上述显示驱动电路01进行分时驱动，在测试(Cell Test)阶段，在使能信号端SW、第一信号端102以及第二信号端103的作用下，将第一信号端102的信号输入至数据传输端101，以向与数据传输端101相连接的数据线提供检测信号，从而对显示面板中像素的显示性能进行检测。同时在静电保护阶段，在使能信号端SW、第一信号端102或第二信号端103的控制下，将数据传输端101的静电通过第一信号端102或第二信号端103进行释放。由此，在设计显示驱动电路01后，可以同时完成静电消除和显示性能检测的相关连线和布局，从而有效解决小尺寸显示面板版图设计时，由于空间小导致布局布线困难而无法设计静电消除电路的问题。
此外，在传统面板进行显示性能检测之后，存在检测单元闲置的问题。对于小尺寸显示面板，尤其是边框为圆形、多边形或具有弧形的其他形状的异形小尺寸的显示面板，造成了布线空间的极大浪费。本公开在有限空间内，通过设计具有功能复用电路10的显示驱动电路01，在显示性能测试阶段对显示面板的显示性能进行检测，在静电保护阶段，可对数据传输端101上的静电进行释放。从而可以避免显示驱动电路01的闲置。
如图2所示，功能复用电路10可以包括第一复用子电路11和第二复用子电路12。
第一复用子电路11连接使能信号端SW、第一信号端102以及数据传输端101。第一复用子电路11配置为在使能信号端SW和第一信号端102的信号的控制下，将第一信号端102的信号输入至数据传输端101以及将数据传输端101上的静电经由第一信号端101进行释放。
第二复用子电路12连接第二信号端103和数据传输端101。第二复用子电路12配置为在第二信号端103和数据传输端101的信号的控制下，稳定数据传输端101的电压以及将数据传输端101上的静电经由第二信号端103进行释放。
下文对第一复用子电路11和第二复用子电路12的示例结构进行说明。如图3所示，第一复用子电路11可包括第一晶体管T1，第一晶体管T1的栅极连接使能信号端SW，第一极连接数据传输端101，第二极与第一信号端102相连接。
第二复用子电路12可包括第二晶体管T2，第二晶体管T2的栅极和第一极连接数据传输端101，第二极与第二信号端103相连接。
需要说明的是，当上述晶体管均为N型晶体管时，其第一极为源极，第二极为漏极。向第二信号端103施加恒定的高电平。当上述晶体管均为P型晶体管时，其第一极为漏极，第二极为源极。向第二信号端103施加恒定的低电平。
此外，上述数据传输端101通过数据引线与数据线相连接，若一数据传输端101仅与一条数据线相连接，对于小尺寸高PPI显示面板，显示面板中的数据引线走线密集，因此极易出现短路现象。因此如图5所示，显示驱动电路01还可以包括多路选择器20。多路选择器20与选通控制端MUX n、数据线data以及功能复用电路10的数据传输端101相连接。其中，多路选择器20配置为在选通控制端MUX n的选通信号的控制下，将功能复用电路10的信号输出至与选通信号相 对应的数据线data上，从而可以减少数据引线的设置，降低走线密集导致短路现象的几率。
如图5所示，多路选择器20可以包括多个选通子电路201，每个选通子电路201与相邻的两个功能复用电路10相连接。
例如，每个选通子电路201可以包括L个选通器2011，其中，奇数位的选通器2011连接奇数位的功能复用电路10和奇数位的数据线data，偶数位的选通器2011连接偶数位的功能复用电路10和偶数位的数据线data；其中L为正整数。
需要说明的是，图5是以L＝6，即一个选通子电路201包括6个选通器2011为例进行的示意。在此情况下，一个数据传输端101可以为6条数据线提供数据信号。本公开实施例中，示例的，每个选通子电路201包括六个晶体管，晶体管的栅极分别连接选通控制端MUX 1-MUX 6，第一极连接数据线data，第二极连接功能复用电路10的数据传输端101。一选通器2011包括一个晶体管，第一个晶体管连接第一个功能复用电路10和第一条数据线，第二个晶体管连接第二个功能复用电路10和第二条数据线，依次类推。
当然，每个选通器201也可以包括其他数目个选通子单元2011，例如3个，即L＝3，在此情况下，一个数据传输端101可以为3条数据线提供数据信号。相对于L＝6的情况，当每个选通子电路201包括3个选通器2011时，会增加数据引线的布线数量。
以下结合图7所示的时序控制图对图6所示的显示驱动电路01的工作过程进行示例说明。
在显示性能的检测阶段，使能信号端SW为高电平，此时第一晶体管T1导通，由第一信号端102输入的检测信号CTDO、CTDE通过数据传输端101输入至多路选择器20中。
当选通控制端MUX 1为高电平时，多路选择器20中的第一个、第四个晶体管开启。由于第一个晶体管与第四个晶体管连接的数据传输端101不同，此时，第一个功能复用电路10中的检测信号传输至与第一个晶体管相连接的数据线data1，第二个功能复用电路10中的检测信号传输至与第四个晶体管相连接的数据线data4中。当选通控制端MUX 1为低电平时，第一个、第四个晶体管截止，此时停止向上述数据线data1和data4写入信号。
在向其他数据线data中写入信号时的原理与上述数据线data1和data4中写入信号的原理相同，此处不再赘述。此外，可以通过控制上述检测信号CTDO、CTDE在相邻两图像帧的高低电平转换，实现列反转驱动，从而降低显示面板中的液晶的旋转角度长时间不变或旋转角度较小，导致液晶老化现象的几率。例如，在第一图像帧，检测信号CTDO为高电平，检测信号CTDE为低电平；在第二图像帧，检测信号CTDO为低电平，检测信号CTDE为高电平。其中，第一图像帧和第二图像帧为相邻的两图像帧。
由此，相邻两列数据线写入的数据信号的电平相反。在进行画面显示时，数据信号不断在高低电平间反转，即使画面的灰阶变化较小，液晶的旋转角度也会不断变化，从而对上述液晶的旋转角度长时间不变导致的液晶老化现象进行缓解。
接下来，在静电防护阶段，由显示面板中的源极驱动器提供数据信号并输入至数据传输端101。其中，使能控制端SW变为低电平，第一信号端102为低电平，第二信号端103为高电平。此时，图3的等效电路图如图4a、4b所示，其中，第一晶体管T1和第二晶体管T2分别操作为二极管D1和二极管D2。二极管D1的正极接低电平；二极管D2的负极接高电平。
当源极驱动器提供至数据线data的数据信号中具有较大的正向静电(例如+30V)时，该静电流向二极管D2，静电的电流方向如图4a中的实线箭头的指向。其中，二极管D2的正极接+30V，负极接+5V，因此二极管D2处于导通状态，此时较大的正向静电传导至二极管D2，并通过第二信号端103进行释放。
当源极驱动器提供至数据线data的数据信号中具有较大的负向静电(例如-30V)时，该静电流向二极管D1，静电的电流方向如图4b中箭头的指向。其中，二极管D1的正极接-5V，负极接-30V，因此二极管D1处于反向击穿状态，此时，二极管D1截止，较大的正向静电传导至二极管D2，并通过第一信号端102进行释放。
如图8所示，本公开实施例提供了一种显示装置，包括根据本公开实施例的显示驱动电路。
根据本公开实施例的显示装置还可以包括位于非显示区域的栅极驱动电路(GOA)、电路检测端子(ET)、快速放电电路(Rapid)、接地端(GND)等。 其中，在检测阶段，上述检测信号CTDO、CTDE以及使能信号端SW的信号可以通过电路检测端子ET输入。
本公开实施例提供一种用于驱动根据本公开实施例的显示驱动电路01的方法，其中功能复用电路10包括第一复用子电路11和第二复用子电路12。以下以晶体管均为N型晶体管，高电平为+5V，低电平为-5V进行举例说明。如图9所示，所述方法可以包括以下步骤。
在步骤S91，在使能信号端SW和第一信号端102的控制下，第一复用子电路11将第一信号端102的信号输入至数据传输端101，以向与数据传输端101相连接的数据线提供检测信号。可以将该阶段称作“检测阶段”。
此外，在第二信号端103和数据传输端101的控制下，第二复用子电路12稳定数据传输端101的电压。
例如，在该检测阶段，使能控制端SW始终保持高电平，从而第一晶体管T1导通。第二信号端103输出高电平。向第一信号端102输入检测信号，由于第一晶体管T1导通，检测信号可以通过数据传输端101传输至显示面板的数据线data中。
当第一信号端102设置为与第二信号端103相同的高电平，此时数据传输端101为高电平。在此情况下，由于第二晶体管T2的栅极的电位与第二极的电位相同，从而第二晶体管T2的栅源电压Vgs＝0，第二晶体管T2截止。
在此情况下，若第一信号端102输入的信号具有较高静电，通过数据传输端101输出的信号也具有较高静电，此时第二晶体管T2的栅极电位升高。当第二晶体管T2的栅源电压Vgs大于其阈值电压Vth时，第二晶体管T2导通。此时，上述静电通过第二晶体管T2传导至第二信号端103，进而使得数据传输端101保持上述高电平。因此，第二晶体管T2可以稳定数据传输端101的电压。
当第一信号端102为低电平时，数据传输端101为低电平，此时第二晶体管T2截止。
在步骤S82，在使能信号端SW和第一信号端102的控制下，第一复用子电路11将数据传输端101上的静电通过第一信号端102进行释放。在第二信号端103和数据传输端101的控制下，第二复用子电路12将数据传输端101上的静电通过第二信号端103进行释放。因此，可以将该阶段称作“静电保护阶段”。
例如，在静电保护阶段，源极驱动器提供的数据信号通过数据传输端101传输至显示面板的数据线data。使能控制端SW、第一信号端102为低电平，第三信号端103为高电平。此时，图3的等效电路图如图4a、4b所示，其中，第一晶体管T1和第二晶体管T2分别操作为二极管D1和二极管D2。二极管D1的正极接低电平；二极管D2的负极接高电平。
当源极驱动器提供至数据线data的数据信号中具有较大的正向静电(例如+30V)时，该静电流向二极管D2，静电的电流方向如图4a中的实线箭头的指向。其中，二极管D2的正极接+30V，负极接+5V，因此二极管D2处于导通状态，此时较大的正向静电传导至二极管D2，并通过第二信号端103进行释放。
当源极驱动器提供至数据线data的数据信号中具有较大的负向静电(例如-30V)时，该静电流向二极管D1，静电的电流方向如图4b中箭头的指向。其中，二极管D1的正极接-5V，负极接-30V，因此二极管D1处于反向击穿状态，此时，二极管D1截止，该静电传导至二极管D2，并通过第一信号端102进行释放。
基于此，通过对上述显示驱动电路01进行分时驱动，在检测(Cell Test)阶段，在使能信号端SW、第一信号端102以及第二信号端103的控制下，将第一信号端102的信号输入至数据传输端101，以向与数据传输端101相连接的数据线提供检测信号，从而对显示面板中像素的显示性能进行检测。在静电保护阶段，在使能信号端SW、第一信号端102或第二信号端103的控制下，将数据传输端101的静电通过第一信号端102或第二信号端103进行释放。这样一来，在设计显示驱动电路01后，就可以同时完成用于静电消除的单元和用于检测显示性能的单元的相关连线和布局，从而有效解决小尺寸显示面板由于空间小，布局布线困难，而无法设计静电消除电路的问题。
此外，上述步骤S92中，第一复用子电路11包括第一晶体管T1，第一复用子电路11将数据传输端101上的静电经由第一信号端102进行释放可以包括：
向使能信号端SW和第一信号端102输入相同电压的信号，以使得第一晶体管T1处于二极管截止状态。
当第一晶体管T1为N型晶体管时，向使能信号端SW和第一信号端102输入低电平，以使得第一晶体管T1处于二极管截止状态。当数据传输端101的信号中具有较大的负向静电时，会使得第一晶体管T1反向击穿，从而该较大的负 向静电通过第一信号端102进行释放。
为了避免显示面板中的液晶的旋转角度长时间不变或旋转角度较小，导致液晶老化的问题，显示驱动电路通常采用列反转的驱动方法。例如，在上述步骤S91中，第一复用子电路11向与数据传输端101相连接的数据线提供检测信号可以包括：
针对第一图像帧，向与奇数位第一复用子电路11相连接的第一信号端102输入高电平；向与偶数位第一复用子电路11相连接的第一信号端102输入低电平。
针对第二图像帧，向与奇数位第一复用子电路11相连接的第一信号端102输入低电平；向与偶数位第一复用子电路11相连接的第一信号端102输入高电平。其中，第一图像帧和第二图像帧为相邻的两图像帧。
由于相邻两列数据线的数据信号的电平相反。在进行相邻两图像帧的画面显示时，数据信号不断在高低电平间反转，即使画面的灰阶变化较小，液晶的旋转角度也会不断变化，从而对上述液晶的旋转角度长时间不变导致的液晶老化现象进行缓解。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种显示驱动电路，包括多个功能复用电路，所述多个功能复用电路中的每一个包括：
    数据传输端，与显示面板内的至少一条数据线相连接；
    使能信号端、第一信号端和第二信号端；
    功能复用电路配置为在所述使能信号端、所述第一信号端以及所述第二信号端的信号的控制下，向所述数据线提供检测信号以及将所述数据传输端上的静电由第一信号端或第二信号端进行释放。
  2. 根据权利要求1所述的显示驱动电路，其中，所述功能复用电路包括第一复用子电路和第二复用子电路；
    所述第一复用子电路连接所述使能信号端、所述第一信号端以及所述数据传输端，配置为在所述使能信号端和所述第一信号端的信号的控制下，将所述第一信号端的信号输入至所述数据传输端以及将所述数据传输端上的静电通过所述第一信号端进行释放；
    所述第二复用子电路连接所述第二信号端和所述数据传输端，配置为在所述第二信号端和所述数据传输端的控制下，稳定所述数据传输端的电压以及将所述数据传输端上的静电通过所述第二信号端进行释放。
  3. 根据权利要求2所述的显示驱动电路，其中，所述第一复用子电路包括第一晶体管；
    所述第一晶体管的栅极连接所述使能信号端，第一极连接所述数据传输端，第二极连接所述第一信号端。
  4. 根据权利要求2或3所述的显示驱动电路，其中，所述第二复用子电路包括第二晶体管；
    所述第二晶体管的栅极和第一极连接所述数据传输端，第二极连接所述第二信号端。
  5. 根据权利要求1所述的显示驱动电路，其中，所述显示驱动电路还包括多路选择器；
    所述多路选择器与选通控制端、所述数据线以及所述功能复用电路的数据传输端相连接，配置为在所述选通控制端的选通信号的控制下，将所述数据传输端 的信号输出至与所述选通信号相匹配的数据线上；
    所述多路选择器包括多个选通子电路，每个所述选通子电路与相邻的两个功能复用电路相连接；
    每个选通子电路包括L个选通器，其中，奇数位选通器连接奇数位功能复用电路和奇数位数据线，偶数位选通器连接偶数位功能复用电路和偶数位数据线；其中L为正整数。
  6. 根据权利要求1所述的显示驱动电路，还包括与所述功能复用电路的数据传输端相连接的源极驱动器，所述源极驱动器用于向所述数据传输端提供数据信号。
  7. 一种显示装置，包括如权利要求1-6任一项所述的显示驱动电路。
  8. 一种用于控制如权利要求1-6任一项所述的显示驱动电路的方法，所述功能复用电路包括第一复用子电路和第二复用子电路，所述方法包括：
    在使能信号端和第一信号端的信号的控制下，所述第一复用子电路将所述第一信号端的信号输入至所述数据传输端，以向与所述数据传输端相连接的数据线提供检测信号；在第二信号端和所述数据传输端的控制下，所述第二复用子模块稳定所述数据传输端的电压；以及
    在所述使能信号端和所述第一信号端的控制下，所述第一复用子电路将所述数据传输端上的静电经由所述第一信号端进行释放；在所述第二信号端和所述数据传输端的控制下，所述第二复用子电路将所述数据传输端上的静电经由所述第二信号端进行释放。
  9. 根据权利要求8所述的方法，其中，所述第一复用子电路包括第一晶体管，所述第一复用子电路将所述数据传输端上的静电经由所述第一信号端进行释放包括：
    向所述使能信号端和所述第一信号端输入相同电压的信号，以使得所述第一晶体管处于二极管截止状态。
  10. 根据权利要求8所述的方法，其中，所述第一复用子电路向与所述数据传输端相连接的数据线提供检测信号包括：
    针对第一图像帧，向与奇数位所述第一复用子电路相连接的第一信号端输入高电平；向与偶数位所述第一复用子电路相连接的第一信号端输入低电平；
    针对第二图像帧，向与奇数位所述第一复用子电路相连接的第一信号端输入低电平；向与偶数位所述第一复用子电路相连接的第一信号端输入高电平；
    其中，所述第一图像帧和所述第二图像帧为相邻的两图像帧。
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