WO2021184348A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2021184348A1
WO2021184348A1 PCT/CN2020/080393 CN2020080393W WO2021184348A1 WO 2021184348 A1 WO2021184348 A1 WO 2021184348A1 CN 2020080393 W CN2020080393 W CN 2020080393W WO 2021184348 A1 WO2021184348 A1 WO 2021184348A1
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WIPO (PCT)
Prior art keywords
layer
area
multiplexer
electrode
transistor
Prior art date
Application number
PCT/CN2020/080393
Other languages
English (en)
French (fr)
Inventor
刘彪
都蒙蒙
董向丹
马宏伟
尚庭华
青海刚
于鹏飞
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/973,637 priority Critical patent/US20220059635A1/en
Priority to PCT/CN2020/080393 priority patent/WO2021184348A1/zh
Priority to CN202080000337.6A priority patent/CN115516410A/zh
Priority to EP20897623.3A priority patent/EP4123427A4/en
Publication of WO2021184348A1 publication Critical patent/WO2021184348A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • the circuit layout design of the Pad (pad) area of the backplane of the display device is particularly important.
  • the OLED driving method is complicated.
  • IC Integrated Circuit, integrated circuit
  • Pin pins
  • COP Chip on Plastic
  • COF Chip On Film
  • multiple multiplexers are provided in the display panel.
  • Each multiplexer can use one data signal source in the IC to drive two columns of sub-pixels in the display panel. This can reduce the number of pins in the IC, reduce the difficulty of the module process and reduce the IC size. Due to the above-mentioned advantages of multiplexers, multiplexers are increasingly used in display panels (for example, AMOLED (Active-matrix Organic Light Emitting Diode, active matrix organic light emitting diode) display panels).
  • AMOLED Active-matrix Organic Light Emitting Diode, active matrix organic light emitting diode
  • a display panel including: a display area including a pixel array provided on a substrate, the pixel array including a plurality of sub-pixels; and a peripheral area surrounding the display area, so
  • the peripheral area includes: a bending area on one side of the display area; a plurality of multiplexers on a side of the bending area away from the display area, wherein the multiple multiplexers The multiplexers are arranged on the substrate, and each multiplexer is connected with at least one signal input line and two signal output lines; Binding area; wherein the multiple multiplexers are electrically connected to the plurality of sub-pixels through the bending area; the signal input line is electrically connected to the binding area, and the signal input line is The orthographic projection on the substrate and the orthographic projection of the bending area on the substrate do not overlap.
  • the plurality of multiplexers includes a first multiplexer and a second multiplexer, wherein the second multiplexer is greater than the first multiplexer The multiplexer is further away from the bending zone.
  • each signal output line is electrically connected to a column of sub-pixels.
  • the signal output line of the second multiplexer is located between two first multiplexers adjacent to the second multiplexer.
  • the display panel further includes: a first fan-out area between the bending area and the display area; between the bending area and the multiple multiplexers And a third fan-out area between the multiplexers and the bonding area; wherein the bonding area passes through the third fan-out area Connected to the multiple multiplexers, and the multiple multiplexers are electrically connected to the multiple sub-multiplexers through the second fan-out area, the bending area, and the first fan-out area Pixels.
  • the display panel further includes: a unit test area between the plurality of multiplexers and the second fan-out area; and a unit test area between the unit test area and the plurality of An electrostatic protection zone between multiplexers; wherein the multiple multiplexers are electrically connected to the electrostatic protection zone, the electrostatic protection zone is electrically connected to the unit test area, and the unit test The area is electrically connected to the plurality of sub-pixels through the second fan-out area, the bending area, and the first fan-out area.
  • each multiplexer includes a first transistor and a second transistor; wherein, the first transistor and the second transistor share a first electrode, and the first electrode passes the signal
  • the input line is electrically connected to the bonding area, the first electrode is configured to receive a data signal; the second electrode of the first transistor is electrically connected to the second electrode through one of the two signal output lines One column of sub-pixels, the control electrode of the first transistor is configured to receive the first control signal; the second electrode of the second transistor is electrically connected to the second signal output line through the other of the two signal output lines In the column of sub-pixels, the control electrode of the second transistor is configured to receive a second control signal.
  • each sub-pixel includes a third transistor and a capacitor
  • the third transistor includes: an active layer; a first insulating layer covering the active layer; A gate on one side of the active layer; a second insulating layer covering the gate; an interlayer insulating layer on the side of the second insulating layer away from the gate; and insulating between the layers
  • the capacitor includes: and the gate electrode A first conductive layer in the same layer, wherein the second insulating layer also covers the first conductive layer; and a second conductive layer on the side of the second insulating layer away from the first conductive layer , Wherein the interlayer insulating layer also covers the second conductive layer.
  • the first electrode, the second electrode of the first transistor, and the second electrode of the second transistor are all connected to the source and the The drain is on the same layer, and the control electrode of the first transistor and the control electrode of the second transistor are on the same layer as the gate.
  • the signal input line of the first multiplexer and the signal input line of the second multiplexer are in different layers.
  • the first electrode of the first multiplexer is electrically connected to the signal input line of the first multiplexer, and the signal input line of the first multiplexer is connected to the signal input line of the first multiplexer.
  • the second conductive layer is in the same layer; and the first electrode of the second multiplexer is electrically connected to the signal input line of the second multiplexer, the second multiplexer The signal input line is on the same layer as the gate.
  • the two signal output lines include a first signal output line and a second signal output line; the second electrode of the first transistor is electrically connected to the first signal output line, and the first signal output line The signal output line and the second conductive layer are in the same layer; and the second electrode of the second transistor is electrically connected to the second signal output line, and the second signal output line and the gate are in the same layer .
  • each sub-pixel further includes: a third insulating layer covering the source electrode and the drain electrode; on the third insulating layer that is far from the source electrode and the drain electrode The first planarization layer on the side; the third conductive layer on the side of the first planarization layer away from the third insulating layer, wherein the third conductive layer is connected to the source or the drain Electrode is electrically connected; a second planarization layer covering the third conductive layer; an anode layer on the side of the second planarization layer away from the third conductive layer, wherein the anode layer and the The third conductive layer is electrically connected; the pixel defining layer having an opening on the second planarization layer, the opening exposing at least a part of the anode layer; the function of being in the opening and connected to the anode layer And a cathode layer on the side of the functional layer away from the anode layer.
  • the bending area includes a plurality of first wires, and each of the plurality of first wires is in the same layer as the third conductive layer; each first wire passes through the second wire or the third conductive layer.
  • Three wires are electrically connected to the display area, the second wire and the gate are in the same layer, and the third wire and the second conductive layer are in the same layer.
  • a display device including: the display panel as described above.
  • FIG. 1 is a schematic diagram showing the structure of a display panel according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing the structural connection of the peripheral area of the display panel according to an embodiment of the present disclosure
  • 3A is a schematic cross-sectional view showing a display panel in the related art
  • 3B is a schematic cross-sectional view showing a display panel according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram showing the circuit connection of a multiplexer according to an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view showing sub-pixels of a display panel according to an embodiment of the present disclosure
  • FIG. 6A is a top view showing a multiplexer according to an embodiment of the present disclosure.
  • 6B is a schematic cross-sectional view showing a multiplexer according to an embodiment of the present disclosure taken along the line A-A' in FIG. 6A;
  • 6C is a schematic cross-sectional view showing a multiplexer according to an embodiment of the present disclosure taken along the line B-B' in FIG. 6A;
  • FIG. 7A is an enlarged schematic diagram showing a partial structure of a multiplexer according to an embodiment of the present disclosure at block 610 shown in FIG. 6A;
  • FIG. 7B is a schematic cross-sectional view showing the structure taken along the line C-C' in FIG. 7A;
  • FIG. 7C is a schematic cross-sectional view showing the structure taken along the line D-D' in FIG. 7A;
  • FIG. 8A is an enlarged schematic diagram showing a partial structure of a multiplexer according to an embodiment of the present disclosure at block 620 shown in FIG. 6A;
  • FIG. 8B is a schematic cross-sectional view showing the structure taken along the line E-E' in FIG. 8A;
  • FIG. 9 is a schematic diagram showing a structure of a bending area of a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram showing the structure of a display panel in the related art.
  • FIG. 11 is an enlarged schematic diagram showing a part of the structure of the display panel in the related art at the block 1040 shown in FIG. 10.
  • a specific device when it is described that a specific device is located between the first device and the second device, there may or may not be an intermediate device between the specific device and the first device or the second device.
  • the specific device When it is described that a specific device is connected to another device, the specific device may be directly connected to the other device without an intervening device, or may not be directly connected to the other device but with an intervening device.
  • FIG. 10 is a schematic diagram showing the structure of a display panel in the related art.
  • the display panel may include a display area 10, a substrate 201, a bending area 210, a binding area 230, a first fan-out area 240, a fan-shaped circuit connection area 1010 and a plurality of multiplexers 1020.
  • the multiplexer 1020 is provided between the display area 10 and the bending area 210.
  • the multiplexer 1020 is below the display area 10.
  • FIG. 11 is an enlarged schematic diagram showing a part of the structure of the display panel in the related art at the block 1040 shown in FIG. 10.
  • the display panel further includes a GOA circuit (Gate Driver on Array) 1102 at the frame of the display panel.
  • GOA circuit Gate Driver on Array
  • the inventors of the present disclosure found that, as shown in FIG. 11, in the related art, since the multiplexer 1020 is arranged between the display area 10 and the bending area 210, the corners or corners of the display panel are rounded, Because the signal lines of the GOA circuit need to be horizontally connected to the sub-pixels of the display area, the multiplexer 1020 placed vertically with the rounded corners is likely to cause wiring conflicts.
  • the inventor of the present disclosure proposes a display panel to reduce the wiring conflict between the multiplexer and the signal line of the GOA circuit.
  • the display panel according to some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • FIG. 1 is a schematic diagram showing the structure of a display panel according to an embodiment of the present disclosure.
  • the display panel includes: a display area 10 and a peripheral area 20 surrounding the display area 10.
  • the display area 10 includes a pixel array disposed on a substrate (for example, the substrate 201 shown in FIG. 3B or FIG. 5 later).
  • the pixel array includes a plurality of sub-pixels 101.
  • the peripheral area 20 includes a bending area 210 on the side of the display area 10, a plurality of multiplexers 221 and 222 on the side of the bending area 210 away from the display area 10, and the multiple multiplexers The binding area 230 on the side away from the bending area 210 of the device.
  • the plurality of multiplexers 221 and 222 are provided on the substrate.
  • the display area may include a part of the substrate below the display area, and the peripheral area may include another part of the substrate below the peripheral area.
  • each signal input line 2210 and two signal output lines 2201 and 2202 are connected to each multiplexer.
  • the signal input line 2210 is electrically connected to the binding area 230.
  • the orthographic projection of the signal input line 2210 on the substrate and the orthographic projection of the bending area 210 on the substrate do not overlap.
  • each signal output line 2201 or 2202 is electrically connected to a column of sub-pixels 101. In this way, the number of pins in the integrated circuit can be reduced, and the process difficulty and cost of the module can be reduced.
  • the bonding area 230 may include bonding terminals (for example, COP) for bonding integrated circuits, or signal input lines for COF.
  • the binding area 230 is electrically connected to the multiple multiplexers.
  • the multiple multiplexers are electrically connected to the multiple sub-pixels 101 through the bending area 210.
  • the display panel includes a display area and a peripheral area surrounding the display area.
  • the display area includes a pixel array disposed on the substrate.
  • the pixel array includes a plurality of sub-pixels.
  • the peripheral area includes: a bending area on one side of the display area; a plurality of multiplexers on the side of the bending area away from the display area; and a side of the multiple multiplexers away from the bending area.
  • the binding area is provided on the substrate. At least one signal input line and two signal output lines are connected to each multiplexer.
  • the binding area is electrically connected to the multiple multiplexers.
  • the multiple multiplexers are electrically connected to the multiple sub-pixels through the bending area.
  • the signal input line is electrically connected to the binding area.
  • the orthographic projection of the signal input line on the substrate and the orthographic projection of the bending area on the substrate do not overlap.
  • the multiple multiplexers are arranged between the bending area and the binding area, that is, under the bending area, so the signals of the multiplexer and the GOA circuit can be reduced.
  • the wiring conflicts of the wires can also reduce the signal interference between the multiplexer and the signal line of the GOA circuit.
  • a multiplexer is provided between the display area and the bending area, and the multiplexer is easily affected by the bending crack of the bending area.
  • the multiplexer is arranged below the bending area. This way, on the one hand, the number of integrated circuit pins is reduced, and the cost and bending difficulty of the integrated circuit are reduced; on the other hand, the risk of bending and cracking can also be avoided as much as possible, thereby improving the yield.
  • the multiple multiplexers include a first multiplexer 221 and a second multiplexer 222.
  • the second multiplexer 222 is farther away from the bending area 210 than the first multiplexer 221.
  • the signal output line of the second multiplexer 222 is located between two first multiplexers 221 adjacent to the second multiplexer 222. In other words, the signal output line of the second multiplexer 222 passes between two first multiplexers adjacent to the second multiplexer.
  • the plurality of multiplexers may include two-row multiplexers.
  • the two-row multiplexer includes a first multiplexer and a second multiplexer arranged in a staggered manner.
  • the first multiplexer is in the first row
  • the second multiplexer is in the second row.
  • the multiplexer adjacent to the multiplexer is in the second row; when a certain multiplexer is in the second row In the case of a row, the multiplexer adjacent to the multiplexer is in the first row.
  • the lateral width of the Pad area in the peripheral area can be reduced (that is, the Pad area is in the multiple multiplexers Width in the row direction), and can reduce the length of the wiring of the multiplexer at both ends away from the bonding area, thereby reducing the impedance of the wiring and improving the stability of the signal.
  • FIG. 2 is a schematic diagram showing the structural connection of the peripheral area of the display panel according to an embodiment of the present disclosure.
  • the display panel includes a bending area 210, a plurality of multiplexers 221 and 222, and a binding area 230.
  • the display panel may further include a first fan-out area 240 between the bending area 210 and the display area 10.
  • the display panel may further include a second fan-out area 250 between the bending area 210 and the multiple multiplexers 221 and 222.
  • the display panel may further include a third fan-out area 260 between the multiple multiplexers 221 and 222 and the binding area 230.
  • the bonding area 230 is electrically connected to the multiple multiplexers through the third fan-out area 260.
  • the multiple multiplexers are electrically connected to a plurality of sub-pixels of the display area 10 through the second fan-out area 250, the bending area 210, and the first fan-out area 240.
  • the display panel may further include a cell test (CT) between the multiplexers 221 and 222 and the second fan-out area 250 District 270.
  • CT cell test
  • the unit test area 270 is electrically connected to the plurality of sub-pixels through the second fan-out area 250, the bending area 210, and the first fan-out area 240.
  • the display panel may further include an electrostatic protection area 280 between the unit test area 270 and the multiple multiplexers 221 and 222.
  • the multiple multiplexers are electrically connected to the electrostatic protection zone 280.
  • the electrostatic protection area also referred to as an ESD (Electro-Static Discharge) area
  • ESD Electro-Static Discharge
  • the structure of the peripheral area of the display panel is provided.
  • the data signal may sequentially pass through the bonding area 230, the third fan-out area 260, multiple multiplexers 221 or 222, the electrostatic protection area 280, the unit test area 270, the second fan-out area 250, and the bending area.
  • 210 and the first fan-out area 240 are transmitted to the sub-pixels in the display area 10 to drive the sub-pixels to emit light. In this way, the display function of the display panel can be realized.
  • FIG. 3A is a schematic cross-sectional view showing a display panel in the related art.
  • the display area 10, the multiplexer 1020, the first fan-out area 240, the bending area 210, the Pad area 310, and the substrate 201 are shown in FIG. 3A.
  • the Pad area 310 may include: a second fan-out area, a unit test area, an electrostatic protection area, a third fan-out area, and a binding area.
  • the lower frame of the display panel includes a portion of the peripheral area from the multiplexer 1020 to the bending portion of the bending area 210. The inventor of the present disclosure found that in the related art, since the multiplexer 1020 is disposed between the display area 10 and the bending area 210, it is not conducive to narrowing the lower frame.
  • FIG. 3B is a schematic cross-sectional view showing a display panel according to an embodiment of the present disclosure.
  • the Pad area 320 may include: a second fan-out area, a unit test area, an electrostatic protection area, a multiplexer 221 or 222, a third fan-out area, and a binding area.
  • the display panel of some embodiments of the present disclosure can obviously narrow the bottom frame.
  • the lower frame of the display panel of this embodiment can be reduced by about 190 ⁇ m. Therefore, the display panel of the embodiment of the present disclosure can not only reduce the conflict between the multiplexer and the signal line of the GOA circuit, but also make the lower frame of the display panel narrower, thereby promoting the realization of a full screen.
  • the bending zone refers to the area from the starting position of the surface curvature of the substrate to the ending position of the surface curvature of the substrate, or it can also be said to refer to the position interval where the curvature of the substrate changes, as shown in FIG. 3B .
  • Fig. 4 is a schematic diagram showing the circuit connection of a multiplexer according to an embodiment of the present disclosure.
  • each multiplexer 221 (or 222) includes a first transistor M1 and a second transistor M2.
  • the first transistor M1 and the second transistor M2 share a first electrode 401.
  • the first electrode 401 is electrically connected to the binding area 230 through a signal input line.
  • the first electrode is configured to receive a data signal S D.
  • the second electrode 412 of the first transistor M1 is electrically connected to the first column of sub-pixels through one of the two signal output lines.
  • the control electrode 413 of the first transistor M1 is configured to receive the first control signal S G1 .
  • the first transistor M1 is configured to be turned on or off under the control of the first control signal S G1.
  • the second electrode 422 of the second transistor M2 is electrically connected to the second column of sub-pixels through the other signal output line of the two signal output lines.
  • the second column of sub-pixels is different from the first column of sub-pixels.
  • the control electrode 423 of the second transistor M2 is configured to receive the second control signal S G2 .
  • the second transistor M2 is configured to be turned on or off under the control of the second control signal S G2.
  • the circuit structure of the multiplexer according to some embodiments of the present disclosure is provided.
  • the first control signal is used to control the first transistor
  • the second control signal is used to control the second transistor, so that the data received by the common electrode (ie, the first electrode) of the two switching transistors can be
  • the signal is transmitted to the corresponding sub-pixel through the first transistor or the second transistor to realize the light emission of the sub-pixel.
  • the multiplexer can reduce the number of pins in the integrated circuit, and reduce the difficulty and cost of the module process.
  • the first transistor M1 and the second transistor may be N-channel Metal Oxide Semiconductor (N-channel Metal Oxide Semiconductor) transistors. In other embodiments, the first transistor M1 and the second transistor may be PMOS (P-channel Metal Oxide Semiconductor, P-channel metal oxide semiconductor) transistors.
  • FIG. 5 is a schematic cross-sectional view showing sub-pixels of a display panel according to an embodiment of the present disclosure.
  • each sub-pixel includes a pixel circuit for driving the sub-pixel to emit light
  • the pixel circuit includes at least a third transistor 510 and a capacitor 530. That is, each sub-pixel may include the third transistor 510 and the capacitor 530.
  • the third transistor 510 and the capacitor 530 are both located above the substrate 201.
  • the third transistor 510 may be a switching transistor or a driving transistor.
  • the aforementioned pixel circuit may be a pixel circuit such as 2T1C, 3T1C, 7T1C, 7T2C, 9T1C, or 9T2C.
  • T represents a transistor
  • C represents a capacitor.
  • 2T1C represents a pixel circuit including 2 transistors and 1 capacitor.
  • the pixel circuit herein is not limited to the pixel circuit disclosed herein, and may also be a pixel circuit with other structures, as long as it can drive the light-emitting device to emit light.
  • the third transistor 510 includes an active layer (for example, it may be referred to as a first active layer) 511.
  • the active layer 511 may be located on the buffer layer 501.
  • the buffer layer 501 is on the substrate 201.
  • the active layer 511 may include a semiconductor layer.
  • the material of the active layer 511 may include at least one of polysilicon and amorphous silicon.
  • the third transistor 510 further includes a first insulating layer 512 covering the active layer 511.
  • the first insulating layer 512 may be an inorganic insulating layer.
  • the material of the first insulating layer 512 may include silicon dioxide, silicon nitride, or the like.
  • the third transistor 510 further includes a gate 513 on the side of the first insulating layer 512 away from the active layer 511.
  • the material of the gate 513 may include metal such as molybdenum (Mo).
  • the third transistor 510 may further include a second insulating layer 514 covering the gate 513.
  • the material of the second insulating layer 514 may be an inorganic insulating layer, such as silicon dioxide or silicon nitride.
  • the third transistor 510 may further include an interlayer insulating layer 516 on the side of the second insulating layer 514 away from the gate 513.
  • the material of the interlayer insulating layer 516 may include an inorganic insulating material.
  • the inorganic insulating material may include silicon dioxide, silicon nitride, or the like.
  • the third transistor 510 further includes a source 517 and a drain 518 on the side of the interlayer insulating layer 516 away from the second insulating layer 514.
  • the material of the source electrode 517 and the drain electrode 518 may include at least one of titanium (Ti) and aluminum (Al).
  • the source electrode 517 and the drain electrode 518 may respectively include a three-layer structure of Ti layer/Al layer/Ti layer.
  • the source electrode 517 and the drain electrode 518 are electrically connected to the active layer 511 respectively.
  • the source electrode 517 is electrically connected to the active layer 511 through a first conductive via 521 passing through the first insulating layer 512, the second insulating layer 514, and the interlayer insulating layer 516.
  • the drain electrode 518 is electrically connected to the active layer 511 through a second conductive via 522 passing through the first insulating layer 512, the second insulating layer 514, and the interlayer insulating layer 516.
  • the capacitor 530 includes a first conductive layer 531 on the same layer as the gate 513.
  • the material of the first conductive layer 531 may be the same as the material of the gate 513. This can facilitate the manufacture of the display panel.
  • the second insulating layer 514 also covers the first conductive layer 531.
  • the capacitor 530 further includes a second conductive layer 532 on the side of the second insulating layer 514 away from the first conductive layer 531.
  • the interlayer insulating layer 516 also covers the second conductive layer 532.
  • the materials of the first conductive layer 531 and the second conductive layer 532 may both include metals such as molybdenum.
  • the capacitor 530 can function to store data.
  • the "same layer” in the embodiments of the present disclosure refers to film layers on the same structural layer.
  • the film layer in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a patterning process.
  • a patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific graphics may also be at different heights or have different thicknesses.
  • the first conductive layer 531 and the gate 513 are in the same layer.
  • the first conductive layer 531 and the gate 513 are both on the first insulating layer 512.
  • the first conductive layer 531 and the gate 513 can be formed by the same patterning process.
  • each sub-pixel may further include a third insulating layer 541 covering the source electrode 517 and the drain electrode 518.
  • the material of the third insulating layer 541 may include silicon dioxide, silicon nitride, or the like.
  • the sub-pixel may further include a first planarization layer 542 on the side of the third insulating layer 541 away from the source electrode 517 and the drain electrode 518.
  • the material of the first planarization layer 542 may include an organic insulating material.
  • the sub-pixel may further include a third conductive layer 543 on a side of the first planarization layer 542 away from the third insulating layer 541.
  • the third conductive layer 543 is electrically connected to the source electrode 517 or the drain electrode 518.
  • the material of the third conductive layer 543 may include at least one of titanium (Ti) and aluminum (Al).
  • the third conductive layer 543 may include a three-layer structure of Ti layer/Al layer/Ti layer.
  • the third conductive layer 543 may be electrically connected to the source electrode 517 or the drain electrode 518 through a third conductive via 523 passing through the third insulating layer 541 and the first planarization layer 542.
  • the sub-pixel may further include a second planarization layer 544 covering the third conductive layer 543.
  • the material of the second planarization layer 544 may include an organic insulating material.
  • the sub-pixel may further include an anode layer 545 on the side of the second planarization layer 544 away from the third conductive layer 543.
  • the anode layer 545 is electrically connected to the third conductive layer 543.
  • the anode layer 545 is electrically connected to the third conductive layer 543 through the fourth conductive via 524 passing through the second planarization layer 544.
  • the sub-pixel may further include a pixel defining layer 546 with an opening 5461 on the second planarization layer 544.
  • the opening 5461 exposes at least a part of the anode layer 545.
  • the sub-pixel may further include a functional layer 547 in the opening 5461 and connected to the anode layer 545.
  • the functional layer 547 may include a light-emitting layer or the like.
  • the sub-pixel may further include a cathode layer 548 on the side of the functional layer 547 away from the anode layer 545.
  • the light emitting device includes an anode layer 545, a functional layer 547, and a cathode layer 548.
  • the display panel may include an encapsulation layer 549 covering the cathode layer 548.
  • the sub-pixel may include a third transistor, a capacitor, a light emitting device, and so on.
  • the sub-pixel may also include other structures or layers, which will not be described in detail here.
  • FIG. 6A is a top view showing a multiplexer according to an embodiment of the present disclosure.
  • 6B is a schematic cross-sectional view showing the multiplexer according to an embodiment of the present disclosure taken along the line A-A' in FIG. 6A.
  • each multiplexer 221 or 222 includes the second electrode 412 and the control electrode 413 of the first transistor, the second electrode 422 and the control electrode 423 of the second transistor, and the first transistor and the second transistor.
  • FIG. 6A also shows the anti-static unit 282 of the electrostatic protection zone 280.
  • the first electrode 401, the second electrode 412 of the first transistor, and the second electrode 422 of the second transistor are all connected to the source
  • the electrode 517 and the drain electrode 518 are in the same layer.
  • the first electrode 401, the second electrodes 412 and 422, the source electrode 517, and the drain electrode 518 are all on the interlayer insulating layer 516.
  • the first electrode 401, the second electrode 412 of the first transistor, and the second electrode 422 of the second transistor are all located on the interlayer insulating layer 516.
  • Such a same-layer design can facilitate the manufacture of the display panel and save costs.
  • control electrode 413 of the first transistor and the control electrode 423 of the second transistor are on the same layer as the gate 513.
  • the control electrode 413 of the first transistor, the control electrode 423 and the gate 513 of the second transistor are all on the first insulating layer 512.
  • the control electrode 413 of the first transistor and the control electrode 423 of the second transistor are both on the first insulating layer 512.
  • the first transistor and the second transistor may share an active layer (may be referred to as a second active layer) 414.
  • the second active layer 414 is located on the buffer layer 501. Therefore, the second active layer 414 and the active layer (ie, the first active layer) 511 of the third transistor are in the same layer.
  • the first electrode 401 is electrically connected to the second active layer 414 through the fifth conductive via 431.
  • the fifth conductive via 431 penetrates the interlayer insulating layer 516, the second insulating layer 514, and the first insulating layer 512.
  • the second electrode 412 of the first transistor is electrically connected to the second active layer 414 through the sixth conductive via 432.
  • the sixth conductive via 432 penetrates the interlayer insulating layer 516, the second insulating layer 514 and the first insulating layer 512.
  • the second electrode 422 of the second transistor is electrically connected to the second active layer 414 through the seventh conductive via 433.
  • the seventh conductive via 433 penetrates the interlayer insulating layer 516, the second insulating layer 514, and the first insulating layer 512.
  • the second electrode 412 of the first transistor is electrically connected to one end of the second active layer 414
  • the second electrode 422 of the second transistor is electrically connected to the other end of the second active layer 414.
  • FIG. 6C is a schematic cross-sectional view showing the multiplexer according to an embodiment of the present disclosure taken along the line B-B' in FIG. 6A.
  • the signal input line 2210 of the first multiplexer 221 (for example, may be referred to as the first signal input line 2211) and the signal input line 2211 of the second multiplexer 222
  • the signal input line 2210 (for example, may be referred to as the second signal input line 2212) is in a different layer.
  • the first electrode 401 of the first multiplexer 221 is electrically connected to the signal input line 2210 (ie, the first signal input line 2211) of the first multiplexer 221.
  • the signal input line of the first multiplexer 221 and the second conductive layer 532 are in the same layer.
  • the signal input line of the first multiplexer 221 and the second conductive layer 532 are both on the second insulating layer 514.
  • the first signal input line 2211 is on the second insulating layer 514.
  • the first electrode 401 of the second multiplexer 222 is electrically connected to the signal input line 2210 (ie, the second signal input line 2212) of the second multiplexer 222.
  • the signal input line of the second multiplexer 222 and the gate 513 are on the same layer.
  • the signal input line of the second multiplexer 222 and the gate 513 are both on the first insulating layer 512.
  • the second signal input line 2212 is on the first insulating layer 512.
  • the signal input line of the first multiplexer and the second conductive layer are on the same layer, and the signal input line of the second multiplexer and the gate are on the same layer, so that It is convenient to manufacture the display panel and saves the cost. In addition, it can also try to prevent the danger of short-circuiting of the signal input lines of different multiplexers.
  • FIG. 7A is an enlarged schematic diagram showing a partial structure of a multiplexer at block 610 shown in FIG. 6A according to an embodiment of the present disclosure.
  • the display panel may further include a first scan signal line 601 and a second scan signal line 602 electrically connected to each multiplexer.
  • the first scan signal line 601 is electrically connected to the control electrode 413 of the first transistor.
  • the first scan signal line 601 can transmit a first control signal to the first transistor.
  • the second scan signal line 602 is electrically connected to the control electrode 423 of the second transistor.
  • the second scan signal line 602 can transmit a second control signal to the second transistor. In this way, the control of the multiplexer can be achieved.
  • a comparison can be set between two layer structures that need to be electrically connected (for example, between the first scan signal line 601 and the control electrode 413 of the first transistor, etc.). More conductive vias, which can reduce the connection impedance between the two layers.
  • FIG. 7B is a schematic cross-sectional view showing the structure taken along the line C-C' in FIG. 7A.
  • the first scan signal line 601 is located on the interlayer insulating layer 516. Therefore, the first scan signal line 601 can be in the same layer as the source 517 and the drain 518 of the third transistor.
  • the first scan signal line is electrically connected to the control electrode 413 of the first transistor through the eighth conductive via 711.
  • the eighth conductive via 711 penetrates the interlayer insulating layer 516 and the second insulating layer 514.
  • the manner in which the second scan signal line 602 is electrically connected to the control electrode 423 of the second transistor is similar to the manner in which the first scan signal line is electrically connected to the control electrode 413 of the first transistor, and will not be described in detail here.
  • Fig. 7C is a schematic cross-sectional view showing the structure taken along the line D-D' in Fig. 7A.
  • the first electrode 401 of the first multiplexer 221 may be electrically connected to the first signal input line 2211 through the ninth conductive via 712.
  • the ninth conductive via 712 penetrates the interlayer insulating layer 516. In this way, the electrical connection between the first electrode and the first signal line is realized.
  • the first electrode 401 of the second multiplexer 222 may be electrically connected to the second signal input line 2212 through a tenth conductive via (not shown in the figure).
  • the tenth conductive via passes through the interlayer insulating layer 516 and the second insulating layer 514.
  • FIG. 8A is an enlarged schematic diagram showing a partial structure of a multiplexer at block 620 shown in FIG. 6A according to an embodiment of the present disclosure.
  • FIG. 8B is a schematic cross-sectional view showing the structure taken along the line E-E' in FIG. 8A.
  • the two signal output lines of each multiplexer include a first signal output line 2201 and a second signal output line 2202.
  • the second electrode 412 of the first transistor is electrically connected to the first signal output line 2201.
  • the first signal output line 2201 and the second conductive layer 532 are in the same layer.
  • the first signal output line 2201 and the second conductive layer 532 are both on the second insulating layer 514.
  • Such a same-layer design can facilitate the manufacture of the display panel and save costs.
  • the first signal output line 2201 is on the second insulating layer 514.
  • the second electrode 412 of the first transistor is electrically connected to the first signal output line 2201 through the eleventh conductive via 811.
  • the eleventh conductive via 811 penetrates the interlayer insulating layer 516.
  • the second electrode 422 of the second transistor is electrically connected to the second signal output line 2202.
  • the second signal output line 2202 and the gate 513 are in the same layer.
  • the second signal output line 2202 and the gate 513 are both on the first insulating layer 512.
  • Such a same-layer design can facilitate the manufacture of the display panel and save costs.
  • the second signal output line 2202 is on the first insulating layer 512.
  • the second electrode 422 of the second transistor is electrically connected to the second signal output line 2202 through the twelfth conductive via 812.
  • the twelfth conductive via 812 penetrates the interlayer insulating layer 516 and the second insulating layer 514.
  • the signal input line and other structures e.g., electrodes
  • the signal input line may be integrally formed.
  • the signal output line and other structures for example, electrodes
  • the signal output line may be integrally formed.
  • FIG. 9 is a schematic diagram showing a structure of a bending area of a display panel according to an embodiment of the present disclosure.
  • the bending area 210 may include a plurality of first wires 211.
  • Each of the plurality of first conductive lines 211 and the third conductive layer 543 are in the same layer.
  • the first conductive line 211 and the third conductive layer 543 are both on the first planarization layer 542.
  • Such a same-layer design can facilitate the manufacture of the display panel and save costs.
  • each first wire 211 is electrically connected to the display area through a second wire 902 or a third wire 903.
  • the second wire 902 and the gate 513 are on the same layer.
  • both the second wire 902 and the gate 513 are on the first insulating layer 512.
  • the third wire 903 and the second conductive layer 532 are in the same layer.
  • the third wire 903 and the second conductive layer 532 are both on the second insulating layer 514. This design can prevent the second wire from being short-circuited with the third conductive line as much as possible.
  • a display device may include the display panel as described above.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.

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Abstract

本公开提供了一种显示面板和显示装置。该显示面板包括显示区域和围绕显示区域的周边区域。该显示区域包括设置在基板上的像素阵列。该像素阵列包括多个子像素。该周边区域包括：在显示区域一侧的弯折区；在弯折区的远离显示区域一侧的多个多路复用器，其中，该多个多路复用器设置在基板上，每个多路复用器至少连接有一个信号输入线和两个信号输出线；以及在该多个多路复用器的远离弯折区一侧的绑定区。该多个多路复用器经过弯折区电连接至多个子像素。该信号输入线电连接至绑定区。该信号输入线在基板上的正投影与弯折区在所述基板上的正投影不重叠。本公开可以减小多路复用器与GOA电路的信号线的布线冲突。

Description

显示面板和显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种显示面板和显示装置。
背景技术
在实现OLED(Organic Light Emitting Diode，有机发光二极管)显示屏的下边框窄化的过程中，显示器件背板的Pad(衬垫)区电路排布设计尤为重要。OLED驱动方式复杂。另外，为了提升显示器的分辨率，需要增加显示器的显示区内的像素，因此需要排布设计更多的信号线来控制这些像素。这导致IC(Integrated Circuit，集成电路)需要更多的管脚(Pin)来输出像素驱动信号。但过多的管脚会导致集成电路的绑定复杂，而且会使COP(Chip on plastic，塑料上的芯片)或COF(Chip On Film，膜上芯片)工艺的实现变得更加困难。因此，在相关技术中，通过设置多路复用器(multiplexer，简称为Mux)电路来减少集成电路的管脚数量。
在相关技术中，在显示面板中设置多个多路复用器。每个多路复用器可以使用IC中的一个数据信号源驱动显示面板中的两列子像素。这样可以减少IC中的管脚数目，降低模组工艺难度并缩减IC尺寸。由于多路复用器具有上述优点，因此，多路复用器被越来越多的应用于显示面板(例如AMOLED(Active-matrix Organic Light Emitting Diode，有源矩阵有机发光二极管)显示面板)。
发明内容
根据本公开实施例的一个方面，提供了一种显示面板，包括：显示区域，包括设置在基板上的像素阵列，所述像素阵列包括多个子像素；和围绕所述显示区域的周边区域，所述周边区域包括：在所述显示区域一侧的弯折区；在所述弯折区的远离所述显示区域一侧的多个多路复用器，其中，所述多个多路复用器设置在所述基板上，每个多路复用器至少连接有一个信号输入线和两个信号输出线；以及在所述多个多路复用器的远离所述弯折区一侧的绑定区；其中，所述多个多路复用器经过所述弯折区电连接至所述多个子像素；所述信号输入线电连接至所述绑定区，所述信号输入线在所述基板上的正投影与所述弯折区在所述基板上的正投影不重叠。
在一些实施例中，所述多个多路复用器包括第一多路复用器和第二多路复用器，其中，所述第二多路复用器比所述第一多路复用器更远离所述弯折区。
在一些实施例中，每个信号输出线电连接至一列子像素。
在一些实施例中，所述第二多路复用器的信号输出线位于与所述第二多路复用器相邻的两个第一多路复用器之间。
在一些实施例中，所述显示面板还包括：在所述弯折区与所述显示区域之间的第一扇出区；在所述弯折区与所述多个多路复用器之间的第二扇出区；以及在所述多个多路复用器与所述绑定区之间的第三扇出区；其中，所述绑定区经过所述第三扇出区电连接至所述多个多路复用器，所述多个多路复用器经过所述第二扇出区、所述弯折区和所述第一扇出区电连接至所述多个子像素。
在一些实施例中，所述显示面板还包括：在所述多个多路复用器与所述第二扇出区之间的单元测试区；以及在所述单元测试区与所述多个多路复用器之间的静电保护区；其中，所述多个多路复用器与所述静电保护区电连接，所述静电保护区与所述单元测试区电连接，所述单元测试区经过所述第二扇出区、所述弯折区和所述第一扇出区电连接所述多个子像素。
在一些实施例中，每个多路复用器包括第一晶体管和第二晶体管；其中，所述第一晶体管和所述第二晶体管共用一个第一电极，所述第一电极通过所述信号输入线电连接到所述绑定区，所述第一电极被配置为接收数据信号；所述第一晶体管的第二电极通过所述两个信号输出线中的一个信号输出线电连接至第一列子像素，所述第一晶体管的控制电极被配置为接收第一控制信号；所述第二晶体管的第二电极通过所述两个信号输出线中的另一个信号输出线电连接至第二列子像素，所述第二晶体管的控制电极被配置为接收第二控制信号。
在一些实施例中，每个子像素包括第三晶体管和电容器，所述第三晶体管包括：有源层；覆盖所述有源层的第一绝缘层；在所述第一绝缘层的远离所述有源层的一侧的栅极；覆盖所述栅极的第二绝缘层；在所述第二绝缘层的远离所述栅极的一侧的层间绝缘层；以及在所述层间绝缘层的远离所述第二绝缘层的一侧的源极和漏极，其中，所述源极和所述漏极分别与所述有源层电连接；所述电容器包括：与所述栅极处于同一层的第一导电层，其中，所述第二绝缘层还覆盖所述第一导电层；以及在所述第二绝缘层的远离所述第一导电层的一侧的第二导电层，其中，所述层间绝缘层还覆盖所述第二导电层。
在一些实施例中，在每个多路复用器中，所述第一电极、所述第一晶体管的第二电极和所述第二晶体管的第二电极均与所述源极和所述漏极处于同一层，所述第一晶体管的控制电极和所述第二晶体管的控制电极与所述栅极处于同一层。
在一些实施例中，所述第一多路复用器的信号输入线与所述第二多路复用器的信号输入线处于不同层。
在一些实施例中，所述第一多路复用器的第一电极电连接至所述第一多路复用器的信号输入线，所述第一多路复用器的信号输入线与所述第二导电层处于同一层；以及所述第二多路复用器的第一电极电连接至所述第二多路复用器的信号输入线，所述第二多路复用器的信号输入线与所述栅极处于同一层。
在一些实施例中，所述两个信号输出线包括第一信号输出线和第二信号输出线；所述第一晶体管的第二电极电连接至所述第一信号输出线，所述第一信号输出线与所述第二导电层处于同一层；以及所述第二晶体管的第二电极电连接至所述第二信号输出线，所述第二信号输出线与所述栅极处于同一层。
在一些实施例中，每个子像素还包括：覆盖在所述源极和所述漏极上的第三绝缘层；在所述第三绝缘层的远离所述源极和所述漏极的一侧的第一平坦化层；在所述第一平坦化层的远离所述第三绝缘层的一侧的第三导电层，其中，所述第三导电层与所述源极或所述漏极电连接；覆盖所述第三导电层的第二平坦化层；在所述第二平坦化层的远离所述第三导电层的一侧的阳极层，其中，所述阳极层与所述第三导电层电连接；在所述第二平坦化层上的具有开口的像素界定层，所述开口露出所述阳极层的至少一部分；在所述开口内且与所述阳极层连接的功能层；以及在所述功能层的远离所述阳极层的一侧的阴极层。
在一些实施例中，所述弯折区包括多个第一导线，所述多个第一导线的每一个与所述第三导电层处于同一层；每个第一导线通过第二导线或第三导线电连接到所述显示区域，所述第二导线与所述栅极处于同一层，所述第三导线与所述第二导电层处于同一层。
根据本公开实施例的另一个方面，提供了一种显示装置，包括：如前所述的显示面板。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是示出根据本公开一个实施例的显示面板的结构示意图；
图2是示出根据本公开一个实施例的显示面板的周边区域的结构连接示意图；
图3A是示出在相关技术中的显示面板的截面示意图；
图3B是示出根据本公开一个实施例的显示面板的截面示意图；
图4是示出根据本公开一个实施例的多路复用器的电路连接示意图；
图5是示出根据本公开一个实施例的显示面板的子像素的截面示意图；
图6A是示出根据本公开一个实施例的多路复用器的俯视图；
图6B是示出根据本公开一个实施例的多路复用器沿着图6A中的线A-A′截取的截面示意图；
图6C是示出根据本公开一个实施例的多路复用器沿着图6A中的线B-B′截取的截面示意图；
图7A是示出根据本公开一个实施例的多路复用器在图6A所示的方框610处的部分结构的放大示意图；
图7B是示出沿着图7A中的线C-C′截取的结构的截面示意图；
图7C是示出沿着图7A中的线D-D′截取的结构的截面示意图；
图8A是示出根据本公开一个实施例的多路复用器在图6A所示的方框620处的部分结构的放大示意图；
图8B是示出沿着图8A中的线E-E′截取的结构的截面示意图；
图9是示出根据本公开一个实施例的显示面板的弯折区的结构示意图；
图10是示出在相关技术中的显示面板的结构示意图；
图11是示出在相关技术中的显示面板在图10所示的方框1040处的部分结构的放大示意图。
应当明白，附图中所示出的各个部分的尺寸并不必须按照实际的比例关系绘制。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定器件位于第一器件和第二器件之间时，在该特定器件与第一器件或第二器件之间可以存在居间器件，也可以不存在居间器件。当描述到特定器件连接其它器件时，该特定器件可以与所述其它器件直接连接而不具有居间器件，也可以不与所述其它器件直接连接而具有居间器件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
图10是示出在相关技术中的显示面板的结构示意图。如图10所示，该显示面板可以包括显示区域10、基板201、弯折区210、绑定区230、第一扇出区240、扇形电路连接区1010和多个多路复用器1020。如图10所示，多路复用器1020被设置在显示区域10与弯折区210之间。该多路复用器1020在显示区域10下方。图11是示出在相关技术中的显示面板在图10所示的方框1040处的部分结构的放大示意图。如图11所示，显示面板还包括在显示面板的边框处的GOA电路(Gate Driver on Array，阵列基板栅极驱动器，也即栅极驱动电路)1102。
本公开的发明人发现，如图11所示，在相关技术中，由于多路复用器1020被设置在显示区域10与弯折区210之间，在显示面板的下方圆角或者拐角位置，因为GOA 电路的信号线需要横向连接显示区域的子像素，因此与圆角位置竖直放置的多路复用器1020容易造成布线冲突。
鉴于此，本公开的发明人提出一种显示面板，以减小多路复用器与GOA电路的信号线的布线冲突。下面结合附图详细描述根据本公开一些实施例的显示面板。
图1是示出根据本公开一个实施例的显示面板的结构示意图。
如图1所示，该显示面板包括：显示区域10和围绕该显示区域10的周边区域20。该显示区域10包括设置在基板(例如在后面图3B或图5中示出的基板201)上的像素阵列。该像素阵列包括多个子像素101。周边区域20包括在显示区域10一侧的弯折区210，在.弯折区210的远离显示区域10一侧的多个多路复用器221和222，以及在该多个多路复用器的远离弯折区210一侧的绑定区230。该多个多路复用器221和222设置在基板上。
需要说明的是，在本公开的实施例中，显示区域可以包括在该显示区域下方的基板的一部分，周边区域可以包括在该周边区域下方的基板的另一部分。
在一些实施例中，如图1所示，每个多路复用器至少连接有一个信号输入线2210和两个信号输出线2201和2202。该信号输入线2210电连接至绑定区230。该信号输入线2210在基板上的正投影与弯折区210在该基板上的正投影不重叠。在一些实施例中，每个信号输出线2201或2202电连接至一列子像素101。这样可以减少集成电路中的管脚数目，降低模组工艺难度和成本。
例如，该绑定区230可以包括用于绑定集成电路的绑定端子(例如COP)，或者用于COF的信号输入线。该绑定区230与该多个多路复用器电连接。该多个多路复用器经过弯折区210电连接至所述多个子像素101。
至此，提供了根据本公开一些实施例的显示面板。该显示面板包括显示区域和围绕显示区域的周边区域。显示区域包括设置在基板上的像素阵列。该像素阵列包括多个子像素。周边区域包括：在显示区域一侧的弯折区；在弯折区的远离显示区域一侧的多个多路复用器；以及在该多个多路复用器的远离弯折区一侧的绑定区。所述多个多路复用器设置在基板上。每个多路复用器至少连接有一个信号输入线和两个信号输出线。绑定区与该多个多路复用器电连接。该多个多路复用器经过弯折区电连接至多个子像素。信号输入线电连接至绑定区。信号输入线在基板上的正投影与弯折区在基板上的正投影不重叠。在该显示面板中，所述多个多路复用器被设置在弯折区与绑定区之间，即在弯折区的下方，因此可以减小多路复用器与GOA电路的信号线的布线 冲突。另外，这样的设计也可以减小多路复用器与GOA电路的信号线的信号干扰。
另外，在相关技术中，多路复用器被设置在显示区域与弯折区之间，该多路复用器容易受弯折区的弯折破裂(Bending Crack)的影响。而在本公开的实施例中，将多路复用器设置在弯折区下方。这样一方面降低集成电路管脚的数量，降低集成电路的成本以及弯折难度；另一方面，也可以尽量避免弯折破裂的危险，从而提高良率。
在一些实施例中，如图1所示，该多个多路复用器包括第一多路复用器221和第二多路复用器222。该第二多路复用器222比第一多路复用器221更远离弯折区210。例如，第二多路复用器222的信号输出线位于与该第二多路复用器222相邻的两个第一多路复用器221之间。或者说，第二多路复用器222的信号输出线从与该第二多路复用器相邻的两个第一多路复用器之间穿过。
在该实施例中，所述多个多路复用器可以包括两行多路复用器。该两行多路复用器包括交错排列的第一多路复用器和第二多路复用器。第一多路复用器处于第一行，第二多路复用器处于第二行。或者说，在某个多路复用器处于第一行的情况下，与该多路复用器相邻的多路复用器处于第二行；在某个多路复用器处于第二行的情况下，与该多路复用器相邻的多路复用器处于第一行。
在上述实施例中，通过将多个多路复用器设置成两行多路复用器，可以减小周边区域的Pad区的横向宽度(即Pad区在所述多个多路复用器的行方向上的宽度)，而且可以减小处于两端的远离绑定区的多路复用器的布线的长度，从而减小该布线的阻抗，提高信号的稳定性。
需要说明的是，虽然图1中示出了两行多路复用器，但是本领域技术人员能够理解，可以设置三行或更多行的多路复用器。因此，本公开实施例的范围并不仅限于此。
图2是示出根据本公开一个实施例的显示面板的周边区域的结构连接示意图。如图2所示，显示面板包括弯折区210、多个多路复用器221和222、和绑定区230。
在一些实施例中，如图2所示，显示面板还可以包括在弯折区210与显示区域10之间的第一扇出区240。在一些实施例中，如图2所示，显示面板还可以包括在弯折区210与多个多路复用器221和222之间的第二扇出区250。在一些实施例中，如图2所示，显示面板还可以包括在所述多个多路复用器221和222与绑定区230之间的第三扇出区260。绑定区230经过第三扇出区260电连接至所述多个多路复用器。所述多个多路复用器经过第二扇出区250、弯折区210和第一扇出区240电连接至显示区域10的多个子像素。
在一些实施例中，如图2所示，显示面板还可以包括在所述多个多路复用器221和222与第二扇出区250之间的单元测试(Cell Test，简称为CT)区270。该单元测试区270经过第二扇出区250、弯折区210和第一扇出区240电连接所述多个子像素。
在一些实施例中，如图2所示，显示面板还可以包括在单元测试区270与所述多个多路复用器221和222之间的静电保护区280。该多个多路复用器与静电保护区280电连接。该静电保护区(也可以称为ESD(Electro-Static discharge，静电放电)区)280与单元测试区270电连接。
至此，提供了根据本公开一些实施例的显示面板的周边区域的结构。例如，数据信号可以依次通过绑定区230、第三扇出区260、多个多路复用器221或222、静电保护区280、单元测试区270、第二扇出区250、弯折区210和第一扇出区240，传输至显示区域10的子像素，驱动子像素发光。这样可以实现显示面板的显示功能。
图3A是示出在相关技术中的显示面板的截面示意图。
图3A中示出了显示区域10、多路复用器1020、第一扇出区240、弯折区210、Pad区310和基板201。在该实施例中，该Pad区310可以包括：第二扇出区、单元测试区、静电保护区、第三扇出区和绑定区。显示面板的下边框包括周边区域的从多路复用器1020到弯折区210的弯折处的部分。本公开的发明人发现，在相关技术中，由于多路复用器1020被设置在显示区域10与弯折区210之间，因此，不利于下边框的窄化。
图3B是示出根据本公开一个实施例的显示面板的截面示意图。
图3B示出了显示区域10、第一扇出区240、弯折区210、多路复用器221或222、Pad区320和基板201。在该实施例中，该Pad区320可以包括：第二扇出区、单元测试区、静电保护区、多路复用器221或222、第三扇出区和绑定区。在该实施例中，由于多路复用器221或222被设置在弯折区的下方，即，该多路复用器被设置在显示面板的背面，因此，相比图3A所示的显示面板，本公开一些实施例的显示面板明显可以缩窄下边框。例如，该实施例的显示面板的下边框可以缩减约190μm。因此，本公开实施例的显示面板不仅可以减小多路复用器与GOA电路的信号线的冲突，而且可以使得显示面板的下边框变得更窄，从而促进全面屏的实现。
这里，弯折区是指从基板的表面弧度的起始位置到该基板的表面弧度的终止位置之间的区域，或者也可以说是指基板的曲率发生变化的位置区间，如图3B所示。
图4是示出根据本公开一个实施例的多路复用器的电路连接示意图。
如图4所示，每个多路复用器221(或222)包括第一晶体管M1和第二晶体管M2。第一晶体管M1和第二晶体管M2共用一个第一电极401。该第一电极401通过信号输入线电连接到绑定区230。该第一电极被配置为接收数据信号S D。
第一晶体管M1的第二电极412通过所述两个信号输出线中的一个信号输出线电连接至第一列子像素。该第一晶体管M1的控制电极413被配置为接收第一控制信号S G1。该第一晶体管M1被配置为在第一控制信号S G1的控制下导通或关断。
第二晶体管M2的第二电极422通过所述两个信号输出线中的另一个信号输出线电连接至第二列子像素。该第二列子像素与第一列子像素不同。该第二晶体管M2的控制电极423被配置为接收第二控制信号S G2。该第二晶体管M2被配置为在第二控制信号S G2的控制下导通或关断。
至此，提供了根据本公开一些实施例的多路复用器的电路结构。在该多路复用器中，利用第一控制信号控制第一晶体管，以及利用第二控制信号控制第二晶体管，从而可以将这两个开关晶体管的共用电极(即第一电极)接收的数据信号通过第一晶体管或第二晶体管传输到相应的子像素，实现子像素的发光。该多路复用器可以减少集成电路中的管脚数目，降低模组工艺难度和成本。
在一些实施例中，第一晶体管M1和第二晶体管可以为NMOS(N-channel Metal Oxide Semiconductor，N型沟道金属氧化物半导体)晶体管。在另一些实施例中，第一晶体管M1和第二晶体管可以为PMOS(P-channel Metal Oxide Semiconductor，P型沟道金属氧化物半导体)晶体管。
图5是示出根据本公开一个实施例的显示面板的子像素的截面示意图。如图5所示，每个子像素包括用于驱动子像素发光的像素电路，该像素电路至少包括第三晶体管510和电容器530。即每个子像素可以包括第三晶体管510和电容器530。该第三晶体管510和电容器530均位于基板201上方。例如，该第三晶体管510可以为开关晶体管或驱动晶体管。
在一些实施例中，上述像素电路可以是2T1C、3T1C、7T1C、7T2C、9T1C或9T2C等像素电路。这里“T”表示晶体管，“C”表示电容器。例如，2T1C表示包括2个晶体管和1个电容器的像素电路。当然，本领域技术人员能够明白，这里的像素电路并不限于这里所公开的像素电路，还可以是具有其他结构的像素电路，只要可以驱动发光器件发光即可。
如图5所示，该第三晶体管510包括有源层(例如，可以称为第一有源层)511。 例如，该有源层511可以位于缓冲层501上。该缓冲层501在基板201上。例如，该有源层511可以包括半导体层。例如，该有源层511的材料可以包括多晶硅和非晶硅等中的至少一种。
如图5所示，该第三晶体管510还包括覆盖有源层511的第一绝缘层512。例如，第一绝缘层512可以为无机绝缘层。例如，第一绝缘层512的材料可以包括二氧化硅或氮化硅等。
如图5所示，该第三晶体管510还包括在第一绝缘层512的远离有源层511的一侧的栅极513。例如，该栅极513的材料可以包括诸如钼(Mo)等金属。
如图5所示，该第三晶体管510还可以包括覆盖该栅极513的第二绝缘层514。例如，第二绝缘层514的材料可以为无机绝缘层，例如可以包括二氧化硅或氮化硅等。
如图5所示，该第三晶体管510还可以包括在第二绝缘层514的远离栅极513的一侧的层间绝缘层516。例如，层间绝缘层516的材料可以包括无机绝缘材料。例如，该无机绝缘材料可以包括二氧化硅或氮化硅等。
如图5所示，该第三晶体管510还包括在层间绝缘层516的远离第二绝缘层514的一侧的源极517和漏极518。例如该源极517和该漏极518的材料可以包括钛(Ti)和铝(Al)中的至少一种。例如，该源极517和该漏极518可以分别包括Ti层/Al层/Ti层这样的三层结构。该源极517和该漏极518分别与有源层511电连接。例如，该源极517通过穿过第一绝缘层512、第二绝缘层514和层间绝缘层516的第一导电通孔521与有源层511电连接。又例如，该漏极518通过穿过第一绝缘层512、第二绝缘层514和层间绝缘层516的第二导电通孔522与有源层511电连接。
至此，描述了根据本公开一些实施例的子像素的第三晶体管。
在一些实施例中，如图5所示，电容器530包括与栅极513处于同一层的第一导电层531。例如，该第一导电层531的材料可以与栅极513的材料相同。这样可以方便显示面板的制造。第二绝缘层514还覆盖该第一导电层531。如图5所示，电容器530还包括在第二绝缘层514的远离第一导电层531的一侧的第二导电层532。层间绝缘层516还覆盖该第二导电层532。例如，该第一导电层531和该第二导电层532的材料可以均包括诸如钼等金属。该电容器530可以起到存储数据的作用。
需要说明的是，本公开实施例的“同一层”指的是处于相同结构层上的膜层。或者例如，处于同一层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图 形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
例如，第一导电层531与栅极513处于同一层。该第一导电层531与该栅极513均处于第一绝缘层512上。例如，该第一导电层531与该栅极513可以通过同一构图工艺形成。
在一些实施例中，如图5所示，每个子像素还可以包括覆盖在源极517和漏极518上的第三绝缘层541。例如，第三绝缘层541的材料可以包括二氧化硅或氮化硅等。
如图5所示，该子像素还可以包括在第三绝缘层541的远离源极517和漏极518的一侧的第一平坦化层542。例如，第一平坦化层542的材料可以包括有机绝缘材料。
如图5所示，该子像素还可以包括在第一平坦化层542的远离第三绝缘层541的一侧的第三导电层543。该第三导电层543与源极517或漏极518电连接。例如，该第三导电层543的材料可以包括钛(Ti)和铝(Al)中的至少一种。例如，该第三导电层543可以包括Ti层/Al层/Ti层这样的三层结构。例如，该第三导电层543可以通过穿过第三绝缘层541和第一平坦化层542的第三导电通孔523电连接至源极517或漏极518。
如图5所示，该子像素还可以包括覆盖第三导电层543的第二平坦化层544。例如，第二平坦化层544的材料可以包括有机绝缘材料。
如图5所示，该子像素还可以包括在第二平坦化层544的远离第三导电层543的一侧的阳极层545。该阳极层545与第三导电层543电连接。例如，该阳极层545通过穿过第二平坦化层544的第四导电通孔524电连接至第三导电层543。
如图5所示，该子像素还可以包括在第二平坦化层544上的具有开口5461的像素界定层546。该开口5461露出阳极层545的至少一部分。
如图5所示，该子像素还可以包括在开口5461内且与阳极层545连接的功能层547。例如，该功能层547可以包括发光层等。
如图5所示，该子像素还可以包括在功能层547的远离阳极层545的一侧的阴极层548。在本公开的实施例中，发光器件包括阳极层545、功能层547和阴极层548。
在一些实施例中，显示面板可以包括覆盖在阴极层548上的封装层549。
至此，提供了根据本公开一些实施例的显示面部的子像素的结构。该子像素可以包括第三晶体管、电容器和发光器件等。当然，本领域技术人员能够理解，该子像素 还可以包括其他结构或层，这里不再详细描述。
图6A是示出根据本公开一个实施例的多路复用器的俯视图。图6B是示出根据本公开一个实施例的多路复用器沿着图6A中的线A-A′截取的截面示意图。
图6A中示出了多路复用器221和222。如图6A所示，每个多路复用器221或222包括第一晶体管的第二电极412和控制电极413、第二晶体管的第二电极422和控制电极423、以及第一晶体管和第二晶体管共用的第一电极401。另外，图6A中还示出了静电保护区280的防静电单元282。
在一些实施例中，如图6A所示，在每个多路复用器221或222中，第一电极401、第一晶体管的第二电极412和第二晶体管的第二电极422均与源极517和漏极518处于同一层。例如，第一电极401、第二电极412和422、源极517和漏极518均处于层间绝缘层516上。如图6B所示，第一电极401、第一晶体管的第二电极412和第二晶体管的第二电极422均位于层间绝缘层516上。这样的同层设计可以方便显示面板的制造，节约成本。
在一些实施例中，如图6A所示，第一晶体管的控制电极413和第二晶体管的控制电极423与栅极513处于同一层。例如，第一晶体管的控制电极413、第二晶体管的控制电极423和栅极513均处于第一绝缘层512上。如图6B所示，第一晶体管的控制电极413和第二晶体管的控制电极423均处于第一绝缘层512上。这样的同层设计可以方便显示面板的制造，节约成本。
在一些实施例中，如图6B所示，在每个多路复用器中，第一晶体管和第二晶体管可以共用一个有源层(可以称为第二有源层)414。该第二有源层414位于缓冲层501上。因此，该第二有源层414和第三晶体管的有源层(即第一有源层)511处于同一层。
如图6B所示，第一电极401通过第五导电通孔431与第二有源层414电连接。该第五导电通孔431穿过层间绝缘层516、第二绝缘层514和第一绝缘层512。第一晶体管的第二电极412通过第六导电通孔432与第二有源层414电连接。该第六导电通孔432穿过层间绝缘层516、第二绝缘层514和第一绝缘层512。第二晶体管的第二电极422通过第七导电通孔433与第二有源层414电连接。该第七导电通孔433穿过层间绝缘层516、第二绝缘层514和第一绝缘层512。这里，第一晶体管的第二电极412电连接至第二有源层414的一端，第二晶体管的第二电极422电连接至第二有源层414的另一端。
图6C是示出根据本公开一个实施例的多路复用器沿着图6A中的线B-B′截取的截面示意图。
在一些实施例中，如图6A和图6C所示，第一多路复用器221的信号输入线2210(例如可以称为第一信号输入线2211)与第二多路复用器222的信号输入线2210(例如可以称为第二信号输入线2212)处于不同层。
在一些实施例中，第一多路复用器221的第一电极401电连接至该第一多路复用器221的信号输入线2210(即第一信号输入线2211)。该第一多路复用器221的信号输入线与第二导电层532处于同一层。例如，该第一多路复用器221的信号输入线与第二导电层532均处于第二绝缘层514上。如图6C所示，第一信号输入线2211处于第二绝缘层514上。
在一些实施例中，第二多路复用器222的第一电极401电连接至第二多路复用器222的信号输入线2210(即第二信号输入线2212)。该第二多路复用器222的信号输入线与栅极513处于同一层。例如，该第二多路复用器222的信号输入线与栅极513均处于第一绝缘层512上。如图6C所示，第二信号输入线2212处于第一绝缘层512上。
在上述实施例中，通过使得第一多路复用器的信号输入线与第二导电层处于同一层，以及将第二多路复用器的信号输入线与栅极处于同一层，从而可以方便显示面板的制造，节约成本，另外也可以尽量防止不同的多路复用器的信号输入线发生短路的危险。
图7A是示出根据本公开一个实施例的多路复用器在图6A所示的方框610处的部分结构的放大示意图。
在一些实施例中，如图6A和图7A所示，显示面板还可以包括与每个多路复用器电连接的第一扫描信号线601和第二扫描信号线602。该第一扫描信号线601与第一晶体管的控制电极413电连接。该第一扫描信号线601可以向第一晶体管传输第一控制信号。该第二扫描信号线602与第二晶体管的控制电极423电连接。该第二扫描信号线602可以向第二晶体管传输第二控制信号。这样可以实现对多路复用器的控制。
在一些实施例中，如图7A所示，在两个需要电连接的层结构之间(例如，在第一扫描信号线601与第一晶体管的控制电极413之间，等等)可以设置比较多的导电通孔，这样可以降低两个层之间的连接阻抗。
图7B是示出沿着图7A中的线C-C′截取的结构的截面示意图。
如图7B所示，该第一扫描信号线601位于层间绝缘层516上。因此，该第一扫描信号线601可以与第三晶体管的源极517和漏极518处于同一层。该第一扫描信号线通过第八导电通孔711与第一晶体管的控制电极413电连接。该第八导电通孔711穿过层间绝缘层516和第二绝缘层514。另外，第二扫描信号线602与第二晶体管的控制电极423电连接的方式和第一扫描信号线与第一晶体管的控制电极413电连接的方式类似，这里不再详细描述。
图7C是示出沿着图7A中的线D-D′截取的结构的截面示意图。
如图7C所示，第一多路复用器221的第一电极401可以通过第九导电通孔712与第一信号输入线2211电连接。该第九导电通孔712穿过层间绝缘层516。这样实现了第一电极与第一信号线的电连接。
在另一些实施例中，第二多路复用器222的第一电极401可以通过第十导电通孔(图中未示出)与第二信号输入线2212电连接。该第十导电通孔穿过层间绝缘层516和第二绝缘层514。
图8A是示出根据本公开一个实施例的多路复用器在图6A所示的方框620处的部分结构的放大示意图。图8B是示出沿着图8A中的线E-E′截取的结构的截面示意图。
如图6A和图8A所示，每个多路复用器的两个信号输出线包括第一信号输出线2201和第二信号输出线2202。如图8A和图8B所示，第一晶体管的第二电极412电连接至第一信号输出线2201。该第一信号输出线2201与第二导电层532处于同一层。例如，该第一信号输出线2201和该第二导电层532均处于第二绝缘层514上。这样的同层设计可以方便显示面板的制造，节约成本。
如图8B所示，该第一信号输出线2201处于第二绝缘层514上。第一晶体管的第二电极412通过第十一导电通孔811与第一信号输出线2201电连接。该第十一导电通孔811穿过层间绝缘层516。
第二晶体管的第二电极422电连接至第二信号输出线2202。第二信号输出线2202与栅极513处于同一层。例如，该第二信号输出线2202与栅极513均处于第一绝缘层512上。这样的同层设计可以方便显示面板的制造，节约成本。
如图8B所示，该第二信号输出线2202处于第一绝缘层512上。第二晶体管的第二电极422通过第十二导电通孔812与第二信号输出线2202电连接。该第十二导电通孔812穿过层间绝缘层516和第二绝缘层514。
在另一些实施例中，如果信号输入线与其他结构(例如电极)之间不采用换层连 接的方式，则信号输入线可以是一体形成的。在另一些实施例中，如果信号输出线与其他结构(例如电极)之间不采用换层连接的方式，则信号输出线可以是一体形成的。
图9是示出根据本公开一个实施例的显示面板的弯折区的结构示意图。
如图9所示，弯折区210可以包括多个第一导线211。该多个第一导线211的每一个与第三导电层543处于同一层。例如，该第一导线211与第三导电层543均处于第一平坦化层542上。这样的同层设计可以方便显示面板的制造，节约成本。
如图9所示，每个第一导线211通过第二导线902或第三导线903电连接到显示区域。该第二导线902与栅极513处于同一层。例如，第二导线902与栅极513均处于第一绝缘层512上。第三导线903与第二导电层532处于同一层。例如，第三导线903与第二导电层532均处于第二绝缘层514上。这样的设计可以尽量防止第二导线与第三导电短路。
在本公开的实施例中，还提供了一种显示装置。该显示装置可以包括如前所述的显示面板。例如，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (15)

  1. 一种显示面板，包括：
    显示区域，包括设置在基板上的像素阵列，所述像素阵列包括多个子像素；和
    围绕所述显示区域的周边区域，所述周边区域包括：
    在所述显示区域一侧的弯折区；
    在所述弯折区的远离所述显示区域一侧的多个多路复用器，其中，所述多个多路复用器设置在所述基板上，每个多路复用器至少连接有一个信号输入线和两个信号输出线；以及
    在所述多个多路复用器的远离所述弯折区一侧的绑定区；
    其中，所述多个多路复用器经过所述弯折区电连接至所述多个子像素；所述信号输入线电连接至所述绑定区，所述信号输入线在所述基板上的正投影与所述弯折区在所述基板上的正投影不重叠。
  2. 根据权利要求1所述的显示面板，其中，
    所述多个多路复用器包括第一多路复用器和第二多路复用器，其中，所述第二多路复用器比所述第一多路复用器更远离所述弯折区。
  3. 根据权利要求2所述的显示面板，其中，
    每个信号输出线电连接至一列子像素。
  4. 根据权利要求3所述的显示面板，其中，
    所述第二多路复用器的信号输出线位于与所述第二多路复用器相邻的两个第一多路复用器之间。
  5. 根据权利要求1至4任意一项所述的显示面板，还包括：
    在所述弯折区与所述显示区域之间的第一扇出区；
    在所述弯折区与所述多个多路复用器之间的第二扇出区；以及
    在所述多个多路复用器与所述绑定区之间的第三扇出区；
    其中，所述绑定区经过所述第三扇出区电连接至所述多个多路复用器，所述多个 多路复用器经过所述第二扇出区、所述弯折区和所述第一扇出区电连接至所述多个子像素。
  6. 根据权利要求5所述的显示面板，还包括：
    在所述多个多路复用器与所述第二扇出区之间的单元测试区；以及
    在所述单元测试区与所述多个多路复用器之间的静电保护区；
    其中，所述多个多路复用器与所述静电保护区电连接，所述静电保护区与所述单元测试区电连接，所述单元测试区经过所述第二扇出区、所述弯折区和所述第一扇出区电连接所述多个子像素。
  7. 根据权利要求3所述的显示面板，其中，
    每个多路复用器包括第一晶体管和第二晶体管；其中，所述第一晶体管和所述第二晶体管共用一个第一电极，所述第一电极通过所述信号输入线电连接到所述绑定区，所述第一电极被配置为接收数据信号；
    所述第一晶体管的第二电极通过所述两个信号输出线中的一个信号输出线电连接至第一列子像素，所述第一晶体管的控制电极被配置为接收第一控制信号；
    所述第二晶体管的第二电极通过所述两个信号输出线中的另一个信号输出线电连接至第二列子像素，所述第二晶体管的控制电极被配置为接收第二控制信号。
  8. 根据权利要求7所述的显示面板，其中，每个子像素包括第三晶体管和电容器，
    所述第三晶体管包括：
    有源层；
    覆盖所述有源层的第一绝缘层；
    在所述第一绝缘层的远离所述有源层的一侧的栅极；
    覆盖所述栅极的第二绝缘层；
    在所述第二绝缘层的远离所述栅极的一侧的层间绝缘层；以及
    在所述层间绝缘层的远离所述第二绝缘层的一侧的源极和漏极，其中，所述源极和所述漏极分别与所述有源层电连接；
    所述电容器包括：
    与所述栅极处于同一层的第一导电层，其中，所述第二绝缘层还覆盖所述第一导电层；以及
    在所述第二绝缘层的远离所述第一导电层的一侧的第二导电层，其中，所述层间绝缘层还覆盖所述第二导电层。
  9. 根据权利要求8所述的显示面板，其中，
    在每个多路复用器中，所述第一电极、所述第一晶体管的第二电极和所述第二晶体管的第二电极均与所述源极和所述漏极处于同一层，所述第一晶体管的控制电极和所述第二晶体管的控制电极与所述栅极处于同一层。
  10. 根据权利要求8所述的显示面板，其中，所述第一多路复用器的信号输入线与所述第二多路复用器的信号输入线处于不同层。
  11. 根据权利要求10所述的显示面板，其中，
    所述第一多路复用器的第一电极电连接至所述第一多路复用器的信号输入线，所述第一多路复用器的信号输入线与所述第二导电层处于同一层；以及
    所述第二多路复用器的第一电极电连接至所述第二多路复用器的信号输入线，所述第二多路复用器的信号输入线与所述栅极处于同一层。
  12. 根据权利要求8所述的显示面板，其中，所述两个信号输出线包括第一信号输出线和第二信号输出线；
    所述第一晶体管的第二电极电连接至所述第一信号输出线，所述第一信号输出线与所述第二导电层处于同一层；以及
    所述第二晶体管的第二电极电连接至所述第二信号输出线，所述第二信号输出线与所述栅极处于同一层。
  13. 根据权利要求8所述的显示面板，其中，每个子像素还包括：
    覆盖在所述源极和所述漏极上的第三绝缘层；
    在所述第三绝缘层的远离所述源极和所述漏极的一侧的第一平坦化层；
    在所述第一平坦化层的远离所述第三绝缘层的一侧的第三导电层，其中，所述第 三导电层与所述源极或所述漏极电连接；
    覆盖所述第三导电层的第二平坦化层；
    在所述第二平坦化层的远离所述第三导电层的一侧的阳极层，其中，所述阳极层与所述第三导电层电连接；
    在所述第二平坦化层上的具有开口的像素界定层，所述开口露出所述阳极层的至少一部分；
    在所述开口内且与所述阳极层连接的功能层；以及
    在所述功能层的远离所述阳极层的一侧的阴极层。
  14. 根据权利要求13所述的显示面板，其中，
    所述弯折区包括多个第一导线，所述多个第一导线的每一个与所述第三导电层处于同一层；
    每个第一导线通过第二导线或第三导线电连接到所述显示区域，所述第二导线与所述栅极处于同一层，所述第三导线与所述第二导电层处于同一层。
  15. 一种显示装置，包括：如权利要求1至14任意一项所述的显示面板。
PCT/CN2020/080393 2020-03-20 2020-03-20 显示面板和显示装置 WO2021184348A1 (zh)

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