WO2018171137A1 - Goa单元及其驱动方法、goa电路、显示装置 - Google Patents

Goa单元及其驱动方法、goa电路、显示装置 Download PDF

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Publication number
WO2018171137A1
WO2018171137A1 PCT/CN2017/102508 CN2017102508W WO2018171137A1 WO 2018171137 A1 WO2018171137 A1 WO 2018171137A1 CN 2017102508 W CN2017102508 W CN 2017102508W WO 2018171137 A1 WO2018171137 A1 WO 2018171137A1
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Prior art keywords
voltage
transistor
terminal
signal
clock signal
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PCT/CN2017/102508
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English (en)
French (fr)
Inventor
兰传艳
金兑炫
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US15/769,058 priority Critical patent/US10504447B2/en
Publication of WO2018171137A1 publication Critical patent/WO2018171137A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a GOA unit for lighting control signals, a driving method thereof, a GOA circuit, and a display device.
  • OLED Organic Light Emitting Diode
  • LCD liquid crystal display
  • the scanning signal line is usually driven by the GOA unit of the scanning signal.
  • the illumination control signal line is driven by the GOA unit of the illumination control signal.
  • the GOA circuit is usually formed by cascading a plurality of GOA units. When powering on or waking up to sleep, as shown in FIG. 1(a) and FIG. 1(b), each level of the GOA unit drives the pixel circuit corresponding thereto, as shown in FIG. 1. (a) shows that the driving transistor Md is in a floating state in the pixel circuit.
  • the driving transistor Md is easily interfered by other signals, so that part of the driving transistor Md in the pixel circuit is turned on, so that the Md and M6 lines have The current flows, causing the pixel of the driving transistor Md to turn on an illuminating phenomenon.
  • the high voltage terminal VDD in the pixel circuit is input with a signal before the low voltage terminal VSS, and the pixel circuit of the driving transistor Md has a current on the Md and M6 lines, the potential value of the low voltage terminal VSS is raised.
  • the power supply that supplies the signal to the high-voltage VDD/low-voltage terminal VSS is damaged or necrotic, and in this case, the SSD (start-up short detection function) in the circuit activates the protection function. , automatically cut off the power, causing the screen to not complete the normal display.
  • a GOA unit for providing an illumination control signal includes a potential control module, a pull-up module, a pull-down module, and a write module; and the potential control module is respectively connected to the first voltage terminal, the second voltage terminal, and the a clock signal terminal, a second clock signal terminal, a signal input terminal, and a first node, configured to output the signal of the second voltage terminal to the first clock signal terminal and the first voltage terminal And outputting, by the first clock signal end, the first voltage end, and the signal input end, the signal of the second clock signal end to the first node
  • the pull-down module is respectively connected to the first node, the first voltage end, the second voltage end, the first clock signal end, the second clock signal end, and the signal output end And for controlling the first voltage end under the control of the first node, the first voltage end, the second voltage end, the first clock signal end, and the second clock signal end Signal output To the signal output end; the pull-up module is respectively connected to the first node, the second voltage end, and
  • the write module includes a first transistor; a gate of the first transistor is connected to the signal control end, a first pole is connected to the second voltage end, and a second pole is connected to the signal output end.
  • the potential control module includes a pull-up control module and a pull-down control module; the pull-up control module is respectively connected to the pull-down control module, the first clock signal end, the first voltage end, and the a second voltage end, and the first node, configured to output, by the first clock signal end and the first voltage end, a signal of the second voltage end to the first node;
  • the control module is further configured to connect the signal input end, the first clock signal end, the second clock signal end, the first voltage end, and the first node, respectively, at the signal input end, And outputting, by the first clock signal end and the first voltage end, a signal of the second clock signal end to the first node.
  • the pull-up control module includes a second transistor, a third transistor, and a first capacitor; a gate of the second transistor is connected to the first clock signal end, and a first pole is connected to the first voltage a second pole connected to a gate of the third transistor; a first of the third transistor The pole is connected to the second voltage end, and the second pole is connected to the first node; the first end of the first capacitor is connected to the second voltage end, and the second end is connected to the gate of the third transistor.
  • the pull-up control module is further connected to the second clock signal end, the pull-up control module further includes a fourth transistor and a fifth transistor; a gate of the fourth transistor is connected to the second transistor a second pole, the first pole is connected to the second voltage end, the second pole is connected to the first pole of the fifth transistor; the gate of the fifth transistor is connected to the second clock signal end, and the second pole is connected The pull-down control module.
  • the pull-down control module includes a sixth transistor, a seventh transistor, an eighth transistor, and a second capacitor; a gate of the sixth transistor is connected to the first clock signal end, and a first pole is connected to the a signal input end, a second pole is connected to the first pole of the seventh transistor; a gate of the seventh transistor is connected to the first voltage end, and a second pole is connected to a gate of the eighth transistor; a first pole of the eight transistor is connected to the second clock signal end, a second pole is connected to the first node; a first end of the second capacitor is connected to a gate of the eighth transistor, and a second end is connected to the The second pole of the eighth transistor.
  • the pull-down control module further includes a ninth transistor; a gate of the ninth transistor is connected to a second pole of the sixth transistor, and a first pole is connected to the first clock signal end, and the second pole Connecting the pull-up control module.
  • the pull-down module includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a third capacitor; a gate of the tenth transistor is connected to the first clock signal end, and the first pole is connected a first voltage terminal, a second pole connected to a gate of the twelfth transistor; a gate of the eleventh transistor connected to the first node, a first pole connected to the second voltage terminal, a second pole Connecting a gate of the twelfth transistor; a first pole of the twelfth transistor is connected to the first voltage end, a second pole is connected to the signal output end; and a first end of the third capacitor is connected to the The second clock signal end is connected to the second terminal of the twelfth transistor.
  • the pull-up module includes a thirteenth transistor; a gate of the thirteenth transistor is connected to the first node, a first pole is connected to the second voltage end, and a second pole is connected to the signal output end.
  • a method for driving a GOA unit of an illumination control signal comprising: in a front N image frame, the write module writes a signal of the second voltage end under the control of the signal control end To the signal output end; starting from the N+1th image frame, in the buffering phase of the image frame, the first clock signal terminal inputs the first voltage, the signal input terminal inputs the first voltage, and the second clock signal terminal inputs the second voltage.
  • a potential control module input at the first clock signal end Controlling, by the first voltage and the first voltage terminal, the signal of the second voltage terminal to the first node, and inputting the first voltage, the first voltage terminal, and the a second voltage input by the second clock signal terminal is output to the first node under control of a first voltage input by the signal input terminal;
  • the pull-down module is at the first node, the first voltage end, the Controlling, by the second voltage terminal, the first voltage input by the first clock signal terminal, and the second voltage input by the second clock signal terminal, the signal of the first voltage terminal to the signal output terminal
  • the second clock signal terminal inputs a first voltage
  • the first clock signal terminal inputs a second voltage
  • the signal input terminal inputs a second voltage
  • the potential control module is Outputting the first voltage input by the second clock signal terminal to the second voltage input by the first clock signal terminal, the first voltage terminal, and the second voltage input by the signal input terminal
  • First a pull-up module outputs a signal of the second voltage terminal
  • a GOA circuit comprising a plurality of cascaded GOA units of illumination control signals as described in the first aspect.
  • a display device comprising the GOA circuit of the third aspect.
  • FIG. 1(a) is a schematic structural diagram of a pixel circuit provided by the prior art
  • Figure 1 (b) is a timing diagram of respective signals used when driving the pixel circuit shown in Figure 1 (a);
  • FIG. 2 is a schematic structural diagram 1 of a GOA unit according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram 2 of a GOA unit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram 1 of a specific structure of each module of the GOA unit shown in FIG. 3;
  • FIG. 5 is a schematic diagram 2 of a specific structure of each module of the GOA unit shown in Figure 3;
  • Figure 6 is a timing diagram of respective signals used when driving the GOA unit shown in Figure 3;
  • FIG. 11 is a schematic flowchart diagram of a driving method of a GOA unit according to an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram of a GOA circuit according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a GOA unit of an illumination control signal, as shown in FIG. 2, including a potential control module 10, a pull-down module 20, a pull-up module 30, and a write module 40.
  • the potential control module 10 is connected to the first voltage terminal V1, the second voltage terminal V2, the first clock signal terminal CK, the second clock signal terminal CB, the signal input terminal EI, and the first node A, respectively, for Controlling, by the first clock signal terminal CK and the first voltage terminal V1, the signal of the second voltage terminal V2 to the first node A; and/or, at the first clock signal terminal CK, the first voltage terminal V1, and The signal of the second clock signal terminal CB is output to the first node A under the control of the signal input terminal EI.
  • the pull-down module 20 is connected to the first node A, the first voltage terminal V1, the second voltage terminal V2, the first clock signal terminal CK, the second clock signal terminal CB, and the signal output terminal EO, respectively, for the first node A.
  • the signal of the first voltage terminal V1 is output to the signal output terminal EO under the control of the first voltage terminal V1, the second voltage terminal V2, the first clock signal terminal CK, and the second clock signal terminal CB.
  • the pull-up module 30 is connected to the first node A, the second voltage terminal V2, and the signal output terminal EO, respectively, for outputting the signal of the second voltage terminal V2 to the signal output terminal EO under the control of the first node A.
  • the writing module 40 is connected to the second voltage terminal V2, the signal control terminal S1, and the signal output terminal EO, respectively, for outputting the voltage of the second voltage terminal V2 to the signal output terminal EO under the control of the signal control terminal S1.
  • An embodiment of the present disclosure provides a GOA unit for an illumination control signal.
  • the write module 40 is turned on, and the second voltage terminal V2 is turned on.
  • the signal is output to the signal output terminal EO, and the light-emitting control transistor in the pixel circuit connected thereto is controlled to be turned off by the signal output terminal EO, so that no current flows to the light-emitting device in the pixel circuit regardless of whether the driving transistor is turned on, and thus the pixel circuit There is no false illumination, and the SSD in the circuit will not cut off the power.
  • the write module 40 in the control GOA unit is turned off, the other modules are normally turned on, and the pixel circuit is controlled to perform normal display. Thereby ensuring the quality of the display screen of the display device.
  • the potential control module 10 includes a pull-up control module 11 and a pull-down control module 12.
  • the pull-up control module 11 is connected to the pull-down control module 12, the first clock signal terminal CK, the first voltage terminal V1, the second voltage terminal V2, and the first node A, respectively, for the first clock signal terminal CK and the first voltage.
  • the signal of the second voltage terminal V2 is output to the first node A under the control of the terminal V1.
  • the pull-down control module 12 is further connected to the signal input terminal EI, the first clock signal terminal CK, the second clock signal terminal CB, the first voltage terminal V1, and the first node A for the signal input terminal EI and the first clock signal.
  • the signal of the second clock signal terminal CB is output to the first node A under the control of the terminal CK and the first voltage terminal V1.
  • the write module 40 includes a first transistor T1.
  • the gate of the first transistor T1 is connected to the signal control terminal S1, the first pole is connected to the second voltage terminal V2, and the second pole is connected to the signal output terminal EO.
  • the writing module 40 may further include a plurality of first transistors T1 connected in parallel.
  • the foregoing is only an illustration of the write module 40.
  • Other structures having the same functions as the write module 40 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the pull-up control module 11 includes a second transistor T2, a third transistor T3, and a first capacitor C1.
  • the gate of the second transistor T2 is connected to the first clock signal terminal CK, the first electrode is connected to the first voltage terminal V1, and the second electrode is connected to the gate of the third transistor T3.
  • the first pole of the third transistor T3 is connected to the second voltage terminal V2, and the second pole is connected to the first node A.
  • the first end of the first capacitor C1 is connected to the second voltage terminal V2, and the second end is connected to the gate of the third transistor T3.
  • the pull-up control module 11 may further include a plurality of switching transistors connected in parallel with the second transistor T2, and/or a plurality of switching transistors connected in parallel with the third transistor T3.
  • the foregoing is only an example of the pull-up control module 11.
  • Other structures that are the same as those of the pull-up control module 11 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the pull-down control module 12 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a second capacitor C2.
  • the gate of the sixth transistor T6 is connected to the first clock signal terminal CK, the first electrode is connected to the signal input terminal EI, and the second electrode is connected to the first electrode of the seventh transistor T7.
  • the gate of the seventh transistor T7 is connected to the first voltage terminal V1, and the second electrode is connected to the gate of the eighth transistor T8.
  • the first pole of the eighth transistor T8 is connected to the second clock signal terminal CB, and the second pole is connected to the first node A.
  • the first end of the second capacitor C2 is connected to the gate of the eighth transistor T8, and the second end is connected to the second pole of the eighth transistor T8.
  • the pull-down control module 12 may further include a plurality of switching transistors connected in parallel with the sixth transistor T6, and/or a plurality of switching transistors connected in parallel with the seventh transistor T7, and/or in parallel with the eighth transistor T8. Multiple switching transistors.
  • the foregoing is only an example of the pull-down control module 12, and other structures having the same functions as those of the pull-down control module 12 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the pull-down module 20 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a third capacitor C3.
  • the gate of the tenth transistor T10 is connected to the first clock signal terminal CK, the first electrode is connected to the first voltage terminal V1, and the second electrode is connected to the gate of the twelfth transistor T12.
  • the gate of the eleventh transistor T11 is connected to the first node A, the first electrode is connected to the second voltage terminal V2, and the second electrode is connected to the gate of the twelfth transistor T12.
  • the first pole of the twelfth transistor T12 is connected to the first voltage terminal V1, and the second pole is connected to the signal output terminal EO.
  • the first end of the third capacitor C3 is connected to the second clock signal terminal CB, and the second end is connected to the gate of the twelfth transistor T12.
  • the pull-down module 20 may further include a plurality of switching transistors connected in parallel with the tenth transistor T10, and/or a plurality of switching transistors connected in parallel with the eleventh transistor T11, and/or with the twelfth transistor T12. Multiple switching transistors in parallel.
  • a drop-down module For example, other structures having the same functions as those of the pull-down module 20 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the pull-up module 30 includes a thirteenth transistor T13.
  • the gate of the thirteenth transistor T13 is connected to the first node A, the first pole is connected to the second voltage terminal V2, and the second pole is connected to the signal output terminal EO.
  • the pull-up module 30 may further include a plurality of switching transistors connected in parallel with the thirteenth transistor T13.
  • the above is only an example of the pull-up module 30.
  • Other structures having the same functions as those of the pull-up module 30 are not described herein again, but all should fall within the protection scope of the present disclosure.
  • the types of transistors in the respective modules and the units are not limited, that is, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4.
  • the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 may It is an N-type transistor or a P-type transistor.
  • the following embodiments of the present disclosure are all the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth
  • the transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are exemplified as P-type transistors. Further, the transistor in the pixel unit connected to the signal output terminal EO of the GOA unit is also a P-type as an example.
  • the first pole of the transistor may be a drain, and the second pole may be a source; or the first pole may be a source, and the second pole may be a drain.
  • the embodiments of the present disclosure do not limit this.
  • the transistors in the above pixel circuit can be classified into an enhancement transistor and a depletion transistor depending on the manner in which the transistors are electrically conductive.
  • the embodiments of the present disclosure do not limit this.
  • the embodiments of the present disclosure are all described in which the second voltage terminal V2 is input to the high level, the first voltage terminal V1 is input to the low level, or the first voltage terminal V1 is grounded as an example, and the height is here. Low refers only to the relative magnitude relationship between the input voltages.
  • a GOA unit that provides an illumination control signal includes a pull-up control module 11, a pull-down control module 12, a pull-down module 20, a pull-up module 30, and a write module 40.
  • the write module 40 includes a first transistor T1.
  • the gate of the first transistor T1 is connected to the signal control terminal S1, and the first pole is connected to the second voltage terminal V2.
  • the second pole is connected to the signal output terminal EO.
  • the pull-up control module 11 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a first capacitor C1.
  • the gate of the second transistor T2 is connected to the first clock signal terminal CK, the first electrode is connected to the first voltage terminal V1, and the second electrode is connected to the gate of the third transistor T3.
  • the first pole of the third transistor T3 is connected to the second voltage terminal V2, and the second pole is connected to the first node A.
  • the gate of the fourth transistor T4 is connected to the second pole of the second transistor T2, the first pole is connected to the second voltage terminal V2, and the second pole is connected to the first pole of the fifth transistor T5.
  • the pull-up control module 11 is also connected to the second clock signal terminal CB
  • the gate of the fifth transistor T5 is connected to the second clock signal terminal CB
  • the second pole is connected to the pull-down control module 12.
  • the first end of the first capacitor C1 is connected to the second voltage terminal V2, and the second end is connected to the gate of the third transistor T3.
  • the pull-down control module 12 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a second capacitor C2.
  • the gate of the sixth transistor T6 is connected to the first clock signal terminal CK, the first electrode is connected to the signal input terminal EI, and the second electrode is connected to the first electrode of the seventh transistor T7.
  • the gate of the seventh transistor T7 is connected to the first voltage terminal V1, and the second electrode is connected to the gate of the eighth transistor T8.
  • the first pole of the eighth transistor T8 is connected to the second clock signal terminal CB, and the second pole is connected to the first node A.
  • the gate of the ninth transistor T9 is connected to the second pole of the sixth transistor T6, the first pole is connected to the first clock signal terminal CK, and the second pole is connected to the pull-up control module 11.
  • the first end of the second capacitor C2 is connected to the second pole of the seventh transistor T7, and the second end is connected to the second pole of the eighth transistor T8.
  • the pull-down module 20 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a third capacitor C3.
  • the gate of the tenth transistor T10 is connected to the first clock signal terminal CK, the first electrode is connected to the first voltage terminal V1, and the second electrode is connected to the gate of the twelfth transistor T12.
  • the gate of the eleventh transistor T11 is connected to the first node A, the first electrode is connected to the second voltage terminal V2, and the second electrode is connected to the gate of the twelfth transistor T12.
  • the first pole of the twelfth transistor T12 is connected to the first voltage terminal V1, and the second pole is connected to the signal output terminal EO.
  • the first end of the third capacitor C3 is connected to the second clock signal terminal CB, and the second end is connected to the gate of the twelfth transistor T12.
  • the pull-up module 30 includes a thirteenth transistor T13.
  • the gate of the thirteenth transistor T13 is connected to the first node A, the first pole is connected to the second voltage terminal V2, and the second pole is connected to the signal output terminal EO.
  • each frame display process of the GOA unit can be divided into a buffer phase P1, a pull-up phase P2, and a pull-down phase P3.
  • the operation principle of the GOA unit of the illumination control signal shown in FIG. 5 will be described in detail below with reference to the timing charts of the respective control signal terminals shown in FIG. 6.
  • the signal control terminal S1 inputs a low voltage signal
  • the first clock signal terminal CK and the second clock signal terminal CB input a high voltage signal.
  • the first transistor T1 is turned on, and the second transistor T1 is turned on.
  • the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the ten transistor T10, the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 are all turned off (in the off state)
  • the transistor is indicated by "x").
  • the first transistor T1 is turned on, the voltage of the second voltage terminal V2 is written to the signal output terminal EO, the signal output terminal EO is always kept at a high voltage, and the transistor connected thereto is controlled to be turned off. At this time, the other transistors in the GOA unit are all kept off due to the high voltage signal.
  • N is a positive integer greater than or equal to 1.
  • the first transistor T1 is turned on, the voltage of the second voltage terminal V2 is written to the signal output terminal EO, and the signal output terminal EO is always kept at a high voltage, and the control thereof is The connected transistor is turned off.
  • the first clock signal terminal CK and the signal input terminal EI input a low voltage signal
  • the second clock signal terminal CB and the signal control terminal S1 input a high voltage signal.
  • the two transistors T12 are all turned on, and the first transistor T1, the fifth transistor T5, the eleventh transistor T11, and the thirteenth transistor T13 are all turned off.
  • the second transistor T2 is turned on, and the signal of the first voltage terminal V1 is written to the gate of the third transistor T3 via the second transistor T2 to control the third transistor T3 to be turned on.
  • the signal of the second voltage terminal V2 is The third transistor T3 is written to the first node A; the sixth transistor T6 and the seventh
  • the transistor T7 is turned on, and the signal of the signal input terminal EI is written to the gate of the eighth transistor T8 via the sixth transistor T6 and the seventh transistor T7 to control the eighth transistor T8 to be turned on.
  • the signal of the second clock signal terminal CB is turned on. It is written to the first node A via the eighth transistor T8.
  • the first node A outputs a high voltage signal.
  • the low voltage signal of the second pole of the seventh transistor T7 is written to the first end of the second capacitor C2 to charge the second capacitor C2.
  • the high voltage signal outputted by the first node A controls the eleventh transistor T11 and the thirteenth transistor T13 to be turned off, the tenth transistor T10 is turned on, and the signal of the first voltage terminal V1 is written to the tenth transistor T10.
  • the gate of the twelve transistor T12 controls the twelfth transistor T12 to be turned on, and the voltage of the first voltage terminal V1 is written to the signal output terminal EO via the twelfth transistor T12.
  • the signal output terminal EO outputs a low voltage signal.
  • the second clock signal terminal CB inputs a low-voltage signal
  • the first clock signal terminal CK, the signal control terminal S1, and the signal input terminal EI input a high-voltage signal.
  • the five transistors T5, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, and the thirteenth transistor T13 are all turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6,
  • the ninth transistor T9, the ten transistor T10, and the twelfth transistor T12 are all turned off.
  • the storage capacitor C2 is discharged, and the eighth transistor T8 is controlled to be turned on, and the low voltage of the second clock signal terminal CB is written to the first node A via the eighth transistor T8.
  • the first node A outputs a low voltage signal.
  • the low voltage of the first node A controls the eleventh transistor T11 and the thirteenth transistor T13, and the voltage of the second voltage terminal V2 is written to the gate of the twelfth transistor T12 via the eleventh transistor T11.
  • the twelfth transistor T12 is turned off, and the voltage of the second voltage terminal V2 is written to the signal output terminal EO via the thirteenth transistor T13.
  • the signal output terminal EO outputs a high voltage signal.
  • the first clock signal terminal CK inputs a low voltage signal
  • the signal input terminal EI, the second clock signal terminal CB, and the signal control terminal S1 input a high voltage signal.
  • the second The transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the ten transistor T10, and the twelfth transistor T12 are all turned on, and the first transistor T1, the fifth transistor T5, and the eighth transistor are turned on.
  • T8 the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 are all turned off.
  • the second transistor T2 is turned on, and the signal of the first voltage terminal V1 is written to the gate of the third transistor T3 via the second transistor T2 to control the third transistor T3 to be turned on. At this time, the signal of the second voltage terminal V2 is The third transistor T3 is written to the first node A.
  • the first node A outputs a high level.
  • the high level of the first node A outputs the eleventh transistor T11 and the thirteenth transistor T13 are turned off, the tenth transistor T10 is turned on, and the signal of the first voltage terminal V1 is written to the tenth transistor T10.
  • the gate of the twelfth transistor T12 controls the twelfth transistor T12 to be turned on, and the voltage of the first voltage terminal V1 is written to the signal output terminal EO via the twelfth transistor T12.
  • the signal output terminal EO outputs a low level.
  • the voltage application sequence is: V1/Vinit on-S1/S2/EM and other control signals start - VDD on - VSS on. That is, in the reset phase, the first signal terminal S1 inputs a low voltage turn-on signal, the enable signal terminal EM and the scan signal terminal S2 input a high voltage cutoff signal; during the data writing phase, the scan signal terminal S2 inputs a low voltage turn-on signal, and the first signal terminal S1. And the enable signal terminal EM inputs a high voltage cutoff signal; in the light emitting phase, the enable signal terminal EM inputs a low voltage turn-on signal, and the first signal terminal S1 and the scan signal terminal S2 input a high voltage cutoff signal.
  • the signal output from the signal output terminal EO is written to the enable signal terminal EM for controlling the turning on and off of the sixth transistor M6, thereby controlling the light emission of the pixel circuit.
  • the t1 time applied by S1 and the t2 time applied by the S2 signal are much shorter than the t3 time applied by EM.
  • the reason is that the signal sequence of FIG. 1(b) should be sequentially applied in the vertical order, so that the horizontal pixels are applied with the control signal during the time t1 is driven, and then the next row of pixels is also applied with the control signal, and finally in the same manner. All pixels are applied with control signals.
  • the pixel circuits are applied with the ELVDD voltage from the high voltage terminal VDD during the period when the enable signal terminal EM becomes low voltage (ie, the light emitting phase), and the voltage is applied to the high voltage terminal VDD to the GND (ie, 0V-Vth) during the data writing phase.
  • the voltage of the high-voltage terminal VDD suddenly abruptly changes to the ELVDD voltage (for example, 4.5 V), thereby causing Vgd of the driving transistor Md (the voltage difference of the Gate-Drain, determining the voltage difference of the TFT switch) to become large, and the voltage becomes abnormal.
  • the current of the driving transistor Md also becomes a large current, causing abnormal driving of the pixel circuit, causing a problem that the screen of the display device blinks on the startup screen.
  • the GOA unit is normally driven from the N+1th frame, and the ELVDD and ELVSS voltages are applied. After the abnormal time of the first frame, the EM normal driving circuit is used, thereby solving the problem that the pixel circuit appears to flicker.
  • the embodiment of the present disclosure further provides a driving method of a GOA unit of an illumination control signal. As shown in FIG. 11, the method includes:
  • the writing module 40 writes the signal of the second voltage terminal V2 to the signal output terminal EO under the control of the signal control terminal S1.
  • N is a positive integer greater than or equal to 1.
  • the first clock signal terminal CK inputs the first voltage
  • the signal input terminal EI inputs the first voltage
  • the second clock signal terminal CB inputs the second voltage.
  • the potential control module 10 outputs the signal of the second voltage terminal V2 to the first node A under the control of the first voltage input by the first clock signal terminal CK and the first voltage terminal V1, and is at the first clock signal terminal CK.
  • the second voltage input from the second clock signal terminal CB is output to the first node A under the control of the input first voltage, the first voltage terminal V1, and the first voltage input by the signal input terminal EI.
  • the pull-down module 20 is under the control of the first node A, the first voltage terminal V1, the second voltage terminal V2, the first voltage input by the first clock signal terminal CK, and the second voltage input by the second clock signal terminal CB.
  • the signal of the first voltage terminal V1 is output to the signal output terminal EO.
  • the first voltage and the second voltage input at each signal terminal are two relative signal values.
  • the first voltage input by the first clock signal terminal CK is a signal for controlling the transistor to be turned on
  • the second voltage input by the first clock signal terminal CK is a signal for controlling the transistor to be turned off.
  • the transistor connected to the first clock signal terminal CK is a P-type transistor
  • the first voltage input by the first clock signal terminal CK is a low voltage turn-on signal
  • the second voltage is a high voltage cutoff signal.
  • a second clock signal terminal CB inputs a first voltage
  • a first clock signal terminal CK inputs a second voltage
  • a signal input terminal EI inputs a second voltage
  • the potential control module 10 is at the first
  • the first voltage input by the second clock signal terminal CB is output to the first node A under the control of the second voltage input by the clock signal terminal CK, the first voltage terminal V1, and the second voltage input from the signal input terminal EI.
  • the pull-up module 30 outputs the signal of the second voltage terminal V2 to the signal output terminal EO under the control of the first node A.
  • the first clock signal terminal CK inputs the first voltage
  • the second clock signal terminal CB inputs the second voltage
  • the signal input terminal EI inputs the second voltage
  • the potential control module is at the first clock signal.
  • the signal of the second voltage terminal V2 is output to the first node A under the control of the first voltage input by the terminal CK and the first voltage terminal V1.
  • the pull-down module 20 is at the first node A, the first voltage terminal V1, the second voltage terminal V2, and the first time
  • the signal of the first voltage terminal V1 is output to the signal output terminal EO under the control of the first voltage input by the clock signal terminal CK and the second voltage input by the second clock signal terminal CB.
  • An embodiment of the present disclosure provides a method for driving a GOA unit of an illumination control signal.
  • the write module 40 is turned on, and the The signal of the two voltage terminals V2 is output to the signal output terminal EO, and the light-emitting control transistor connected thereto is controlled to be turned off by the signal output terminal EO, so that no current flows to the light-emitting device in the pixel circuit regardless of whether the driving transistor is turned on, and thus the pixel circuit There is no false illumination, and the SSD in the circuit will not cut off the power.
  • the write module 40 in the control GOA unit is turned off, the other modules are normally turned on, and the pixel circuit is controlled to perform normal display. Thereby ensuring the quality of the display screen of the display device.
  • Embodiments of the present disclosure also provide a GOA circuit, as shown in FIG. 12, comprising a plurality of cascaded GOA units of the above-described lighting control signals.
  • the signal input terminal EI sequentially inputs a low voltage on signal
  • the signal output terminal EO sequentially outputs an illumination control signal
  • the GOA circuit provided by the embodiment of the present disclosure has the same advantageous effects as the GOA unit provided by the foregoing embodiments of the present disclosure. Since the GOA unit has been described in detail in the foregoing embodiments, details are not described herein again.
  • Embodiments of the present disclosure also provide a display device including the above GOA circuit.
  • the display device provided by the embodiment of the present disclosure has the same advantageous effects as the GOA unit provided by the foregoing embodiments of the present disclosure. Since the GOA unit has been described in detail in the foregoing embodiments, details are not described herein again.

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Abstract

一种发光控制信号的GOA单元及其驱动方法、GOA电路、显示装置，可避免显示装置出现画面闪烁或显示异常的现象。发光控制信号的GOA单元包括电位控制模块（10）；下拉模块（20）；上拉模块（30）；写入模块（40），连接第二电压端（V2）、信号控制端（S1）、信号输出端（EO），将第二电压端（V2）的电压输出至信号输出端（EO）。

Description

GOA单元及其驱动方法、GOA电路、显示装置
本申请要求于2017年03月20日提交中国专利局、申请号为201710167240.4、发明名称为“一种GOA单元及其驱动方法、GOA电路、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种发光控制信号的GOA单元及其驱动方法、GOA电路、显示装置。
背景技术
有机电致发光二极管(Organic Light Emitting Diode，OLED)显示器是目前研究领域的热点之一，与液晶显示器(Liquid Crystal Display，LCD)相比，OLED具有低能耗、生产成本低、自发光、宽视角及相应速度快等优点。
现有的显示装置中，每行像素单元连接有一条扫描信号线和一条发光控制信号线，现有技术中，为了使显示装置实现窄边框化，通常采用扫描信号的GOA单元驱动扫描信号线，用发光控制信号的GOA单元驱动发光控制信号线。GOA电路通常由多个GOA单元级联形成，在开机或唤醒睡眠时，如图1(a)和图1(b)所示，每级GOA单元在驱动与其对应的像素电路前，如图1(a)所示，像素电路中驱动晶体管Md处于floating(悬浮)状态，此时，驱动晶体管Md容易受其他信号的干扰，使得像素电路中部分驱动晶体管Md被打开，使得Md、M6线路上有电流流过，导致驱动晶体管Md打开的像素出现错误发光现象。
此外，由于显示过程中像素电路中的高压端VDD比低压端VSS先输入信号，而驱动晶体管Md打开了的像素电路中在Md、M6线路上有电流，会将低压端VSS的电位值拉高，导致向高压端VDD/低压端VSS提供信号的电源发生损伤或坏死，而在这种情况下，电路中的SSD(start-up short detection function，上电短路侦测功能)便会启动保护功能，自动切断电源，导致屏幕不能完成正常显示。
发明内容
本公开的实施例采用如下技术方案：
第一方面，提供一种发光控制信号的GOA单元，包括电位控制模块、上拉模块、下拉模块、以及写入模块；所述电位控制模块，分别连接第一电压端、第二电压端、第一时钟信号端、第二时钟信号端、信号输入端、以及第一节点，用于在所述第一时钟信号端和所述第一电压端的控制下，将所述第二电压端的信号输出至所述第一节点；和/或，在所述第一时钟信号端、所述第一电压端、以及所述信号输入端的控制下将所述第二时钟信号端的信号输出至所述第一节点；所述下拉模块，分别连接所述第一节点、所述第一电压端、所述第二电压端、所述第一时钟信号端、所述第二时钟信号端、以及所述信号输出端，用于在所述第一节点、所述第一电压端、所述第二电压端、所述第一时钟信号端、以及所述第二时钟信号端的控制下，将所述第一电压端的信号输出至所述信号输出端；所述上拉模块，分别连接所述第一节点、所述第二电压端、以及信号输出端，用于在所述第一节点的控制下，将所述第二电压端的信号输出至所述信号输出端；所述写入模块，分别连接所述第二电压端、信号控制端、以及所述信号输出端，用于在所述信号控制端的控制下，将所述第二电压端的电压输出至所述信号输出端。
可选的，所述写入模块包括第一晶体管；所述第一晶体管的栅极连接所述信号控制端，第一极连接所述第二电压端，第二极连接所述信号输出端。
可选的，所述电位控制模块包括上拉控制模块和下拉控制模块；所述上拉控制模块分别连接所述下拉控制模块、所述第一时钟信号端、所述第一电压端、所述第二电压端、以及所述第一节点，用于在所述第一时钟信号端和所述第一电压端的控制下将所述第二电压端的信号输出至所述第一节点；所述下拉控制模块还分别连接所述信号输入端、所述第一时钟信号端、所述第二时钟信号端、所述第一电压端、以及所述第一节点，用于在所述信号输入端、所述第一时钟信号端、所述第一电压端的控制下，将所述第二时钟信号端的信号输出至所述第一节点。
可选的，所述上拉控制模块包括第二晶体管、第三晶体管、以及第一电容；所述第二晶体管的栅极连接所述第一时钟信号端，第一极连接所述第一电压端，第二极连接所述第三晶体管的栅极；所述第三晶体管的第一 极连接所述第二电压端，第二极连接所述第一节点；所述第一电容的第一端连接所述第二电压端，第二端连接所述第三晶体管的栅极。
进一步可选的，所述上拉控制模块还连接第二时钟信号端，所述上拉控制模块还包括第四晶体管和第五晶体管；所述第四晶体管的栅极连接所述第二晶体管的第二极，第一极连接所述第二电压端，第二极连接所述第五晶体管的第一极；所述第五晶体管的栅极连接所述第二时钟信号端，第二极连接所述下拉控制模块。
可选的，所述下拉控制模块包括第六晶体管、第七晶体管、第八晶体管、以及第二电容；所述第六晶体管的栅极连接所述第一时钟信号端，第一极连接所述信号输入端，第二极连接所述第七晶体管的第一极；所述第七晶体管的栅极连接所述第一电压端，第二极连接所述第八晶体管的栅极；所述第八晶体管的第一极连接所述第二时钟信号端，第二极连接所述第一节点；所述第二电容的第一端连接所述第八晶体管的栅极，第二端连接所述第八晶体管的第二极。
进一步可选的，所述下拉控制模块还包括第九晶体管；所述第九晶体管的栅极连接所述第六晶体管的第二极，第一极连接所述第一时钟信号端，第二极连接所述上拉控制模块。
可选的，所述下拉模块包括第十晶体管、第十一晶体管、第十二晶体管、以及第三电容；所述第十晶体管的栅极连接所述第一时钟信号端，第一极连接所述第一电压端，第二极连接所述第十二晶体管的栅极；所述第十一晶体管的栅极连接所述第一节点，第一极连接所述第二电压端，第二极连接所述第十二晶体管的栅极；所述第十二晶体管的第一极连接所述第一电压端，第二极连接所述信号输出端；所述第三电容的第一端连接所述第二时钟信号端，第二端连接所述第十二晶体管的栅极。
可选的，所述上拉模块包括第十三晶体管；所述第十三晶体管的栅极连接所述第一节点，第一极连接所述第二电压端，第二极连接所述信号输出端。
第二方面，提供一种第一方面所述的发光控制信号的GOA单元的驱动方法，包括：在前N图像帧内，写入模块在信号控制端的控制下，将第二电压端的信号写入至信号输出端；从第N+1图像帧开始，在一图像帧的缓冲阶段，第一时钟信号端输入第一电压、信号输入端输入第一电压、第二时钟信号端输入第二电压，电位控制模块在所述第一时钟信号端输入的 第一电压和第一电压端的控制下，将所述第二电压端的信号输出至第一节点，并在所述第一时钟信号端输入的第一电压、所述第一电压端、以及所述信号输入端输入的第一电压的控制下将所述第二时钟信号端输入的第二电压输出至所述第一节点；下拉模块在所述第一节点、所述第一电压端、所述第二电压端、所述第一时钟信号端输入的第一电压、以及所述第二时钟信号端输入的第二电压的控制下，将所述第一电压端的信号输出至所述信号输出端；在一图像帧的上拉阶段，所述第二时钟信号端输入第一电压、所述第一时钟信号端输入第二电压、所述信号输入端输入第二电压，所述电位控制模块在所述第一时钟信号端输入的第二电压、所述第一电压端、以及所述信号输入端输入的第二电压的控制下将所述第二时钟信号端输入的第一电压输出至所述第一节点；上拉模块在所述第一节点的控制下，将所述第二电压端的信号输出至所述信号输出端；在一图像帧的下拉阶段，所述第一时钟信号端输入第一电压、所述第二时钟信号端输入第二电压、所述信号输入端输入第二电压，所述电位控制模块在所述第一时钟信号端输入的第一电压和所述第一电压端的控制下，将所述第二电压端的信号输出至所述第一节点；下拉模块在所述第一节点、所述第一电压端、所述第二电压端、所述第一时钟信号端输入的第一电压、以及所述第二时钟信号端输入的第二电压的控制下，将所述第一电压端的信号输出至所述信号输出端；其中，N为大于等于1的正整数。
第三方面，提供一种GOA电路，包括多个级联的如第一方面所述的发光控制信号的GOA单元。
第四方面，提供一种显示装置，包括第三方面所述的GOA电路。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1(a)为现有技术提供的一种像素电路的结构示意图；
图1(b)为用于驱动图1(a)所示的像素电路时采用的各个信号的时序图；
图2为本公开实施例提供的一种GOA单元的结构示意图一；
图3为本公开实施例提供的一种GOA单元的结构示意图二；
图4为图3所示的GOA单元各个模块的一种具体结构示意图一；
图5为图3所示的GOA单元各个模块的一种具体结构示意图二；
图6为用于驱动图3所示的GOA单元时采用的各个信号的时序图；
图7-10为图3所示的GOA单元对应不同情况时的等效电路图；
图11为本公开实施例提供的一种GOA单元的驱动方法流程示意图；
图12为本公开实施例提供的一种GOA电路的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开实施例提供一种发光控制信号的GOA单元，如图2所示，包括电位控制模块10、下拉模块20、上拉模块30、以及写入模块40。
具体的，电位控制模块10，分别连接第一电压端V1、第二电压端V2、第一时钟信号端CK、第二时钟信号端CB、信号输入端EI、以及第一节点A，用于在第一时钟信号端CK和第一电压端V1的控制下，将第二电压端V2的信号输出至第一节点A；和/或，在第一时钟信号端CK、第一电压端V1、以及信号输入端EI的控制下将第二时钟信号端CB的信号输出至第一节点A。
下拉模块20，分别连接第一节点A、第一电压端V1、第二电压端V2、第一时钟信号端CK、第二时钟信号端CB、以及信号输出端EO，用于在第一节点A、第一电压端V1、第二电压端V2、第一时钟信号端CK、以及第二时钟信号端CB的控制下，将第一电压端V1的信号输出至信号输出端EO。
上拉模块30，分别连接第一节点A、第二电压端V2、以及信号输出端EO，用于在第一节点A的控制下，将第二电压端V2的信号输出至信号输出端EO。
写入模块40，分别连接第二电压端V2、信号控制端S1、以及信号输出端EO，用于在信号控制端S1的控制下，将第二电压端V2的电压输出至信号输出端EO。
本公开实施例提供一种发光控制信号的GOA单元，通过在GOA单元内增设写入模块40，并在前N图像帧内将其他模块均关闭，写入模块40开启，将第二电压端V2的信号输出至信号输出端EO，通过信号输出端EO控制与其连接的像素电路中的发光控制晶体管关闭，这样一来，无论驱动晶体管是否开启，像素电路中均无电流流向发光器件，因此像素电路不会出现错误发光现象，电路中的SSD也不会切断电源。待像素电路稳定后，控制GOA单元中的写入模块40关闭，其他模块正常开启，控制像素电路进行正常显示。从而保证显示装置画面显示的质量。
可选的，如图3所示，电位控制模块10包括上拉控制模块11和下拉控制模块12。
上拉控制模块11分别连接下拉控制模块12、第一时钟信号端CK、第一电压端V1、第二电压端V2、以及第一节点A，用于在第一时钟信号端CK和第一电压端V1的控制下将第二电压端V2的信号输出至第一节点A。
下拉控制模块12还分别连接信号输入端EI、第一时钟信号端CK、第二时钟信号端CB、第一电压端V1、以及第一节点A，用于在信号输入端EI、第一时钟信号端CK、第一电压端V1的控制下，将第二时钟信号端CB的信号输出至第一节点A。
以下对图3所示的发光控制信号的GOA单元中的各个模块的具体结构进行详细的说明。
具体的，如图4所示，写入模块40包括第一晶体管T1。
第一晶体管T1的栅极连接信号控制端S1，第一极连接第二电压端V2，第二极连接信号输出端EO。
需要说明的是，写入模块40还可以包括并联的多个第一晶体管T1。上述仅仅是对写入模块40的举例说明，其它与该写入模块40功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
如图4所示，上拉控制模块11包括第二晶体管T2、第三晶体管T3以及第一电容C1。
第二晶体管T2的栅极连接第一时钟信号端CK，第一极连接第一电压端V1，第二极连接第三晶体管T3的栅极。
第三晶体管T3的第一极连接第二电压端V2，第二极连接第一节点A。
第一电容C1的第一端连接第二电压端V2，第二端连接第三晶体管T3的栅极。
需要说明的是，所述上拉控制模块11还可以包括与第二晶体管T2并联的多个开关晶体管，和/或与第三晶体管T3并联的多个开关晶体管。上述仅仅是对上拉控制模块11的举例说明，其它与上拉控制模块11功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
如图4所示，下拉控制模块12包括第六晶体管T6、第七晶体管T7、第八晶体管T8、以及第二电容C2。
第六晶体管T6的栅极连接第一时钟信号端CK，第一极连接信号输入端EI，第二极连接第七晶体管T7的第一极。
第七晶体管T7的栅极连接第一电压端V1，第二极连接第八晶体管T8的栅极。
第八晶体管T8的第一极连接第二时钟信号端CB，第二极连接第一节点A。
第二电容C2的第一端连接第八晶体管T8的栅极，第二端连接第八晶体管T8的第二极。
需要说明的是，所述下拉控制模块12还可以包括与第六晶体管T6并联的多个开关晶体管，和/或与第七晶体管T7并联的多个开关晶体管，和/或与第八晶体管T8并联的多个开关晶体管。上述仅仅是对下拉控制模块12的举例说明，其它与下拉控制模块12功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
如图4所示，下拉模块20包括第十晶体管T10、第十一晶体管T11、第十二晶体管T12、以及第三电容C3。
第十晶体管T10的栅极连接第一时钟信号端CK，第一极连接第一电压端V1，第二极连接第十二晶体管T12的栅极。
第十一晶体管T11的栅极连接第一节点A，第一极连接第二电压端V2，第二极连接第十二晶体管T12的栅极。
第十二晶体管T12的第一极连接第一电压端V1，第二极连接信号输出端EO。
第三电容C3的第一端连接第二时钟信号端CB，第二端连接第十二晶体管T12的栅极。
需要说明的是，所述下拉模块20还可以包括与第十晶体管T10并联的多个开关晶体管，和/或与第十一晶体管T11并联的多个开关晶体管，和/或与第十二晶体管T12并联的多个开关晶体管。上述仅仅是对下拉模块 20的举例说明，其它与下拉模块20功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
如图4所示，上拉模块30包括第十三晶体管T13。
第十三晶体管T13的栅极连接第一节点A，第一极连接第二电压端V2，第二极连接信号输出端EO。
需要说明的是，上拉模块30还可以包括与第十三晶体管T13并联的多个开关晶体管。上述仅仅是对上拉模块30的举例说明，其它与上拉模块30功能相同的结构在此不再一一赘述，但都应当属于本公开的保护范围。
此处，需要说明的是，第一、本公开实施例对各个模块以及单元中的晶体管的类型不做限定，即上述第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、以及第十三晶体管T13可以是为N型晶体管或者P型晶体管。本公开以下实施例均是以第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、第十一晶体管T11、第十二晶体管T12、以及第十三晶体管T13为P型晶体管为例进行的说明。此外，与该GOA单元的信号输出端EO相连接的像素单元中的晶体管也为P型为例。
其中，上述晶体管的第一极可以是漏极、第二极可以是源极；或者，第一极可以是源极、第二极可以是漏极。本公开实施例对此不作限制。
此外，根据晶体管导电方式的不同，可以将上述像素电路中的晶体管分为增强型晶体管和耗尽型晶体管。本公开实施例对此不作限制。
第二、本公开实施例均是以第二电压端V2输入高电平，第一电压端V1输入低电平，或将第一电压端V1接地处理为例进行的说明，并且，这里的高、低仅表示输入的电压之间的相对大小关系。
以下，根据一个具体的实施例对本公开提供的GOA单元进行说明。
实施例一
如图5所示，提供一种发光控制信号的GOA单元，包括上拉控制模块11、下拉控制模块12、下拉模块20、上拉模块30、以及写入模块40。
具体的，写入模块40包括第一晶体管T1。
第一晶体管T1的栅极连接信号控制端S1，第一极连接第二电压端V2， 第二极连接信号输出端EO。
上拉控制模块11包括第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、以及第一电容C1。
第二晶体管T2的栅极连接第一时钟信号端CK，第一极连接第一电压端V1，第二极连接第三晶体管T3的栅极。
第三晶体管T3的第一极连接第二电压端V2，第二极连接第一节点A。第四晶体管T4的栅极连接第二晶体管T2的第二极，第一极连接第二电压端V2，第二极连接第五晶体管T5的第一极。
在上拉控制模块11还连接第二时钟信号端CB的情况下，第五晶体管T5的栅极连接第二时钟信号端CB，第二极连接下拉控制模块12。
第一电容C1的第一端连接第二电压端V2，第二端连接第三晶体管T3的栅极。
下拉控制模块12包括第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、以及第二电容C2。
第六晶体管T6的栅极连接第一时钟信号端CK，第一极连接信号输入端EI，第二极连接第七晶体管T7的第一极。
第七晶体管T7的栅极连接第一电压端V1，第二极连接第八晶体管T8的栅极。
第八晶体管T8的第一极连接第二时钟信号端CB，第二极连接第一节点A。
第九晶体管T9的栅极连接第六晶体管T6的第二极，第一极连接第一时钟信号端CK，第二极连接上拉控制模块11。
第二电容C2的第一端连接第七晶体管T7的第二极，第二端连接第八晶体管T8的第二极。
下拉模块20包括第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第三电容C3。
第十晶体管T10的栅极连接第一时钟信号端CK，第一极连接第一电压端V1，第二极连接第十二晶体管T12的栅极。
第十一晶体管T11的栅极连接第一节点A，第一极连接第二电压端V2，第二极连接第十二晶体管T12的栅极。
第十二晶体管T12的第一极连接第一电压端V1，第二极连接信号输出端EO。
第三电容C3的第一端连接第二时钟信号端CB，第二端连接第十二晶体管T12的栅极。
上拉模块30包括第十三晶体管T13。
第十三晶体管T13的栅极连接第一节点A，第一极连接第二电压端V2，第二极连接信号输出端EO。
如图6所示，该GOA单元的每一帧显示过程可以分为缓冲阶段P1、上拉阶段P2、和下拉阶段P3。以下结合图6所示的各个控制信号端的时序图，对图5所示的发光控制信号的GOA单元的工作原理进行详细的说明。
在前N图像帧内，信号控制端S1输入低压信号，第一时钟信号端CK、第二时钟信号端CB输入高压信号，此时，如图7所示，第一晶体管T1导通，第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5
、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、十晶体管T10、第十一晶体管T11、第十二晶体管T12、以及第十三晶体管T13均截止(处于截止状态的晶体管以打“×”表示)。
其中，第一晶体管T1导通，第二电压端V2的电压写入到信号输出端EO，信号输出端EO一直保持高电压，控制与其连接的晶体管截止。此时，GOA单元内的其他晶体管在高压信号作用下全部保持截止状态。
此处，N为大于或等于1的正整数，本公开实施例可选的，N＝1，即在第一图像帧内，信号控制端S1输入低压信号，第一时钟信号端CK、第二时钟信号端CB输入高压信号，此时，如图7所示，第一晶体管T1导通，第二电压端V2的电压写入到信号输出端EO，信号输出端EO一直保持高电压，控制与其连接的晶体管截止。
从第N+1图像帧开始，在一图像帧的缓冲阶段P1，第一时钟信号端CK、信号输入端EI输入低压信号，第二时钟信号端CB、信号控制端S1输入高压信号，此时，如图8所示，第二晶体管T2、第三晶体管T3、第四晶体管T4、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第十晶体管T10、以及第十二晶体管T12均导通，第一晶体管T1、第五晶体管T5、第十一晶体管T11、以及第十三晶体管T13均截止。
其中，第二晶体管T2导通，第一电压端V1的信号经第二晶体管T2写入至第三晶体管T3的栅极以控制第三晶体管T3开启，此时，第二电压端V2的信号经第三晶体管T3写入至第一节点A；第六晶体管T6和第七 晶体管T7开启，信号输入端EI的信号经第六晶体管T6和第七晶体管T7写入至第八晶体管T8的栅极，以控制第八晶体管T8开启，此时，第二时钟信号端CB的信号经第八晶体管T8写入至第一节点A。第一节点A输出高压信号。与此同时，第七晶体管T7第二极的低压信号写入至第二电容C2的第一端对第二电容C2进行充电。
在此基础上，第一节点A输出的高压信号控制第十一晶体管T11和第十三晶体管T13关闭，第十晶体管T10导通，第一电压端V1的信号经第十晶体管T10写入至第十二晶体管T12的栅极，控制第十二晶体管T12开启，第一电压端V1的电压经第十二晶体管T12写入至信号输出端EO。信号输出端EO输出低压信号。
在一图像帧的上拉阶段P2，第二时钟信号端CB输入低压信号，第一时钟信号端CK、信号控制端S1、信号输入端EI输入高压信号，此时，如图9所示，第五晶体管T5、第七晶体管T7、第八晶体管T8、第十一晶体管T11、以及第十三晶体管T13均导通，第二晶体管T2、第三晶体管T3、第四晶体管T4、第六晶体管T6、第九晶体管T9、十晶体管T10、以及第十二晶体管T12均截止。
其中，存储电容C2进行放电，控制第八晶体管T8导通，第二时钟信号端CB的低压经第八晶体管T8写入至第一节点A。第一节点A输出低压信号。
在此基础上，第一节点A的低压控制第十一晶体管T11和第十三晶体管T13开启，第二电压端V2的电压经第十一晶体管T11写入至第十二晶体管T12的栅极，控制第十二晶体管T12截止，第二电压端V2的电压经第十三晶体管T13写入至信号输出端EO。信号输出端EO输出高压信号。
在一图像帧的下拉阶段P3，第一时钟信号端CK输入低压信号，信号输入端EI、第二时钟信号端CB、信号控制端S1输入高压信号，此时，如图10所示，第二晶体管T2、第三晶体管T3、第四晶体管T4、第六晶体管T6、第七晶体管T7、十晶体管T10、以及第十二晶体管T12均导通，第一晶体管T1、第五晶体管T5、第八晶体管T8、第九晶体管T9、第十一晶体管T11、以及第十三晶体管T13均截止。
其中，第二晶体管T2导通，第一电压端V1的信号经第二晶体管T2写入至第三晶体管T3的栅极以控制第三晶体管T3开启，此时，第二电压端V2的信号经第三晶体管T3写入至第一节点A。第一节点A输出高电平。
在此基础上，第一节点A输出的高电平控制第十一晶体管T11和第十三晶体管T13关闭，第十晶体管T10导通，第一电压端V1的信号经第十晶体管T10写入至第十二晶体管T12的栅极，控制第十二晶体管T12开启，第一电压端V1的电压经第十二晶体管T12写入至信号输出端EO。信号输出端EO输出低电平。
如图1(a)所示的像素电路，电压的施加顺序为：V1/Vinit on—S1/S2/EM等控制信号开始—VDD on—VSS on。即在复位阶段，第一信号端S1输入低压开启信号，使能信号端EM以及扫描信号端S2输入高压截止信号；数据写入阶段，扫描信号端S2输入低压开启信号，第一信号端S1、以及使能信号端EM输入高压截止信号；发光阶段，使能信号端EM输入低压开启信号，第一信号端S1、以及扫描信号端S2输入高压截止信号。信号输出端EO输出的信号，写入到使能信号端EM，用于控制第六晶体管M6的开启与关闭，从而控制像素电路的发光。
如图1(b)所示，S1施加的t1时间和S2信号施加的t2时间比EM施加的t3时间要短很多。其原因是图1(b)的信号顺序应该依次按照竖向顺序施加，因此t1驱动的时间内横向的像素被施加控制信号，接着下一排的像素也被施加控制信号，最后以同样的方式，所有像素都被施加控制信号。所以大部分像素电路在使能信号端EM变为低压期间(即发光阶段)从高压端VDD被施加ELVDD电压，而在数据写入阶段，高压端VDD被施加电压为GND(即0V-Vth)，在发光阶段高压端VDD的电压突然突变为ELVDD电压(例如为4.5V)，从而导致驱动晶体管Md的Vgd(Gate-Drain的电压差，决定TFT开关的电压差)变大，电压变得异常，因此驱动晶体管Md的电流也会变为大电流，导致像素电路出现异常驱动，使得显示装置的开机画面出现屏幕闪烁的问题。虽然可以通过在使能信号端EM变为低压前(即与其连接的GOA电路驱动之前)施加ELVDD，ELVSS电压来解决上述异常驱动的问题，但在这种情况下，由于没有GOA信号，整个画面就会发亮，就会出现使用者并不希望出现的异常显示画面。
本公开实施例提供的GOA单元，通过在前N帧(像素电路出现异常驱动的几帧，例如N＝1)控制信号输出端EO输出高电平，使EM信号持续保持高压，不让电流流向发光器件，从第N+1帧开始，GOA单元正常驱动，施加ELVDD，ELVSS电压，第一帧异常时间过后，使用EM正常驱动电路，从而很好的解决了像素电路出现画面闪烁的问题。
本公开实施例还提供一种发光控制信号的GOA单元的驱动方法，如图11所示，所述方法包括：
S10、在前N图像帧内，写入模块40在信号控制端S1的控制下，将第二电压端V2的信号写入至信号输出端EO。
其中，N为大于等于1的正整数。
S20、从第N+1图像帧开始，在一图像帧的缓冲阶段P1，第一时钟信号端CK输入第一电压、信号输入端EI输入第一电压、第二时钟信号端CB输入第二电压，电位控制模块10在第一时钟信号端CK输入的第一电压和第一电压端V1的控制下，将第二电压端V2的信号输出至第一节点A，并在第一时钟信号端CK输入的第一电压、第一电压端V1、以及信号输入端EI输入的第一电压的控制下将第二时钟信号端CB输入的第二电压输出至第一节点A。
下拉模块20在第一节点A、第一电压端V1、第二电压端V2、第一时钟信号端CK输入的第一电压、以及第二时钟信号端CB输入的第二电压的控制下，将第一电压端V1的信号输出至信号输出端EO。
其中，此处每一个信号端输入的第一电压和第二电压是两个相对的信号值。例如第一时钟信号端CK输入的第一电压为控制晶体管导通的信号，则第一时钟信号端CK输入的第二电压为控制晶体管截止的信号。具体的，与第一时钟信号端CK连接的晶体管为P型晶体管，则第一时钟信号端CK输入的第一电压为低压开启信号，第二电压为高压截止信号。
S30、在一图像帧的上拉阶段P2，第二时钟信号端CB输入第一电压、第一时钟信号端CK输入第二电压、信号输入端EI输入第二电压，电位控制模块10在第一时钟信号端CK输入的第二电压、第一电压端V1、以及信号输入端EI输入的第二电压的控制下将第二时钟信号端CB输入的第一电压输出至第一节点A。
上拉模块30在第一节点A的控制下，将第二电压端V2的信号输出至信号输出端EO。
S40、在一图像帧的下拉阶段P3，第一时钟信号端CK输入第一电压、第二时钟信号端CB输入第二电压、信号输入端EI输入第二电压，电位控制模块在第一时钟信号端CK输入的第一电压和第一电压端V1的控制下，将第二电压端V2的信号输出至第一节点A。
下拉模块20在第一节点A、第一电压端V1、第二电压端V2、第一时 钟信号端CK输入的第一电压、以及第二时钟信号端CB输入的第二电压的控制下，将第一电压端V1的信号输出至信号输出端EO。
本公开实施例提供一种发光控制信号的GOA单元的驱动方法，通过在GOA单元内增设写入模块40，并在前N图像帧内将其他模块均关闭，写入模块40开启，并将第二电压端V2的信号输出至信号输出端EO，通过信号输出端EO控制与其连接的发光控制晶体管关闭，这样一来，无论驱动晶体管是否开启，像素电路中均无电流流向发光器件，因此像素电路不会出现错误发光现象，电路中的SSD也不会切断电源。待像素电路稳定后，控制GOA单元中的写入模块40关闭，其他模块正常开启，控制像素电路进行正常显示。从而保证显示装置画面显示的质量。
本公开实施例还提供一种GOA电路，如图12所示，包括多个级联的上述发光控制信号的GOA单元。
其中，从第一行到第n+1行，信号输入端EI依次输入低压开启信号，信号输出端EO依次输出发光控制信号。
此外，由于每个GOA单元依次开启，因此，在同一时刻，相邻的奇数行DOA单元中的第一时钟信号端CK和第二时钟信号端CB与偶数行DOA单元中的第一时钟信号端CK和第二时钟信号端CB在图7中的波形正好相反。
本公开实施例提供的GOA电路具有与本公开前述实施例提供的GOA单元相同的有益效果，由于GOA单元在前述实施例中已经进行了详细说明，此处不再赘述。
本公开实施例还提供一种显示装置，包括上述GOA电路。
本公开实施例提供的显示装置具有与本公开前述实施例提供的GOA单元相同的有益效果，由于GOA单元在前述实施例中已经进行了详细说明，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种发光控制信号的GOA单元，包括电位控制模块、上拉模块、下拉模块、以及写入模块；
    所述电位控制模块分别连接第一电压端、第二电压端、第一时钟信号端、第二时钟信号端、信号输入端、以及第一节点，用于在所述第一时钟信号端和所述第一电压端的控制下，将所述第二电压端的信号输出至所述第一节点；和/或，在所述第一时钟信号端、所述第一电压端、以及所述信号输入端的控制下将所述第二时钟信号端的信号输出至所述第一节点；
    所述下拉模块分别连接所述第一节点、所述第一电压端、所述第二电压端、所述第一时钟信号端、所述第二时钟信号端、以及所述信号输出端，用于在所述第一节点、所述第一电压端、所述第二电压端、所述第一时钟信号端、以及所述第二时钟信号端的控制下，将所述第一电压端的信号输出至所述信号输出端；
    所述上拉模块分别连接所述第一节点、所述第二电压端、以及信号输出端，用于在所述第一节点的控制下，将所述第二电压端的信号输出至所述信号输出端；
    所述写入模块分别连接所述第二电压端、信号控制端、以及所述信号输出端，用于在所述信号控制端的控制下，将所述第二电压端的电压输出至所述信号输出端。
  2. 根据权利要求1所述的GOA单元，其中，所述写入模块包括第一晶体管；
    所述第一晶体管的栅极连接所述信号控制端，第一极连接所述第二电压端，第二极连接所述信号输出端。
  3. 根据权利要求1所述的GOA单元，其中，所述电位控制模块包括上拉控制模块和下拉控制模块；
    所述上拉控制模块分别连接所述下拉控制模块、所述第一时钟信号端、所述第一电压端、所述第二电压端、以及所述第一节点，用于在所述第一时钟信号端和所述第一电压端的控制下将所述第二电压端的信号输出至所述第一节点；
    所述下拉控制模块还分别连接所述信号输入端、所述第一时钟信号端、所述第二时钟信号端、所述第一电压端、以及所述第一节点，用于在所述信号输入端、所述第一时钟信号端、所述第一电压端的控制下，将所述第 二时钟信号端的信号输出至所述第一节点。
  4. 根据权利要求3所述的GOA单元，其中，所述上拉控制模块包括第二晶体管、第三晶体管、以及第一电容；
    所述第二晶体管的栅极连接所述第一时钟信号端，第一极连接所述第一电压端，第二极连接所述第三晶体管的栅极；
    所述第三晶体管的第一极连接所述第二电压端，第二极连接所述第一节点；
    所述第一电容的第一端连接所述第二电压端，第二端连接所述第三晶体管的栅极。
  5. 根据权利要求4所述的GOA单元，其中，所述上拉控制模块还连接第二时钟信号端，所述上拉控制模块还包括第四晶体管和第五晶体管；
    所述第四晶体管的栅极连接所述第二晶体管的第二极，第一极连接所述第二电压端，第二极连接所述第五晶体管的第一极；
    所述第五晶体管的栅极连接所述第二时钟信号端，第二极连接所述下拉控制模块。
  6. 根据权利要求3所述的GOA单元，其中，所述下拉控制模块包括第六晶体管、第七晶体管、第八晶体管、以及第二电容；
    所述第六晶体管的栅极连接所述第一时钟信号端，第一极连接所述信号输入端，第二极连接所述第七晶体管的第一极；
    所述第七晶体管的栅极连接所述第一电压端，第二极连接所述第八晶体管的栅极；
    所述第八晶体管的第一极连接所述第二时钟信号端，第二极连接所述第一节点；
    所述第二电容的第一端连接所述第八晶体管的栅极，第二端连接所述第八晶体管的第二极。
  7. 根据权利要求6所述的GOA单元，其中，所述下拉控制模块还包括第九晶体管；
    所述第九晶体管的栅极连接所述第六晶体管的第二极，第一极连接所述第一时钟信号端，第二极连接所述上拉控制模块。
  8. 根据权利要求1所述的GOA单元，其中，所述下拉模块包括第十晶体管、第十一晶体管、第十二晶体管、以及第三电容；
    所述第十晶体管的栅极连接所述第一时钟信号端，第一极连接所述第 一电压端，第二极连接所述第十二晶体管的栅极；
    所述第十一晶体管的栅极连接所述第一节点，第一极连接所述第二电压端，第二极连接所述第十二晶体管的栅极；
    所述第十二晶体管的第一极连接所述第一电压端，第二极连接所述信号输出端；
    所述第三电容的第一端连接所述第二时钟信号端，第二端连接所述第十二晶体管的栅极。
  9. 根据权利要求1所述的GOA单元，其中，所述上拉模块包括第十三晶体管；
    所述第十三晶体管的栅极连接所述第一节点，第一极连接所述第二电压端，第二极连接所述信号输出端。
  10. 一种权利要求1-9任一项所述的发光控制信号的GOA单元的驱动方法，包括：
    在前N图像帧内，写入模块在信号控制端的控制下，将第二电压端的信号写入至信号输出端；
    从第N+1图像帧开始，在一图像帧的缓冲阶段，第一时钟信号端输入第一电压、信号输入端输入第一电压、第二时钟信号端输入第二电压，电位控制模块在所述第一时钟信号端输入的第一电压和第一电压端的控制下，将所述第二电压端的信号输出至第一节点，并在所述第一时钟信号端输入的第一电压、所述第一电压端、以及所述信号输入端输入的第一电压的控制下将所述第二时钟信号端输入的第二电压输出至所述第一节点；
    下拉模块在所述第一节点、所述第一电压端、所述第二电压端、所述第一时钟信号端输入的第一电压、以及所述第二时钟信号端输入的第二电压的控制下，将所述第一电压端的信号输出至所述信号输出端；
    在一图像帧的上拉阶段，所述第二时钟信号端输入第一电压、所述第一时钟信号端输入第二电压、所述信号输入端输入第二电压，所述电位控制模块在所述第一时钟信号端输入的第二电压、所述第一电压端、以及所述信号输入端输入的第二电压的控制下将所述第二时钟信号端输入的第一电压输出至所述第一节点；
    上拉模块在所述第一节点的控制下，将所述第二电压端的信号输出至所述信号输出端；
    在一图像帧的下拉阶段，所述第一时钟信号端输入第一电压、所述第 二时钟信号端输入第二电压、所述信号输入端输入第二电压，所述电位控制模块在所述第一时钟信号端输入的第一电压和所述第一电压端的控制下，将所述第二电压端的信号输出至所述第一节点；
    下拉模块在所述第一节点、所述第一电压端、所述第二电压端、所述第一时钟信号端输入的第一电压、以及所述第二时钟信号端输入的第二电压的控制下，将所述第一电压端的信号输出至所述信号输出端；
    其中，N为大于等于1的正整数。
  11. 一种GOA电路，包括多个级联的如权利要求1-9任一项所述的发光控制信号的GOA单元。
  12. 一种显示装置，包括权利要求11所述的GOA电路。
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