WO2016119467A1 - 驱动电路及其驱动方法、显示装置 - Google Patents
驱动电路及其驱动方法、显示装置 Download PDFInfo
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- WO2016119467A1 WO2016119467A1 PCT/CN2015/089759 CN2015089759W WO2016119467A1 WO 2016119467 A1 WO2016119467 A1 WO 2016119467A1 CN 2015089759 W CN2015089759 W CN 2015089759W WO 2016119467 A1 WO2016119467 A1 WO 2016119467A1
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- clock signal
- driver
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- timing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/18—Timing circuits for raster scan displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
Definitions
- the present invention relates to the field of display technologies, and in particular, to a driving circuit, a driving method thereof, and a display device.
- the data signal and the clock signal are outputted by the timing controller, the driver of the display panel receives the data signal and the clock signal, and performs based on the data signal and the clock signal A logic operation to generate a drive signal for driving the display panel.
- the phase difference between the data signal and the clock signal is a predetermined value, that is, the data signal and the clock signal are mutually corresponding.
- the data signal and the clock signal may have different degrees of signal delay, resulting in the data signal and the clock signal actually received by the driver. It does not match the data signal and the clock signal that it needs, which affects the display quality of the display device.
- an embodiment of the present invention provides a driving circuit, a driving method thereof, and a display device, which are used to solve the problem that the data signal and the clock signal actually received by the driver in the prior art cannot be between the data signal and the clock signal required by the driver. Matching each other, thereby affecting the display quality of the display device.
- Embodiments of the present invention provide a driving circuit including a timing controller, a timing regulator, and a driver, the timing regulator being connected to an output end of the timing controller, and an output end of the timing regulator being connected to the driver
- the timing controller is configured to output a first data signal and a first clock signal
- the timing adjuster is configured to adjust a phase of the first data signal and the first clock signal to generate a second data signal corresponding to each other
- a second clock signal the driver is configured to generate a driving signal according to the second data signal and the second clock signal.
- the timing adjuster may include a conversion unit and an synchronization unit, an input end of the conversion unit is connected to the timing controller, and a first output end of the conversion unit is connected to a first input end of the synchronization unit, a second output of the conversion unit is coupled to the driver, a second input of the synchronization unit is coupled to the timing controller, an output of the synchronization unit is coupled to the driver; Adjusting a phase of the first clock signal to generate the second clock signal; the synchronization unit is configured to adjust a phase of the first data signal according to the second clock signal to generate a second data signal, The second data signal and the second clock signal have a predetermined phase difference.
- the conversion unit may include a plurality of delay circuits.
- the delay circuit can include an inverter.
- the inverter may be selected from the group consisting of an NMOS type inverter, a PMOS type inverter, and a CMOS type inverter.
- the synchronization unit may include a D flip-flop.
- the driver can include a source driver.
- the driver and the timing adjuster can be integrated.
- Embodiments of the present invention also provide a display device including a display panel and any of the above driving circuits.
- the embodiment of the invention further provides a driving method of a driving circuit, the driving circuit includes a timing controller, a timing regulator and a driver, and the timing regulator is connected to an output end of the timing controller, and the timing regulator The output is connected to the driver; the driving method includes:
- a drive signal is generated by the driver based on the second data signal and the second clock signal.
- the timing adjuster may include a conversion unit and an synchronization unit, an input end of the conversion unit is connected to the timing controller, and a first output end of the conversion unit is connected to a first input end of the synchronization unit, a second output of the conversion unit is coupled to the driver, and a second input of the synchronization unit is coupled to the timing controller, the synchronization An output of the unit is coupled to the driver; wherein a phase of the first data signal and the first clock signal is adjusted by the timing adjuster to generate a second data signal and a second clock signal corresponding to each other
- the steps include:
- the conversion unit may include a plurality of delay circuits.
- the delay circuit can include an inverter.
- the inverter may be selected from the group consisting of an NMOS type inverter, a PMOS type inverter, and a CMOS type inverter.
- the synchronization unit may include a D flip-flop.
- the driver can include a source driver.
- the driver and the timing adjuster can be integrated.
- the driving circuit includes a timing controller, a timing controller and a driver, and the timing controller outputs a first data signal and a first clock signal, a timing adjuster adjusting a phase of the first data signal and the first clock signal to generate a second data signal and a second clock signal corresponding to each other, the driver according to the second data signal and the second The clock signal produces a drive signal.
- the timing adjuster actively adjusts the first data signal and the first clock signal output by the timing controller to generate mutually corresponding second data signals and second clock signals actually needed by the driver, thereby implementing and displaying
- the perfect matching of the panels further improves the display quality of the display device.
- FIG. 1 is a schematic block diagram of a driving circuit according to Embodiment 1 of the present invention.
- FIG. 2 is a schematic block diagram of the timing adjuster shown in FIG. 1;
- FIG. 3 is a flowchart of a driving method of a driving circuit according to Embodiment 3 of the present invention.
- FIG. 1 is a schematic block diagram of a driving circuit according to Embodiment 1 of the present invention.
- the driving circuit may include a timing controller 101, a timing regulator 102, and a driver 103.
- the timing regulator 102 is connected to an output of the timing controller 101, and an output of the timing regulator 102 is connected to the driver 103.
- the timing controller 101 is configured to output a first data signal and a first clock signal
- the timing adjuster 102 is configured to adjust a phase of the first data signal and the first clock signal to generate a second data signal and a second clock signal corresponding to each other.
- the driver 103 is configured to generate a driving signal according to the second data signal and the second clock signal.
- the timing controller 101 generates a first data signal and a first clock signal, and transmits the first data signal and the first clock signal to the timing adjuster 102.
- the phase difference between the first data signal and the first clock signal is a predetermined value.
- factors such as circuit layout may cause the first data signal and the first clock signal to appear to different degrees.
- the signal is delayed such that the phase difference between the first data signal and the first clock signal deviates from a predetermined value.
- the timing adjuster 102 after receiving the first data signal and the first clock signal, adjusts the phases of the first data signal and the first clock signal to generate the phase-corrected second data signal and the second clock.
- the signal, the second data signal and the second clock signal correspond to each other.
- the driver 103 receives the second data signal and the second clock signal, and then generates a driving signal required by the display panel according to the second data signal and the second clock signal, thereby achieving perfect matching with the display panel, thereby improving the display quality of the display device.
- the timing adjuster 102 is connected to the output of the timing controller 101, and the output of the timing adjuster 102 is connected to the driver 103.
- the timing adjuster 102 can include a conversion unit 104 and a synchronization unit 105.
- the input of the conversion unit 104 is connected to the timing controller 101, and the conversion unit
- the first output of the 104 is coupled to the first input of the synchronization unit 105
- the second output of the conversion unit 104 is coupled to the driver 103
- the second input of the synchronization unit 105 is coupled to the timing controller 101.
- the output of the synchronization unit 105 The terminal is connected to the drive 103.
- the conversion unit 104 receives the first clock signal output from the timing controller 101, then adjusts the phase of the first clock signal to generate a second clock signal, and transmits the second clock signal to the synchronization unit 105 and the driver 103, respectively.
- the synchronization unit 105 receives the first data signal output by the timing controller 101 and the second clock signal output by the conversion unit 104, and then adjusts the phase of the first data signal according to a predetermined phase difference to generate a corresponding to the second clock signal. The second data signal.
- the predetermined phase difference refers to a phase difference between a clock signal and a data signal actually required by the driver of the display panel.
- one or more predetermined phase differences may be pre-stored in a storage unit (not shown in the drawing) according to parameters such as the size of the display panel, and the predetermined phase difference is set according to actual conditions. So that when the synchronization unit receives the second clock signal, the phase of the first data signal can be adjusted according to a predetermined phase difference, thereby generating a driver corresponding to the second clock signal that is actually required by the driver driving the display panel. The second data signal.
- the conversion unit 104 includes a plurality of delay circuits. Each delay circuit provides a different degree of signal delay to the first clock signal to adjust the phase of the first clock signal to produce a second clock signal.
- the phase of the first clock signal may be delayed by any known delay circuit, which is not specifically limited herein.
- the delay circuit typically includes an inverter.
- the inverter is an NMOS type inverter or a PMOS type inverter. Since the NMOS type inverter or the PMOS type inverter only needs to use one type of transistor, the manufacturing cost of the drive circuit can be reduced.
- the inverter is a CMOS type inverter.
- the CMOS type inverter has a relatively low resistance value, which can reduce the power consumption of the circuit, and the CMOS type inverter has the advantage of high processing efficiency, and is more suitable for the driving circuit provided by the present invention.
- the synchronization unit 105 includes a D flip-flop.
- the D flip-flop includes a first input terminal for receiving the second clock signal, a second input terminal for receiving the first data signal, and an output terminal for outputting the first data signal to the driver 103. Two data signals.
- the driver 103 includes a source driver.
- the source driver receives the second clock signal generated by the conversion unit 104 and the second data signal generated by the synchronization unit 105, and then generates a drive signal based on the second clock signal and the second data signal. Since the second data signal and the second clock signal correspond to each other and are the data signals and clock signals actually needed by the driver, perfect matching with the display panel can be achieved, thereby improving the display quality of the display device.
- the timing adjuster 102 is integrated with the driver 103, so that the influence of factors such as the circuit layout on the signal can be further reduced, and the driver 103 can obtain the data signal and the clock signal that are actually needed, thereby facilitating the improvement of the display device. Display quality.
- the driving circuit includes a timing controller, a timing controller and a driver, and the timing controller outputs the first data signal and the first clock signal, and the timing adjuster adjusts the first data signal and the first clock signal Phases to generate mutually corresponding second data signals and second clock signals, and the driver generates drive signals based on the second data signals and the second clock signals.
- the timing regulator actively adjusts the first data signal and the first clock signal output by the timing controller to generate a second data signal and a second clock signal that are actually required by the driver, thereby implementing the display panel Perfect matching, which in turn increases the display quality of the display device.
- the present embodiment provides a display device, including a display panel and a driving circuit provided in Embodiment 1.
- a display device including a display panel and a driving circuit provided in Embodiment 1.
- the driving circuit includes a timing controller, a timing controller and a driver, and the timing controller outputs the first data signal and the first clock signal, and the timing adjuster adjusts the first data signal and the first clock signal Phases to generate mutually corresponding second data signals and second clock signals, and the driver generates drive signals based on the second data signals and the second clock signals.
- the timing regulator actively adjusts the first data signal and the first clock signal output by the timing controller to generate a second data signal and a second clock signal that are actually required by the driver, thereby implementing the display panel Perfect matching, which in turn improves the display quality of the display device.
- FIG. 3 is a flowchart of a driving method of a driving circuit according to Embodiment 3 of the present invention.
- the driving circuit may include a timing controller, a timing regulator and a driver, the timing regulator is connected to the output of the timing controller, and the output of the timing regulator is connected to the driver.
- the driving method may include the following steps 3001-3003.
- Step 3001 Output a first data signal and a first clock signal through a timing controller.
- the timing controller generates the first data signal and the first clock signal, and transmits the first data signal and the first clock signal to the timing adjuster.
- the phase difference between the first data signal and the first clock signal is a predetermined value.
- factors such as circuit layout may cause the first data signal and the first clock signal to appear to different degrees.
- the signal is delayed such that the phase difference between the first data signal and the first clock signal deviates from a predetermined value.
- Step 3002 Adjust a phase of the first data signal and the first clock signal by a timing adjuster to generate a second data signal and a second clock signal corresponding to each other.
- the timing adjuster after receiving the first data signal and the first clock signal, the timing adjuster adjusts the phases of the first data signal and the first clock signal to generate the phase-corrected second data signal and the second The clock signal, the second data signal and the second clock signal correspond to each other.
- the timing adjuster may include a conversion unit and an synchronization unit, the input end of the conversion unit being connected to the timing controller, the first output end of the conversion unit being connected to the first input end of the synchronization unit, and the second output end of the conversion unit Connected to the driver, the second input of the synchronization unit is connected to the timing controller, and the output of the synchronization unit is connected to the driver.
- the conversion unit receives the first clock signal output by the timing controller, then adjusts the phase of the first clock signal to generate a second clock signal, and transmits the second clock signal to the synchronization unit and the driver, respectively.
- the synchronization unit receives the first data signal output by the timing controller and the second clock signal output by the conversion unit, and then adjusts the phase of the first data signal according to the predetermined phase difference to generate second data corresponding to the second clock signal. signal.
- the conversion unit may include a plurality of delay circuits. Each delay circuit provides a different degree of signal delay to the first clock signal to adjust the phase of the first clock signal to produce a second clock signal.
- the phase of the first clock signal may be delayed by any known delay circuit, which is not specifically limited herein.
- the delay circuit typically includes an inverter.
- the inverter is an NMOS type inverter or a PMOS type inverter. Since the NMOS type inverter or the PMOS type inverter only needs to use one type of transistor, the manufacturing cost of the drive circuit can be reduced.
- the inverter is a CMOS type inverter.
- the CMOS type inverter has a relatively low resistance value, which can reduce the power consumption of the circuit, and the CMOS type inverter has the advantage of a higher processing rate, and is more suitable for the driving circuit provided by the present invention.
- the synchronization unit includes a D flip-flop.
- the D flip-flop includes a first input terminal for receiving the second clock signal, a second input terminal for receiving the first data signal, and an output terminal for outputting the second data to the driver. Data signal.
- Step 3003 Generate a driving signal by the driver according to the second data signal and the second clock signal.
- the driver receives the second data signal and the second clock signal, and then generates a driving signal required by the display panel according to the second data signal and the second clock signal, thereby achieving perfect matching with the display panel, thereby improving The display quality of the display device.
- the driver includes a source driver.
- the source driver receives the second clock signal generated by the conversion unit and the second data signal generated by the synchronization unit, and then generates a driving signal according to the second clock signal and the second data signal. Since the second data signal and the second clock signal correspond to each other and are the data signals and clock signals actually needed by the driver, perfect matching with the display panel can be achieved, thereby improving the display quality of the display device.
- the timing adjuster is integrated with the driver, so that the influence of factors such as the circuit layout on the signal can be further reduced, and the driver can obtain the data signal and the clock signal that are actually needed by the driver, thereby facilitating the display quality of the display device.
- the driving circuit includes a timing controller, a timing controller and a driver, the timing controller outputs a first data signal and a first clock signal, and the timing adjuster adjusts the first data signal and the first
- the phases of the clock signals are used to generate mutually corresponding second data signals and second clock signals
- the driver generates drive signals based on the second data signals and the second clock signals.
- the timing regulator actively adjusts the first data signal and the first clock signal output by the timing controller to generate mutually corresponding second data signals and second clock signals actually needed by the driver, thereby implementing the display panel The perfect match, which in turn improves the display quality of the display device.
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Abstract
Description
Claims (17)
- 一种驱动电路,包括时序控制器、时序调节器和驱动器,所述时序调节器与所述时序控制器的输出端连接,所述时序调节器的输出端与所述驱动器连接;所述时序控制器用于输出第一数据信号和第一时钟信号;所述时序调节器用于调节所述第一数据信号和所述第一时钟信号的相位,以产生相互对应的第二数据信号和第二时钟信号;所述驱动器用于根据所述第二数据信号和所述第二时钟信号产生驱动信号。
- 根据权利要求1所述的驱动电路,其中,所述时序调节器包括转换单元和同步单元,所述转换单元的输入端与所述时序控制器连接,所述转换单元的第一输出端与所述同步单元的第一输入端连接,所述转换单元的第二输出端与所述驱动器连接,所述同步单元的第二输入端与所述时序控制器连接,所述同步单元的输出端与所述驱动器连接;所述转换单元用于调节所述第一时钟信号的相位以产生所述第二时钟信号;所述同步单元用于根据所述第二时钟信号对所述第一数据信号的相位进行调节,从而产生第二数据信号,所述第二数据信号与所述第二时钟信号具有预定的相位差。
- 根据权利要求2所述的驱动电路,其中,所述转换单元包括多个延迟电路。
- 根据权利要求3所述的驱动电路,其中,所述延迟电路包括反相器。
- 根据权利要求4所述的驱动电路,其中,所述反相器选自NMOS型反相器、PMOS型反相器和CMOS型反相器。
- 根据权利要求2所述的驱动电路,其中,所述同步单元包括D触发器。
- 根据权利要求1所述的驱动电路,其中,所述驱动器包括源极驱动器。
- 根据权利要求1所述的驱动电路,其中,所述驱动器与所述时序调节器集成设置。
- 一种显示装置,包括显示面板和权利要求1-8任一所述的驱动电路。
- 一种驱动电路的驱动方法,所述驱动电路包括时序控制器、时序调节器和驱动器,所述时序调节器与所述时序控制器的输出端连接,所述时序调节器的输出端与所述驱动器连接;所述驱动方法包括:通过所述时序控制器输出第一数据信号和第一时钟信号;通过所述时序调节器调节所述第一数据信号和所述第一时钟信号的相位,以产生相互对应的第二数据信号和第二时钟信号;根据所述第二数据信号和所述第二时钟信号,通过所述驱动器产生驱动信号。
- 根据权利要求10所述的驱动电路的驱动方法,其中,所述时序调节器包括转换单元和同步单元,所述转换单元的输入端与所述时序控制器连接,所述转换单元的第一输出端与所述同步单元的第一输入端连接,所述转换单元的第二输出端与所述驱动器连接,所述同步单元的第二输入端与所述时序控制器连接,所述同步单元的输出端与所述驱动器连接;其中通过所述时序调节器调节所述第一数据信号和所述第一时钟信号的相位,以产生相互对应的第二数据信号和第二时钟信号的步骤包括:通过所述转换单元调节所述第一时钟信号的相位,以产生所述第二时钟信号;根据所述第二时钟信号,通过所述同步单元对所述第一数据信号的相位进行调节,从而产生第二数据信号,所述第二数据信号与所述第二时钟信号具有预定的相位差。
- 根据权利要求11所述的驱动电路的驱动方法,其中,所述转换单元包括多个延迟电路。
- 根据权利要求12所述的驱动电路的驱动方法,其中,所述延迟电路包括反相器。
- 根据权利要求13所述的驱动电路的驱动方法,其中,所述反相器选自NMOS型反相器、PMOS型反相器和CMOS型反相器。
- 根据权利要求11所述的驱动电路的驱动方法,其中,所述同步单元包括D触发器。
- 根据权利要求10所述的驱动电路的驱动方法,其中,所述驱动器包括源极驱动器。
- 根据权利要求10所述的驱动电路的驱动方法,其中,所述驱动器与所述时序调节器集成设置。
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109787724A (zh) * | 2017-11-10 | 2019-05-21 | 京东方科技集团股份有限公司 | 传输参数配置信息的确定方法、装置及通信*** |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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US10783842B2 (en) | 2017-10-06 | 2020-09-22 | Japan Display Inc. | Display device |
JP2020030346A (ja) * | 2018-08-23 | 2020-02-27 | 堺ディスプレイプロダクト株式会社 | 表示装置及び表示装置におけるデータ伝送方法 |
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CN109493782A (zh) * | 2018-12-19 | 2019-03-19 | 惠科股份有限公司 | 信号校正控制器、信号校正控制方法及显示装置 |
CN111179804B (zh) * | 2020-01-13 | 2023-04-18 | 合肥鑫晟光电科技有限公司 | 一种时序控制器、显示装置、信号调整方法 |
CN111491162B (zh) * | 2020-05-19 | 2021-08-13 | 京东方科技集团股份有限公司 | 一种检测驱动电路、驱动方法及检测装置 |
CN115083363B (zh) * | 2022-06-15 | 2024-07-09 | 海宁奕斯伟集成电路设计有限公司 | 时序信号产生装置、方法及屏幕逻辑板和液晶显示器装置 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101042843A (zh) * | 2006-03-21 | 2007-09-26 | 联詠科技股份有限公司 | 可自动调整信号偏移的显示***及相关驱动方法 |
CN101089686A (zh) * | 2006-06-16 | 2007-12-19 | Lg.菲利浦Lcd株式会社 | 显示器件及其制造方法 |
CN101127199A (zh) * | 2007-09-06 | 2008-02-20 | 友达光电股份有限公司 | 输出无重叠扫描信号的栅极驱动器、液晶显示器及方法 |
CN101202027A (zh) * | 2006-12-13 | 2008-06-18 | 群康科技(深圳)有限公司 | 显示器屏幕显示控制***与控制方法 |
US20080266477A1 (en) * | 2007-04-27 | 2008-10-30 | Samsung Electronics Co., Ltd. | Gate driving circuit and liquid crystal display having the same |
US20080284768A1 (en) * | 2007-05-18 | 2008-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for driving liquid crystal display device |
CN104505017A (zh) * | 2015-01-26 | 2015-04-08 | 京东方科技集团股份有限公司 | 一种驱动电路及其驱动方法、显示装置 |
CN204375392U (zh) * | 2015-01-26 | 2015-06-03 | 京东方科技集团股份有限公司 | 一种驱动电路和显示装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002196732A (ja) * | 2000-04-27 | 2002-07-12 | Toshiba Corp | 表示装置、画像制御半導体装置、および表示装置の駆動方法 |
JP2002202760A (ja) * | 2000-12-27 | 2002-07-19 | Nec Corp | 液晶表示装置の駆動方法及び駆動回路 |
JP3779687B2 (ja) * | 2003-01-29 | 2006-05-31 | Necエレクトロニクス株式会社 | 表示装置駆動回路 |
KR100542768B1 (ko) * | 2003-06-21 | 2006-01-20 | 엘지.필립스 엘시디 주식회사 | 액정표시장치의 구동장치 |
JP4209430B2 (ja) * | 2006-05-25 | 2009-01-14 | パナソニック株式会社 | ドライバ制御装置 |
JP5211591B2 (ja) * | 2007-09-10 | 2013-06-12 | セイコーエプソン株式会社 | データ線駆動回路、電気光学装置及び電子機器 |
US8704805B2 (en) * | 2010-04-19 | 2014-04-22 | Himax Technologies Limited | System and method for handling image data transfer in a display driver |
-
2015
- 2015-01-26 CN CN201510038539.0A patent/CN104505017A/zh active Pending
- 2015-09-16 US US14/908,327 patent/US20160372084A1/en not_active Abandoned
- 2015-09-16 WO PCT/CN2015/089759 patent/WO2016119467A1/zh active Application Filing
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101042843A (zh) * | 2006-03-21 | 2007-09-26 | 联詠科技股份有限公司 | 可自动调整信号偏移的显示***及相关驱动方法 |
CN101089686A (zh) * | 2006-06-16 | 2007-12-19 | Lg.菲利浦Lcd株式会社 | 显示器件及其制造方法 |
CN101202027A (zh) * | 2006-12-13 | 2008-06-18 | 群康科技(深圳)有限公司 | 显示器屏幕显示控制***与控制方法 |
US20080266477A1 (en) * | 2007-04-27 | 2008-10-30 | Samsung Electronics Co., Ltd. | Gate driving circuit and liquid crystal display having the same |
US20080284768A1 (en) * | 2007-05-18 | 2008-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for driving liquid crystal display device |
CN101127199A (zh) * | 2007-09-06 | 2008-02-20 | 友达光电股份有限公司 | 输出无重叠扫描信号的栅极驱动器、液晶显示器及方法 |
CN104505017A (zh) * | 2015-01-26 | 2015-04-08 | 京东方科技集团股份有限公司 | 一种驱动电路及其驱动方法、显示装置 |
CN204375392U (zh) * | 2015-01-26 | 2015-06-03 | 京东方科技集团股份有限公司 | 一种驱动电路和显示装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109787724A (zh) * | 2017-11-10 | 2019-05-21 | 京东方科技集团股份有限公司 | 传输参数配置信息的确定方法、装置及通信*** |
CN109787724B (zh) * | 2017-11-10 | 2021-12-14 | 京东方科技集团股份有限公司 | 传输参数配置信息的确定方法、装置及通信*** |
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US20160372084A1 (en) | 2016-12-22 |
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