WO2016065850A1 - Goa单元及驱动方法、goa电路和显示装置 - Google Patents

Goa单元及驱动方法、goa电路和显示装置 Download PDF

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Publication number
WO2016065850A1
WO2016065850A1 PCT/CN2015/076285 CN2015076285W WO2016065850A1 WO 2016065850 A1 WO2016065850 A1 WO 2016065850A1 CN 2015076285 W CN2015076285 W CN 2015076285W WO 2016065850 A1 WO2016065850 A1 WO 2016065850A1
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Prior art keywords
node
transistor
level
signal
terminal
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PCT/CN2015/076285
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English (en)
French (fr)
Inventor
李付强
胡理科
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to EP15787122.9A priority Critical patent/EP3214616B1/en
Priority to US14/890,345 priority patent/US9530345B2/en
Publication of WO2016065850A1 publication Critical patent/WO2016065850A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to the field of display manufacturing, and in particular, to a GOA unit and a driving method, a GOA circuit, and a display device.
  • GOA Gate Driver on Array
  • the GOA technology is used to integrate the gate switching circuit on the array substrate of the display panel, so that the gate driving integrated circuit portion can be omitted to reduce the product cost from both the material cost and the manufacturing process.
  • Such a gate switching circuit integrated on an array substrate using GOA technology is also referred to as a GOA circuit or a shift register circuit.
  • the GOA circuit includes a plurality of GOA units, each of which includes a plurality of thin film transistors (TFTs), wherein each GOA unit corresponds to one gate line, and the output of each GOA unit is connected to a gate line. Since the GOA circuit requires a large-scale integrated circuit IC implementation, how to control the scale of the IC while ensuring the performance of the GOA circuit becomes the development direction of the GOA circuit.
  • TFTs thin film transistors
  • the embodiment of the invention provides a GOA unit and a driving method, a GOA circuit and a display device, which can reduce the scale of the IC while ensuring the performance of the GOA circuit, thereby reducing the production cost.
  • a GOA unit including a first node control unit, a second node control unit, and an output unit; wherein the first node control unit is connected to the first input end, the second input end, and the first a level terminal, a second level terminal, a first node, a second node, and a fourth level terminal, configured to pull the level of the first node and the signal of the first level terminal under the control of the signal of the first input end Or, for controlling the level of the first node and the signal of the second level end under the control of the signal of the second input; the second node control unit is connected to the first a flat end, the second level end, a third level end, the fourth level end, a second clock signal end, and a third clock signal end, the first node and the second node, Controlling the first level terminal, the second level terminal, the second clock signal terminal, and the third clock signal terminal The voltage of the two nodes is aligned with the signal of the third level terminal,
  • the first node control unit includes: a first transistor, a gate of the first transistor is connected to the first input end, and a source of the first transistor is connected to the first level end a drain of the first transistor connected to the first node, for aligning a voltage of the first node with the first level terminal under control of a signal of the first input terminal; and a second transistor, a gate of the second transistor is connected to the second input end, a source of the second transistor is connected to the second level terminal, and a drain of the second transistor is connected to the first node, The voltage of the first node is aligned with the second level terminal under the control of the signal of the second input.
  • the first node control unit is further configured to: under the control of the second node, level the level of the first node and the signal of the fourth level end, and the first node
  • the control unit further includes a sixth transistor, a gate of the sixth transistor is connected to the second node, a source of the sixth transistor is connected to the first node, and a drain of the sixth transistor is connected to the first a four-level terminal for aligning the voltage of the first node with the fourth level terminal under the control of a signal of the second node.
  • the output unit includes: a third transistor, a gate of the third transistor is connected to the first node, a source of the third transistor is connected to the first clock signal end, and the second a drain connected to the output terminal for outputting a signal of the first clock signal terminal at the output terminal under control of the first node; and a fourth transistor having a gate connected to the fourth transistor a second node, a source of the fourth transistor is coupled to the output terminal, and a drain of the fourth transistor is coupled to the fourth level terminal for controlling the signal of the second node The voltage at the output is aligned with the fourth level terminal.
  • the output unit further includes: a second capacitor, a first pole of the second capacitor is connected to the first node, and a second pole of the second capacitor is connected to the output end, for storing The voltage of the first node is described.
  • the second node control unit includes: a fifth transistor, a gate of the fifth transistor is connected to the first node, and a source of the fifth transistor is connected to the second node, where a drain of the fifth transistor is connected to the fourth level terminal for aligning a voltage of the second node with the fourth level terminal under control of a signal of the first node; a seventh transistor, a gate of the seventh transistor is connected to the second clock signal end, a source of the seventh transistor is connected to the first level terminal, and an eighth transistor is connected to a gate of the eighth transistor End, the drain of the eighth transistor is connected to the second level terminal, the source of the eighth transistor is connected to the drain of the seventh transistor; and the ninth transistor is connected to the gate of the ninth transistor a drain of the seventh transistor, a source of the ninth transistor is connected to the third level terminal, and a drain of the ninth transistor is connected to the second node.
  • the second node control unit includes: a fifth transistor, a gate of the fifth transistor is connected to the first node, and a source of the fifth transistor is connected to the second node, where a drain of the fifth transistor is connected to the fourth level terminal for aligning a voltage of the second node with the fourth level terminal under control of a signal of the first node; a seventh transistor, a gate of the seventh transistor is connected to the first level terminal, a source of the seventh transistor is connected to the second clock signal terminal, and an eighth transistor is connected to a gate of the eighth transistor a drain of the eighth transistor is connected to the third clock signal terminal, a source of the eighth transistor is connected to a drain of the seventh transistor, and a ninth transistor is connected to a gate of the ninth transistor a drain of the seventh transistor, a source of the ninth transistor is connected to the third level terminal, and a drain of the ninth transistor is connected to the second node.
  • the second node control unit further includes: a first capacitor, a first pole of the first capacitor is connected to the second node, and a second pole of the first capacitor is connected to the fourth level end
  • the first capacitor is used to maintain the voltage of the second node.
  • a method for driving a GOA unit comprising: in a first stage, the first node control unit aligns the voltage of the first node with the first level end under the control of the signal of the first input end And the second node control unit aligns the voltage of the second node with the fourth level end under the control of the signal of the first node; in the second stage, the output unit sets the first one under the control of the first node a signal of the clock signal end is output at the output end, and the second node control unit pulls the voltage of the second node and the fourth level end under the control of the signal of the first node; in the third stage, the second node control unit is The voltage of the second node is aligned with the signal of the third level terminal under the control of the first level terminal, the second level terminal, the second clock signal terminal and the third clock signal terminal, and the first node control unit is used for Leveling the level of the first node with a signal of the second level terminal under signal control of the
  • the first node control unit is further configured to: compare the level of the first node with the first node under the control of the second node The signal at the four-level end is pulled.
  • a method for driving a GOA unit comprising: in a first stage, the first node control unit pulls the voltage of the first node and the second level end under the control of the signal of the second input end And the second node control unit aligns the voltage of the second node with the fourth level end under the control of the signal of the first node; in the second stage, the output unit sets the first one under the control of the first node a signal of the clock signal end is output at the output end, and the second node control unit pulls the voltage of the second node and the fourth level end under the control of the signal of the first node; in the third stage, the second node control unit is The voltage of the second node is aligned with the signal of the third level terminal under the control of the first level terminal, the second level terminal, the second clock signal terminal and the third clock signal terminal, and the first node control unit is used for Leveling the first node with a signal of the first level terminal under control of a signal of the
  • the first node control unit is further configured to: at a level of the first node and a fourth level end, under the control of the second node The signal is pulled.
  • a GOA circuit comprising at least three levels of GOA units cascaded, wherein the GOA unit is any one of the above GOA units; wherein, in addition to the first level GOA unit and the last level GOA unit The output end of each level of the GOA unit is connected to the second input end of the upper stage GOA unit and the first input end of the next stage GOA unit; wherein the output end of the first stage GOA unit is connected to the next stage GOA unit a first input end, the output end of the last stage GOA unit is connected to a second input end of the upper level GOA unit; the first input end of the first stage GOA unit inputs a frame start signal, or the last A first input of the primary GOA unit inputs a frame start signal.
  • a display device comprising the above GOA circuit.
  • control of the level of the first node is implemented by the first node control unit, and the level of the second node is controlled by the second node control unit, and the output unit of the second node is used by the first node and the second node.
  • Controlling the output of the gate drive signal at the output of the output unit can reduce the size of the IC while ensuring the performance of the GOA, thereby reducing the production cost.
  • FIG. 1 is a schematic structural diagram of a GOA circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram showing a timing state of a system clock signal of the GOA circuit shown in FIG. 1 according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a GOA unit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a GOA unit according to another embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a GOA unit according to another embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a GOA unit according to still another embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a GOA unit according to another embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a timing state of a driving signal of a GOA unit according to an embodiment of the present disclosure
  • FIG. 9 is a schematic structural diagram of a GOA unit according to another embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a GOA unit according to still another embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of a GOA unit according to another embodiment of the present invention.
  • FIG. 12 is a schematic structural diagram of a GOA unit according to another embodiment of the present invention.
  • FIG. 13 is a schematic flowchart diagram of a driving method of a GOA unit according to an embodiment of the present disclosure
  • FIG. 14 is a schematic flow chart of a driving method of a GOA unit according to another embodiment of the present invention.
  • the switching transistor and the driving transistor used in all embodiments of the present invention may each be a thin film crystal Tube or FET or other devices with the same characteristics. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, in order to distinguish the two poles of the transistor except the gate, one of the poles is referred to as a source and the other pole is referred to as a drain. According to the form in the drawing, the middle end of the switching transistor is a gate, the signal input end is a drain, and the output end is a source.
  • the switching transistor used in the embodiment of the present invention includes two types of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level; the N-type switch The transistor is turned on when the gate is at a high level, and is turned off when the gate is at a low level; and the driving transistor includes a P-type driving transistor and an N-type driving transistor, wherein the P-type driving transistor has a low gate voltage (the gate voltage is less than Source voltage) and the absolute value of the gate-source voltage difference is greater than the threshold voltage in an amplified state or a saturated state; wherein the N-type driving transistor is at a high level of the gate voltage (gate voltage is greater than the source voltage) and the gate When the absolute value of the voltage difference of the pole source is greater than the threshold voltage, it is in an amplified state or a saturated state.
  • the P-type driving transistor has a low gate voltage (the gate voltage
  • an embodiment of the present invention provides a GOA circuit, including at least three levels of GOA units that are cascaded.
  • each stage GOA unit is connected to the second input end of the upper level GOA unit and the first input end of the next stage GOA unit;
  • the output end of the first stage GOA unit is connected to the first input end of the next stage GOA unit, and the output end of the last stage GOA unit is connected to the second input end of the upper level GOA unit;
  • An input terminal inputs a frame start signal, or a first input end of the last stage GOA unit inputs a frame start signal.
  • the GOA circuit includes a plurality of cascaded GOA units, wherein an output terminal OUTPUT of the GOA unit SR1 is connected to a gate line OG1, and simultaneously connected to a first input terminal IN of the GOA unit SR2; an output of the GOA unit SR2 The terminal OUTPUT is connected to a gate line OG2, and is simultaneously connected to the second input terminal INPUT of the upper stage GOA unit SR1 and the first input terminal IN of the next stage GOA unit SR3; the other GOA units are connected in accordance with this method.
  • Each GOA unit has a first clock signal terminal CLK1, a second clock signal terminal CLK2, a third clock signal terminal CLK3 and four level input terminals: a first level terminal CN, a second level terminal CNB, The three-level terminal VGH and the fourth level terminal VGL.
  • a clock signal is supplied to three clock signal terminals CLK1-3 of each GOA unit through four system clock signals Clock1-4, wherein CK1 of SR1 is input to the first clock signal Clock1, and CK2 input of SR1 is second.
  • Clock 1-4 is a clock signal with a duty ratio of 25%, and each period of Clock 1-4 includes a single pulse, wherein the rising edge of Clock1 is one pulse width ahead of the rising edge of Clock2.
  • the rising edge of Clock2 is one pulse width ahead of the rising edge of Clock3; the rising edge of Clock3 is one pulse width ahead of the rising edge of Clock4, and each of the above pulses is taken with the same pulse width as an example. Description.
  • the GOA circuit provided by the embodiment of the present invention can implement bidirectional scanning.
  • the first GOA unit is SR1
  • the first input terminal IN of the GOA unit SR1 inputs an activation pulse signal, optionally as a frame start signal STV, and the frame start signal STV is in a frame.
  • the time period is a single pulse signal.
  • FIG. 2 the relationship between the STV single pulse signal and the system clock signal is also shown, wherein the rising edge of the STV single pulse signal is synchronized with the rising edge of the first pulse of the system clock signal Clock4, and the last GOA unit SRn
  • the second input INPUT is idle.
  • an activation pulse signal is input at the second input INPUT of the last GOA unit SRn, at which time the first input IN of the GOA unit SR1 is idle.
  • an embodiment of the present invention provides a GOA unit used in the above GOA circuit.
  • a GOA unit including a first node control unit 31, a second node control unit 32, and an output unit. 33.
  • the first node control unit 31 is connected to the first input terminal IN, the second input terminal INPUT, the first level terminal CN, the second level terminal CNB, the first node PU, the second node PD, and the fourth level terminal VGL; Leveling the level of the first node PU with the signal of the first level terminal CN under the control of the signal of the first input terminal IN, or for controlling under the signal of the second input terminal INPUT The level of the first node PU is aligned with the signal of the second level terminal CNB.
  • the first node control unit may be further configured to align the level of the first node PU with the signal of the fourth level terminal VGL under the control of the second node PD.
  • the second node control unit 32 is connected to the first level terminal CN, the second level terminal CNB, the third level terminal VGH, the fourth level terminal VGL, the second clock signal terminal CK2, and the third clock signal.
  • a terminal CK3, the first node PU and the second node PD; for the first level terminal CN, the second level terminal CNB, the second clock signal terminal CK2 and the third clock signal end Controlling, by the control of CK3, the voltage of the second node PD and the signal of the third level terminal VGH, or for controlling the voltage of the second node PD under the control of the first node PU
  • the fourth level terminal VGL is pulled.
  • the output unit 33 is connected to the output terminal OUTPUT, the first clock signal terminal CK1, the first node PU, the second node PD and the fourth level terminal VGL; for controlling at the first node PU And outputting the signal of the first clock signal terminal CK1 at the output terminal OUTPUT, or for controlling the level of the output terminal OUTPUT and the fourth level terminal VGL under the control of the second node PD Lacy.
  • the control of the first node PU voltage is implemented by the first node control unit 31, and the control of the second node PD voltage is implemented by the second node control unit 32, and the output is performed by the first node PU and the second node PD.
  • the control of the unit 33 outputs a gate drive signal at the output terminal OUTPUT of the output unit 33, which can reduce the scale of the IC while ensuring the performance of the GOA unit, thereby reducing the production cost.
  • the first node control unit 31 includes: a first transistor T1 and a second transistor T2.
  • a gate of the first transistor T1 is connected to the first input terminal IN, a source of the first transistor T1 is connected to the first level terminal CN, and a drain of the first transistor T1 is connected to the first a node PU; for aligning the voltage of the first node PU with the first level terminal CN under the control of the signal of the first input terminal IN.
  • a gate of the second transistor T2 is connected to the second input terminal INPUT, a source of the second transistor T2 is connected to the second level terminal CNB, and a drain of the second transistor T2 is connected to the first a node PU; for aligning the voltage of the first node PU with the second level terminal CNB under the control of the signal of the second input terminal INPUT.
  • the first node control unit 31 may further include: a sixth transistor T6. a gate of the sixth transistor T6 is connected to the second node PD, a source of the sixth transistor T6 is connected to the first node PU, and a drain of the sixth transistor T6 is connected to the fourth level terminal. VGL; for aligning the voltage of the first node PU with the fourth level terminal VGL under the control of the signal of the second node PD.
  • the output unit 33 includes a third transistor T3 and a fourth transistor T4.
  • a gate of the third transistor T3 is connected to the first node PU, a source of the third transistor T3 is connected to the first clock signal terminal CK1, and a drain of the second transistor T2 is connected to an output terminal OUTPUT. And a signal for outputting the first clock signal terminal CK1 at the output terminal OUTPUT under the control of the first node PU.
  • a gate of the fourth transistor T4 is connected to the second node PD, a source of the fourth transistor T4 is connected to the output terminal OUTPUT, and a drain of the fourth transistor T4 is connected to the fourth level terminal VGL And for aligning the voltage of the output terminal OUTPUT with the fourth level terminal VGL under the control of the signal of the second node PD.
  • the output unit 33 further includes: a second capacitor C2.
  • the first pole of the second capacitor C2 is connected to the first node PU, and the second pole of the second capacitor C2 is connected to the output terminal OUTPUT for storing the voltage of the first node PU.
  • the second node control unit 32 includes a fifth transistor T5, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.
  • a gate of the fifth transistor T5 is connected to the first node PU, a source of the fifth transistor T5 is connected to the second node PD, and a drain of the fifth transistor T5 is connected to the fourth level terminal.
  • VGL for aligning the voltage of the second node PD with the fourth level terminal VGL under the control of the signal of the first node PU.
  • the gate of the seventh transistor T7 is connected to the second clock signal terminal CK2, and the source of the seventh transistor T7 is connected to the first level terminal CN.
  • a gate of the eighth transistor T8 is connected to the third clock signal terminal CK3, a drain of the eighth transistor T8 is connected to the second level terminal CNB, and a source of the eighth transistor T8 is connected to the first The drain of the seven transistor T7.
  • a gate of the ninth transistor T9 is connected to a drain of the seventh transistor T7, a source of the ninth transistor T9 is connected to the third level terminal VGH, and a drain of the ninth transistor T9 is connected to the The second node PD.
  • the seventh transistor T7 is configured to align a gate voltage of the ninth transistor T9 with the first voltage terminal CN
  • the eighth transistor T8 is configured to compare a gate voltage of the ninth transistor T9 with The second voltage terminal CNB is aligned
  • the ninth transistor T9 is configured to align the voltage of the second node PD with the third level terminal VGH under the control of its gate voltage.
  • the second node control unit 32 further includes: a first capacitor C1.
  • a first pole of the first capacitor C1 is connected to the second node PD, a second pole of the first capacitor C1 is connected to the fourth level terminal VGL, and the first capacitor C1 is used to maintain the second node PD Voltage.
  • the GOA unit can also include both the first capacitor C1 and the second capacitor C2.
  • the GOA cells provided in Figures 4-7 each contain 9 transistors, which significantly reduces the number of transistors compared to the prior art 12T1C (12 transistors with 1 capacitor structure), thereby saving production costs.
  • the driving method of the GOA unit shown in FIG. 7 provided by the embodiment of the present invention is described with reference to the timing signal state diagram shown in FIG. 8.
  • the CK1 input Clock1, the CK2 input Clock2, the CK3 input Clock4, and all the transistors are high.
  • CN and CNB are signals for controlling forward and backward scanning; when CN is high and CNB is low, GOA unit is forward scanning, CN is low level, and CNB is high level when GOA is In the reverse scan, VGL is a negative low level and VGH is a positive high level.
  • Figure 8 shows the corresponding signal timing.
  • CN is high and CNB is low.
  • IN is high level
  • Clock1 and Clock2 are low level
  • Clock4 is high level
  • T1 is turned on
  • CN charges C2 through T1
  • PU becomes high level
  • T5 turns on
  • the PD node is pulled low
  • T8 is turned on
  • CNB low level control T9 is turned off.
  • Clock2 is high level
  • Clock1 and Clock4 are low level
  • T7 is turned on
  • CN charges T9 gate through T7 to make T9 turn on
  • VGH charges C1 through T9, so that PD is pulled High is high, thus controlling T4 and T6 to simultaneously discharge to C2, while INPUT is High level, T2 is also turned on to discharge C2, and OUTPUT is pulled low.
  • the function of the first capacitor C1 is to maintain the high level of the PD after the OUTPUT output, although in the absence of the first capacitor C1 (as shown in FIG. 3), the parasitic capacitance of the transistor T5 can maintain the high level of the PD. However, in the presence of C1, the noise at the PD node can be greatly reduced. Similarly, the circuit can also maintain the level of the PU node by the parasitic capacitance of the transistor T3, without setting the capacitor C2.
  • the above is an example of forward scanning. In the reverse scanning, only the CN is adjusted to a low level and the CNB is adjusted to a high level. The principle is similar and will not be described again.
  • another GOA unit provided by the embodiment of the present invention includes a first node control unit 31, a second node control unit 32, and an output unit 33.
  • the first node control unit 31 includes three transistors T1, T2, and T6, and the connection relationship of T1, T2, and T6 is referred to the corresponding embodiment of FIG. 4-7, and details are not described herein again.
  • the output unit 33 includes transistors T3 and T4, wherein the connection relationship between T3 and T4 is referred to the corresponding embodiment of FIG. 4-7, and details are not described herein again.
  • the output unit 33 may further include a second capacitor C2, which is the same as the embodiment corresponding to FIGS. 5 and 7, and details are not described herein again.
  • the second node control unit 32 includes a fifth transistor T5, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.
  • a gate of the fifth transistor T5 is connected to the first node PU, a source of the fifth transistor T5 is connected to the second node PD, and a drain of the fifth transistor T5 is connected to the fourth level terminal.
  • VGL for aligning the voltage of the second node PD with the fourth level terminal VGL under the control of the signal of the first node PU.
  • the gate of the seventh transistor T7 is connected to the first level terminal CN, and the source of the seventh transistor T7 is connected to the second clock signal terminal CK2.
  • a gate of the eighth transistor T8 is connected to the second level terminal CNB, a drain of the eighth transistor T8 is connected to the third clock signal terminal CK3, and a source of the eighth transistor T8 is connected to the first The drain of the seven transistor T7.
  • a gate of the ninth transistor T9 is connected to a drain of the seventh transistor T7, a source of the ninth transistor T9 is connected to the third level terminal VGH, and a drain of the ninth transistor T9 is connected to the The second node PD.
  • the seventh transistor T7 is for aligning the gate voltage of the ninth transistor T9 with the second clock signal terminal CK2
  • the eighth transistor T8 is for using the gate voltage of the ninth transistor T9 Aligned with the third clock signal terminal CK3
  • the ninth transistor T9 is used for its gate voltage
  • the voltage of the second node PD is aligned with the third level terminal VGH under the control of the control.
  • the second node control unit 32 further includes a first capacitor C1, the first pole of the first capacitor C1 is connected to the second node PD, and the first capacitor C1 is The second pole is connected to the fourth level terminal VGL, and the first capacitor C1 is used to maintain the voltage of the second node PD.
  • the GOA unit can also include both the first capacitor C1 and the second capacitor C2.
  • the GOA cells provided in Figures 9-12 each contain 9 transistors, which significantly reduces the number of transistors compared to the prior art 12T1C (12 transistors with 1 capacitor structure), thereby saving production costs.
  • the driving method of the GOA unit shown in FIG. 12 provided by the embodiment of the present invention is described with reference to the timing signal state diagram shown in FIG. 8.
  • the CK1 input Clock1, the CK2 input Clock2, and the CK3 input Clock4 are all high levels.
  • CN and CNB are signals for controlling forward and backward scanning; when CN is high and CNB is low, GOA unit is forward scanning, CN is low level, and CNB is high level when GOA is In the reverse scan, VGL is a negative low level and VGH is a positive high level.
  • Figure 8 shows the corresponding signal timing.
  • CN is high and CNB is low.
  • IN is high level
  • Clock1 and Clock2 are low level
  • Clock4 is high level
  • T1 is turned on
  • CN charges C2 through T1
  • PU becomes high level
  • T5 turns on
  • the PD node is pulled low
  • T8 is off
  • T7 is on
  • Clock2 is low to control T9 off.
  • T7 in the GOA unit shown in Figure 9-12 is in the three states, and T8 is in the off state in all three phases. .
  • the role of the first capacitor C1 is to maintain the PD high level after the OUTPUT output, although In the absence of the first capacitor C1 (as shown in FIG. 3), the parasitic capacitance of the transistor T5 can also maintain the high level of the PD, whereas in the presence of C1, the noise at the PD node can be greatly reduced. Similarly, the circuit can also maintain the level of the PU node by the parasitic capacitance of the transistor T3, without setting the capacitor C2.
  • the above is an example of forward scanning. In the reverse scanning, only the CN is adjusted to a low level and the CNB is adjusted to a high level. At this time, the T8 in the GOA unit shown in FIG. 9-12 is in three stages. The middle is in the on state, and T7 is in the cutoff state in all three phases. The working principle of other parts of the GOA unit is similar to the above embodiment and will not be described again.
  • the types of the respective switching transistors are not limited. In the above embodiment, all the transistors are turned on as a high-level example for description. When adjusting the type of the transistor, only the corresponding signal needs to be adjusted. The level signal applied by the line or the signal line may be used.
  • the driving method of the GOA unit provided by the embodiment of the present invention is taken as a standard, and the person skilled in the art bases on the GOA unit and the driving method provided by the embodiment of the present invention. Any combination that can be easily conceived and realized is within the scope of the invention.
  • the embodiment of the present invention further provides a driving method of the foregoing GOA unit, where the driving method is applied to a forward scanning process, including the following steps.
  • the first node control unit 31 under the control of the signal at the first input, aligns the voltage of the first node with the first level terminal; and the signal of the second node control unit 32 at the first node Controlling, the voltage of the second node is aligned with the fourth level end;
  • the output unit 33 outputs the signal of the first clock signal end at the output end under the control of the first node; the second node control unit 32 will control under the signal of the first node The voltage of the second node is aligned with the fourth level terminal;
  • the second node control unit 32 controls the voltage of the second node and the third level end under the control of the first level terminal, the second level terminal, the second clock signal terminal, and the third clock signal terminal.
  • the first node control unit 31 is further configured to align the level of the first node with the signal of the second level end under the signal control of the second input end; the output unit 33 for aligning the level of the output with the fourth level terminal under the control of the second node.
  • the first node control unit 31 is further configured to: align the level of the first node with the signal of the fourth level end under the control of the second node .
  • the control of the first node voltage is implemented by the first node control unit
  • the control of the second node voltage is implemented by the second node control unit
  • the output unit is controlled by the first node and the second node in the output unit.
  • Output output gate drive signal which can guarantee GOA Road performance reduces the size of the IC while reducing production costs.
  • the first node control unit 31 includes: a first transistor, a second transistor, and a sixth transistor.
  • the specific operation of the driving method in each stage is as follows.
  • the first transistor is in an on state
  • the second transistor is in an off state
  • the sixth transistor is in an off state.
  • the first transistor is in an off state
  • the second transistor is in an off state
  • the sixth transistor is in an off state.
  • the first transistor is in an off state
  • the second transistor is in an on state
  • the sixth transistor is in an on state.
  • the output unit includes: a third transistor and a fourth transistor.
  • the specific operation of the driving method in each stage is as follows.
  • the third transistor is in an off state and the fourth transistor is in an off state.
  • the third transistor is in an on state and the fourth transistor is in an off state.
  • the third transistor is in an off state, and the fourth transistor is in an on state.
  • the output unit includes: a fifth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; and a connection relationship between the fifth transistor, the seventh transistor, the eighth transistor, and the ninth transistor is the above FIG. 7
  • the specific operation of the driving method in each stage is as follows.
  • the fifth transistor is in an on state
  • the seventh transistor is in an off state
  • the eighth transistor is in an on state
  • the ninth transistor is in an off state.
  • the fifth transistor is in an on state
  • the seventh transistor is in an off state
  • the eighth transistor is in an off state
  • the ninth transistor is in an off state.
  • the fifth transistor is in an off state
  • the seventh transistor is in an on state
  • the eighth transistor is in an off state
  • the ninth transistor is in an on state.
  • the output unit includes: a fifth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; and a connection relationship of the fifth transistor, the seventh transistor, the eighth transistor, and the ninth transistor is the above FIG. 9 12
  • the specific operation of the driving method in each stage is as follows.
  • the fifth transistor is in an on state
  • the seventh transistor is in an on state
  • the eighth transistor is in an off state
  • the ninth transistor is in an off state.
  • the fifth transistor is in an on state
  • the seventh transistor is in an on state
  • the eighth transistor is in an off state
  • the ninth transistor is in an off state.
  • the fifth transistor is in an off state
  • the seventh transistor is in an on state
  • the eighth transistor is in an off state
  • the ninth transistor is in an on state.
  • the embodiment of the present invention further provides a driving method of the foregoing GOA unit, and the driving method is applied to a reverse scanning process, and includes the following steps.
  • the first node control unit 31 under the control of the signal of the second input, pulls the voltage of the first node with the second level end; and the signal of the second node control unit 32 at the first node Controlling the voltage of the second node to be aligned with the fourth level terminal.
  • the output unit 33 outputs the signal of the first clock signal end at the output end under the control of the first node; the second node control unit 32 will control under the signal of the first node The voltage of the second node is aligned with the fourth level terminal.
  • the second node control unit 32 controls the voltage of the second node and the third level terminal under the control of the first level terminal, the second level terminal, the second clock signal terminal, and the third clock signal terminal.
  • the first node control unit 31 is configured to align the level of the first node with the signal of the fourth level end under the control of the second node; the first node controls The unit 31 is further configured to align the level of the first node with the signal of the first level end under the signal control of the first input end; the output unit 33 is used at the second node Controlling the level of the output terminal to be aligned with the fourth level terminal.
  • the control of the first node voltage is implemented by the first node control unit
  • the control of the second node voltage is implemented by the second node control unit
  • the output unit is controlled by the first node and the second node in the output unit.
  • the output terminal outputs a gate drive signal, which can reduce the size of the IC while ensuring the performance of the GOA circuit, thereby reducing the production cost.
  • the first node control unit includes: a first transistor, a second transistor, and a sixth transistor.
  • the specific operation of the driving method in each stage is as follows.
  • the first transistor is in an off state
  • the second transistor is in an on state
  • the sixth transistor is in an off state
  • the first transistor is in an off state
  • the second transistor is in an off state
  • the sixth transistor is in an off state.
  • the first transistor is in an on state
  • the second transistor is in an off state
  • the sixth transistor is in an on state
  • the output unit includes: a third transistor and a fourth transistor.
  • the specific operation of the driving method in each stage is as follows.
  • the third transistor is in an off state
  • the fourth transistor is in an off state
  • the third transistor is in an on state, and the fourth transistor is in an off state.
  • the third transistor is in an off state, and the fourth transistor is in an on state.
  • the output unit includes: a fifth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; and a connection relationship between the fifth transistor, the seventh transistor, the eighth transistor, and the ninth transistor is the above FIG. 7
  • the specific operation of the driving method in each stage is as follows.
  • the fifth transistor is in an on state
  • the seventh transistor is in an off state
  • the eighth transistor is in an on state
  • the ninth transistor is in an off state.
  • the fifth transistor is in an on state
  • the seventh transistor is in an off state
  • the eighth transistor is in an off state
  • the ninth transistor is in an off state.
  • the fifth transistor is in an off state
  • the seventh transistor is in an on state
  • the eighth transistor is in an off state
  • the ninth transistor is in an on state.
  • the output unit includes: a fifth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; and a connection relationship of the fifth transistor, the seventh transistor, the eighth transistor, and the ninth transistor is the above FIG. 9 12
  • the specific operation of the driving method in each stage is as follows.
  • the fifth transistor is in an on state
  • the seventh transistor is in an off state
  • the eighth transistor is in an on state
  • the fifth transistor is in an on state
  • the seventh transistor is in an off state
  • the eighth transistor is in an on state
  • the fifth transistor is in an off state
  • the seventh transistor is in an off state
  • the eighth transistor is in an on state
  • the ninth transistor is in an on state.
  • Embodiments of the present invention provide a display device including: a display circuit.
  • the display circuit includes a pixel array, a first gate driving unit and a second gate driving unit, each of the first gate driving unit and the second gate driving unit comprising a GOA circuit provided by an embodiment of the present invention, the GOA circuit comprising a stage At least three levels of the GOA unit provided by the embodiments of the present invention.
  • the display device can be a display device such as an electronic paper, a mobile phone, a television, a digital photo frame, or the like.

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Abstract

提供了一种GOA单元，包括第一节点控制单元（31），第二节点控制单元（32）和输出单元（33）；所述第一节点控制单元（31）用于在第一输入端（IN）的信号控制下将第一节点（PU）的电平与第一电平端（CN）的信号拉齐，或用于在第二输入端（INPUT）信号的控制下将第一节点（PU）的电平与第二电平端（CNB）信号拉齐；所述第二节点控制单元（32）用于在第一电平端（CN）、第二电平端（CNB）、第二时钟信号端（CK2）和第三时钟信号端（CK3）的控制下将第二节点（PD）的电压与第三电平端（VGH）信号拉齐，或用于在第一节点（PU）的控制下将第二节点（PD）的电压与第四电平端（VGL）拉齐；所述输出单元（33）用于在第一节点（PU）的控制下将第一时钟信号端（CK1）的信号在输出端（OUTPUT）输出，或用于在第二节点（PD）的控制下将输出端（OUTPUT）的电平与第四电平端（VGL）拉齐。还提供了一种GOA电路、显示装置以及一种GOA驱动方法。

Description

GOA单元及驱动方法、GOA电路和显示装置 技术领域
本发明涉及显示器制造领域，尤其涉及一种GOA单元及驱动方法、GOA电路和显示装置。
背景技术
近些年来显示器的发展呈现出了高集成度，低成本的发展趋势。其中一项非常重要的技术就是阵列基板行驱动GOA(Gate Driver on Array)技术的量产化实现。利用GOA技术将栅极开关电路集成在显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。这种利用GOA技术集成在阵列基板上的栅极开关电路也称为GOA电路或移位寄存器电路。
GOA电路包括若干个GOA单元，每个GOA单元包含若干薄膜晶体管TFT(Thin Film Transistor)，其中，每一GOA单元对应一条栅线，具体的每一GOA单元的输出端连接一条栅线。由于GOA电路需要大规模的集成电路IC实现，因此如何在保证GOA电路性能的同时控制IC的规模成为GOA电路的发展方向。
发明内容
本发明实施例提供一种GOA单元及驱动方法、GOA电路和显示装置，能够在保证GOA电路性能的同时减小IC的规模，从而降低了生产成本。
根据本发明第一方面，提供一种GOA单元，包括第一节点控制单元，第二节点控制单元和输出单元；其中，所述第一节点控制单元连接第一输入端、第二输入端、第一电平端、第二电平端、第一节点、第二节点和第四电平端，用于在第一输入端的信号的控制下将第一节点的电平与所述第一电平端的信号拉齐，或者用于在所述第二输入端的信号的控制下将所述第一节点的电平与所述第二电平端的信号拉齐；所述第二节点控制单元连接所述第一电平端、所述第二电平端、第三电平端、所述第四电平端、第二时钟信号端、第三时钟信号端，所述第一节点和所述第二节点，用于在所述第一电平端、所述第二电平端、所述第二时钟信号端和第三时钟信号端的控制下将所述第 二节点的电压与所述第三电平端的信号拉齐，或者用于在所述第一节点的控制下将所述第二节点的电压与所述第四电平端拉齐；所述输出单元连接输出端、第一时钟信号端、所述第一节点，所述第二节点和所述第四电平端，用于在所述第一节点的控制下将所述第一时钟信号端的信号在所述输出端输出，或者用于在所述第二节点的控制下将所述输出端的电平与所述第四电平端拉齐。
可选的，所述第一节点控制单元包括：第一晶体管，所述第一晶体管的栅极连接所述第一输入端，所述第一晶体管的源极连接所述第一电平端，所述第一晶体管的漏极连接所述第一节点，用于在所述第一输入端的信号的控制下将所述第一节点的电压与所述第一电平端拉齐；以及第二晶体管，所述第二晶体管的栅极连接所述第二输入端，所述第二晶体管的源极连接所述第二电平端，所述第二晶体管的漏极连接所述第一节点，用于在所述第二输入端的信号的控制下将所述第一节点的电压与所述第二电平端拉齐。
可选的，所述第一节点控制单元还用于在所述第二节点的控制下将所述第一节点的电平与所述第四电平端的信号拉齐，并且所述第一节点控制单元还包括第六晶体管，所述第六晶体管的栅极连接所述第二节点，所述第六晶体管的源极连接所述第一节点，所述第六晶体管的漏极连接所述第四电平端，用于在所述第二节点的信号的控制下将所述第一节点的电压与所述第四电平端拉齐。
可选的，所述输出单元包括：第三晶体管，所述第三晶体管的栅极连接所述第一节点，所述第三晶体管的源极连接所述第一时钟信号端，所述第二晶体管的漏极连接输出端，用于在所述第一节点的控制下在所述输出端输出所述第一时钟信号端的信号；以及第四晶体管，所述第四晶体管的栅极连接所述第二节点，所述第四晶体管的源极连接所述输出端，所述第四晶体管的漏极连接所述第四电平端，用于在所述第二节点的信号的控制下将所述输出端的电压与所述第四电平端拉齐。
可选的，所述输出单元还包括：第二电容，所述第二电容的第一极连接所述第一节点，所述第二电容的第二极连接所述输出端，用于存储所述第一节点的电压。
可选的，所述第二节点控制单元包括：第五晶体管，所述第五晶体管的栅极连接所述第一节点，所述第五晶体管的源极连接所述第二节点，所述第 五晶体管的漏极连接所述第四电平端，用于在所述第一节点的信号的控制下将所述第二节点的电压与所述第四电平端拉齐；第七晶体管，所述第七晶体管的栅极连接所述第二时钟信号端，所述第七晶体管的源极连接所述第一电平端；第八晶体管，所述第八晶体管的栅极连接所述第三时钟信号端，所述第八晶体管的漏极连接所述第二电平端，所述第八晶体管的源极连接所述第七晶体管的漏极；以及第九晶体管，所述第九晶体管的栅极连接所述第七晶体管的漏极，所述第九晶体管的源极连接所述第三电平端，所述第九晶体管的漏极连接所述第二节点。
可选的，所述第二节点控制单元包括：第五晶体管，所述第五晶体管的栅极连接所述第一节点，所述第五晶体管的源极连接所述第二节点，所述第五晶体管的漏极连接所述第四电平端，用于在所述第一节点的信号的控制下将所述第二节点的电压与所述第四电平端拉齐；第七晶体管，所述第七晶体管的栅极连接所述第一电平端，所述第七晶体管的源极连接所述第二时钟信号端；第八晶体管，所述第八晶体管的栅极连接所述第二电平端，所述第八晶体管的漏极连接所述第三时钟信号端，所述第八晶体管的源极连接所述第七晶体管的漏极；以及第九晶体管，所述第九晶体管的栅极连接所述第七晶体管的漏极，所述第九晶体管的源极连接所述第三电平端，所述第九晶体管的漏极连接所述第二节点。
可选的，所述第二节点控制单元还包括：第一电容，所述第一电容的第一极连接所述第二节点，所述第一电容的第二极连接所述第四电平端，所述第一电容用于保持第二节点的电压。
根据本发明第二方面，提供一种GOA单元的驱动方法，包括：第一阶段，第一节点控制单元在第一输入端的信号的控制下，将第一节点的电压与第一电平端拉齐，并且第二节点控制单元在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐；第二阶段，输出单元在所述第一节点的控制下将所述第一时钟信号端的信号在所述输出端输出，并且第二节点控制单元在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐；第三阶段，第二节点控制单元在第一电平端、第二电平端、第二时钟信号端和第三时钟信号端的控制下将第二节点的电压与所述第三电平端的信号拉齐，所述第一节点控制单元用于在所述第二输入端的信号控制下将所述第一节点的电平与所述第二电平端的信号拉齐，并且所述输出单元用于在所述第二节点的控制 下将所述输出端的电平与所述第四电平端拉齐。
可选的，在所述驱动方法中，在所述第三阶段，所述第一节点控制单元还用于在所述第二节点的控制下将所述第一节点的电平与所述第四电平端的信号拉齐。
根据本发明第三方面，提供一种GOA单元的驱动方法，包括：第一阶段，第一节点控制单元在第二输入端的信号的控制下，将第一节点的电压与第二电平端拉齐，并且第二节点控制单元在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐；第二阶段，输出单元在所述第一节点的控制下将所述第一时钟信号端的信号在所述输出端输出，并且第二节点控制单元在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐；第三阶段，第二节点控制单元在第一电平端、第二电平端、第二时钟信号端和第三时钟信号端的控制下将第二节点的电压与所述第三电平端的信号拉齐，所述第一节点控制单元用于在所述第一输入端的信号的控制下将所述第一节点的电平与所述第一电平端的信号拉齐，并且所述输出单元用于在所述第二节点的控制下将所述输出端的电平与所述第四电平端拉齐。
在所述驱动方法中，在所述第三阶段，所述第一节点控制单元还用于在所述第二节点的控制下将所述第一节点的电平与所述第四电平端的信号拉齐。
根据本发明第四方面，提供一种GOA电路，包括级联的至少三级GOA单元，其中所述GOA单元为上述任一GOA单元；其中，除第一级GOA单元和最后一级GOA单元外，每一级GOA单元的输出端连接上一级GOA单元的第二输入端和下一级GOA单元的第一输入端；其中，所述第一级GOA单元的输出端连接下一级GOA单元的第一输入端，所述最后一级GOA单元的输出端连接上一级GOA单元的第二输入端；所述第一级GOA单元的第一输入端输入帧起始信号，或者所述最后一级GOA单元的第一输入端输入帧起始信号。
根据本发明第五方面，提供一种显示装置，包括上述的GOA电路。
上述方案中，通过第一节点控制单元实现对第一节点的电平的控制，通过第二节点控制单元实现对第二节点的电平的控制，通过第一节点和第二节点对输出单元的控制在输出单元的输出端输出栅极驱动信号，能够在保证GOA性能的同时减小IC的规模，从而降低生产成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种GOA电路的结构示意图；
图2为本发明实施例提供的如图1所示的GOA电路的***时钟信号的时序状态示意图；
图3为本发明实施例提供的一种GOA单元的结构示意图；
图4为本发明另一实施例提供的一种GOA单元的结构示意图；
图5为本发明又一实施例提供的一种GOA单元的结构示意图；
图6为本发明再一实施例提供的一种GOA单元的结构示意图；
图7为本发明另一实施例提供的一种GOA单元的结构示意图；
图8为本发明实施例提供的一种GOA单元的驱动信号的时序状态示意图；
图9为本发明又一实施例提供的一种GOA单元的结构示意图；
图10为本发明再一实施例提供的一种GOA单元的结构示意图；
图11为本发明另一实施例提供的一种GOA单元的结构示意图；
图12为本发明又一实施例提供的一种GOA单元的结构示意图；
图13为本发明实施例提供的一种GOA单元的驱动方法流程示意图；
图14本发明另一实施例提供的一种GOA单元的驱动方法流程示意图。
具体实施方式
下面结合附图对本发明实施例提供的GOA单元及驱动方法、GOA电路和显示装置进行详细描述，其中用相同的附图标记指示本文中的相同元件。在下面的描述中，为便于解释，给出了大量具体细节，以便提供对一个或多个实施例的全面理解。然而，很明显，也可以不用这些具体细节来实现所述实施例。在其它例子中，以方框图形式示出公知结构和设备，以便于描述一个或多个实施例。
本发明所有实施例中采用的开关晶体管和驱动晶体管均可以为薄膜晶体 管或场效应管或其他特性相同的器件，由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本发明实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为漏极、输出端为源极。此外，本发明实施例所采用的开关晶体管包括P型开关晶体管和N型开关晶体管两种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止；N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止；并且驱动晶体管包括P型驱动晶体管和N型驱动晶体管，其中P型驱动晶体管在栅极电压为低电平(栅极电压小于源极电压)且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态；其中N型驱动晶体管在栅极电压为高电平(栅极电压大于源极电压)且栅极源极的压差的绝对值大于阈值电压时处于放大状态或饱和状态。
具体的，本发明实施例提供一种GOA电路，包括级联的至少三级GOA单元。
其中，除第一级GOA单元和最后一级GOA单元外，每一级GOA单元的输出端连接上一级GOA单元的第二输入端和下一级GOA单元的第一输入端；所述第一级GOA单元的输出端连接下一级GOA单元的第一输入端，所述最后一级GOA单元的输出端连接上一级GOA单元的第二输入端；所述第一级GOA单元的第一输入端输入帧起始信号，或者所述最后一级GOA单元的第一输入端输入帧起始信号。
如图1所示，该GOA电路包括若干个级联的GOA单元，其中GOA单元SR1的输出端OUTPUT连接一条栅线OG1，且同时连接GOA单元SR2的第一输入端IN；GOA单元SR2的输出端OUTPUT连接一条栅线OG2，且同时连接上一级GOA单元SR1的第二输入端INPUT和下一级GOA单元SR3的第一输入端IN；其他的GOA单元依照此方法连接。
每个GOA单元都有一个第一时钟信号端CLK1、一个第二时钟信号端CLK2，一个第三时钟信号端CLK3及四个电平输入端：第一电平端CN、第二电平端CNB、第三电平端VGH和第四电平端VGL。参照图1所示，通过四个***时钟信号Clock1-4向每个GOA单元的三个时钟信号端CLK1-3提供时钟信号，其中SR1的CK1输入第一时钟信号Clock1，SR1的CK2输入第二时钟信号Clock2，SR1的CK3输入第四时钟信号Clock4；SR2的CK1 输入第二时钟信号Clock2，SR2的CK2输入第三时钟信号Clock3，SR2的CK3输入第一时钟信号Clock1；SR3的CK1输入第三时钟信号Clock3，SR3的CK2输入第四时钟信号Clock4，SR3的CK3输入第二时钟信号Clock2；SR4的CK1输入第四时钟信号Clock4，SR4的CK2输入第一时钟信号Clock1，SR4的CK3输入第三时钟信号Clock3；以后每4个连续的GOA单元如此循环，这里不再赘述。
其中***时钟信号的时序状态参照图2所示，Clock1-4的时钟周期均相同，Clock2相对于Clock1滞后1/4时钟周期，Clock3相对于Clock2滞后1/4时钟周期，Clock4相对于Clock3滞后1/4时钟周期，Clock1相对于Clock4滞后1/4时钟周期。具体地，例如，Clock1-4均为占空比25％的时钟信号，Clock1-4中的每个周期均包含一个单脉冲，其中Clock1的脉冲上升沿比Clock2的脉冲上升沿提前一个单脉冲宽度；Clock2的脉冲上升沿比Clock3的脉冲上升沿提前一个单脉冲宽度；Clock3的脉冲上升沿比Clock4的脉冲上升沿提前一个单脉冲宽度，以上均所述的各个脉冲均以相同脉冲宽度为例进行说明。
本发明实施例提供的GOA电路可以实现双向扫描。在正向扫描时，第一个GOA单元为SR1，则GOA单元SR1的第一输入端IN输入一个激活脉冲信号，可选的如帧起始信号STV，该帧起始信号STV在一帧的时间段内为单脉冲信号。参照图2所示，同时示出了STV单脉冲信号与***时钟信号的关系，其中STV单脉冲信号的上升沿与***时钟信号Clock4的第一脉冲上升沿同步，此时最后一个GOA单元SRn的第二输入端INPUT闲置。在反向扫描时，则在最后一个GOA单元SRn的第二输入端INPUT输入一个激活脉冲信号，此时GOA单元SR1的第一输入端IN闲置。
进一步的，本发明实施例提供了上述GOA电路采用的GOA单元，参照图3所示，本发明实施例提供一种GOA单元，包括第一节点控制单元31，第二节点控制单元32和输出单元33。
所述第一节点控制单元31连接第一输入端IN、第二输入端INPUT、第一电平端CN、第二电平端CNB、第一节点PU、第二节点PD和第四电平端VGL；用于在第一输入端IN的信号的控制下将第一节点PU的电平与所述第一电平端CN的信号拉齐，或者用于在所述第二输入端INPUT的信号的控制下将所述第一节点PU的电平与所述第二电平端CNB的信号拉齐。此外，所 述第一节点控制单元还可以用于在所述第二节点PD的控制下将所述第一节点PU的电平与所述第四电平端VGL的信号拉齐。
所述第二节点控制单元32连接所述第一电平端CN、所述第二电平端CNB、第三电平端VGH、所述第四电平端VGL、第二时钟信号端CK2、第三时钟信号端CK3，所述第一节点PU和所述第二节点PD；用于在所述第一电平端CN、所述第二电平端CNB、所述第二时钟信号端CK2和第三时钟信号端CK3的控制下将所述第二节点PD的电压与所述第三电平端VGH的信号拉齐，或者用于在所述第一节点PU的控制下将所述第二节点PD的电压与所述第四电平端VGL拉齐。
所述输出单元33连接输出端OUTPUT、第一时钟信号端CK1、所述第一节点PU，所述第二节点PD和所述第四电平端VGL；用于在所述第一节点PU的控制下将所述第一时钟信号端CK1的信号在所述输出端OUTPUT输出，或者用于在所述第二节点PD的控制下将所述输出端OUTPUT的电平与所述第四电平端VGL拉齐。
上述方案中，通过第一节点控制单元31实现对第一节点PU电压的控制，通过第二节点控制单元32实现对第二节点PD电压的控制，通过第一节点PU和第二节点PD对输出单元33的控制在输出单元33的输出端OUTPUT输出栅极驱动信号，能够在保证GOA单元性能的同时减小IC的规模，从而降低生产成本。
参照图4所示，对本发明实施例提供的GOA单元的内部器件的连接关系进行详述。
具体的，所述第一节点控制单元31包括：第一晶体管T1、第二晶体管T2。
所述第一晶体管T1的栅极连接所述第一输入端IN，所述第一晶体管T1的源极连接所述第一电平端CN，所述第一晶体管T1的漏极连接所述第一节点PU；用于在所述第一输入端IN的信号的控制下将所述第一节点PU的电压与所述第一电平端CN拉齐。
所述第二晶体管T2的栅极连接所述第二输入端INPUT，所述第二晶体管T2的源极连接所述第二电平端CNB，所述第二晶体管T2的漏极连接所述第一节点PU；用于在所述第二输入端INPUT的信号的控制下将所述第一节点PU的电压与所述第二电平端CNB拉齐。
此外，所述第一节点控制单元31还可以包括：第六晶体管T6。所述第六晶体管T6的栅极连接所述第二节点PD，所述第六晶体管T6的源极连接所述第一节点PU，所述第六晶体管T6的漏极连接所述第四电平端VGL；用于在所述第二节点PD的信号的控制下将所述第一节点PU的电压与所述第四电平端VGL拉齐。
所述输出单元33包括：第三晶体管T3以及第四晶体管T4。
所述第三晶体管T3的栅极连接所述第一节点PU，所述第三晶体管T3的源极连接所述第一时钟信号端CK1，所述第二晶体管T2的漏极连接输出端OUTPUT，用于在所述第一节点PU的控制下在所述输出端OUTPUT输出所述第一时钟信号端CK1的信号。
所述第四晶体管T4的栅极连接所述第二节点PD，所述第四晶体管T4的源极连接所述输出端OUTPUT，所述第四晶体管T4的漏极连接所述第四电平端VGL，用于在所述第二节点PD的信号的控制下将所述输出端OUTPUT的电压与所述第四电平端VGL拉齐。
可选的，参照图5所示，所述输出单元33还包括：第二电容C2。
所述第二电容C2的第一极连接所述第一节点PU，所述第二电容C2的第二极连接所述输出端OUTPUT，用于存储所述第一节点PU的电压。
参照图4或5所示，所述第二节点控制单元32包括：第五晶体管T5、第七晶体管T7、第八晶体管T8以及第九晶体管T9。
所述第五晶体管T5的栅极连接所述第一节点PU，所述第五晶体管T5的源极连接所述第二节点PD，所述第五晶体管T5的漏极连接所述第四电平端VGL，用于在所述第一节点PU的信号的控制下将所述第二节点PD的电压与所述第四电平端VGL拉齐。
所述第七晶体管T7的栅极连接所述第二时钟信号端CK2，所述第七晶体管T7的源极连接所述第一电平端CN。
所述第八晶体管T8的栅极连接所述第三时钟信号端CK3，所述第八晶体管T8的漏极连接所述第二电平端CNB，所述第八晶体管T8的源极连接所述第七晶体管T7的漏极。
所述第九晶体管T9的栅极连接所述第七晶体管T7的漏极，所述第九晶体管T9的源极连接所述第三电平端VGH，所述第九晶体管T9的漏极连接所述第二节点PD。
所述第七晶体管T7用于将所述第九晶体管T9的栅极电压与所述第一电压端CN拉齐，所述第八晶体管T8用于将所述第九晶体管T9的栅极电压与所述第二电压端CNB拉齐，所述第九晶体管T9用于在其栅极电压的控制下将所述第二节点PD的电压与所述第三电平端VGH拉齐。
可选的，参照图6所示，所述第二节点控制单元32还包括：第一电容C1。
所述第一电容C1的第一极连接所述第二节点PD，所述第一电容C1的第二极连接所述第四电平端VGL，所述第一电容C1用于保持第二节点PD的电压。
当然，参照图7所示，GOA单元也可同时包含第一电容C1和第二电容C2两者。图4-7提供的GOA单元均包含9个晶体管，相对于现有技术的12T1C(12个晶体管1个电容的结构)，明显减少晶体管的数量，从而节约生产成本。
结合图8所示的时序信号状态图，对本发明实施例提供的图7所示的GOA单元的驱动方法进行说明，其中CK1输入Clock1、CK2输入Clock2、CK3输入Clock4，以所有晶体管为高电平导通为例进行说明，CN和CNB为控制正反扫描的信号；CN为高电平且CNB为低电平时GOA单元为正向扫描，CN为低电平且CNB为高电平时GOA单元为反向扫描，VGL为负的低电平，VGH为正的高电平。
以下以正向扫描为例说明，图8为相应的信号时序；正向扫描时，CN为高电平，CNB为低电平。
在第一阶段“a”，IN为高电平，Clock1和Clock2为低电平，Clock4为高电平；T1导通，CN通过T1给C2充电，PU变为高电平，T5导通将PD节点拉至低电平；T8导通，CNB为低电平控制T9截止。
在第二阶段“b”，IN为低电平，Clock1为高电平，Clock2和Clock4为低电平；T1截止，T3导通，由于C2的自举作用(Self Boost)PU的电平进一步提高，输出端OUTPUT输出Clock1的高电平，此时T5继续导通，PD保持低电平。
在第三阶段“c”，Clock2为高电平，Clock1和Clock4为低电平，T7导通，CN通过T7给T9栅极充电使得T9导通，VGH通过T9给C1充电，使得将PD拉高为高电平，从而控制T4和T6同时导通给C2放电，同时INPUT为 高电平，T2导通也给C2放电，OUTPUT被拉低为低电平。
第一电容C1的作用是在OUTPUT输出之后保持PD的高电平，尽管在没有第一电容C1的情况下(如图3所示)依靠晶体管T5的寄生电容也可以维持PD的高电平，然而在存在C1的情况下可以大大降低PD节点处的噪声。同理，该电路也可同样依靠晶体管T3的寄生电容维持PU节点的电平，而不设置电容C2。以上是以正向扫描为例进行说明，反向扫描时仅是将CN调整为低电平且将CNB调整为高电平，原理类似不再赘述。
替换地，可选的，参照图9-12所示，本发明实施例提供的另一种GOA单元包括第一节点控制单元31、第二节点控制单元32和输出单元33。
所述第一节点控制单元31包括三个晶体管T1、T2和T6，其中T1、T2和T6的连接关系参照图4-7对应的实施例，这里不再赘述。
所述输出单元33，包括晶体管T3和T4，其中T3和T4的连接关系参照图4-7对应的实施例，这里不再赘述。可选的，输出单元33还可以包括第二电容C2，与图5和7对应的实施例相同，不再赘述。
所述第二节点控制单元32包括：第五晶体管T5、第七晶体管T7、第八晶体管T8以及第九晶体管T9。
所述第五晶体管T5的栅极连接所述第一节点PU，所述第五晶体管T5的源极连接所述第二节点PD，所述第五晶体管T5的漏极连接所述第四电平端VGL，用于在所述第一节点PU的信号的控制下将所述第二节点PD的电压与所述第四电平端VGL拉齐。
所述第七晶体管T7的栅极连接所述第一电平端CN，所述第七晶体管T7的源极连接所述第二时钟信号端CK2。
所述第八晶体管T8的栅极连接所述第二电平端CNB，所述第八晶体管T8的漏极连接所述第三时钟信号端CK3，所述第八晶体管T8的源极连接所述第七晶体管T7的漏极。
所述第九晶体管T9的栅极连接所述第七晶体管T7的漏极，所述第九晶体管T9的源极连接所述第三电平端VGH，所述第九晶体管T9的漏极连接所述第二节点PD。
所述第七晶体管T7用于将所述第九晶体管T9的栅极电压与所述第二时钟信号端CK2拉齐，所述第八晶体管T8用于将所述第九晶体管T9的栅极电压与所述第三时钟信号端CK3拉齐，所述第九晶体管T9用于在其栅极电压 的控制下将所述第二节点PD的电压与所述第三电平端VGH拉齐。
可选的，参照图11、12所示，第二节点控制单元32还包括第一电容C1，所述第一电容C1的第一极连接所述第二节点PD，所述第一电容C1的第二极连接所述第四电平端VGL，所述第一电容C1用于保持第二节点PD的电压。
当然，参照图12所示，GOA单元也可同时包含第一电容C1和第二电容C2两者。图9-12提供的GOA单元均包含9个晶体管，相对于现有技术的12T1C(12个晶体管1个电容的结构)，明显减少晶体管的数量，从而节约生产成本。
结合图8所示的时序信号状态图，对本发明实施例提供的图12所示的GOA单元的驱动方法进行说明，其中CK1输入Clock1、CK2输入Clock2、CK3输入Clock4，以所有晶体管为高电平导通为例进行说明，CN和CNB为控制正反扫描的信号；CN为高电平且CNB为低电平时GOA单元为正向扫描，CN为低电平且CNB为高电平时GOA单元为反向扫描，VGL为负的低电平，VGH为正的高电平。
以下以正向扫描为例说明，图8为相应的信号时序；正向扫描时，CN为高电平，CNB为低电平。
在第一阶段“a”，IN为高电平，Clock1和Clock2为低电平、Clock4为高电平；T1导通，CN通过T1给C2充电，PU变为高电平，T5导通将PD节点拉至低电平；T8截止，T7导通，Clock2为低电平控制T9截止。
在第二阶段“b”，IN为低电平，Clock1为高电平，Clock2和Clock4为低电平；T1截止，T3导通，由于C2的自举作用(Self Boost)PU的电平进一步提高，输出端OUTPUT输出Clock1的高电平，此时T5继续导通，PD保持低电平；同时T7导通，Clock2为低电平控制T9截止。
在第三阶段“c”，Clock2为高电平，Clock1和Clock4为低电平，T7导通；Clock2为高电平通过T7给T9的栅极充电使得T9导通，VGH通过T9给C1充电，使得将PD拉高为高电平，从而控制T4和T6同时导通给C2放电，同时INPUT为高电平，T2导通也给C2放电，OUTPUT被拉低为低电平。
与图4-7所示的GOA单元的工作原理有区别的是，图9-12所示的GOA单元中T7在三个阶段中均处于导通状态，T8在三个阶段中均处于截止状态。
第一电容C1的作用是在OUTPUT输出之后保持PD的高电平，尽管在 没有第一电容C1的情况下(如图3所示)依靠晶体管T5的寄生电容也可以维持PD的高电平，然而在存在C1的情况下可以大大降低PD节点处的噪声。同理，该电路也可同样依靠晶体管T3的寄生电容维持PU节点的电平，而不设置电容C2。以上是以正向扫描为例进行说明，反向扫描时仅是将CN调整为低电平且将CNB调整为高电平，此时图9-12所示的GOA单元中T8在三个阶段中均处于导通状态，T7在三个阶段中均处于截止状态，GOA单元其他部分的工作原理与上述实施例类似不再赘述。
在本发明实施例中对各个开关晶体管的类型不做限制，上述实施例中是以所有晶体管均为高电平导通为例进行说明，在调整晶体管的类型时只需要相应的调整对应的信号线或信号线施加的电平信号即可，当然这里以能够实现本发明实施例提供的GOA单元的驱动方法为准，本领域技术人员在本发明实施例提供的GOA单元和驱动方法的基础上可轻易想到并实现的任一组合均在本发明的保护范围内。
如图13所示，本发明实施例还提供了上述GOA单元的驱动方法，该驱动方法应用于正向扫描过程，包括如下步骤。
在第一阶段801，第一节点控制单元31在第一输入端的信号的控制下，将第一节点的电压与第一电平端拉齐；并且第二节点控制单元32在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐；
在第二阶段802，输出单元33在所述第一节点的控制下将所述第一时钟信号端的信号在所述输出端输出；第二节点控制单元32在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐；
在第三阶段803，第二节点控制单元32在第一电平端、第二电平端、第二时钟信号端和第三时钟信号端的控制下将第二节点的电压与所述第三电平端的信号拉齐；所述第一节点控制单元31还用于在所述第二输入端的信号控制下将所述第一节点的电平与所述第二电平端的信号拉齐；所述输出单元33用于在所述第二节点的控制下将所述输出端的电平与所述第四电平端拉齐。
此外，在所述第三阶段803，所述第一节点控制单元31还用于在所述第二节点的控制下将所述第一节点的电平与所述第四电平端的信号拉齐。
上述方案中，通过第一节点控制单元实现对第一节点电压的控制，通过第二节点控制单元实现对第二节点电压的控制，通过第一节点和第二节点对输出单元的控制在输出单元的输出端输出栅极驱动信号，能够在保证GOA电 路性能的同时减小IC的规模，从而降低生产成本。
可选的，所述第一节点控制单元31包括：第一晶体管、第二晶体管、第六晶体管。所述驱动方法在各阶段中的具体操作如下所述。
在所述第一阶段801，所述第一晶体管为导通状态，所述第二晶体管为截止状态；所述第六晶体管为截止状态。
在所述第二阶段802，所述第一晶体管为截止状态，所述第二晶体管为截止状态；所述第六晶体管为截止状态。
在所述第三阶段803，所述第一晶体管为截止状态，所述第二晶体管为导通状态；所述第六晶体管为导通状态。
可选的，所述输出单元包括：第三晶体管和第四晶体管。所述驱动方法在各阶段中的具体操作如下所述。
在所述第一阶段801，所述第三晶体管为截止状态，所述第四晶体管为截止状态。
在所述第二阶段802，所述第三晶体管为导通状态，所述第四晶体管为截止状态。
在所述第三阶段803，所述第三晶体管为截止状态，所述第四晶体管为导通状态。
可选的，所述输出单元包括：第五晶体管、第七晶体管、第八晶体管和第九晶体管；并且第五晶体管、第七晶体管、第八晶体管和第九晶体管的连接关系为上述图4-7对应的实施例所述的任一GOA单元中的连接方式。所述驱动方法在各阶段中的具体操作如下所述。
在所述第一阶段801，所述第五晶体管为导通状态，所述第七晶体管为截止状态，所述第八晶体管为导通状态，所述第九晶体管为截止状态。
在所述第二阶段802，所述第五晶体管为导通状态，所述第七晶体管为截止状态，所述第八晶体管为截止状态，所述第九晶体管为截止状态。
在所述第三阶段803，所述第五晶体管为截止状态，所述第七晶体管为导通状态，所述第八晶体管为截止状态，所述第九晶体管为导通状态。
可选的，所述输出单元包括：第五晶体管、第七晶体管、第八晶体管和第九晶体管；并且第五晶体管、第七晶体管、第八晶体管和第九晶体管的连接关系为上述图9-12对应的实施例所述的任一GOA单元中的连接方式。所述驱动方法在各阶段中的具体操作如下所述。
在所述第一阶段801，所述第五晶体管为导通状态，所述第七晶体管为导通状态，所述第八晶体管为截止状态，所述第九晶体管为截止状态。
在所述第二阶段802，所述第五晶体管为导通状态，所述第七晶体管为导通状态，所述第八晶体管为截止状态，所述第九晶体管为截止状态。
在所述第三阶段803，所述第五晶体管为截止状态，所述第七晶体管为导通状态，所述第八晶体管为截止状态，所述第九晶体管为导通状态。
如图14所示，本发明实施例还提供了上述GOA单元的驱动方法，该驱动方法应用于反向扫描过程，包括如下步骤。
在第一阶段901，第一节点控制单元31在第二输入端的信号的控制下，将第一节点的电压与第二电平端拉齐；并且第二节点控制单元32在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐。
在第二阶段902，输出单元33在所述第一节点的控制下将所述第一时钟信号端的信号在所述输出端输出；第二节点控制单元32在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐。
在第三阶段903，第二节点控制单元32在第一电平端、第二电平端、第二时钟信号端和第三时钟信号端的控制下将第二节点的电压与所述第三电平端的信号拉齐；所述第一节点控制单元31用于在所述第二节点的控制下将所述第一节点的电平与所述第四电平端的信号拉齐；所述第一节点控制单元31还用于在所述第一输入端的信号控制下将所述第一节点的电平与所述第一电平端的信号拉齐；所述输出单元33用于在所述第二节点的控制下将所述输出端的电平与所述第四电平端拉齐。
上述方案中，通过第一节点控制单元实现对第一节点电压的控制，通过第二节点控制单元实现对第二节点电压的控制，通过第一节点和第二节点对输出单元的控制在输出单元的输出端输出栅极驱动信号，能够在保证GOA电路性能的同时减小IC的规模，从而降低生产成本。
可选的，所述第一节点控制单元包括：第一晶体管、第二晶体管、第六晶体管。所述驱动方法在各阶段中的具体操作如下所述。
在所述第一阶段901，所述第一晶体管为截止状态，所述第二晶体管为导通状态；所述第六晶体管为截止状态。
在所述第二阶段902，所述第一晶体管为截止状态，所述第二晶体管为截止状态；所述第六晶体管为截止状态。
在所述第三阶段903，所述第一晶体管为导通状态，所述第二晶体管为截止状态；所述第六晶体管为导通状态。
可选的，所述输出单元包括：第三晶体管和第四晶体管。所述驱动方法在各阶段中的具体操作如下所述。
在所述第一阶段901，所述第三晶体管为截止状态，所述第四晶体管为截止状态。
在所述第二阶段902，所述第三晶体管为导通状态，所述第四晶体管为截止状态。
在所述第三阶段903，所述第三晶体管为截止状态，所述第四晶体管为导通状态。
可选的，所述输出单元包括：第五晶体管、第七晶体管、第八晶体管和第九晶体管；并且第五晶体管、第七晶体管、第八晶体管和第九晶体管的连接关系为上述图4-7对应的实施例所述的任一GOA单元中的连接方式。所述驱动方法在各阶段中的具体操作如下所述。
在所述第一阶段901，所述第五晶体管为导通状态，所述第七晶体管为截止状态，所述第八晶体管为导通状态，所述第九晶体管为截止状态。
在所述第二阶段902，所述第五晶体管为导通状态，所述第七晶体管为截止状态，所述第八晶体管为截止状态，所述第九晶体管为截止状态。
在所述第三阶段903，所述第五晶体管为截止状态，所述第七晶体管为导通状态，所述第八晶体管为截止状态，所述第九晶体管为导通状态。
可选的，所述输出单元包括：第五晶体管、第七晶体管、第八晶体管和第九晶体管；并且第五晶体管、第七晶体管、第八晶体管和第九晶体管的连接关系为上述图9-12对应的实施例所述的任一GOA单元中的连接方式。所述驱动方法在各阶段中的具体操作如下所述。
在所述第一阶段901，所述第五晶体管为导通状态，所述第七晶体管为截止状态，所述第八晶体管为导通状态，所述第九晶体管的截止状态。
在所述第二阶段902，所述第五晶体管为导通状态，所述第七晶体管为截止状态，所述第八晶体管为导通状态，所述第九晶体管的截止状态。
在所述第三阶段903，所述第五晶体管为截止状态，所述第七晶体管为截止状态，所述第八晶体管为导通状态，所述第九晶体管的导通状态。
本发明实施例提供一种显示装置，包括：显示电路。所述显示电路包括 像素阵列、第一栅极驱动单元和第二栅极驱动单元，所述第一栅极驱动单元和第二栅极驱动单元每个包括本发明实施例提供的GOA电路，所述GOA电路包括级联的至少三级本发明实施例提供的GOA单元。该显示装置可以为电子纸、手机、电视、数码相框等等显示设备。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所附权利要求的保护范围为准。
本申请要求2014年10月31日提交的申请号为“CN 201410602347.3”且发明名称为“一种GOA单元及驱动方法，GOA电路和显示装置”的中国优先申请的优先权，通过引用将其全部内容并入于此。

Claims (14)

  1. 一种GOA单元，其特征在于，包括第一节点控制单元，第二节点控制单元和输出单元；
    其中，所述第一节点控制单元连接第一输入端、第二输入端、第一电平端、第二电平端、第一节点、第二节点和第四电平端；用于在第一输入端的信号的控制下将第一节点的电平与所述第一电平端的信号拉齐，或者用于在所述第二输入端的信号的控制下将所述第一节点的电平与所述第二电平端的信号拉齐；
    所述第二节点控制单元连接所述第一电平端、所述第二电平端、第三电平端、所述第四电平端、第二时钟信号端、第三时钟信号端，所述第一节点和所述第二节点；用于在所述第一电平端、所述第二电平端、所述第二时钟信号端和第三时钟信号端的控制下将所述第二节点的电压与所述第三电平端的信号拉齐，或者用于在所述第一节点的控制下将所述第二节点的电压与所述第四电平端拉齐；
    所述输出单元连接输出端、第一时钟信号端、所述第一节点，所述第二节点和所述第四电平端；用于在所述第一节点的控制下将所述第一时钟信号端的信号在所述输出端输出，或者用于在所述第二节点的控制下将所述输出端的电平与所述第四电平端拉齐。
  2. 根据权利要求1所述的GOA单元，其特征在于，所述第一节点控制单元包括：
    第一晶体管，所述第一晶体管的栅极连接所述第一输入端，所述第一晶体管的源极连接所述第一电平端，所述第一晶体管的漏极连接所述第一节点，用于在所述第一输入端的信号的控制下将所述第一节点的电压与所述第一电平端拉齐；以及
    第二晶体管，所述第二晶体管的栅极连接所述第二输入端，所述第二晶体管的源极连接所述第二电平端，所述第二晶体管的漏极连接所述第一节点，用于在所述第二输入端的信号的控制下将所述第一节点的电压与所述第二电平端拉齐。
  3. 根据权利要求2所述的GOA单元，其特征在于，所述第一节点控制单元还用于在所述第二节点的控制下将所述第一节点的电平与所述第四电平 端的信号拉齐，并且所述第一节点控制单元还包括第六晶体管，
    所述第六晶体管的栅极连接所述第二节点，所述第六晶体管的源极连接所述第一节点，所述第六晶体管的漏极连接所述第四电平端，用于在所述第二节点的信号的控制下将所述第一节点的电压与所述第四电平端拉齐。
  4. 根据权利要求1所述的GOA单元，其特征在于，所述输出单元包括：
    第三晶体管，所述第三晶体管的栅极连接所述第一节点，所述第三晶体管的源极连接所述第一时钟信号端，所述第二晶体管的漏极连接输出端，用于在所述第一节点的控制下在所述输出端输出所述第一时钟信号端的信号；以及
    第四晶体管，所述第四晶体管的栅极连接所述第二节点，所述第四晶体管的源极连接所述输出端，所述第四晶体管的漏极连接所述第四电平端，用于在所述第二节点的信号的控制下将所述输出端的电压与所述第四电平端拉齐。
  5. 根据权利要求4所述的GOA单元，其特征在于，所述输出单元还包括：
    第二电容，所述第二电容的第一极连接所述第一节点，所述第二电容的第二极连接所述输出端，用于存储所述第一节点的电压。
  6. 根据权利要求1所述的GOA单元，其特征在于，所述第二节点控制单元包括：
    第五晶体管，所述第五晶体管的栅极连接所述第一节点，所述第五晶体管的源极连接所述第二节点，所述第五晶体管的漏极连接所述第四电平端，用于在所述第一节点的信号的控制下将所述第二节点的电压与所述第四电平端拉齐；
    第七晶体管，所述第七晶体管的栅极连接所述第二时钟信号端，所述第七晶体管的源极连接所述第一电平端；
    第八晶体管，所述第八晶体管的栅极连接所述第三时钟信号端，所述第八晶体管的漏极连接所述第二电平端，所述第八晶体管的源极连接所述第七晶体管的漏极；以及
    第九晶体管，所述第九晶体管的栅极连接所述第七晶体管的漏极，所述第九晶体管的源极连接所述第三电平端，所述第九晶体管的漏极连接所述第二节点。
  7. 根据权利要求1所述的GOA单元，其特征在于，所述第二节点控制单元包括：
    第五晶体管，所述第五晶体管的栅极连接所述第一节点，所述第五晶体管的源极连接所述第二节点，所述第五晶体管的漏极连接所述第四电平端，用于在所述第一节点的信号的控制下将所述第二节点的电压与所述第四电平端拉齐；
    第七晶体管，所述第七晶体管的栅极连接所述第一电平端，所述第七晶体管的源极连接所述第二时钟信号端；
    第八晶体管，所述第八晶体管的栅极连接所述第二电平端，所述第八晶体管的漏极连接所述第三时钟信号端，所述第八晶体管的源极连接所述第七晶体管的漏极；
    第九晶体管，所述第九晶体管的栅极连接所述第七晶体管的漏极，所述第九晶体管的源极连接所述第三电平端，所述第九晶体管的漏极连接所述第二节点。
  8. 根据权利要求6或7所述的GOA单元，其特征在于，所述第二节点控制单元还包括：
    第一电容，所述第一电容的第一极连接所述第二节点，所述第一电容的第二极连接所述第四电平端，所述第一电容用于保持第二节点的电压。
  9. 一种GOA单元的驱动方法，其特征在于，包括：
    第一阶段，第一节点控制单元在第一输入端的信号的控制下，将第一节点的电压与第一电平端拉齐；并且第二节点控制单元在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐；
    第二阶段，输出单元在所述第一节点的控制下将所述第一时钟信号端的信号在所述输出端输出；并且第二节点控制单元在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐；
    第三阶段，第二节点控制单元在第一电平端、第二电平端、第二时钟信号端和第三时钟信号端的控制下将第二节点的电压与所述第三电平端的信号拉齐；所述第一节点控制单元用于在所述第二输入端的信号控制下将所述第一节点的电平与所述第二电平端的信号拉齐；并且所述输出单元用于在所述第二节点的控制下将所述输出端的电平与所述第四电平端拉齐。
  10. 如权利要求9所述的GOA单元的驱动方法，其特征在于，
    在所述第三阶段，所述第一节点控制单元还用于在所述第二节点的控制下将所述第一节点的电平与所述第四电平端的信号拉齐。
  11. 一种GOA单元的驱动方法，其特征在于，包括：
    第一阶段，第一节点控制单元在第二输入端的信号的控制下，将第一节点的电压与第二电平端拉齐；并且第二节点控制单元在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐；
    第二阶段，输出单元在所述第一节点的控制下将所述第一时钟信号端的信号在所述输出端输出；并且第二节点控制单元在第一节点的信号的控制下将第二节点的电压与第四电平端拉齐；
    第三阶段，第二节点控制单元在第一电平端、第二电平端、第二时钟信号端和第三时钟信号端的控制下将第二节点的电压与所述第三电平端的信号拉齐；所述第一节点控制单元还用于在所述第一输入端的信号控制下将所述第一节点的电平与所述第一电平端的信号拉齐；所述输出单元用于在所述第二节点的控制下将所述输出端的电平与所述第四电平端拉齐。
  12. 如权利要求11所述的GOA单元的驱动方法，其特征在于，
    在所述第三阶段，所述第一节点控制单元还用于在所述第二节点的控制下将所述第一节点的电平与所述第四电平端的信号拉齐。
  13. 一种GOA电路，其特征在于，包括级联的至少三级GOA单元，其中所述GOA单元为如权利要求1-7任一项所述的GOA单元；
    其中，除第一级GOA单元和最后一级GOA单元外，每一级GOA单元的输出端连接上一级GOA单元的第二输入端和下一级GOA单元的第一输入端；
    其中，所述第一级GOA单元的输出端连接下一级GOA单元的第一输入端，所述最后一级GOA单元的输出端连接上一级GOA单元的第二输入端；
    所述第一级GOA单元的第一输入端输入帧起始信号，或者所述最后一级GOA单元的第一输入端输入帧起始信号。
  14. 一种显示装置，其特征在于，包括如权利要求13所述的GOA电路。
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