WO2016019642A1 - Dispositif permettant d'empêcher le courant de circuler vers l'arrière - Google Patents

Dispositif permettant d'empêcher le courant de circuler vers l'arrière Download PDF

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Publication number
WO2016019642A1
WO2016019642A1 PCT/CN2014/090191 CN2014090191W WO2016019642A1 WO 2016019642 A1 WO2016019642 A1 WO 2016019642A1 CN 2014090191 W CN2014090191 W CN 2014090191W WO 2016019642 A1 WO2016019642 A1 WO 2016019642A1
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Prior art keywords
mos transistor
capacitor
resistor
circuit
drain
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PCT/CN2014/090191
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English (en)
Chinese (zh)
Inventor
宗节保
曹青
欧阳艳红
彭轶
黄建华
张金涛
刘飞云
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中兴通讯股份有限公司
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Publication of WO2016019642A1 publication Critical patent/WO2016019642A1/fr

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J1/00—Circuit arrangements for dc mains or dc distribution networks
    • H02J1/10—Parallel operation of dc sources
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac

Definitions

  • the present invention relates to the field of power electronics, and more particularly to an apparatus for preventing current backflow.
  • the existing switching power supply In order to achieve the goal of high conversion efficiency, the existing switching power supply generally adopts synchronous rectification technology, but the problem also arises.
  • the switching power supply when the input is quickly powered down, the output reverses the energy to the input, and the output inductor generates a continuously accumulated negative current. At this time, the synchronous rectifier is turned off, and the reverse current on the inductor is not freewheeling.
  • the circuit directly charges the parasitic capacitance of the FET MOS tube. When the backflow energy is large enough, the MOS tube will be avalanche breakdown and damaged.
  • the problem is that the switching power supply input undervoltage protection has a slow response to the input fast power failure, and the inductor accumulates the reverse energy without the bleeder circuit, thereby damaging the synchronous rectifier.
  • embodiments of the present invention are intended to provide an apparatus for preventing current backflow.
  • An apparatus for preventing current backflow includes: a sampling circuit connected to a power input end of the isolated power supply circuit, a comparison circuit connected to the sampling circuit, An isolation circuit connected to the comparison circuit and a drive circuit connected to the isolation circuit;
  • the sampling circuit is configured to sample the power input voltage of the isolated power supply circuit in real time, and output the sampled voltage signal to the comparison circuit, wherein the isolated power supply circuit has a plurality of synchronous rectifier MOS tubes;
  • the comparison circuit is configured to compare the voltage signal with a preset reference voltage, and output a control signal according to the comparison result;
  • the isolation circuit is configured to receive a control signal of the comparison circuit and transmit the control signal to the drive circuit;
  • the driving circuit is configured to control turn-on or turn-off of the plurality of synchronous rectification MOS transistors of the isolated power supply circuit according to the control signal, and the driving circuit is further connected to the isolated power supply circuit.
  • the power input voltage of the isolated power supply circuit is collected by the input end of the sampling circuit, the output voltage signal of the output end is output to the input end of the comparison circuit, and the other input end of the comparison circuit inputs the reference voltage, and the output end is based on
  • the comparison result outputs a control signal, and the control signal is transmitted from the primary side to the secondary side through the isolation circuit, and the synchronous rectifier MOS tube of the isolated power supply circuit is controlled to be turned on and off by the driving circuit.
  • the sampling circuit can sample the input voltage of the isolated power supply circuit in real time, and can quickly react when the input voltage is quickly powered down, and the comparison circuit output control signal quickly turns off the secondary synchronous rectifier MOS tube of the isolated power supply circuit, thereby preventing the inductance from accumulating. Reverse current causes MOS tube avalanche breakdown damage.
  • FIG. 1 is a schematic diagram of an anti-backflow circuit under the input fast power-down according to the present invention
  • Figure 2 is a circuit schematic diagram of a first embodiment of the present invention
  • Figure 3 is a circuit schematic diagram of a second embodiment of the present invention.
  • Figure 4 is a circuit schematic diagram of a third embodiment of the present invention.
  • Figure 5 is a circuit schematic diagram of a fourth embodiment of the present invention.
  • Figure 6 is a circuit schematic diagram of a fifth embodiment of the present invention.
  • Figure 7 is a circuit schematic diagram of a sixth embodiment of the present invention.
  • 1-sampling circuit 2-comparing circuit, 3-isolated circuit, 4-drive circuit, 5-isolated power supply circuit.
  • the invention is directed to the prior art, the switching power supply input undervoltage protection has a slow response to the input fast power failure, and the inductor cumulative reverse energy has no bleed circuit to damage the synchronous rectifier tube, and provides a device for preventing current backflow, through the sampling circuit Real-time sampling of the input voltage of the isolated power supply circuit, when the input voltage is quickly powered down, it can react quickly, and the comparison circuit output control signal turns off the secondary synchronous MOS transistor of the isolated power supply circuit, which not only prevents the inductor from accumulating reverse current to cause MOS Tube avalanche breakdown damage, and it helps to improve the reliability of the product, thereby increasing the competitiveness and attractiveness of the product.
  • the apparatus for preventing current backflow includes: a sampling circuit 1 connected to a power input end of the isolated power supply circuit 5, a comparison circuit 2 connected to the sampling circuit 1, and An isolation circuit 3 connected to the comparison circuit 2 and a drive circuit 4 connected to the isolation circuit 3;
  • the sampling circuit 1 is configured to sample the power input voltage of the isolated power supply circuit 5 in real time, and output the sampled voltage signal to the comparison circuit 2, wherein the isolated power supply circuit 5 has a plurality of synchronous rectifier MOS tubes ;
  • the comparison circuit 2 is configured to compare the voltage signal with a preset reference voltage, and output a control signal according to the comparison result;
  • the device used in the comparison circuit 2 may be a comparator, an operational amplifier or a fast operational amplifier, but is not limited to a comparator, an operational amplifier or a fast operational amplifier, and any input voltage that can be sampled can be realized.
  • the circuit for comparing Vin with the preset reference voltage Vref is within the protection scope of the present invention, and is not exemplified herein.
  • the preset reference voltage Vref is determined by debugging, and the inductor voltage does not generate a continuous reverse current or a reverse current as small as possible.
  • the isolation circuit 3 is configured to receive the control signal of the comparison circuit 2 and pass it to the drive circuit 4;
  • the driving circuit 4 is configured to control turn-on or turn-off of the plurality of synchronous rectification MOS transistors of the isolated power supply circuit 5 according to the control signal, and the driving circuit 4 is further connected to the isolated power supply circuit 5.
  • the device used in the above isolation circuit 3 may be an optical coupler, or may be an isolator, but is not limited to an optocoupler and an isolator, and any device that can transmit a control signal from the primary side of the isolation circuit 3 to the secondary side. All of them belong to the protection scope of the present invention, and are not exemplified herein.
  • the isolated power supply circuit 5 includes a synchronous rectification MOS transistor having a primary side circuit and a synchronous rectification MOS transistor having a secondary side circuit.
  • the real-time sampling circuit 1 of the input voltage can sample the input voltage Vin in real time through the resistor division, the capacitor is filtered and input to one of the input terminals of the comparison circuit 2, the other input terminal is the preset reference voltage Vref, and the comparison circuit 2 can sample the voltage.
  • the input input voltage Vin is compared with the preset reference voltage Vref, and the output signal is transmitted from the primary side to the secondary side through the isolation circuit 3, and the secondary side synchronous rectification MOS transistor of the isolated power supply circuit 5 is controlled to be turned on and off by the drive circuit 4.
  • the sampling circuit 1 includes:
  • the one end of the second resistor R3 is connected to the input end of the isolated power supply circuit 5
  • One end of the first resistor R2 is connected to one end of the first capacitor C2
  • the other end of the second resistor R3 is connected to one end of the first resistor R2
  • the other end of the second resistor R3 is further Connected to an input of the sampling circuit 1.
  • the other end of the first resistor R2 is grounded to the other end of the first capacitor C2.
  • the comparison circuit 2 includes: a comparator D1 having a positive input terminal, a negative input terminal, and an output terminal, and the second resistor R3 The other end is connected to the negative input terminal of the comparator D1, the preset reference voltage is input to the positive input terminal of the comparator D1, and the output terminal of the comparator D1 is connected to the isolation circuit 3, and outputs one.
  • the control signal is generated by the comparator D1 having a positive input terminal, a negative input terminal, and an output terminal, and the second resistor R3 The other end is connected to the negative input terminal of the comparator D1, the preset reference voltage is input to the positive input terminal of the comparator D1, and the output terminal of the comparator D1 is connected to the isolation circuit 3, and outputs one.
  • the control signal is: a comparator D1 having a positive input terminal, a negative input terminal, and an output terminal, and the second resistor R3 The other end is connected to the negative input terminal of the comparator D1, the preset reference voltage is input to the positive input terminal of
  • the isolation circuit 3 includes: an optical coupler having a first primary side and a first secondary side, and a first one of the optical coupler a first primary side circuit connected to the primary side and a first secondary side circuit connected to the first secondary side of the optical coupler;
  • the photocoupler may be that the first primary side is a light emitting diode and the first secondary side of the optical coupler is a phototransistor; or the first primary side may be a light emitting diode and the optical coupling
  • the first secondary side of the device is a photodiode.
  • the above is merely an example. Any device that can realize the transmission of the control signal from the primary side to the secondary side of the isolation circuit 3 is within the protection scope of the present invention. I will not give examples here.
  • the first primary side of the optical coupler is a light emitting diode and the first secondary side of the optical coupler is a phototransistor.
  • the first primary side circuit includes: a third resistor R4, a first diode VD1, a fourth resistor R5, a second capacitor C3, a first MOS transistor VT9, a fifth resistor R6, and a sixth resistor R7;
  • one end of the third resistor R4 is connected to an output end of the comparator D1, and the other end of the third resistor R4 is connected to an input end of the first diode VD1;
  • One end of the fourth resistor R5 is connected to one end of the second capacitor C3, the output end of the first diode VD1 is connected to one end of the fourth resistor R5, and the other end of the fourth resistor R5 One end is grounded to the other end of the second capacitor C3;
  • One end of the fourth resistor R5 is also connected to the gate of the first MOS transistor VT9;
  • the source of the first MOS transistor VT9 is grounded to the other end of the second capacitor C3;
  • the drain of the first MOS transistor VT9 is connected to the output end of the first primary side of the optical coupler
  • One end of the fifth resistor R6 is connected to one end of the sixth resistor R7, and one end of the fifth resistor R6 is also connected to the internal power supply voltage VCC, and the other end of the fifth resistor R6 is different from the sixth resistor R7.
  • One end is connected, and the other end of the fifth resistor R6 is further connected to an input end of the first primary side of the optical coupler;
  • the first secondary circuit includes: a seventh resistor R8, an eighth resistor R9, a ninth resistor R10, a third capacitor C4, a first transistor VT10, a fourth capacitor C5, and a tenth resistor R11;
  • the one end of the seventh resistor R8 is connected to the power supply voltage VDD, and the other end of the seventh resistor R8 is connected to the input end of the first secondary side of the optical coupler;
  • One end of the eighth resistor R9 is connected to an output end of the first secondary side of the optical coupler
  • One end of the third capacitor C4 is also connected to an output end of the first secondary side of the optical coupler
  • the other end of the ninth resistor R10 is connected to one end of the ninth resistor R10, and the other end of the ninth resistor R10 is grounded to the other end of the third capacitor C4;
  • the other end of the eighth resistor R9 is further connected to the base of the first transistor VT10, and the emitter of the first transistor VT10 is connected to the ground;
  • the fourth capacitor C5 and the tenth resistor R11 are connected in parallel between the collector of the first transistor VT10 and the ground, and one end of the fourth capacitor C5 is connected to one end of the tenth resistor R11.
  • the collector of the first transistor VT10 is connected to one end of the fourth capacitor C5, and the other end of the fourth capacitor C5 is connected to the other end of the tenth resistor R11;
  • the collector of the first transistor VT10 is also connected to a control signal of the driver circuit Number input;
  • the driving signal output end of the driver D3 is connected to the isolated power supply circuit 5, and outputs a driving signal through at least one driving signal output end, wherein the driver may have a driving signal output end of each of the multiple driving signal output ends.
  • the circuit that needs to be driven can be controlled.
  • the driving signal output end includes a first driving end and a second driving end
  • the secondary side of the isolated power supply circuit 5 is four MOS transistors, and
  • the four MOS transistors are divided into two groups of conduction, and one of the MOS transistors is connected to any one of the first driving end or the second driving end; the other group of MOS transistors, and the remaining one
  • the drive signal output is connected to complete the circuit connection of the drive control.
  • the driving circuit 4 includes: a driver ENABLE D3 having a control signal input end and a driving signal output end, wherein the driving signal output end is connected to the
  • the isolated power supply circuit 5 includes the first driving end DRIVE1 and the second driving end DRIVE2.
  • the isolated power supply circuit 5 includes: a transformer having a second primary side and a second secondary side;
  • a second primary side circuit connected to the second primary side, and the power input end of the second primary side circuit is connected to the sampling circuit 1;
  • a second secondary circuit connected to the second secondary side, and a gate of the plurality of synchronously rectified MOS transistor circuits of the second secondary circuit is connected to the drive signal output end of the driver.
  • the second primary side circuit includes: the second primary side circuit includes: a second MOS transistor VT21, a third MOS transistor VT22, fourth MOS transistor VT23 and fifth MOS transistor VT24;
  • the second MOS transistor VT21, the third MOS transistor VT22, the fourth MOS transistor VT23, and the fifth MOS transistor VT24 form a full bridge topology.
  • a gate of the second MOS transistor VT21 and a gate of the fifth MOS transistor VT24 are both connected to one terminal of an external driving chip;
  • a gate of the third MOS transistor VT22 and the fourth MOS transistor The gate of the VT23 is connected to the other terminal of the external driving chip;
  • the drain of the second MOS transistor VT21 is connected to the anode of the power input voltage
  • a source of the second MOS transistor VT21 is connected to a drain of the fourth MOS transistor VT23;
  • the drain of the fourth MOS transistor VT23 is also connected to one end of the second primary side of the first transformer T21;
  • a source of the fourth MOS transistor VT23 is connected to a cathode of the power input voltage
  • the source of the fourth MOS transistor VT23 is also connected to the source of the fifth MOS transistor VT24;
  • the drain of the fifth MOS transistor VT24 is connected to the other end of the second primary side of the first transformer T21;
  • the drain of the fifth MOS transistor VT24 is also connected to the source of the third MOS transistor VT22;
  • the drain of the third MOS transistor VT22 is connected to the drain of the second MOS transistor VT21;
  • the second secondary circuit includes:
  • a sixth MOS transistor VT25 a seventh MOS transistor VT26, an eighth MOS transistor VT27, a ninth MOS transistor VT28, an eleventh resistor R21, a first inductor L21 and a fifth capacitor C21;
  • the sixth MOS transistor VT25, the seventh MOS transistor VT26, the eighth MOS transistor VT27, and the ninth MOS transistor VT28 constitute a full bridge topology, and the gate and the gate of the sixth MOS transistor VT25
  • the gate of the ninth MOS transistor VT28 is selected from the first driving end DRIVE1 or the second driving end DRIVE2 of the driver a driving signal output terminal is connected; a gate of the eighth MOS transistor VT27 and a gate of the seventh MOS transistor VT26 are connected to another driving signal output end of the driver;
  • the drain of the seventh MOS transistor VT26 is connected to the source of the sixth MOS transistor VT25;
  • the drain of the sixth MOS transistor VT25 is connected to the drain of the eighth MOS transistor VT27, and the drain of the eighth MOS transistor VT27 is also connected to one end of the first inductor L21;
  • the other end of the first inductor L21 is connected to one end of the fifth capacitor C21, the fifth capacitor C21 is connected in parallel with the eleventh resistor R21, and one end of the fifth capacitor C21 is opposite to the eleventh One end of the resistor R21 is connected, the other end of the eleventh resistor R21 is connected to the other end of the fifth capacitor C21, and the other end of the fifth capacitor C21 is also connected to the source of the ninth MOS transistor VT28. a pole, the output voltage of the eleventh resistor R21 is outputted at both ends;
  • the drain of the ninth MOS transistor VT28 is connected to the source of the eighth MOS transistor VT27;
  • the drain of the ninth MOS transistor VT28 is further connected to one end of the second secondary side of the first transformer T21; the source of the ninth MOS transistor VT28 is connected to the source of the seventh MOS transistor VT26 ;
  • the drain of the seventh MOS transistor VT26 is also connected to the other end of the second secondary side of the first transformer T21.
  • the circuit of FIG. 2 is an anti-backflow irrigation circuit of the invention with fast input power-down according to FIG. 1 applied to an isolated power supply of a primary-side full-bridge topology secondary full-bridge synchronous rectification, including a synchronous rectifier (sixth MOS)
  • the specific working principle is to take the circuit working principle of the preferred embodiment of the present invention by taking FIG. 2 as an example.
  • the real-time sampling circuit 1 divides and collects the input voltage Vin through the first resistor R2 and the second resistor R3.
  • the operational amplifier D1 operates to output a high level.
  • the signal FS is input to the gate of the first MOS transistor VT9 through the third resistor R4 and the first diode VD1, and then the first MOS transistor VT9 is turned on, thereby isolating the optocoupler D2 to be turned on, and outputting high power.
  • the flat signal SHUT is connected to the base of the first transistor VT10, and the first transistor VT10 is turned on, pulling down the enable end signal ENABLE of the driver D3, causing the driving output to the secondary side of the driving signal of the first driving end DRIVE1 and
  • the second driving terminal DRIVE2 is turned off, and the sixth MOS transistor VT25, the seventh MOS transistor VT26, the eighth MOS transistor VT27, and the ninth MOS transistor VT28 of the secondary synchronous rectification MOS transistor are turned off, and the first driving terminal DRIVE1 of the driving signal is turned off.
  • the second driving terminal DRIVE2 terminal is connected to the sixth MOS transistor VT25 and the ninth MOS transistor VT28 of the rectifying MOS transistor, and the other driving signal output terminal is connected to the seventh MOS transistor VT26 and the eighth MOS transistor VT27. . Since the point set by the turn-off is to turn off the synchronous rectification MOS transistor when the inductor does not generate an additional negative current or the negative current is small, the smaller reverse current energy of the inductor is weak, and the synchronous rectification MOS is not caused. The tube stress exceeds the standard, thereby achieving the purpose of protecting the synchronous rectification MOS tube under the condition of input power failure, and improving the reliability of the power supply.
  • the second primary side circuit includes: a tenth MOS transistor VT31, an eleventh MOS transistor VT32, and a first Six capacitor C31 and seventh capacitor C32;
  • the tenth MOS transistor VT31, the eleventh MOS transistor VT32, the sixth capacitor C31, and the seventh capacitor C32 form a half bridge topology, and the gate of the tenth MOS transistor VT31 and the outside world a terminal of the driving chip is connected, and a gate of the eleventh MOS transistor VT32 is connected to another terminal of the external driving chip;
  • One end of the sixth capacitor C31 is connected to one end of the seventh capacitor C32, and one end of the sixth capacitor C31 is further connected to one end of the second primary side of the second transformer T31, and the other end of the sixth capacitor C31 is Connected to the positive pole of the power input voltage, the other end of the seventh capacitor C32 is connected to the negative pole of the power input voltage;
  • a drain of the tenth MOS transistor VT31 is connected to one end of the sixth capacitor C31, and a source of the tenth MOS transistor VT31 is connected to a drain of the eleventh MOS transistor VT32, the eleventh MOS
  • the drain of the transistor VT32 is also connected to the other end of the second primary side of the second transformer T31, and the source of the eleventh MOS transistor VT32 is connected to the other end of the seventh capacitor C32;
  • the second secondary circuit includes: a twelfth MOS transistor VT33, a thirteenth MOS transistor VT34, an eighth capacitor C33, a twelfth resistor R31 and a second inductor L31;
  • the gate of the thirteenth MOS transistor VT34 is connected to the first driving end DRIVE1 of the driver or the second driving end DRIVE2 is connected to a driving signal output end;
  • a gate of the twelfth MOS transistor VT33 is connected to another driving signal output end of the driver;
  • the source of the twelfth MOS transistor VT33 is connected to the source of the thirteenth MOS transistor VT34, and the drain of the twelfth MOS transistor VT33 is connected to one end of the second sub side of the second transformer T31. ;
  • the drain of the thirteenth MOS transistor VT34 is connected to the second transformer T31
  • the other end of the second side, the source of the thirteenth MOS transistor VT34 is connected to one end of the eighth capacitor C33, and one end of the eighth capacitor C33 is further connected to one end of the twelfth resistor R31.
  • the twelfth resistor R31 and the eighth capacitor C33 are connected in parallel, and the other end of the eighth capacitor C33 and the other end of the twelfth resistor R31 are connected to one end of the second inductor L31;
  • the other end of the second inductor L31 is connected to the second secondary side of the second transformer T31.
  • the second embodiment is applied to an isolated power supply in which the primary side is a full-wave synchronous rectification for the secondary side of the half bridge topology, and the working process is similar to that of the first embodiment.
  • the second primary side circuit includes:
  • the fourteenth MOS transistor VT41, the fifteenth MOS transistor VT42, the ninth capacitor C41, and the tenth capacitor C42 constitute an active clamp topology, and the fourteenth MOS transistor VT41 The gate is connected to one terminal of the external driving chip, and the gate of the fifteenth MOS transistor VT42 is connected to the other terminal of the external driving chip;
  • One end of the ninth capacitor C41 is connected to the anode of the power input voltage, and is connected to one end of the second primary side of the third transformer T41;
  • the other end of the ninth capacitor C41 is connected to a negative pole of the power input voltage
  • the other end of the ninth capacitor C41 is further connected to the source of the fourteenth MOS transistor VT41;
  • the drain of the fourteenth MOS transistor VT41 is connected to one end of the tenth capacitor C42, and the other end of the tenth capacitor C42 is connected to the other end of the second primary side of the third transformer T41;
  • the drain of the fifteenth MOS transistor VT42 is also connected to the third transformer T41 The other end of the second primary side;
  • the source of the fifteenth MOS transistor VT42 is also connected to the source of the fourteenth MOS transistor VT41;
  • the second secondary circuit includes: a sixteenth MOS transistor VT43, a seventeenth MOS transistor VT44, an eleventh capacitor C43, a thirteenth resistor R41 and a third inductor L41;
  • the first driving terminal DRIVE1 or the second driving terminal DRIVE2 of the driving signal output end of the driver is connected to the driving signal output terminal;
  • the gate of the seventeenth MOS transistor VT44 is connected to another driving signal output end of the driver;
  • a source of the sixteenth MOS transistor VT43 is connected to one end of the second secondary side of the third transformer T41, and a drain of the sixteenth MOS transistor VT43 is connected to one end of the third inductor L41;
  • the other end of the third inductor L41 is connected to one end of the thirteenth resistor R41, the thirteenth resistor R41 is connected in parallel with the eleventh capacitor C43, and the thirteenth resistor R41 is also connected at one end.
  • One end of the eleventh capacitor C43 is connected, the other end of the thirteenth resistor R41 is further connected to the other end of the eleventh capacitor C43, and the other end of the eleventh capacitor C43 is connected to the first a source of the seventeenth MOS transistor VT44, the output voltage of the thirteenth resistor R41;
  • the source of the seventeenth MOS transistor VT44 is connected to the other end of the second secondary side of the third transformer T41, and the drain of the seventeenth MOS transistor VT44 is also connected to one end of the third inductor L41. .
  • the third embodiment is applied to an isolated power supply in which the primary side is a synchronous clamped active side of the active clamp topology.
  • the The two primary circuits include: an eighteenth MOS transistor VT51, a nineteenth MOS transistor VT52, a twelfth capacitor C51 and a thirteenth capacitor C52;
  • the eighteenth MOS transistor VT51, the nineteenth MOS transistor VT52, the twelfth capacitor C51 and the thirteenth capacitor C52 constitute an active clamp circuit, and the eighteenth MOS transistor VT51 a gate is connected to a terminal of the external driving chip, and a gate of the nineteenth MOS transistor VT52 is connected to another terminal of the external driving chip;
  • One end of the twelfth capacitor C51 is connected to the anode of the power input voltage
  • the other end of the twelfth capacitor C51 is connected to a negative pole of the power input voltage
  • One end of the thirteenth capacitor C52 is connected to one end of the twelfth capacitor C51, and one end of the thirteenth capacitor C52 is further connected to one end of the second primary side of the fourth transformer T51;
  • the other end of the thirteenth capacitor C52 is connected to the drain of the eighteenth MOS transistor VT51;
  • the source of the eighteenth MOS transistor VT51 is connected to the other end of the second primary side of the fourth transformer T51;
  • a source of the eighteenth MOS transistor (VT51) is further connected to a drain of the nineteenth MOS transistor VT52;
  • the source of the nineteenth MOS transistor VT52 is connected to the other end of the twelfth capacitor C51;
  • the second secondary circuit includes: a twentieth MOS transistor VT53, a twenty-first MOS transistor VT54, a fourteenth capacitor C53, a fourteenth resistor R51 and a fourth inductor L51;
  • the gate of the twentieth MOS transistor VT53 is connected to the first driving end DRIVE1 of the driving signal output end of the driver or the second driving end DRIVE2 is connected with a driving signal output end;
  • the gate of the twenty-first MOS transistor VT54 is connected to another driving signal output end of the driver;
  • a source of the twentieth MOS transistor VT53 is connected to one end of the second secondary side of the fourth transformer T51, and a drain of the twentieth MOS transistor VT53 is connected to one end of the fourth inductor L51;
  • the other end of one end of the fourth inductor L51 is connected to one end of the fourteenth resistor R51, the fourteenth resistor R51 and the fourteenth capacitor C53 are connected in parallel, and one end of the fourteenth resistor R51 is further One end of the fourteenth capacitor C53 is connected, the other end of the fourteenth resistor R51 is further connected to the other end of the fourteenth capacitor C53, and the other end of the fourteenth capacitor C53 is connected to the The source of the twenty-first MOS transistor VT54 outputs a voltage across the fourteenth resistor R51;
  • the source of the 21st MOS transistor VT54 is connected to the other end of the second secondary side of the fourth transformer T51, and the drain of the 21st MOS transistor VT54 is also connected to the fourth inductor L51. One end.
  • clamp capacitance of the fourth embodiment is a flyback clamp
  • clamp capacitance of the third embodiment is a boost clamp
  • both primary sides are active clamp topologies, and vice
  • the side circuits are all synchronous rectification.
  • the second primary side circuit and the second secondary side circuit of the isolated power supply circuit 5 As shown in FIG. 6, in the apparatus for preventing current backflow according to the fifth embodiment of the present invention, the second primary side circuit and the second secondary side circuit of the isolated power supply circuit 5;
  • the second primary side circuit includes: a twenty-second MOS transistor VT61, a twenty-third MOS transistor VT62, a fifteenth capacitor C61 and a sixteenth capacitor C62;
  • the twenty-second MOS transistor VT61, the twenty-third MOS transistor VT62, the fifteenth capacitor C61, and the sixteenth capacitor C62 form a half bridge topology, and the twenty-second MOS transistor
  • the gate of the VT61 is connected to one terminal of the external driving chip, and the gate of the twenty-third MOS transistor VT62 is connected to the other terminal of the external driving chip;
  • the fifteenth capacitor C61 is connected to the positive pole of the power input voltage, the other end of the fifteenth capacitor C61 is connected to one end of the second primary side of the fifth transformer T61, and the fifteenth electric The other end of the capacitor C61 is connected to one end of the sixteenth capacitor C62, and the other end of the sixteenth capacitor C62 is connected to the cathode of the power input voltage;
  • the drain of the twenty-second MOS transistor VT61 is connected to one end of the fifteenth capacitor C61, and the source of the second twelve MOS transistor VT61 is connected to the drain of the twenty-third MOS transistor VT62.
  • the drain of the 23rd MOS transistor VT62 is further connected to the other end of the second primary side of the fifth transformer T61, and the source of the 23rd MOS transistor VT62 is connected to the 16th The other end of the capacitor C62;
  • the second secondary circuit includes: a twenty-fourth MOS transistor VT63, a twenty-fifth MOS transistor VT64, a twenty-sixth MOS transistor VT65, a twenty-seventh MOS transistor VT66, a fifteenth resistor R61, and a fifth inductor L61 and seventeenth capacitor C63;
  • the twenty-fourth MOS transistor VT63, the twenty-fifth MOS transistor VT64, the twenty-sixth MOS transistor VT65, and the twenty-seventh MOS transistor VT66 form a full bridge topology, and the second a gate of the MOS transistor VT63 and a gate of the 27th MOS transistor VT66 are connected to the first driving terminal DRIVE1 or the second driving terminal DRIVE2 of the driver; a gate of the twenty-sixth MOS transistor VT65 and a gate of the twenty-fifth MOS transistor VT64 are connected to another driving signal output end of the driver;
  • a drain of the twenty-fifth MOS transistor VT64 is connected to a source of the twenty-fourth MOS transistor VT63;
  • the drain of the twenty-fourth MOS transistor VT63 is connected to the drain of the second sixteen MOS transistor VT65, and the drain of the second sixteen MOS transistor VT65 is further connected to one end of the fifth inductor L61. on;
  • the other end of the fifth inductor L61 is connected to one end of the seventeenth capacitor C63, the seventeenth capacitor C63 is connected in parallel with the fifteenth resistor R61, and one end of the seventeenth capacitor C63 is also One end of the fifteenth resistor R61 is connected, and the other end of the seventeenth capacitor C63 is The other end of the fifteenth resistor R61 is connected, and the other end of the seventeenth capacitor C63 is further connected to the source of the twenty-seventh MOS transistor VT66 at both ends of the fifteenth resistor R61.
  • a drain of the twenty-seventh MOS transistor VT66 is connected to a source of the second sixteen MOS transistor VT65;
  • the drain of the twenty-seventh MOS transistor VT66 is further connected to one end of the second secondary side of the fifth transformer T61;
  • a source of the twenty-seventh MOS transistor VT66 is connected to a source of the twenty-fifth MOS transistor VT64;
  • the drain of the twenty-fifth MOS transistor VT64 is also connected to the other end of the second secondary side of the fifth transformer T61.
  • the difference from the circuit schematic of the second embodiment is that the secondary side of the second embodiment uses full-wave synchronous rectification, and the secondary side of the fifth embodiment uses full-bridge synchronous rectification, both of which have a half-bridge topology.
  • the second primary side circuit and the second secondary side circuit of the isolated power supply circuit 5 includes: a twenty-eighth MOS transistor VT71, a twenty-ninth MOS transistor VT72, a thirtieth MOS transistor VT73 and a thirty-first MOS transistor VT74;
  • the twenty-eighth MOS transistor VT71, the twenty-ninth MOS transistor VT72, the thirtieth MOS transistor VT73, and the thirty-first MOS transistor VT74 constitute a full bridge topology, and the gate of the twenty-eighth MOS transistor VT71 and The gate of the thirty-first MOS transistor VT74 is connected to one terminal of the external driving chip; the gate of the twenty-ninth MOS transistor VT72 and the gate of the thirtieth MOS transistor VT73 are both Connected to another terminal of the external driving chip;
  • a drain of the twenty-eighth MOS transistor VT71 is connected to a positive pole of the power input voltage
  • a source of the twenty-eighth MOS transistor VT71 is connected to a drain of the thirtieth MOS transistor VT73;
  • the drain of the thirtieth MOS transistor VT73 is further connected to one end of the second primary side of the sixth transformer T71;
  • a source of the thirtieth MOS transistor VT73 is connected to a negative pole of the power input voltage
  • the source of the thirtieth MOS transistor VT73 is also connected to the source of the thirty-first MOS transistor VT74;
  • the drain of the 31st MOS transistor VT74 is connected to the other end of the second primary side of the sixth transformer T71;
  • the drain of the thirty-first MOS transistor VT74 is also connected to the source of the twenty-ninth MOS transistor VT72;
  • the drain of the twenty-ninth MOS transistor VT72 is connected to the drain of the twenty-eighth MOS transistor VT71;
  • the second secondary circuit includes: a thirty-second MOS transistor VT75, a thirty-third MOS transistor VT76, an eighteenth capacitor C71, a sixteenth resistor R71 and a sixth inductor L71;
  • the gate of the thirty-three MOS transistor VT76 is connected to the first driving end DRIVE1 of the driver or the second driving end DRIVE2 is connected with a driving signal output end;
  • the gate of the thirty-second MOS transistor VT75 is connected to another driving signal output end of the driver;
  • the source of the thirty-second MOS transistor VT75 is connected to the source of the thirty-third MOS transistor VT76, and the drain of the thirty-second MOS transistor VT75 is connected to the sixth transformer T71 One end of the second side;
  • a drain of the thirty-third MOS transistor VT76 is connected to the sixth transformer T71
  • the other end of the second secondary side, the source of the thirteenth MOS transistor VT76 is connected to one end of the eighteenth capacitor C71, and one end of the eighteenth capacitor C71 is further connected to the tenth One end of the six resistor R71, outputting a voltage across the sixteenth resistor R71;
  • the sixteenth resistor R71 and the eighteenth capacitor C71 are connected in parallel, and the other end of the eighteenth capacitor C71 and the other end of the sixteenth resistor R71 are connected to one end of the sixth inductor L71;
  • the other end of the sixth inductor L71 is connected to the second secondary side of the sixth transformer T71.
  • the difference from the circuit schematic of the first embodiment is that the secondary side of the first embodiment uses full-bridge synchronous rectification, and the secondary side of the sixth embodiment uses full-wave synchronous rectification, both of which have a full-bridge topology.
  • the device for preventing current backflow can quickly react when the input voltage is powered off, and the comparison circuit 2 outputs a control signal to quickly turn off the secondary side synchronous rectification MOS tube of the isolated power supply circuit 5, so that It prevents the inductor from accumulating reverse current and causes avalanche breakdown damage of the MOS tube, and helps to improve the reliability of the product, thereby increasing the competitiveness and attractiveness of the product.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

L'invention concerne un dispositif permettant d'empêcher un courant de circuler vers l'arrière, comprenant un circuit d'échantillonnage (1), un circuit de comparaison (2), un circuit d'isolation (3) et un circuit d'attaque (4), le circuit d'échantillonnage échantillonnant la tension d'entrée de puissance d'un circuit de puissance d'isolation et transmettant un signal de tension échantillonnée obtenu au circuit de comparaison, le circuit de puissance d'isolation comportant une pluralité de transistors MOS de redressement synchrone, le circuit de comparaison comparant le signal de tension avec une tension de référence prédéfinie et transmettant un signal de commande selon un résultat de comparaison, le circuit d'isolation recevant le signal de commande et transmettant le signal de commande au circuit d'attaque, et le circuit d'attaque commandant l'état passant/bloqué de la pluralité de transistors MOS de redressement synchrone du circuit de puissance d'isolation selon le signal de commande. Le dispositif protège efficacement le transistor MOS de redressement synchrone.
PCT/CN2014/090191 2014-08-07 2014-11-03 Dispositif permettant d'empêcher le courant de circuler vers l'arrière WO2016019642A1 (fr)

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CN201410386535.7A CN105337483A (zh) 2014-08-07 2014-08-07 一种防止电流反灌的装置

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