WO2016008186A1 - 应用于2d-3d信号设置的栅极驱动电路 - Google Patents
应用于2d-3d信号设置的栅极驱动电路 Download PDFInfo
- Publication number
- WO2016008186A1 WO2016008186A1 PCT/CN2014/084331 CN2014084331W WO2016008186A1 WO 2016008186 A1 WO2016008186 A1 WO 2016008186A1 CN 2014084331 W CN2014084331 W CN 2014084331W WO 2016008186 A1 WO2016008186 A1 WO 2016008186A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- gate
- signal
- pull
- transistor
- module
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
- H04N13/30—Image reproducers
- H04N13/332—Displays for viewing with the aid of special glasses or head-mounted displays [HMD]
- H04N13/344—Displays for viewing with the aid of special glasses or head-mounted displays [HMD] with head-mounted left-right displays
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
- H04N13/30—Image reproducers
- H04N13/356—Image reproducers having separate monoscopic and stereoscopic modes
- H04N13/359—Switching between monoscopic and stereoscopic modes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
- G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
- G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
Definitions
- the present invention relates to the field of display technologies, and in particular, to a gate 3-zone dynamic circuit applied to a 2D-3D signal setting. Background technique
- the GOA Gate Driver on Array
- TFT Thin Film Transistor
- the functions of the GOA circuit mainly include: charging the capacitor in the shift register unit by using a high level signal outputted by the gate line of the previous row, so that the gate line of the current line outputs a high level signal, and then using the high output of the next line of the gate line output.
- the flat signal is reset.
- the GOA circuit transfer architecture is directly transferred from the current horizontal scanning line G(n) (n is a natural number) to the next lower horizontal scanning line G(n+1), and in the 3D display mode.
- GOA's circuit transmission architecture is transmitted from the current horizontal scanning line G(n) to the next two horizontal scanning lines G(n+2)
- the next horizontal scanning line G(n+1) maintains the same phase as the current horizontal scanning line G (>.
- a floating period of high frequency signal width is added between G(n), causing leakage problems.
- the signal transmission method generally adopted is the n-th stage to the n-th stage.
- FIG. 1 is a schematic diagram of a gate driving circuit architecture that currently uses GOA technology.
- the method includes: cascading a plurality of GOA units, and charging the display area Nth horizontal scanning line G(N) according to the Nth level GOA unit, the Nth stage GOA unit includes a pull-up control module 100, a pull-up module 200, The downlink module 300, the first pull-down module 400, the bootstrap capacitor module 500, and the pull-down holding module 600.
- the pull-up module 200, The first pull-down module 400, the pull-down maintaining module 600, and the bootstrap capacitor module 500 are electrically connected to the gate signal point Q(N) and the N-th horizontal scanning line G(N), respectively, and the pull-up control module 100
- the lowering module 300 is electrically connected to the gate signal point Q(N), and the pull-down maintaining module 600 inputs a DC low voltage VSS.
- the pull-up control module 100 includes a first transistor T1, the pull-up module 200 includes a second transistor ⁇ 2, the downlink module 300 includes a third transistor ⁇ 3, and the first pull-down module 400 includes a fourth transistor ⁇ 4 And the fifth transistor ⁇ 5, the bootstrap capacitor module 500 includes a capacitor Cb; the first transistor T1 includes a first gate gl, a first source s1, a first drain dl, and the second transistor T2 includes a second gate g2 , a second source s2, a second drain d2, the third transistor T3 includes a third gate g3 , a third source s3, a third drain d3, and the fourth transistor T4 The fourth gate g4, the fourth source s4, and the fourth drain d4, the fifth transistor T5 includes a fifth gate g5, a fifth source s5, and a fifth drain d5; Gl inputs a downlink signal ST(N-4) from the N-4th GOA unit, and the first drain dl is electrically connected to
- the fifth gate g5 is electrically connected to the N+4th horizontal scanning line G(N+4), and the fifth drain d5 is electrically connected to the gate signal point Q(N).
- the fifth source s5 is input to the DC low voltage VSS; the upper plate of the capacitor Cb is electrically connected to the gate signal point Q(N), and the lower plate of the capacitor Cb is electrically connected to the Nth Level horizontal scanning line G (N:).
- the first transistor T1, the second transistor ⁇ 2, the third transistor ⁇ 3, the fourth transistor ⁇ 4, and the fifth transistor ⁇ 5 are all thin film transistors.
- the circuit architecture shown in FIG. 1 is mainly for the connection scheme when the high-frequency clock signal GOA technology adopts eight high-frequency clock signal lines.
- the control signal of the pull-up control module 100 is mainly from the ⁇ -4.
- the horizontal scanning line G (N-4) is horizontal
- the control signal in the first pull-down module 400 is from the N+4 horizontal scanning line G (N+4).
- FIG. 2a is a timing diagram of signal transmission for the gate driving circuit shown in FIG. 1 in the 2D mode.
- the gate driving circuit uses eight high frequency clock signals CK1 ⁇ CK8, and two adjacent high frequency clock signals. A half pulse width between them.
- the first-stage high-frequency clock signal CK1 in FIG. 2a corresponds to the first rise of the N-4th horizontal scanning line G(N-4) and the gate signal point QN), and the fifth-stage high-frequency clock signal CK5 and Level N
- the horizontal scanning line G(N) corresponds to the second rise of the gate signal point Q(N).
- the transmission mode of the eight high-frequency clock signals CK is that the N-4th horizontal scanning line G(N-4) is transmitted to the Nth horizontal scanning line G(N;), but between the two signals There is a large time gap without any signal action, which causes a certain leakage gap between the first and second potential rises of the gate signal point Q(N), that is, the gate signal point Q (N). After the first potential rise, the potential will decrease again, which will seriously affect the second bootstrap effect of the gate signal point Q(N). If the leakage is severe under high temperature, it will affect the Nth horizontal scan line.
- the normal output of G(N). Please refer to FIG. 2b, a timing diagram for signal transmission of the gate driving circuit shown in FIG. 1 in the 3D mode.
- the gate driving circuit uses eight high frequency clock signals CK1 ⁇ CK8, wherein the first stage high frequency clock
- the signal CK1 is in the same phase as the second-stage high-frequency clock signal CK2
- the third-stage high-frequency clock signal CK3 is in the same phase as the fourth-stage high-frequency clock signal CK4
- the fifth-stage high-frequency clock signal CK5 and the sixth-stage high-frequency are
- the phase of the clock signal CK6 is the same
- the phase of the seventh-stage high-frequency clock signal CK7 and the eighth-stage high-frequency clock signal CK8 are the same, and the high-frequency clock signals between adjacent different phases are separated by half a pulse.
- the first-stage high-frequency clock signal CK1 and the second-stage high-frequency clock signal CK2 having the same phase in FIG. 2b and the N-th horizontal scanning line G(N-4) and the gate signal point Q(N)
- the fifth-stage high-frequency clock signal CK5 and the sixth-stage high-frequency clock signal CK6 having the same phase and the second-order horizontal scanning line G(N) and the second gate signal point Q(N)
- the second rise corresponds.
- the two high frequency clock signals CK are simultaneously output, if the N-4th horizontal scanning line G(N-4) is still transmitted to the Nth horizontal scanning line G ( N), there will be no leakage gap problem during signal transmission, and the gate signal point Q(N) can rise normally without significant potential loss.
- An object of the present invention is to provide a gate driving circuit applied to a 2D-3D signal setting, which solves the problem caused by the leakage gap during 2D signal transmission while avoiding the influence on the 3D signal transmission.
- the present invention provides a gate driving circuit applied to a 2D-3D signal setting, comprising: a plurality of cascaded GOA units, and controlling a display area according to an Nth-level GOA unit
- the Nth horizontal scanning line G(N) is charged, and the Nth stage GOA unit includes a pull-up control module, a pull-up module, a downlink module, a first pull-down module, a bootstrap capacitor module, a pull-down maintenance module, and a pull-up a compensation module;
- the pull-up module, the first pull-down module, the pull-down maintaining module, and the bootstrap capacitor module are electrically connected to the gate signal point Q(N) and the N-th horizontal scanning line G(N), respectively
- the pull-up control module, the downlink module and the pull-up compensation module are respectively electrically connected to the gate signal point Q(N), and the pull-down maintaining module inputs a DC low voltage VSS;
- the pull-up control module includes a first transistor T1, the pull-up module includes a second transistor T2, the down-transmission module includes a third transistor T3, and the first pull-down module includes a fourth transistor T4 and a fifth transistor.
- the bootstrap capacitor module includes a capacitor Cb;
- the first transistor T1 includes a first gate gl, a first source s1, a first drain dl, and the second transistor T2 includes a second gate g2 a second source s2, a second drain d2,
- the third transistor T3 includes a third gate g3, a third source s3, a third drain d3, and the fourth transistor T4 includes a fourth gate g4, a fourth source s4, a fourth drain d4,
- the fifth transistor T5 includes a fifth gate g5, a fifth source s5, and a fifth drain d5;
- the first gate gl is input to the N-4th stage downlink signal ST(N-4), and the first drain dl is electrically connected to the N-4th horizontal scanning line G(N-4).
- the first source is electrically connected to the gate signal point Q(N); the second gate g2 is electrically connected to the gate signal point Q(N;), and the second drain d2 is input.
- the m-th high-frequency clock signal CK(m;), the second source s2 is electrically connected to the N-th horizontal scanning line G(N);
- the third gate g3 is electrically connected to the gate a signal point Q(N), the third drain d3 is input to the mth-order high-frequency clock signal CK(m), and the third source s3 outputs an Nth-stage down-converting signal ST(N);
- the fourth gate g 4 is electrically connected to the N+4th horizontal scanning line G(N+4), and the fourth drain d4 is electrically connected to the Nth horizontal scanning line G(N), the fourth The source s4 is input to the DC low voltage VSS;
- the fifth gate g5 is electrically connected to the N+4th horizontal scan line G(N+4), and the fifth drain d5 is electrically connected to the gate a signal point Q(N), the fifth source s5 is input to the DC low voltage VSS;
- an upper plate of the capacitor Cb is electrically connected to
- the signal transmission mode adopted by the gate driving circuit is that the N-4th horizontal scanning line G(N-4) is transmitted to the Nth horizontal scanning line G(N); the high frequency clock signal CK is eight;
- the first transistor T1, the second transistor ⁇ 2, the third transistor ⁇ 3, the fourth transistor ⁇ 4, and the fifth transistor ⁇ 5 are all thin film transistors.
- the phase of the first-stage high-frequency clock signal CK1 and the second-stage high-frequency clock signal CK2 are the same, and the phase of the third-stage high-frequency clock signal CK3 and the fourth-stage high-frequency clock signal CK4 are Similarly, the fifth-stage high-frequency clock signal CK5 and the sixth-stage high-frequency clock signal CK6 have the same phase, and the seventh-stage high-frequency clock signal CK7 and the eighth-stage high-frequency clock signal CK8 have the same phase, and adjacent adjacent phases
- the high frequency clock signal is separated by a half pulse.
- the pull-up compensation module includes a sixth transistor T6, the sixth transistor ⁇ 6 includes a sixth gate g6, a sixth source s6, and a sixth drain d6, and the sixth gate g6 is input to the m-2th stage.
- a high frequency clock signal CK(m-2) the sixth drain d6 is electrically connected to the N-2th horizontal scanning line G(N-2) or the N-2th level downlink signal ST(N-2)
- the sixth source s6 is electrically connected to the gate signal point (3 ⁇ 4N) as an output terminal of the pull-up compensation module;
- the signal transmission mode adopted by the gate driving circuit is the N-4th horizontal scanning line G (N-4) is transmitted to the Nth horizontal scanning line G(N), or the N-4th downlink signal ST(N-4) is transmitted to the Nth stage downlink signal ST(N);
- the transistor T6 is a thin film transistor.
- the pull compensation module comprises a sixth transistor T6, a seventh transistor and a DC ⁇ 7 ,, and increases the DC control signal source; the sixth transistor T6 'includes a sixth gate g 6', sixth source s6 ' a sixth drain d6', the seventh transistor T7' includes a seventh gate g7 ', a seventh source s7', and a seventh drain d7', and the sixth gate g6' is input to the mth- a second-stage high-frequency clock signal CK(m-2), the sixth drain d6' and the seventh source s7' are electrically connected to the first circuit point DN;), the first circuit point D(N) For the input end of the sixth transistor T6', the sixth source s6' is electrically connected to the output terminal of the pull-up compensation module to the gate signal point Q(N), and the seventh gate g7' is input to the DC control.
- the signal source DC, the seventh drain d7' is electrically connected to the N-2th horizontal
- the DC control signal source DC controls the closing and opening of the pull-up compensation module.
- the DC control signal source DC provides a positive high potential to open the pull-up compensation module
- the DC control signal source DC provides a The negative pull-down compensation module is turned off in the negative direction.
- the signal transmission mode adopted by the gate driving circuit is that the N-4th horizontal scanning line G(N-4) is transmitted to the Nth horizontal scanning line G(N), or the N-4th horizontal transmission signal ST ( N-4) is transmitted to the Nth stage down signal ST N); the sixth transistor T6 and the seventh transistor ⁇ 7 are both thin film transistors.
- Pull compensation module comprises a sixth transistor ⁇ 6 "seventh transistor ⁇ 7", and an increase in the DC current control signal source; the sixth transistor T6 "includes a sixth gate g 6", sixth source s6 ", the first a sixth drain d6", the seventh transistor T7” includes a seventh gate g7 ", a seventh source s7", a seventh drain d7"; the sixth gate g6" input DC control signal source DC
- the sixth drain d6" and the seventh source s7" are electrically connected to the first circuit point DN;), the first circuit point DN) is the input end of the sixth transistor T6";
- the source s6" is electrically connected to the output terminal of the pull-up compensation module to the gate signal point Q(N;), and the seventh gate g7" is input to the m-2th high-frequency clock signal CK(m-2)
- the seventh drain d7 is electrically connected to the N-2th horizontal scanning line G(N-2) or the The N-2 stage transmits the
- the DC control signal source DC controls the closing and opening of the pull-up compensation module.
- the DC control signal source DC provides a positive high potential to open the pull-up compensation module
- the DC control signal source DC provides a The negative pull-down compensation module is turned off in the negative direction.
- the signal transmission mode adopted by the gate driving circuit is that the N-4th horizontal scanning line G(N-4) is transmitted to the Nth horizontal scanning line G(N), or the N-4th horizontal transmission signal ST ( N-4) is transmitted to the Nth stage down signal ST N); the sixth transistor T6" and the seventh transistor T7" are both thin film transistors.
- the present invention also provides a gate driving circuit applied to a 2D-3D signal setting, comprising: a plurality of cascaded GOA units, and controlling the Nth horizontal scanning line G(N) of the display area according to the Nth stage GOA unit control
- the Nth stage GOA unit includes a pull-up control module, a pull-up module, a downlink module, a first pull-down module, a bootstrap capacitor module, a pull-down maintenance module, and a pull-up compensation module; the pull-up module, the first The pull-up module, the pull-down maintaining module, and the bootstrap capacitor module are electrically connected to the gate signal point Q(N) and the N-th horizontal scanning line G(N), respectively, the pull-up control module, the downlink module, and the pull-up
- the compensation module is electrically connected to the gate signal point Q(N), and the pull-down maintaining module inputs a DC low voltage VSS;
- the pull-up control module includes a first transistor T1, the pull-up module includes a second transistor T2, the down-transmission module includes a third transistor T3, and the first pull-down module includes a fourth transistor T4 and a fifth transistor.
- the bootstrap capacitor module includes a capacitor Cb;
- the first transistor T1 includes a first gate gl, a first source s1, a first drain dl, and the second transistor T2 includes a second gate g2 a second source s2, a second drain d2,
- the third transistor T3 includes a third gate g3, a third source s3, and a third drain d3, and the fourth transistor T4 includes a fourth gate g4
- the fourth source s4, the fourth drain d4, the fifth transistor T5 includes a fifth gate g5, a fifth source s5, and a fifth drain d5;
- the first gate gl is input to the N-4th stage downlink signal ST(N-4), and the first drain dl is electrically connected to the N-4th horizontal scanning line G(N-4).
- the first source is electrically connected to the gate signal point Q(N); the second gate g2 is electrically connected to the gate signal point Q(N;), and the second drain d2 is input.
- the m-th high-frequency clock signal CK(m;), the second source s2 is electrically connected to the N-th horizontal scanning line G(N);
- the third gate g3 is electrically connected to the gate a signal point Q(N), the third drain d3 is input to the mth-level high-frequency clock signal CK(m;), and the third source s3 outputs an Nth-stage down-converting signal ST(N);
- the fourth gate g 4 is electrically connected to the N+4th horizontal scanning line G(N+4), and the fourth drain d4 is electrically connected to the Nth horizontal scanning line G(N),
- the fourth source g4 is electrically connected to the N+4th horizontal scanning line G(N+4), and the fifth drain d5 is electrically connected to the gate.
- the fifth source s5 inputs the DC low voltage VSS; the upper plate of the capacitor Cb is electrically connected to The gate signal point Q(N), the lower plate of the capacitor Cb is electrically connected to the Nth horizontal scanning line G(N);
- the signal transmission mode adopted by the gate driving circuit is that the N-4th horizontal scanning line G(N-4) is transmitted to the Nth horizontal scanning line G(N); the high frequency clock signal CK is eight;
- the first transistor T1, the second transistor ⁇ 2, the third transistor ⁇ 3, the fourth transistor ⁇ 4, and the fifth transistor ⁇ 5 are all thin film transistors;
- the phase of the first-stage high-frequency clock signal CK1 and the second-stage high-frequency clock signal CK2 are the same, and the phase of the third-stage high-frequency clock signal CK3 is the same as that of the fourth-stage high-frequency clock signal CK4, and the fifth stage is high.
- the frequency clock signal CK5 is in the same phase as the sixth-stage high-frequency clock signal CK6, and the seventh-stage high-frequency clock signal CK7 is in the same phase as the eighth-stage high-frequency clock signal CK8, and the high-frequency clock signals between adjacent different phases are separated.
- the pull-up compensation module includes a sixth transistor ⁇ 6, the sixth transistor ⁇ 6 includes a sixth gate g6, a sixth source s6, and a sixth drain d6, and the sixth gate g6 is input to the m-2th stage.
- a high frequency clock signal CK(m-2) the sixth drain d6 is electrically connected to the N-2th horizontal scanning line G(N-2) or the N-2th level downlink signal ST(N-2)
- the sixth source s6 is electrically connected to the gate signal point (3 ⁇ 4N) as an output terminal of the pull-up compensation module;
- the signal transmission mode adopted by the gate driving circuit is the N-4th horizontal scanning line G (N-4) is transmitted to the Nth horizontal scanning line G(N), or the N-4th downlink signal ST(N-4) is transmitted to the Nth stage downlink signal ST(N);
- the transistor T6 is a thin film transistor.
- the present invention provides a gate driving circuit applied to a 2D-3D signal setting, and a pull-up compensation module is added to an existing gate driving circuit using GOA technology, and the main function of the module It is to compensate the leakage gap existing when the 2D signal is transmitted, to ensure that the potential of the gate signal point Q(N) does not decrease during the leakage gap; to control the opening and closing of the pull-up compensation module by introducing an additional DC control signal source DC, It makes it work for compensation when it is turned on in 2D mode, and turns off in 3D mode to avoid the influence of 3D signal transmission, and thus effectively controls the pull-up compensation module.
- FIG. 1 is a schematic diagram of a gate driving circuit architecture currently using GOA technology
- FIG. 2a is a timing diagram of signal transmission of the gate driving circuit shown in FIG. 1 in 2D mode
- FIG. 2b is a timing diagram of signal transmission by the gate driving circuit shown in FIG. 1 in 3D mode
- FIG. 3 is an application of the present invention.
- FIG. 4 is a circuit diagram of a first embodiment of the gate driving circuit shown in FIG. 3;
- Figure 5 is a circuit diagram of a second embodiment of the gate driving circuit shown in Figure 3;
- FIG. 6 is a circuit diagram of a third embodiment of the gate driving circuit shown in FIG. 3;
- FIG. 7 is a timing chart of the gate driving circuit shown in FIGS. 5 and 6 in the 2D mode; and FIG. 8 is a timing chart of the gate driving circuit shown in FIGS. 5 and 6 in the 3D mode.
- FIG. 3 is a schematic diagram of a gate driving circuit structure applied to a 2D-3D signal setting according to the present invention.
- the method includes: cascading a plurality of GOA units, and charging the display area Nth horizontal scanning line G(N) according to the Nth stage GOA unit, the Nth stage GOA unit includes a pull-up control module 100, a pull-up module 200, The downlink module 300, the first pull-down module 400, the bootstrap capacitor module 500, the pull-down maintaining module 600, the pull-up compensation module 700 (Pull-up compensation part) o the pull-up module 200, the first pull-down module 400,
- the pull-down maintaining module 600 and the bootstrap capacitor module 500 are electrically connected to the gate signal point Q(N) and the N-th horizontal scanning line G(N), respectively, the pull-up control module 100, the downlink module 300 and the upper
- the pull compensation module 700 is electrically connected to the gate signal point Q(N), and the pull-down maintaining module 600 inputs a DC low
- the pull-up control module 100 includes a first transistor T1, the pull-up module 200 includes a second transistor ⁇ 2, the downlink module 300 includes a third transistor ⁇ 3, and the first pull-down module 400 includes a fourth transistor ⁇ 4.
- the bootstrap capacitor module 500 includes a capacitor Cb;
- the first transistor T1 includes a first gate gl, a first source s1, a first drain dl, and the second transistor T2 includes a second gate g2 , a second source s2, a second drain d2,
- the third transistor T3 includes a third gate g3, a third source s3, and a third drain d3, wherein the fourth transistor T4 includes a fourth gate g4, a fourth source s4, and a fourth drain d4,
- the fifth transistor T5 includes a fifth gate g5, a fifth source s5, and a fifth drain d5;
- the first drain dl is electrically connected
- the first transistor T1, the second transistor ⁇ 2, the third transistor ⁇ 3, the fourth transistor ⁇ 4, and the fifth transistor ⁇ 5 are all thin film transistors.
- the pull-up compensation module 700 can compensate for the leakage gap in the 2D mode to ensure that the potential of the gate signal point Q(N) does not decrease after the first rise in the 2D display mode.
- FIG. 4 is a circuit diagram of the first embodiment of the gate driving circuit shown in FIG.
- the first embodiment mainly performs the first design of the pull-up compensation module 700 shown in FIG. 3.
- the pull-up compensation module 700 includes a sixth transistor T6 for compensating for a leakage gap
- the sixth transistor ⁇ 6 includes a sixth gate g 6 , a sixth source s6 , and a sixth drain d6
- the sixth transistor T6 is a thin film transistor.
- the sixth gate g 6 is input to the m-2th high frequency clock signal CK(m-2), and the sixth drain d6 is electrically connected to the N-2th horizontal scanning line G(N-2) Or the N-2 stage downlink signal ST(N-2), the sixth source s6 is electrically connected to the gate signal point Q(N) as the output end of the pull-up compensation module 700, so that the N-2 horizontal scanning line G(N-2) to compensate the transmission gap between the N-4th horizontal scanning line G(N-4) and the Nth horizontal scanning line G(N), or to utilize the
- the N-2 stage transmits a signal ST(N-2) to compensate for the transmission gap between the N-4th downlink signal ST(N-4) and the Nth stage downlink signal ST(N).
- the leakage gap existing in the 2D signal transmission can be compensated in the 2D mode, and the potential of the gate signal point Q(N) does not decrease during the leakage gap, but the pull-up compensation module cannot be normally closed in the 3D mode. Indeed, it will affect the bootstrap action of the gate signal point Q(N) in 3D mode.
- FIG. 5 is a circuit diagram of a second embodiment of the gate driving circuit shown in FIG.
- the second embodiment mainly performs the second design of the pull-up compensation module 700 shown in FIG. 3.
- the pull-up compensation module 700 includes a sixth transistor T6 and a seventh transistor ⁇ 7, And adding a DC control signal source DC, the DC control signal source DC controls the closing and opening of the pull-up compensation module 700;
- the sixth transistor T6, and the seventh transistor ⁇ 7 are both thin film transistors, the sixth
- the transistor T6' includes a sixth gate g 6', a sixth source s6', and a sixth drain d6'.
- the seventh transistor T7' includes a seventh gate g 7', a seventh source s7', and a Seven drain d7';
- the sixth gate g6' is input to the m-2th high frequency clock signal CK(m-2), and the sixth drain d6' and the seventh source s7' are electrically connected to the first circuit point D ( N), that is, the first circuit point D(N) is the input end of the sixth transistor T6';
- the sixth source s6' is electrically connected to the gate signal point Q as the output end of the pull-up compensation module 700' ( N)
- the seventh gate g7' is input to the DC control signal source DC
- the seventh drain d7' is electrically connected to the N-2th horizontal scanning line G(N-2) or the N-2th stage Down signal ST(N-2);
- This design can compensate the N-4th horizontal scanning line G(N-4) and the Nth stage by using the N-2th horizontal scanning line G(N-2).
- the transmission gap between the horizontal scanning lines G(N) or the N-2 level downlink signal ST(N-2) is used to compensate the N-4th downlink signal ST(N-4) and the Nth stage.
- the transmission gap between the signals ST(N) is transmitted, and at the same time, it can be ensured that the DC control signal source DC provides a positive high potential to open the pull-up compensation module 700' in the 2D mode, and the DC control signal source DC is provided in the 3D mode.
- a negative low potential turns off the pull-up compensation module 700', which can both compensate and Free pull on the compensation module 700 'of the 3D signal transmission.
- FIG. 6 is a circuit diagram of a third embodiment of the gate driving circuit shown in FIG.
- the third embodiment mainly performs the third design of the pull-up compensation module 700 shown in FIG. 3.
- the pull-up compensation module 700" includes a sixth transistor T6" and a seventh transistor T7", And adding a DC control signal source DC, the DC control signal source DC controls the closing and opening of the pull-up compensation module 700";
- the sixth transistor T6" and the seventh transistor T7” are thin film transistors,
- the sixth The transistor T6" includes a sixth gate g 6", a sixth source s6", a sixth drain d6", and the seventh transistor T7” includes a seventh gate g 7", a seventh source s7", a seventh drain d7";
- the sixth gate g6" inputs a DC control signal source DC, and the sixth drain d6" and the seventh source s7" are electrically connected to the first circuit point D(N), that is,
- the first circuit point D(N) that
- the pull-up compensation module 700 of the first embodiment compensates for the leakage gap by a transistor.
- This design can compensate for the leakage gap existing in the 2D signal transmission only in the 2D mode, ensuring The potential of the gate signal point Q(N) does not decrease during the leakage gap; the pull-up compensation module 700' of the second embodiment and the pull-up compensation module 700" of the third embodiment both pass two transistors and introduce an additional
- the DC control signal source DC for controlling the pull-up compensation module 700' or 700" is turned on and turned on, thereby ensuring that the pull-up compensation module 700' or 700" in the 2D mode is compensated when the operation is turned on; in the 3D mode
- the pull compensation module 700' or 700" is turned off to avoid the effects on 3D signal transmission.
- the difference between the second embodiment and the third embodiment is that two crystals
- the gate terminal signal input of the tube is different.
- the sixth gate g6' of the sixth transistor T6' is input to the m-2th high frequency clock signal CK(m-2), and the seventh transistor T7, seven gate g 7, the DC input DC control signal source; and the third embodiment of the sixth transistor T6 "sixth gate g 6" DC control signal source input DC, the seventh transistor T7 "seventh gate g of 7" Input the m-2th high frequency clock signal CK(m-2).
- FIG. 7 is a timing diagram of the gate driving circuit shown in FIG. 5 and FIG. 6 in a 2D mode.
- the GOA circuit uses eight high frequency clock signals CK1 ⁇ CK8, adjacent to two. The high frequency clock signals are separated by a half pulse width.
- the working process of the present invention in the 2D mode is: the first stage high frequency clock signal CK1 and the N-4th horizontal scanning line G(N-4) or the N-4 level down signal ST (N-4), and the first rise of the gate signal point Q(N), the fifth stage high frequency clock signal CK5 and the Nth horizontal scanning line G(N) or the Nth stage down signal ST (N), corresponding to the second rise of the gate signal point Q(N); the third stage high frequency clock signal CK3 and the N-2th horizontal scanning line G(N-2) or the N-2th stage
- the downlink signal ST(N-2) corresponds to compensate for the transmission gap between the N-4th horizontal scanning line G(N-4) and the Nth horizontal scanning line G(N), or the N-4th
- the transfer gap between the stage down signal ST(N-4) and the Nth stage down signal ST(N) ensures the potential of the gate signal point Q(N) during the leakage gap (the position indicated by the dashed box in Fig.
- FIG. 8 is a timing diagram of the gate driving circuit shown in FIG. 5 and FIG. 6 in a 3D mode.
- the GOA circuit uses eight high frequency clock signals CK1 CK CK8 , wherein the first stage high frequency clock signal CK1
- the phase of CK6 is the same, the phase of the seventh-stage high-frequency clock signal CK7 is the same as that of the eighth-stage high-frequency clock signal CK8, and the high-frequency clock signals between adjacent different phases are separated by half a pulse.
- the working process of the present invention in the 3D mode is: the first-stage high-frequency clock signal CK1 and the second-stage high-frequency clock signal CK2 having the same phase and the N-th horizontal scanning line G (N) -4) or the first rise of the N-4 stage down signal ST(N-4) and the gate signal point Q(N), the fifth stage high frequency clock signal CK5 and the same phase having the same phase
- the sixth-stage high-frequency clock signal CK6 corresponds to the second rise of the Nth horizontal scanning line G(N) or the Nth stage down signal ST(N;), and the gate signal point ( ⁇ ).
- the DC control signal source DC needs to provide a negative low potential, in which case the 3D signal is due to the pull-up compensation module 700' or 700" effectively turned off. Passing is not subject to the pull-up compensation module 700' or 700" effect.
- the present invention provides a gate driving circuit applied to a 2D-3D signal setting, and a pull-up compensation module is added to the existing gate driving circuit using the GOA technology, and the main function of the module is Compensating for the leakage gap existing when the 2D signal is transmitted, ensuring that the potential of the gate signal point Q(N) does not decrease during the leakage gap; controlling the opening and closing of the pull-up compensation module by introducing an additional DC control signal source DC It works as a compensation when it is turned on in 2D mode, and is turned off in 3D mode to avoid the influence of 3D signal transmission, thereby effectively controlling the pull-up compensation module.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Shift Register Type Memory (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
一种应用于2D-3D信号设置的栅极驱动电路,包括:级联的多个GOA单元,按照第N级GOA单元控制对显示区域第N级水平扫描线G(N)充电,该第N级GOA单元包括上拉控制模块、上拉模块、下传模块、第一下拉模块、自举电容模块、下拉维持模块、上拉补偿模块;在现有的采用GOA技术的栅极驱动电路基础上增加一个上拉补偿模块,来补偿2D信号传递时存在的漏电间隙,确保漏电间隙期间栅极信号点Q(N)的电位不会降低;通过引入一条额外的直流控制信号源DC来控制上拉补偿模块的开启和关闭,使其在2D模式下打开工作时起到补偿工作,在3D模式下关闭以避免对3D信号传递的影响,进而有效的控制上拉补偿模块。
Description
应用于 2D-3D信号设置的栅极驱动电路
技术领域
本发明涉及显示技术领域, 尤其涉及一种应用于 2D-3D信号设置的栅 极 3区动电路。 背景技术
GOA (Gate Driver on Array, 阵列基板行驱动) 技术是将作为栅极开关 电路的 TFT (Thin Film Transistor, 薄膜场效应晶体管) 集成于阵列基板上, 从而省掉原先设置在阵列基板外的栅极驱动集成电路部分, 从材料成本和 工艺步骤两个方面来降低产品的成本。 GOA 技术是目前 TFT-LCD (Thin Film Transistor-Liquid Crystal Display, 薄膜场效应晶体管液晶显示器) 技术 领域常用的一种栅极驱动电路技术, 其制作工艺简单, 具有良好的应用前 景。 GOA电路的功能主要包括: 利用上一行栅线输出的高电平信号对移位 寄存器单元中的电容充电, 以使本行栅线输出高电平信号, 再利用下一行 栅线输出的高电平信号实现复位。
在 2D显示模式中, GOA的电路传递架构由当前级水平扫描线 G(n) (n 为自然数) 直接传递至其后的下一级水平扫描线 G(n+1), 而在 3D 显示模 式中 (需分别扫描显示左右眼图像), 由于扫描频率的升高, GOA 的电路 传递架构由当前级水平扫描线 G(n)传递至其后的下两级水平扫描线 G(n+2), 而下一级水平扫描线 G(n+1)保持与当前级水平扫描线 G( >相同的 相位。 如此一来, 在下两级水平扫描线 G(n+2)与当前级水平扫描线 G(n)之 间会多出一个高频信号宽度的悬浮期间 (floating period), 造成漏电问题。
对于大尺寸面板, 如果采用 GOA技术, 考虑到面板显示区域和 GOA 电路区域走线、 元件尺寸的寄生电容和电阻的负载较大, 一般会采用多条 高频时钟信号线来减轻 RC负载, 至少六条, 有的甚至采用八条。 对于八条 高频时钟信号线的 GOA电路, 一般采用的信号传递方式是第 n-4级传递给 第 n级。
请参阅图 1, 为目前常采用 GOA技术的栅极驱动电路架构示意图。 包 括: 级联的多个 GOA单元, 按照第 N级 GOA单元控制对显示区域第 N级 水平扫描线 G(N)充电, 该第 N级 GOA单元包括上拉控制模块 100、 上拉 模块 200、 下传模块 300、 第一下拉模块 400 (Key pull-down part)、 自举电 容模块 500、下拉維持模块 600 (Pull-down holding part)。所述上拉模块 200、
第一下拉模块 400、下拉維持模块 600及自举电容模块 500分别与栅极信号 点 Q(N)和该第 N级水平扫描线 G(N)电性连接, 所述上拉控制模块 100与 下传模块 300分别与该栅极信号点 Q(N)电性连接, 所述下拉維持模块 600 输入直流低电压 VSS。 所述上拉控制模块 100包括第一晶体管 Tl, 所述上 拉模块 200包括第二晶体管 Τ2, 所述下传模块 300包括第三晶体管 Τ3, 所 述第一下拉模块 400 包括第四晶体管 Τ4与第五晶体管 Τ5, 所述自举电容 模块 500包括电容 Cb;所述第一晶体管 T1包括第一栅极 gl、 第一源极 sl、 第一漏极 dl, 所述第二晶体管 T2包括第二栅极 g2、 第二源极 s2、 第二漏 极 d2, 所述第三晶体管 T3包括第三栅极 g3、 第三源极 s3、 第三漏极 d3, 所述第四晶体管 T4包括第四栅极 g4、 第四源极 s4、 第四漏极 d4, 所述第 五晶体管 T5包括第五栅极 g5、 第五源极 s5、 第五漏极 d5 ; 所述第一栅极 gl输入来自第 N-4级 GOA单元的下传信号 ST(N-4), 所述第一漏极 dl 电 性连接于第 N-4级水平扫描线 G(N-4), 所述第一源极 si电性连接于该栅极 信号点 Q(N) ; 所述第二栅极 g2电性连接于该栅极信号点 Q(N;), 所述第二 漏极 d2输入第 m级高频时钟信号 CK(m;), 所述第二源极 s2电性连接于第 N级水平扫描线 G(N); 所述第三栅极 g3电性连接于该栅极信号点 Q(N), 所述第三漏极 d3输入第 m级高频时钟信号 CK(m), 所述第三源极 s3输出 第 N级下传信号 ST(N) ;所述第四栅极 g4电性连接于第 N+4级水平扫描线 G(N+4), 所述第四漏极 d4电性连接于第 N级水平扫描线 G(N), 所述第四 源极 s4输入直流低电压 VSS ; 所述第五栅极 g5电性连接于第 N+4级水平 扫描线 G(N+4), 所述第五漏极 d5电性连接于该栅极信号点 Q(N), 所述第 五源极 s5输入该直流低电压 VSS ; 所述电容 Cb的上极板电性连接于该栅 极信号点 Q(N), 所述电容 Cb 的下极板电性连接于该第 N 级水平扫描线 G(N:)。 所述第一晶体管 Tl、 第二晶体管 Τ2、 第三晶体管 Τ3、 第四晶体管 Τ4、 第五晶体管 Τ5均为薄膜晶体管。如图 1所示的电路架构主要是针对大 尺寸液晶面板 GOA技术采用八个高频时钟信号线时的连接方案, 由图 1可 知,上拉控制模块 100的控制信号主要是来自第 Ν-4级水平扫描线 G(N-4), 而第一下拉模块 400中的控制信号来自第 N+4级水平扫描线 G(N+4)。
对于大尺寸面板, 如果还要考虑 2D显示和 3D显示信号切换的话, 不 同模式下的时钟信号设置还会存在一定的差异。 请参阅图 2a, 为 2D模式 下图 1 所示的栅极驱动电路进行信号传递的时序图, 该栅极驱动电路采用 了八个高频时钟信号 CK1~CK8, 相邻两个高频时钟信号之间相隔半个脉 宽。 图 2a中第一级高频时钟信号 CK1 与第 N-4级水平扫描线 G(N-4)及栅 极信号点 Q N)的第一次抬升相对应, 第五级高频时钟信号 CK5 与第 N级
水平扫描线 G(N)及栅极信号点 Q(N)的第二次抬升相对应。 在 2D模式下八 个高频时钟信号 CK的传递方式是第 N-4级水平扫描线 G(N-4)传递给第 N 级水平扫描线 G(N;), 但是两个信号之间会存在一个较大的时间间隙没有任 何信号作用, 这样会导致栅极信号点 Q(N)的第一次和第二次电位抬升之间 存在着一定的漏电间隙, 即栅极信号点 Q(N)在第一次电位抬升之后电位又 会降低, 严重影响栅极信号点 Q(N)第二次的自举作用, 如果在高温搡作下 漏电严重的话,还会影响第 N级水平扫描线 G(N)的正常输出。请参阅图 2 b, 为 3D模式下图 1所示的栅极驱动电路进行信号传递的时序图,该栅极驱动 电路采用了八个高频时钟信号 CK1~CK8, 其中第一级高频时钟信号 CK1 与第二级高频时钟信号 CK2的相位相同,第三级高频时钟信号 CK3与第四 级高频时钟信号 CK4的相位相同,第五级高频时钟信号 CK5与第六级高频 时钟信号 CK6的相位相同,第七级高频时钟信号 CK7与第八级高频时钟信 号 CK8的相位相同, 相邻的不同相位间的高频时钟信号相隔半个脉冲。 图 2b中具有相同相位的第一级高频时钟信号 CK1及第二级高频时钟信号 CK2 与第 N-4级水平扫描线 G(N-4)及栅极信号点 Q(N)的第一次抬升相对应, 具 有相同相位的第五级高频时钟信号 CK5及第六级高频时钟信号 CK6与第 N 级水平扫描线 G(N)及栅极信号点 Q(N)的第二次抬升相对应。在 3D模式下, 由于 3D画面显示的原因, 两个高频时钟信号 CK会同时输出, 如果依然是 第 N-4级水平扫描线 G(N-4)传递给第 N级水平扫描线 G(N),则不会存在信 号传递时的漏电间隙问题, 栅极信号点 Q(N)能够正常抬升而不会有明显的 电位损失。
因此, 如果将 GOA技术应用于大尺寸面板驱动, 且考虑到 2D和 3D 模式下的信号设置问题, 必须设计一种特殊的采用 GOA技术的栅极驱动电 路方案来解决如下问题: (1 )、 在 2D模式下, 需要补偿信号传递之间存在 的较大的漏电间隙问题; (2)、 在 3D模式下, 设计的采用 GOA技术的栅极 驱动电路还需要不影响这样的 3D信号传递; (3)、 确保 2D显示和 3D显示 下, 采用 GOA技术的栅极驱动电路均能正常工作。 发明内容
本发明的目的在于提供一种应用于 2D-3D信号设置的栅极驱动电路, 解决了 2D信号传递时漏电间隙带来的问题, 同时避免对 3D信号传递的影 响。
为实现上述目的, 本发明提供一种应用于 2D-3D信号设置的栅极驱动 电路, 包括: 级联的多个 GOA单元, 按照第 N级 GOA单元控制对显示区
域第 N级水平扫描线 G(N)充电, 该第 N级 GOA单元包括上拉控制模块、 上拉模块、 下传模块、 第一下拉模块、 自举电容模块、 下拉維持模块、 上 拉补偿模块; 所述上拉模块、 第一下拉模块、 下拉維持模块及自举电容模 块分别与栅极信号点 Q(N)和该第 N级水平扫描线 G(N)电性连接, 所述上 拉控制模块、下传模块及上拉补偿模块分别与该栅极信号点 Q(N)电性连接, 所述下拉維持模块输入直流低电压 VSS ;
所述上拉控制模块包括第一晶体管 Tl, 所述上拉模块包括第二晶体管 Τ2, 所述下传模块包括第三晶体管 Τ3, 所述第一下拉模块包括第四晶体管 Τ4与第五晶体管 Τ5, 所述自举电容模块包括电容 Cb; 所述第一晶体管 T1 包括第一栅极 gl、 第一源极 sl、 第一漏极 dl, 所述第二晶体管 T2包括第 二栅极 g2、 第二源极 s2、 第二漏极 d2, 所述第三晶体管 T3包括第三栅极 g3、 第三源极 s3、 第三漏极 d3, 所述第四晶体管 T4包括第四栅极 g4、 第 四源极 s4、 第四漏极 d4, 所述第五晶体管 T5包括第五栅极 g5、 第五源极 s5、 第五漏极 d5 ;
所述第一栅极 gl输入第 N-4级下传信号 ST(N-4),所述第一漏极 dl电 性连接于第 N-4级水平扫描线 G(N-4), 所述第一源极 si电性连接于该栅极 信号点 Q(N) ; 所述第二栅极 g2电性连接于该栅极信号点 Q(N;), 所述第二 漏极 d2输入第 m级高频时钟信号 CK(m;), 所述第二源极 s2电性连接于第 N级水平扫描线 G(N); 所述第三栅极 g3电性连接于该栅极信号点 Q(N), 所述第三漏极 d3输入该第 m级高频时钟信号 CK(m), 所述第三源极 s3输 出第 N级下传信号 ST(N);所述第四栅极 g4电性连接于第 N+4级水平扫描 线 G(N+4), 所述第四漏极 d4电性连接于第 N级水平扫描线 G(N), 所述第 四源极 s4输入该直流低电压 VSS ; 所述第五栅极 g5电性连接于第 N+4级 水平扫描线 G(N+4), 所述第五漏极 d5电性连接于该栅极信号点 Q(N), 所 述第五源极 s5输入该直流低电压 VSS ; 所述电容 Cb的上极板电性连接于 该栅极信号点 Q(N), 所述电容 Cb的下极板电性连接于该第 N级水平扫描 线 G(N)。
所述栅极驱动电路采用的信号传递方式是第 N-4级水平扫描线 G(N-4) 传递给第 N级水平扫描线 G(N) ; 所述高频时钟信号 CK为八个; 所述第一 晶体管 Tl、 第二晶体管 Τ2、 第三晶体管 Τ3、 第四晶体管 Τ4、 及第五晶体 管 Τ5均为薄膜晶体管。
在 2D模式下相邻两个高频时钟信号之间相隔半个脉宽。
在 3D模式下第一级高频时钟信号 CK1与第二级高频时钟信号 CK2的 相位相同,第三级高频时钟信号 CK3与第四级高频时钟信号 CK4的相位相
同, 第五级高频时钟信号 CK5与第六级高频时钟信号 CK6的相位相同, 第 七级高频时钟信号 CK7与第八级高频时钟信号 CK8的相位相同,相邻的不 同相位间的高频时钟信号相隔半个脉冲。
所述上拉补偿模块包括第六晶体管 T6, 所述第六晶体管 Τ6 包括第六 栅极 g6、 第六源极 s6、 第六漏极 d6, 所述第六栅极 g6输入第 m-2级高频 时钟信号 CK(m-2),所述第六漏极 d6电性连接于第 N-2级水平扫描线 G(N-2) 或第 N-2级下传信号 ST(N-2), 所述第六源极 s6作为上拉补偿模块的输出 端电性连接于栅极信号点(¾N); 所述栅极驱动电路采用的信号传递方式是 第 N-4级水平扫描线 G(N-4)传递给第 N级水平扫描线 G(N),或第 N-4级下 传信号 ST(N-4)传递给第 N级下传信号 ST(N) ; 所述第六晶体管 T6为薄膜 晶体管。
所述上拉补偿模块包括第六晶体管 T6,与第七晶体管 Τ7,, 并增加一条 直流控制信号源 DC;所述第六晶体管 T6'包括第六栅极 g6'、 第六源极 s6'、 第六漏极 d6', 所述第七晶体管 T7'包括第七栅极 g7'、 第七源极 s7'、 第七 漏极 d7', 所述第六栅极 g6'输入第 m-2级高频时钟信号 CK(m-2), 所述第 六漏极 d6'与第七源极 s7'电性连接于第一电路点 D N;), 所述第一电路点 D(N)为第六晶体管 T6'的输入端, 所述第六源极 s6'作为上拉补偿模块的输 出端电性连接于栅极信号点 Q(N), 所述第七栅极 g7'输入直流控制信号源 DC, 所述第七漏极 d7'电性连接于第 N-2级水平扫描线 G(N-2)或第 N-2级 下传信号 ST(N-2)。
所述直流控制信号源 DC控制上拉补偿模块的关闭和开启, 在 2D模式 下直流控制信号源 DC提供一个正向的高电位打开上拉补偿模块, 在 3D模 式下直流控制信号源 DC提供一个负向的低电位关闭上拉补偿模块。
所述栅极驱动电路采用的信号传递方式是第 N-4级水平扫描线 G(N-4) 传递给第 N级水平扫描线 G(N), 或第 N-4级下传信号 ST(N-4)传递给第 N 级下传信号 ST N);所述第六晶体管 T6,与第七晶体管 Τ7,均为薄膜晶体管。
上拉补偿模块包括第六晶体管 Τ6"与第七晶体管 Τ7", 并增加一条直 流控制信号源 DC; 所述第六晶体管 T6"包括第六栅极 g6"、 第六源极 s6"、 第六漏极 d6", 所述第七晶体管 T7"包括第七栅极 g7"、 第七源极 s7"、 第 七漏极 d7" ;所述第六栅极 g6"输入直流控制信号源 DC,所述第六漏极 d6" 与第七源极 s7"电性连接于第一电路点 D N;), 所述第一电路点 D N)为第六 晶体管 T6"的输入端;所述第六源极 s6"作为上拉补偿模块的输出端电性连 接于栅极信号点 Q(N;), 所述第七栅极 g7"输入第 m-2 级高频时钟信号 CK(m-2), 所述第七漏极 d7"电性连接于第 N-2 级水平扫描线 G(N-2)或第
N-2级下传信号 ST(N-2)。
所述直流控制信号源 DC控制上拉补偿模块的关闭和开启, 在 2D模式 下直流控制信号源 DC提供一个正向的高电位打开上拉补偿模块, 在 3D模 式下直流控制信号源 DC提供一个负向的低电位关闭上拉补偿模块。
所述栅极驱动电路采用的信号传递方式是第 N-4级水平扫描线 G(N-4) 传递给第 N级水平扫描线 G(N), 或第 N-4级下传信号 ST(N-4)传递给第 N 级下传信号 ST N);所述第六晶体管 T6"与第七晶体管 T7"均为薄膜晶体管。
本发明还提供一种应用于 2D-3D信号设置的栅极驱动电路, 包括: 级 联的多个 GOA单元,按照第 N级 GOA单元控制对显示区域第 N级水平扫 描线 G(N)充电, 该第 N级 GOA单元包括上拉控制模块、 上拉模块、 下传 模块、 第一下拉模块、 自举电容模块、 下拉維持模块、 上拉补偿模块; 所 述上拉模块、 第一下拉模块、 下拉維持模块及自举电容模块分别与栅极信 号点 Q(N)和该第 N级水平扫描线 G(N)电性连接, 所述上拉控制模块、 下 传模块及上拉补偿模块分别与该栅极信号点 Q(N)电性连接, 所述下拉維持 模块输入直流低电压 VSS ;
所述上拉控制模块包括第一晶体管 Tl, 所述上拉模块包括第二晶体管 Τ2, 所述下传模块包括第三晶体管 Τ3, 所述第一下拉模块包括第四晶体管 Τ4与第五晶体管 Τ5, 所述自举电容模块包括电容 Cb; 所述第一晶体管 T1 包括第一栅极 gl、 第一源极 sl、 第一漏极 dl, 所述第二晶体管 T2包括第 二栅极 g2、 第二源极 s2、 第二漏极 d2, 所述第三晶体管 T3包括第三栅极 g3、 第三源极 s3、 第三漏极 d3, 所述第四晶体管 T4包括第四栅极 g4、 第 四源极 s4、 第四漏极 d4, 所述第五晶体管 T5包括第五栅极 g5、 第五源极 s5、 第五漏极 d5 ;
所述第一栅极 gl输入第 N-4级下传信号 ST(N-4),所述第一漏极 dl电 性连接于第 N-4级水平扫描线 G(N-4), 所述第一源极 si电性连接于该栅极 信号点 Q(N) ; 所述第二栅极 g2电性连接于该栅极信号点 Q(N;), 所述第二 漏极 d2输入第 m级高频时钟信号 CK(m;), 所述第二源极 s2电性连接于第 N级水平扫描线 G(N); 所述第三栅极 g3电性连接于该栅极信号点 Q(N), 所述第三漏极 d3输入该第 m级高频时钟信号 CK(m;), 所述第三源极 s3输 出第 N级下传信号 ST(N);所述第四栅极 g4电性连接于第 N+4级水平扫描 线 G(N+4), 所述第四漏极 d4电性连接于第 N级水平扫描线 G(N), 所述第 四源极 s4输入该直流低电压 VSS ; 所述第五栅极 g5电性连接于第 N+4级 水平扫描线 G(N+4), 所述第五漏极 d5电性连接于该栅极信号点 Q(N), 所 述第五源极 s5输入该直流低电压 VSS ; 所述电容 Cb的上极板电性连接于
该栅极信号点 Q(N), 所述电容 Cb的下极板电性连接于该第 N级水平扫描 线 G(N);
所述栅极驱动电路采用的信号传递方式是第 N-4级水平扫描线 G(N-4) 传递给第 N级水平扫描线 G(N) ; 所述高频时钟信号 CK为八个; 所述第一 晶体管 Tl、 第二晶体管 Τ2、 第三晶体管 Τ3、 第四晶体管 Τ4、 及第五晶体 管 Τ5均为薄膜晶体管;
在 2D模式下相邻两个高频时钟信号之间相隔半个脉宽;
在 3D模式下第一级高频时钟信号 CK1与第二级高频时钟信号 CK2的 相位相同,第三级高频时钟信号 CK3与第四级高频时钟信号 CK4的相位相 同, 第五级高频时钟信号 CK5与第六级高频时钟信号 CK6的相位相同, 第 七级高频时钟信号 CK7与第八级高频时钟信号 CK8的相位相同,相邻的不 同相位间的高频时钟信号相隔半个脉冲;
所述上拉补偿模块包括第六晶体管 Τ6, 所述第六晶体管 Τ6 包括第六 栅极 g6、 第六源极 s6、 第六漏极 d6, 所述第六栅极 g6输入第 m-2级高频 时钟信号 CK(m-2),所述第六漏极 d6电性连接于第 N-2级水平扫描线 G(N-2) 或第 N-2级下传信号 ST(N-2), 所述第六源极 s6作为上拉补偿模块的输出 端电性连接于栅极信号点(¾N); 所述栅极驱动电路采用的信号传递方式是 第 N-4级水平扫描线 G(N-4)传递给第 N级水平扫描线 G(N),或第 N-4级下 传信号 ST(N-4)传递给第 N级下传信号 ST(N) ; 所述第六晶体管 T6为薄膜 晶体管。
本发明的有益效果: 本发明提供一种应用于 2D-3D信号设置的栅极驱 动电路,在现有的采用 GOA技术的栅极驱动电路基础上增加一个上拉补偿 模块, 该模块的主要作用就是补偿 2D信号传递时存在的漏电间隙, 确保漏 电间隙期间栅极信号点 Q(N)的电位不会降低; 通过引入一条额外的直流控 制信号源 DC来控制上拉补偿模块的开启和关闭, 使其在 2D模式下打开工 作时起到补偿工作, 在 3D模式下关闭以避免对 3D信号传递的影响, 进而 有效的控制上拉补偿模块。
为了能更进一步了解本发明的特征以及技术内容, 请参阅以下有关本 发明的详细说明与附图, 然而附图仅提供参考与说明用, 并非用来对本发 明加以限制。 附图说明
下面结合附图, 通过对本发明的具体实施方式详细描述, 将使本发明 的技术方案及其它有益效果显而易见。
附图中,
图 1为目前常采用 GOA技术的栅极驱动电路架构示意图;
图 2a为 2D模式下图 1所示的栅极驱动电路进行信号传递的时序图; 图 2b为 3D模式下图 1所示的栅极驱动电路进行信号传递的时序图; 图 3为本发明应用于 2D-3D信号设置的栅极驱动电路架构示意图; 图 4为图 3所示的栅极驱动电路第一实施例的电路图;
图 5为图 3所示的栅极驱动电路第二实施例的电路图;
图 6为图 3所示的栅极驱动电路第三实施例的电路图;
图 7为图 5与图 6所示的栅极驱动电路在 2D模式下的时序图; 图 8为图 5与图 6所示的栅极驱动电路在 3D模式下的时序图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果, 以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 3, 为本发明应用于 2D-3D信号设置的栅极驱动电路架构示 意图。 包括: 级联的多个 GOA单元, 按照第 N级 GOA单元控制对显示区 域第 N级水平扫描线 G(N)充电,该第 N级 GOA单元包括上拉控制模块 100、 上拉模块 200、 下传模块 300、 第一下拉模块 400、 自举电容模块 500、 下 拉維持模块 600、 上拉补偿模块 700 (Pull-up compensation part) o 所述上拉 模块 200、 第一下拉模块 400、 下拉維持模块 600及自举电容模块 500分别 与栅极信号点 Q(N)和该第 N级水平扫描线 G(N)电性连接, 所述上拉控制 模块 100、 下传模块 300及上拉补偿模块 700分别与该栅极信号点 Q(N)电 性连接, 所述下拉維持模块 600输入直流低电压 VSS。 所述上拉控制模块 100包括第一晶体管 Tl, 所述上拉模块 200包括第二晶体管 Τ2, 所述下传 模块 300 包括第三晶体管 Τ3, 所述第一下拉模块 400 包括第四晶体管 Τ4 与第五晶体管 Τ5, 所述自举电容模块 500 包括电容 Cb ; 所述第一晶体管 T1包括第一栅极 gl、 第一源极 sl、 第一漏极 dl, 所述第二晶体管 T2包括 第二栅极 g2、 第二源极 s2、 第二漏极 d2, 所述第三晶体管 T3包括第三栅 极 g3、 第三源极 s3、 第三漏极 d3, 所述第四晶体管 T4包括第四栅极 g4、 第四源极 s4、 第四漏极 d4, 所述第五晶体管 T5包括第五栅极 g5、 第五源 极 s5、 第五漏极 d5 ; 所述第一栅极 gl输入来自第 N-4级 GOA单元的下传 信号 ST(N-4), 所述第一漏极 dl电性连接于第 N-4级水平扫描线 G(N-4), 所述第一源极 si 电性连接于该栅极信号点 Q(N) ; 所述第二栅极 g2电性连 接于该栅极信号点 Q(N;), 所述第二漏极 d2 输入第 m 级高频时钟信号
CK(m), 所述第二源极 s2电性连接于第 N级水平扫描线 G(N); 所述第三栅 极 g3电性连接于该栅极信号点 Q(N), 所述第三漏极 d3输入第 m级高频时 钟信号 CK(m;), 所述第三源极 s3输出第 N级下传信号 ST(N) ; 所述第四栅 极 g4电性连接于第 N+4级水平扫描线 G(N+4),所述第四漏极 d4电性连接 于第 N级水平扫描线 G(N), 所述第四源极 s4输入该直流低电压 VSS ; 所 述第五栅极 g5电性连接于第 N+4级水平扫描线 G(N+4), 所述第五漏极 d5 电性连接于该栅极信号点 Q(N), 所述第五源极 s5输入该直流低电压 VSS ; 所述电容 Cb的上极板电性连接于该栅极信号点 Q(N),所述电容 Cb的下极 板电性连接于该第 N级水平扫描线 G(N) ;
所述第一晶体管 Tl、 第二晶体管 Τ2、 第三晶体管 Τ3、 第四晶体管 Τ4、 第五晶体管 Τ5均为薄膜晶体管。 所述上拉补偿模块 700可以补偿 2D模式 下的漏电间隙, 以确保在 2D显示模式下栅极信号点 Q(N)的第一次抬升后 电位不会降低。
请参阅图 4并结合图 3, 图 4为图 3所示的栅极驱动电路第一实施例的 电路图。 该第一实施例主要是将图 3 中所示的上拉补偿模块 700进行了第 一种设计, 本实施例中该上拉补偿模块 700 包括用于补偿漏电间隙的第六 晶体管 T6, 所述第六晶体管 Τ6包括第六栅极 g6、 第六源极 s6、 第六漏极 d6, 该第六晶体管 T6为薄膜晶体管。 所述第六栅极 g6输入第 m-2级高频 时钟信号 CK(m-2),所述第六漏极 d6电性连接于第 N-2级水平扫描线 G(N-2) 或第 N-2级下传信号 ST(N-2), 所述第六源极 s6作为上拉补偿模块 700的 输出端电性连接于栅极信号点 Q(N), 这样就可以利用第 N-2级水平扫描线 G(N-2),来补偿第 N-4级水平扫描线 G(N-4)和第 N级水平扫描线 G(N)之间 的传递间隙, 或者利用第 N-2级下传信号 ST(N-2), 来补偿第 N-4级下传信 号 ST(N-4)和第 N级下传信号 ST(N)之间的传递间隙。 本实施例在 2D模式 下能够补偿 2D信号传递时存在的漏电间隙,确保漏电间隙期间栅极信号点 Q(N)的电位不会降低, 但在 3D模式下该上拉补偿模块无法正常关闭, 严重 的话会影响 3D模式下栅极信号点 Q(N)的自举作用。
请参阅图 5并结合图 3, 图 5为图 3所示的栅极驱动电路第二实施例的 电路图。 该第二实施例主要是将图 3 中所示的上拉补偿模块 700进行了第 二种设计,本实施例中该上拉补偿模块 700,包括第六晶体管 T6,与第七晶体 管 Τ7,, 并增加一条直流控制信号源 DC, 所述直流控制信号源 DC控制上 拉补偿模块 700,的关闭和开启; 所述第六晶体管 T6,与第七晶体管 Τ7,均为 薄膜晶体管, 所述第六晶体管 T6'包括第六栅极 g6'、 第六源极 s6'、 第六漏 极 d6',所述第七晶体管 T7'包括第七栅极 g7'、第七源极 s7'、第七漏极 d7' ;
所述第六栅极 g6'输入第 m-2级高频时钟信号 CK(m-2), 所述第六漏极 d6' 与第七源极 s7'电性连接于第一电路点 D(N), 即第一电路点 D(N)为第六晶 体管 T6'的输入端; 所述第六源极 s6'作为上拉补偿模块 700'的输出端电性 连接于栅极信号点 Q(N), 所述第七栅极 g7'输入直流控制信号源 DC, 所述 第七漏极 d7'电性连接于第 N-2级水平扫描线 G(N-2)或第 N-2级下传信号 ST(N-2); 这样的设计可以利用第 N-2级水平扫描线 G(N-2), 来补偿第 N-4 级水平扫描线 G(N-4)和第 N级水平扫描线 G(N)之间的传递间隙,或者利用 第 N-2级下传信号 ST(N-2), 来补偿第 N-4级下传信号 ST(N-4)和第 N级下 传信号 ST(N)之间的传递间隙, 同时可以确保在 2D模式下直流控制信号源 DC提供一个正向的高电位打开上拉补偿模块 700', 在 3D模式下直流控制 信号源 DC提供一个负向的低电位关闭上拉补偿模块 700', 这样既可以起 到补偿作用又可以避免上拉补偿模块 700'对 3D信号传递的影响。
请参阅图 6并结合图 3, 图 6为图 3所示的栅极驱动电路第三实施例的 电路图。 该第三实施例主要是将图 3 中所示的上拉补偿模块 700进行了第 三种设计, 本实施例中该上拉补偿模块 700"包括第六晶体管 T6"与第七晶 体管 T7", 并增加一条直流控制信号源 DC, 所述直流控制信号源 DC控 制上拉补偿模块 700"的关闭和开启;所述第六晶体管 T6"与第七晶体管 T7" 均为薄膜晶体管, 所述第六晶体管 T6"包括第六栅极 g6"、 第六源极 s6"、 第六漏极 d6", 所述第七晶体管 T7"包括第七栅极 g7"、 第七源极 s7"、 第 七漏极 d7" ;所述第六栅极 g6"输入直流控制信号源 DC,所述第六漏极 d6" 与第七源极 s7"电性连接于第一电路点 D(N), 即第一电路点 D(N)为第六晶 体管 T6"的输入端; 所述第六源极 s6"作为上拉补偿模块 700"的输出端电 性连接于栅极信号点 Q(N;), 所述第七栅极 g7"输入第 m-2级高频时钟信号 CK(m-2), 所述第七漏极 d7"电性连接于第 N-2 级水平扫描线 G(N-2)或第 N-2级下传信号 ST(N-2)。本实施例与第二实施例可以起到同样的补偿效果, 且不影响 3D信号的传递。
由图 4、 图 5、 及图 6可知, 第一实施例的上拉补偿模块 700通过一个 晶体管来补偿漏电间隙, 这种设计仅在 2D模式下能够补偿 2D信号传递时 存在的漏电间隙, 确保漏电间隙期间栅极信号点 Q(N)的电位不降低; 第二 实施例的上拉补偿模块 700'与第三实施例上拉补偿模块 700"均是通过两个 晶体管, 并引入一条额外的用于控制上拉补偿模块 700'或 700"关闭与开启 的直流控制信号源 DC, 进而确保在 2D模式下上拉补偿模块 700'或 700" 打开工作时起到补偿作用; 在 3D模式下上拉补偿模块 700'或 700"关闭以 避免对 3D信号传递的影响。第二实施例与第三实施例的差别在于两个晶体
管的栅极端信号输入不一样, 第二实施例中第六晶体管 T6'的第六栅极 g6' 输入第 m-2级高频时钟信号 CK(m-2), 第七晶体管 T7,的第七栅极 g7,输入 直流控制信号源 DC; 而第三实施例中第六晶体管 T6"的第六栅极 g6"输入 直流控制信号源 DC, 第七晶体管 T7"的第七栅极 g7"输入第 m-2级高频时 钟信号 CK(m-2)。
请参阅图 7并结合图 2a, 图 7为图 5与图 6所示的栅极驱动电路在 2D 模式下的时序图, 该 GOA电路采用了八个高频时钟信号 CK1~CK8, 相邻 两个高频时钟信号之间相隔半个脉宽。 具体地, 可以看出本发明在 2D模式 下的工作过程为: 第一级高频时钟信号 CK1与第 N-4级水平扫描线 G(N-4) 或第 N-4级下传信号 ST(N-4)、 及栅极信号点 Q(N)的第一次抬升相对应, 第五级高频时钟信号 CK5 与第 N级水平扫描线 G(N)或第 N级下传信号 ST(N),及栅极信号点 Q(N)的第二次抬升相对应;第三级高频时钟信号 CK3 与第 N-2级水平扫描线 G(N-2) 或第 N-2级下传信号 ST(N-2)相对应, 来补 偿第 N-4级水平扫描线 G(N-4)与第 N级水平扫描线 G(N)之间的传递间隙, 或者第 N-4级下传信号 ST(N-4)与第 N级下传信号 ST(N)之间的传递间隙, 确保漏电间隙期间栅极信号点 Q(N)的电位 (图 7中虚线框指示的位置) 不 会降低。 与图 2a相比可以看出, 栅极信号点 Q(N)的波形由于上拉补偿模块 700'或 700"的作用不会在漏电间隙期间产生电位下降, 此时直流控制信号 源 DC 需要提供一个正向的高电位, 主要负责开启上拉补偿模块 700,或 700"。
请参阅图 8,为图 5与图 6所示的栅极驱动电路在 3D模式下的时序图, 该 GOA电路采用了八个高频时钟信号 CK1~CK8, 其中第一级高频时钟信 号 CK1与第二级高频时钟信号 CK2的相位相同,第三级高频时钟信号 CK3 与第四级高频时钟信号 CK4的相位相同,第五级高频时钟信号 CK5与第六 级高频时钟信号 CK6的相位相同,第七级高频时钟信号 CK7与第八级高频 时钟信号 CK8的相位相同, 相邻的不同相位间的高频时钟信号相隔半个脉 冲。 具体地, 可以看出本发明在 3D模式下的工作过程为: 具有相同相位的 第一级高频时钟信号 CK1及第二级高频时钟信号 CK2与第 N-4级水平扫描 线 G(N-4)或第 N-4级下传信号 ST(N-4)、 及栅极信号点 Q(N)的第一次抬升 相对应, 具有相同相位的第五级高频时钟信号 CK5及第六级高频时钟信号 CK6与第 N级水平扫描线 G(N) 或第 N级下传信号 ST(N;)、 及栅极信号点 (^Ν)的第二次抬升相对应。 为了确保上拉补偿模块 700'或 700"能够关闭, 直流控制信号源 DC需要提供一个负向的低电位,在这种情况下由于上拉补 偿模块 700'或 700"有效的关闭, 则 3D信号传递不会受到该上拉补偿模块
700'或 700"的影响。
综上所述, 本发明提供一种应用于 2D-3D信号设置的栅极驱动电路, 在现有的采用 GOA技术的栅极驱动电路基础上增加一个上拉补偿模块,该 模块的主要作用就是补偿 2D信号传递时存在的漏电间隙,确保漏电间隙期 间栅极信号点 Q(N)的电位不会降低; 通过引入一条额外的直流控制信号源 DC来控制上拉补偿模块的开启和关闭, 使其在 2D模式下打开工作时起到 补偿工作, 在 3D模式下关闭以避免对 3D信号传递的影响, 进而有效的控 制上拉补偿模块。
以上所述, 对于本领域的普通技术人员来说, 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形, 而所有这些改变和变形 都应属于本发明权利要求的保护范围。
Claims
1、 一种应用于 2D-3D 信号设置的栅极驱动电路, 包括: 级联的多个 GOA单元,按照第 N级 GOA单元控制对显示区域第 N级水平扫描线充电, 该第 N级 GOA单元包括上拉控制模块、 上拉模块、 下传模块、 第一下拉模 块、 自举电容模块、 下拉維持模块、 上拉补偿模块; 所述上拉模块、 第一 下拉模块、 下拉維持模块及自举电容模块分别与栅极信号点和该第 N级水 平扫描线电性连接, 所述上拉控制模块、 下传模块及上拉补偿模块分别与 该栅极信号点电性连接, 所述下拉維持模块输入直流低电压;
所述上拉控制模块包括第一晶体管, 所述上拉模块包括第二晶体管, 所述下传模块包括第三晶体管, 所述第一下拉模块包括第四晶体管与第五 晶体管, 所述自举电容模块包括电容; 所述第一晶体管包括第一栅极、 第 一源极、 第一漏极, 所述第二晶体管包括第二栅极、 第二源极、 第二漏极, 所述第三晶体管包括第三栅极、 第三源极、 第三漏极, 所述第四晶体管包 括第四栅极、 第四源极、 第四漏极, 所述第五晶体管包括第五栅极、 第五 源极、 第五漏极;
所述第一栅极输入第 N-4级下传信号,所述第一漏极电性连接于第 N-4 级水平扫描线, 所述第一源极电性连接于该栅极信号点; 所述第二栅极电 性连接于该栅极信号点, 所述第二漏极输入第 m级高频时钟信号, 所述第 二源极电性连接于第 N级水平扫描线; 所述第三栅极电性连接于该栅极信 号点, 所述第三漏极输入该第 m级高频时钟信号, 所述第三源极输出第 N 级下传信号; 所述第四栅极电性连接于第 N+4级水平扫描线, 所述第四漏 极电性连接于第 N级水平扫描线, 所述第四源极输入该直流低电压; 所述 第五栅极电性连接于第 N+4级水平扫描线, 所述第五漏极电性连接于该栅 极信号点, 所述第五源极输入该直流低电压; 所述电容的上极板电性连接 于该栅极信号点, 所述电容的下极板电性连接于该第 N级水平扫描线。
2、如权利要求 1所述的应用于 2D-3D信号设置的栅极驱动电路,其中, 所述栅极驱动电路采用的信号传递方式是第 N-4级水平扫描线传递给第 N 级水平扫描线; 所述高频时钟信号为八个; 所述第一晶体管、 第二晶体管、 第三晶体管、 第四晶体管、 及第五晶体管均为薄膜晶体管。
3、如权利要求 2所述的应用于 2D-3D信号设置的栅极驱动电路,其中, 在 2D模式下相邻两个高频时钟信号之间相隔半个脉宽。
4、如权利要求 2所述的应用于 2D-3D信号设置的栅极驱动电路,其中,
在 3D模式下第一级高频时钟信号与第二级高频时钟信号的相位相同, 第三 级高频时钟信号与第四级高频时钟信号的相位相同, 第五级高频时钟信号 与第六级高频时钟信号的相位相同, 第七级高频时钟信号与第八级高频时 钟信号的相位相同, 相邻的不同相位间的高频时钟信号相隔半个脉冲。
5、如权利要求 1所述的应用于 2D-3D信号设置的栅极驱动电路,其中, 所述上拉补偿模块包括第六晶体管, 所述第六晶体管包括第六栅极、 第六 源极、 第六漏极, 所述第六栅极输入第 m-2 级高频时钟信号, 所述第六漏 极电性连接于第 N-2级水平扫描线或第 N-2级下传信号, 所述第六源极作 为上拉补偿模块的输出端电性连接于栅极信号点; 所述栅极驱动电路采用 的信号传递方式是第 N-4级水平扫描线传递给第 N级水平扫描线,或第 N-4 级下传信号传递给第 N级下传信号; 所述第六晶体管为薄膜晶体管。
6、如权利要求 1所述的应用于 2D-3D信号设置的栅极驱动电路,其中, 所述上拉补偿模块包括第六晶体管与第七晶体管, 并增加一条直流控制信 号源; 所述第六晶体管包括第六栅极、 第六源极、 第六漏极, 所述第七晶 体管包括第七栅极、 第七源极、 第七漏极, 所述第六栅极输入第 m-2 级高 频时钟信号, 所述第六漏极与第七源极电性连接于第一电路点, 所述第一 电路点为第六晶体管的输入端, 所述第六源极作为上拉补偿模块的输出端 电性连接于栅极信号点, 所述第七栅极输入直流控制信号源, 所述第七漏 极电性连接于第 N-2级水平扫描线或第 N-2级下传信号。
7、如权利要求 6所述的应用于 2D-3D信号设置的栅极驱动电路,其中, 所述直流控制信号源控制上拉补偿模块的关闭和开启,在 2D模式下直流控 制信号源提供一个正向的高电位打开上拉补偿模块,在 3D模式下直流控制 信号源提供一个负向的低电位关闭上拉补偿模块。
8、如权利要求 6所述的应用于 2D-3D信号设置的栅极驱动电路,其中, 所述栅极驱动电路采用的信号传递方式是第 N-4级水平扫描线传递给第 N 级水平扫描线, 或第 N-4级下传信号传递给第 N级下传信号; 所述第六晶 体管与第七晶体管均为薄膜晶体管。
9、如权利要求 1所述的应用于 2D-3D信号设置的栅极驱动电路,其中, 上拉补偿模块包括第六晶体管与第七晶体管, 并增加一条直流控制信号源; 所述第六晶体管包括第六栅极、 第六源极、 第六漏极, 所述第七晶体管包 括第七栅极、 第七源极、 第七漏极; 所述第六栅极输入直流控制信号源, 所述第六漏极与第七源极电性连接于第一电路点, 所述第一电路点为第六 晶体管的输入端; 所述第六源极作为上拉补偿模块的输出端电性连接于栅 极信号点, 所述第七栅极输入第 m-2 级高频时钟信号, 所述第七漏极电性
连接于第 N-2级水平扫描线或第 N-2级下传信号。
10、 如权利要求 9所述的应用于 2D-3D信号设置的栅极驱动电路, 其 中, 所述直流控制信号源控制上拉补偿模块的关闭和开启, 在 2D模式下直 流控制信号源提供一个正向的高电位打开上拉补偿模块,在 3D模式下直流 控制信号源提供一个负向的低电位关闭上拉补偿模块。
11、 如权利要求 9所述的应用于 2D-3D信号设置的栅极驱动电路, 其 中, 所述栅极驱动电路采用的信号传递方式是第 N-4 级水平扫描线传递给 第 N级水平扫描线, 或第 N-4级下传信号传递给第 N级下传信号; 所述第 六晶体管与第七晶体管均为薄膜晶体管。
12、 一种应用于 2D-3D信号设置的栅极驱动电路, 包括: 级联的多个
GOA单元,按照第 N级 GOA单元控制对显示区域第 N级水平扫描线充电, 该第 N级 GOA单元包括上拉控制模块、 上拉模块、 下传模块、 第一下拉模 块、 自举电容模块、 下拉維持模块、 上拉补偿模块; 所述上拉模块、 第一 下拉模块、 下拉維持模块及自举电容模块分别与栅极信号点和该第 N级水 平扫描线电性连接, 所述上拉控制模块、 下传模块及上拉补偿模块分别与 该栅极信号点电性连接, 所述下拉維持模块输入直流低电压;
所述上拉控制模块包括第一晶体管, 所述上拉模块包括第二晶体管, 所述下传模块包括第三晶体管, 所述第一下拉模块包括第四晶体管与第五 晶体管, 所述自举电容模块包括电容; 所述第一晶体管包括第一栅极、 第 一源极、 第一漏极, 所述第二晶体管包括第二栅极、 第二源极、 第二漏极, 所述第三晶体管包括第三栅极、 第三源极、 第三漏极, 所述第四晶体管包 括第四栅极、 第四源极、 第四漏极, 所述第五晶体管包括第五栅极、 第五 源极、 第五漏极;
所述第一栅极输入第 N-4级下传信号,所述第一漏极电性连接于第 N-4 级水平扫描线, 所述第一源极电性连接于该栅极信号点; 所述第二栅极电 性连接于该栅极信号点, 所述第二漏极输入第 m级高频时钟信号, 所述第 二源极电性连接于第 N级水平扫描线; 所述第三栅极电性连接于该栅极信 号点, 所述第三漏极输入该第 m级高频时钟信号, 所述第三源极输出第 N 级下传信号; 所述第四栅极电性连接于第 N+4级水平扫描线, 所述第四漏 极电性连接于第 N级水平扫描线, 所述第四源极输入该直流低电压; 所述 第五栅极电性连接于第 N+4级水平扫描线, 所述第五漏极电性连接于该栅 极信号点, 所述第五源极输入该直流低电压; 所述电容的上极板电性连接 于该栅极信号点, 所述电容的下极板电性连接于该第 N级水平扫描线; 其中, 所述栅极驱动电路采用的信号传递方式是第 N-4 级水平扫描线
传递给第 N级水平扫描线; 所述高频时钟信号为八个; 所述第一晶体管、 第二晶体管、 第三晶体管、 第四晶体管、 及第五晶体管均为薄膜晶体管; 其中, 在 2D模式下相邻两个高频时钟信号之间相隔半个脉宽; 其中,在 3D模式下第一级高频时钟信号与第二级高频时钟信号的相位 相同, 第三级高频时钟信号与第四级高频时钟信号的相位相同, 第五级高 频时钟信号与第六级高频时钟信号的相位相同, 第七级高频时钟信号与第 八级高频时钟信号的相位相同, 相邻的不同相位间的高频时钟信号相隔半 个脉冲;
其中, 所述上拉补偿模块包括第六晶体管, 所述第六晶体管包括第六 栅极、 第六源极、 第六漏极, 所述第六栅极输入第 m-2 级高频时钟信号, 所述第六漏极电性连接于第 N-2级水平扫描线或第 N-2级下传信号, 所述 第六源极作为上拉补偿模块的输出端电性连接于栅极信号点; 所述栅极驱 动电路采用的信号传递方式是第 N-4级水平扫描线传递给第 N级水平扫描 线, 或第 N-4级下传信号传递给第 N级下传信号; 所述第六晶体管为薄膜 晶体管。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/398,739 US9472150B1 (en) | 2014-07-15 | 2014-08-14 | Gate driving circuit applied for 2D-3D signal setting |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410337587.5 | 2014-07-15 | ||
CN201410337587.5A CN104091577B (zh) | 2014-07-15 | 2014-07-15 | 应用于2d-3d信号设置的栅极驱动电路 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2016008186A1 true WO2016008186A1 (zh) | 2016-01-21 |
Family
ID=51639287
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2014/084331 WO2016008186A1 (zh) | 2014-07-15 | 2014-08-14 | 应用于2d-3d信号设置的栅极驱动电路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9472150B1 (zh) |
CN (1) | CN104091577B (zh) |
WO (1) | WO2016008186A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104575439A (zh) * | 2015-02-15 | 2015-04-29 | 北京京东方多媒体科技有限公司 | 一种显示补偿方法、装置及显示设备 |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160017279A (ko) * | 2014-08-01 | 2016-02-16 | 삼성디스플레이 주식회사 | 표시 장치 |
CN104575420B (zh) * | 2014-12-19 | 2017-01-11 | 深圳市华星光电技术有限公司 | 一种扫描驱动电路 |
CN104700801B (zh) * | 2015-03-24 | 2016-11-02 | 深圳市华星光电技术有限公司 | Pmos栅极驱动电路 |
CN104934002B (zh) * | 2015-06-04 | 2018-03-27 | 武汉华星光电技术有限公司 | 一种扫描驱动电路 |
CN106297624B (zh) * | 2015-06-11 | 2020-03-17 | 南京瀚宇彩欣科技有限责任公司 | 移位寄存器和显示装置 |
CN105204249B (zh) * | 2015-10-29 | 2018-07-17 | 深圳市华星光电技术有限公司 | 阵列基板上的扫描驱动电路及阵列基板 |
CN105280153B (zh) * | 2015-11-24 | 2017-11-28 | 深圳市华星光电技术有限公司 | 一种栅极驱动电路及其显示装置 |
CN105448266B (zh) * | 2016-01-07 | 2018-01-12 | 武汉华星光电技术有限公司 | 栅极驱动电路和使用栅极驱动电路的液晶显示器 |
CN105869593B (zh) * | 2016-06-01 | 2018-03-13 | 深圳市华星光电技术有限公司 | 一种显示面板及其栅极驱动电路 |
CN106448595B (zh) * | 2016-10-24 | 2018-11-09 | 南京华东电子信息科技股份有限公司 | 一种高可靠性的栅极驱动电路 |
CN106710546B (zh) * | 2016-12-27 | 2019-05-07 | 武汉华星光电技术有限公司 | 栅极驱动电路及显示装置 |
CN106486078B (zh) * | 2016-12-30 | 2019-05-03 | 深圳市华星光电技术有限公司 | 一种扫描驱动电路、驱动电路及显示装置 |
CN106782395B (zh) * | 2016-12-30 | 2019-02-26 | 深圳市华星光电技术有限公司 | Goa电路的驱动方法和驱动装置 |
CN107103887B (zh) * | 2017-05-16 | 2020-07-03 | 深圳市华星光电半导体显示技术有限公司 | 一种goa电路以及液晶显示器 |
JP2019070731A (ja) * | 2017-10-10 | 2019-05-09 | シャープ株式会社 | シフトレジスタおよびそれを備えた表示装置 |
US10510314B2 (en) * | 2017-10-11 | 2019-12-17 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | GOA circuit having negative gate-source voltage difference of TFT of pull down module |
CN107808650B (zh) * | 2017-11-07 | 2023-08-01 | 深圳市华星光电半导体显示技术有限公司 | Goa电路 |
CN107705768B (zh) * | 2017-11-15 | 2019-07-02 | 深圳市华星光电半导体显示技术有限公司 | Goa电路 |
CN108010489B (zh) * | 2017-11-30 | 2019-11-15 | 南京中电熊猫平板显示科技有限公司 | 一种有机发光二极管驱动电路及其显示装置 |
CN108172170B (zh) * | 2017-11-30 | 2019-12-13 | 南京中电熊猫平板显示科技有限公司 | 一种触发驱动电路及有机发光显示装置 |
CN110120200B (zh) | 2018-02-05 | 2021-08-10 | 群创光电股份有限公司 | 显示装置 |
CN108665865B (zh) * | 2018-05-14 | 2020-12-01 | 昆山龙腾光电股份有限公司 | 栅极驱动单元以及显示装置 |
CN108877718B (zh) * | 2018-07-24 | 2021-02-02 | 武汉华星光电技术有限公司 | Goa电路及显示装置 |
CN108962171B (zh) * | 2018-07-27 | 2020-02-18 | 深圳市华星光电半导体显示技术有限公司 | Goa电路及具有该goa电路的液晶显示装置 |
CN108962175A (zh) * | 2018-08-06 | 2018-12-07 | 深圳市华星光电技术有限公司 | Goa电路 |
WO2020047797A1 (en) * | 2018-09-06 | 2020-03-12 | Boe Technology Group Co., Ltd. | A compensated triple gate driving circuit, a method, and a display apparatus |
CN109935188B (zh) * | 2019-03-08 | 2020-11-24 | 合肥京东方卓印科技有限公司 | 栅极驱动单元、方法、栅极驱动模组、电路及显示装置 |
CN109817177A (zh) * | 2019-03-20 | 2019-05-28 | 深圳市华星光电技术有限公司 | 栅极驱动电路及阵列基板 |
CN110007628B (zh) * | 2019-04-10 | 2022-02-01 | 深圳市华星光电半导体显示技术有限公司 | Goa电路及显示面板 |
CN110570800A (zh) * | 2019-08-13 | 2019-12-13 | 深圳市华星光电半导体显示技术有限公司 | 栅极驱动电路和显示面板 |
CN110570799B (zh) * | 2019-08-13 | 2022-10-04 | 深圳市华星光电半导体显示技术有限公司 | Goa电路及显示面板 |
TWI715159B (zh) * | 2019-08-22 | 2021-01-01 | 友達光電股份有限公司 | 顯示裝置與工作線路 |
CN110930918B (zh) * | 2019-11-19 | 2023-06-02 | 深圳市华星光电半导体显示技术有限公司 | Goa电路以及显示面板 |
CN111105763A (zh) * | 2019-12-19 | 2020-05-05 | 深圳市华星光电半导体显示技术有限公司 | Goa电路及显示面板 |
CN111312175B (zh) * | 2020-04-22 | 2020-12-25 | 南京中电熊猫液晶显示科技有限公司 | 触发驱动电路及有机发光显示装置 |
CN114664223B (zh) * | 2022-03-31 | 2022-11-25 | 惠科股份有限公司 | 显示面板的驱动电路、阵列基板及其驱动方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103065577A (zh) * | 2012-09-17 | 2013-04-24 | 友达光电股份有限公司 | 用于切换显示模式的移位寄存电路及控制方法 |
CN103500550A (zh) * | 2013-05-10 | 2014-01-08 | 友达光电股份有限公司 | 电压拉升电路、移位寄存器和栅极驱动模块 |
CN103680386A (zh) * | 2013-12-18 | 2014-03-26 | 深圳市华星光电技术有限公司 | 用于平板显示的goa电路及显示装置 |
CN103745700A (zh) * | 2013-12-27 | 2014-04-23 | 深圳市华星光电技术有限公司 | 自修复型栅极驱动电路 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101341909B1 (ko) * | 2009-02-25 | 2013-12-13 | 엘지디스플레이 주식회사 | 쉬프트 레지스터 |
KR101963595B1 (ko) * | 2012-01-12 | 2019-04-01 | 삼성디스플레이 주식회사 | 게이트 구동 회로 및 이를 구비한 표시 장치 |
TWI511459B (zh) * | 2012-10-11 | 2015-12-01 | Au Optronics Corp | 可防止漏電之閘極驅動電路 |
CN103680453B (zh) * | 2013-12-20 | 2015-09-16 | 深圳市华星光电技术有限公司 | 阵列基板行驱动电路 |
CN103730094B (zh) * | 2013-12-30 | 2016-02-24 | 深圳市华星光电技术有限公司 | Goa电路结构 |
-
2014
- 2014-07-15 CN CN201410337587.5A patent/CN104091577B/zh active Active
- 2014-08-14 US US14/398,739 patent/US9472150B1/en active Active
- 2014-08-14 WO PCT/CN2014/084331 patent/WO2016008186A1/zh active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103065577A (zh) * | 2012-09-17 | 2013-04-24 | 友达光电股份有限公司 | 用于切换显示模式的移位寄存电路及控制方法 |
CN103500550A (zh) * | 2013-05-10 | 2014-01-08 | 友达光电股份有限公司 | 电压拉升电路、移位寄存器和栅极驱动模块 |
CN103680386A (zh) * | 2013-12-18 | 2014-03-26 | 深圳市华星光电技术有限公司 | 用于平板显示的goa电路及显示装置 |
CN103745700A (zh) * | 2013-12-27 | 2014-04-23 | 深圳市华星光电技术有限公司 | 自修复型栅极驱动电路 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104575439A (zh) * | 2015-02-15 | 2015-04-29 | 北京京东方多媒体科技有限公司 | 一种显示补偿方法、装置及显示设备 |
US10002574B2 (en) | 2015-02-15 | 2018-06-19 | Boe Technology Group Co., Ltd. | Method, apparatus for display compensation and display device |
Also Published As
Publication number | Publication date |
---|---|
CN104091577B (zh) | 2016-03-09 |
US9472150B1 (en) | 2016-10-18 |
CN104091577A (zh) | 2014-10-08 |
US20160284294A1 (en) | 2016-09-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2016008186A1 (zh) | 应用于2d-3d信号设置的栅极驱动电路 | |
JP6788068B2 (ja) | 半導体装置 | |
US10235958B2 (en) | Gate driving circuits and liquid crystal devices | |
KR101818384B1 (ko) | Goa회로구조 | |
US7310402B2 (en) | Gate line drivers for active matrix displays | |
US9928797B2 (en) | Shift register unit and driving method thereof, gate driving apparatus and display apparatus | |
US10186223B2 (en) | GOA circuit and liquid crystal display | |
US10614768B2 (en) | Shift register, gate integrated driving circuit, and display apparatus | |
KR102444173B1 (ko) | 표시 장치 | |
US8049704B2 (en) | Liquid crystal display device | |
US8305326B2 (en) | Gate driving circuit having improved tolerance to gate voltage ripple and display device having the same | |
TWI406503B (zh) | 移位暫存器電路 | |
CN109509459B (zh) | Goa电路及显示装置 | |
US20070171172A1 (en) | Flat display structure and method for driving flat display | |
WO2020151227A1 (zh) | 显示装置 | |
WO2018040462A1 (zh) | 一种栅极驱动单元及驱动电路 | |
KR20190035855A (ko) | Goa 회로 | |
WO2014173025A1 (zh) | 移位寄存器单元、栅极驱动电路与显示器件 | |
WO2014172960A1 (zh) | 栅极驱动装置和显示装置 | |
WO2015161513A1 (zh) | 一种用于液晶显示的goa电路及液晶显示装置 | |
WO2013155851A1 (zh) | 栅极驱动电路及显示器 | |
JP5819514B2 (ja) | シフトレジスタ、ドライバ回路、表示装置 | |
WO2017124731A1 (zh) | 移位寄存器及其驱动方法、goa电路以及显示装置 | |
WO2015051643A1 (zh) | 电平转换模块、阵列基板及显示装置 | |
EA035508B1 (ru) | Схема драйвера затвора на матрице (goa) на основе полупроводниковых тонкопленочных транзисторов из низкотемпературного поликремния (ltps) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 14398739 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14897450 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 14897450 Country of ref document: EP Kind code of ref document: A1 |