WO2015108151A1 - 積層型電子部品およびその実装構造体 - Google Patents
積層型電子部品およびその実装構造体 Download PDFInfo
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- WO2015108151A1 WO2015108151A1 PCT/JP2015/051097 JP2015051097W WO2015108151A1 WO 2015108151 A1 WO2015108151 A1 WO 2015108151A1 JP 2015051097 W JP2015051097 W JP 2015051097W WO 2015108151 A1 WO2015108151 A1 WO 2015108151A1
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/02—Mountings
- H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10015—Non-printed capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to a multilayer electronic component and its mounting structure.
- Patent Document 1 discloses that a conductive material, which is a propagation medium of capacitor vibration, has a mounting structure that is farthest from the most vibrating portion of the capacitor, so that vibration is less likely to propagate to the circuit board. Yes.
- the present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer electronic component that can reduce noise when mounted on a substrate, and a mounting structure thereof.
- the multilayer electronic component of the present invention includes a first cover layer which is an effective layer in which dielectric layers and internal electrode layers are alternately stacked, and a pair of cover layers provided on both sides of the effective layer in the stacking direction. And a main body having a second cover layer, and a plurality of external electrodes provided on the outer surface of the main body, wherein the internal electrode layer is connected to the different external electrodes for each layer,
- the first cover layer has a high Young's modulus layer having a higher Young's modulus than the dielectric layer.
- the multilayer electronic component mounting structure according to the present invention is formed by bonding the above-described multilayer electronic component to a mounting surface of a substrate, and the first cover layer of the multilayer electronic component faces the mounting surface. ing.
- FIG. 1A and 1B show a multilayer electronic component according to a first embodiment, where FIG. 1A is a perspective view, FIG. 1B is a plan view seen from a first surface side, and FIG. 1C is a cross-sectional view taken along line A1-A1 in FIG. It is.
- FIG. 2 shows a mounting structure in which the multilayer electronic component according to the first embodiment is mounted on a substrate, and is a cross-sectional view taken along line A1-A1 in the multilayer electronic component of FIG.
- the laminated type electronic component in 2nd Embodiment is shown, (a) is a disassembled perspective view, (b) is a perspective view, (c) is the top view seen from the 1st surface side.
- FIG. 9 is a cross-sectional view taken along line A2-A2 of the multilayer electronic component of FIG. 3C, illustrating a mounting structure in which the multilayer electronic component according to the second embodiment is mounted on a substrate.
- the laminated type electronic component in 3rd Embodiment is shown, (a) is a disassembled perspective view, (b) is a perspective view, (c) is the top view seen from the 1st surface side.
- FIG. 9 shows a mounting structure in which a multilayer electronic component according to a third embodiment is mounted on a substrate, where (a) is a cross-sectional view taken along line A3-A3 in the multilayer electronic component of FIG.
- FIG. 7 is a cross-sectional view taken along line B3-B3 in the multilayer electronic component of FIG. It is a top view which shows the dimension of each part which looked at the multilayer electronic component in 3rd Embodiment from the 1st surface side.
- 1 shows a conventional multilayer electronic component, (a) is a perspective view, (b) is a plan view seen from the z-axis direction of the coordinate axis, and (c) is a conventional mounting structure in which the multilayer electronic component is mounted on a substrate.
- 4B is a cross-sectional view taken along line A4-A4 in the multilayer electronic component of FIG. It is the schematic of the measuring apparatus of a sound pressure level. It is a graph which shows the sound pressure level of the sound of the conventional multilayer ceramic capacitor, Comprising: (a) is a graph which shows the actually measured sound pressure level, (b) is a graph which shows the sound pressure level obtained by simulation. It is a graph which shows the impedance measurement result at the time of applying the DC bias of 4V to the conventional monolithic ceramic capacitor single-piece
- the multilayer electronic component according to the first embodiment is a multilayer capacitor including a main body 1 and external electrodes 2 provided on the outer surfaces of both ends thereof. is there. It is assumed that the stacking direction of the main body 1 coincides with the z-axis direction of the coordinate axis.
- the main body 1 includes an effective layer 5 in which dielectric layers 3 and internal electrode layers 4 are alternately stacked, and a pair of covers provided on both sides of the effective layer 5 in the stacking direction. It has the 1st cover layer 6 and the 2nd cover layer 7 which are layers.
- the effective layer 5 is one in which the dielectric layers 3 and the internal electrode layers 3 are alternately laminated, and the internal electrode layer 4 exists in the outermost layer.
- the internal electrode layer 4 is electrically connected to the external electrode 2 at either one of both end portions of the main body 1.
- the internal electrode layers 4 are electrically connected to different external electrodes 2 for each layer, and are sandwiched between a pair of internal electrode layers 4 connected to different external electrodes 2 by applying a voltage to the external electrodes 2.
- the effective layer 5 includes the internal electrode layer 4 that contributes to the generation of capacitance and the dielectric layer 3 sandwiched between the internal electrodes 4.
- the structure of the dielectric layer 3 and the internal electrode layer 4 shown in FIG. 1 (c) is a schematic structure. In practice, several to several hundreds of dielectric layers 3 and internal electrode layers 4 are formed. Many layers are used. The same applies to other forms described later.
- the multilayer electronic component has a rectangular parallelepiped shape, and is a pair of surfaces positioned opposite to each other in the stacking direction, and is positioned on the first surface 8 on the first cover layer 6 side and on the second cover layer 7 side. It has the 2nd surface 9 and four side surfaces.
- the multilayer electronic component is viewed from the first surface 8 side, there are a surface of the rectangular main body 1 and surfaces of the external electrodes 2 provided at both ends thereof, and the external electrode 2 is the main body in the y-axis direction.
- the protruding amount is sufficiently smaller than the width of the main body 1 in the y-axis direction.
- the multilayer electronic component having such a shape has a rectangular parallelepiped shape.
- the first cover layer 6 is the high Young's modulus layer 10 having a higher Young's modulus than the dielectric layer 3.
- the high Young's modulus layer 10 can be obtained by using a material having a higher Young's modulus than the composition of the material constituting the dielectric layer 3. Even if the material has the same composition as that of the dielectric layer 3, the Young's modulus can be increased more than that of the dielectric layer 3 by making the density higher than that of the dielectric layer 3.
- the Young's modulus may be considered to have a specific value for each material.
- the magnitude relationship between the Young's modulus of the dielectric layer 3 and the high Young's modulus layer 10 is the same as that of the dielectric layer 3 and the high Young's modulus layer 10, respectively. This can be determined by confirming the composition, crystal structure, and density (porosity) of the constituent material. Further, the Young's modulus of the dielectric layer 3 and the high Young's modulus layer 10 may be directly measured by a nanoindentation method or the like.
- the Young's modulus of the bulk body produced using the material constituting the dielectric layer 3 and the bulk body produced using the material constituting the high Young's modulus layer 10 can be expressed as stress-strain by a tensile test. Each may be measured by measurement or the like.
- the material composition, crystal structure, and density (pores) of each component (dielectric layer 3, cover layer, internal electrode layer 4, external electrode 2, etc.) of the multilayer electronic component Rate) and a simulation may be performed based on the obtained material information.
- a simulation is performed by a method as described later, and the resonance frequency and band of the impedance are fitted, so that the Young's modulus of each component can be evaluated more accurately.
- Such a multilayer electronic component can be manufactured, for example, by the following method.
- a binder and an organic solvent are added to and mixed with a raw material powder of a ferroelectric material such as barium titanate, and the obtained slurry is used to produce a green sheet that becomes the dielectric layer 3 by a known sheet molding method or the like.
- the green sheet used as the high Young's modulus layer 10 is similarly produced using the raw material powder of paraelectric materials, such as a barium zirconate.
- the raw material powder may be an inorganic compound for the purpose of sintering aid, adjustment of electrical and mechanical properties, or control of reaction between dielectric material and internal electrode (conductive) material during sintering, if desired. May be added.
- a paste made of a conductive material that becomes the internal electrode layer 4 is applied on the green sheet that becomes the dielectric layer 3 by screen printing or the like to form an internal electrode pattern.
- the main body before firing that becomes the effective layer 5 is obtained.
- a cover sheet is further laminated on both surfaces (on the internal electrode pattern) in the laminating direction of the main body before firing to be the effective layer 5.
- one of the cover sheets is a green sheet that becomes the high Young's modulus layer 10 and is integrated by pressing.
- the main body 1 of the multilayer electronic component is obtained by cutting the main body before firing integrated by pressing into a predetermined size and firing. If desired, barrel polishing or the like may be performed before firing or after firing.
- the firing temperature is not particularly limited, but may be, for example, 1000 to 1300 ° C.
- the dielectric layer 3 is made of ceramic, and the dielectric layer 3, the internal electrode layer 4, and the pair of cover layers are integrated by firing.
- One of the pair of cover layers constituting the main body 1 is a first cover layer 6 that is also a high Young's modulus layer 10, and the other is a second cover layer made of a material having a Young's modulus similar to that of the dielectric layer 3. 7.
- FIG. 2 is a cross-sectional view of the mounting structure according to the present embodiment taken along line A1-A1 in the multilayer electronic component of FIG.
- the multilayer electronic component and the land pattern 22 on the substrate 21 are electrically connected via a conductor 23 such as solder. Fixed in a connected state.
- the conductor 23 fills the gap between the external electrode 2 and the land pattern 22 and further covers the external electrode 2.
- the external electrode 2 covers an end portion of the main body 1 where the internal electrode is exposed, a side surface adjacent to the end portion, and a part of the upper and lower surfaces.
- the first cover layer 6 of the multilayer electronic component faces the mounting surface of the substrate 21, that is, the first surface 8 on the side where the high Young's modulus layer 10 is located and the substrate 21. It is important that the multilayer electronic component and the substrate 21 are bonded so that the mounting surface faces each other.
- the conventional multilayer electronic component includes a rectangular parallelepiped main body 101 and external electrodes 102 provided on the outer surfaces of both ends as shown in FIG.
- FIG. 9B is a plan view seen from the z-axis direction of FIG.
- FIG. 9C shows a conventional multilayer electronic component mounted on the substrate 21, and is a cross-sectional view taken along line A4-A4 in the multilayer electronic component of FIG. 9B.
- the main body 101 includes an effective layer 105 in which dielectric layers 103 and internal electrode layers 104 are alternately stacked, and a pair of cover layers provided on both sides of the effective layer 105 in the stacking direction. 107.
- the high Young's modulus layer 10 is not provided.
- the internal electrode layer 104 is electrically connected to the external electrode 102 at one of both end portions of the main body 101.
- a multilayer ceramic capacitor which is one of the multilayer electronic components, uses a ferroelectric material such as barium titanate as the dielectric layer 103 and a metal material such as Ni as the internal electrode layer 104.
- the external electrode 102 is usually made by baking a Cu paste as a base electrode and applying Ni and Sn plating to the surface thereof.
- the external electrode 102 and the land pattern 22 on the substrate 21 are electrically connected via a conductor 123 such as solder (hereinafter referred to as solder 123). Fixed in a connected state.
- the solder 123 fills the gap between the external electrode 102 and the land pattern 22 and further covers the external electrode 102.
- the external electrode 102 covers an end portion of the main body 101 where the internal electrode layer 104 is exposed, and a side surface adjacent to the end portion and a part of the upper and lower surfaces.
- the DC voltage is applied to the dielectric layer 103 having an electrostrictive effect, whereby the dielectric layer 103 Piezoelectric properties occur, and piezoelectric vibration is generated by an AC voltage. Furthermore, the piezoelectric vibration of the multilayer ceramic capacitor is transmitted to the substrate 21 via the solder 123, and the substrate 21 vibrates, and when the substrate 21 resonates at a resonance frequency in the audible range, a vibration sound called “sounding” is generated.
- the sound of a conventional mounting structure in which a multilayer ceramic capacitor, which is a conventional multilayer electronic component, was mounted on a substrate 21 was measured.
- a 1005 type monolithic ceramic capacitor (capacitance 10 ⁇ F, rated voltage 4 V, hereinafter also referred to as evaluation part) is used as the monolithic ceramic capacitor
- the substrate 21 is FR4 (Flame Retardant Type 4) of 100 ⁇ 40 mm and a thickness of 0.8 mm
- a glass epoxy substrate made of a material was used.
- the multilayer ceramic capacitor was mounted on the center of the substrate 21 using Sn—Ag—Cu (SAC) solder. After mounting the evaluation component on the substrate 21, the mounting state was observed with a microscope, and it was confirmed that the fillet height of the solder 123 was 460 ⁇ m and the distance C between the substrate 21 and the evaluation component was 45 ⁇ m.
- FIG. 11 (a) shows the sounding measurement results when a DC voltage of 4 V (DC bias) and an AC voltage of 1 Vpp are applied to the multilayer ceramic capacitor.
- the sound pressure level is indicated by an A characteristic sound pressure level (dBA).
- a characteristic sound pressure level of 0 dBA corresponds to the lowest sound pressure level that humans can hear as sound.
- the A-weighted sound pressure level is a sound pressure level weighted for each frequency so as to be close to human hearing, and is described in the standard of a sound level meter (sound level meter) (JISC 1509-1: 2005).
- FIG. 13 schematically shows a finite element method model used for impedance simulation. This is a 1/8 model considering symmetry, and the two cross sections appearing on the front surface of FIG. 13 and the lower cross section are symmetry planes.
- Table 1 shows the parameters (elastic stiffness c ij and piezoelectric constant e ij ) of the dielectric layer 103 obtained by the fitting. From Table 1, it can be seen that the material properties of the dielectric layer 103 of the evaluation part have anisotropy (c 11 > c 33 , c 22 > c 33 ). This is considered due to the compressive stress caused by the internal electrode layer 104.
- FIG. 11B is a graph showing the result of converting the vibration amplitude of the mounting substrate 31 obtained by the simulation into an A characteristic sound pressure level. Since the frequency characteristic of the sound depends on the vibration characteristic of the evaluation component and the resonance mode of the mounting substrate 31, the simulation result shown in FIG. 11B shows that the sound pressure is particularly low in a low frequency region of 10 kHz or less. Both the sound pressure level and the frequency characteristics were in good agreement with the actually measured values shown in FIG. Therefore, by performing a simulation using this parameter, it is possible to confirm the influence on the sound produced when the structure of the mounting structure or the evaluation component itself is changed.
- FIG. 14 shows the calculation result at 10 kHz.
- 14A is a view from the inside (symmetrical plane side) of the 1/8 model
- FIG. 14B is the opposite side of FIG. 14A, that is, the outside of the 1/8 model. Viewed from the side (surface side).
- the broken line indicates the shape of the evaluation component in a state where no AC voltage is applied
- the solid line indicates the shape of the evaluation component that is displaced to the maximum by the AC voltage. From this result, it can be seen that in the audible frequency range, the evaluation component performs spreading vibration in the direction of the lamination surface and stretching vibration in the thickness direction (stacking direction).
- the multilayer electronic component by adopting a structure that can suppress the spread vibration in the direction of the multilayer surface, the propagation of the piezoelectric vibration of the multilayer electronic component to the substrate 21 when the multilayer electronic component is mounted on the substrate 21 is suppressed. Therefore, it is thought that the noise can be reduced.
- the first cover layer 6 of the main body 1 has a high Young's modulus higher than that of the dielectric layer 3 as in the present embodiment shown in FIGS.
- the rate layer 10 is provided, and the multilayer electronic component may be mounted on the substrate 21 so that the first cover layer 6 and the mounting surface of the substrate 21 face each other.
- the high Young's modulus layer 10 suppresses the spread vibration of the multilayer electronic component on the first surface 8 side fixed to the substrate 21 and can reduce noise.
- a sound simulation was performed using the following model of the present embodiment.
- the conditions relating to the main body 1 and the external electrode 2 are the same as in the simulation of the sound of the evaluation part described above (dielectric material: barium titanate material, internal electrode: Ni, external electrode: Cu, main body size: 1100 ⁇ 620 ⁇ 620 ⁇ m, external electrode thickness 20 ⁇ m).
- the material of the high Young's modulus layer 10 was BaZrO 3 (Young's modulus 220 GPa), and the thickness T1 of the high Young's modulus layer 10 was 155 ⁇ m.
- the second cover layer 7 preferably has a Young's modulus equal to or lower than that of the dielectric layer 3.
- a Young's modulus equal to or lower than that of the dielectric layer 3 a material having a Young's modulus lower than that of the material constituting the dielectric layer 3, for example, various insulating resins may be used.
- the second cover layer 7 is integrated with the effective layer 5 and the first cover layer 6 by firing, for example, the same composition as the dielectric layer 3 and a lower density than the dielectric layer 3 (high porosity) ) Material may be used.
- the first cover layer 6 and the second cover layer 7 can be bonded to the effective layer 5 via an adhesive or the like, but are bonded directly to the effective layer 5 by firing from the viewpoint of moisture resistance and reliability.
- the integrated main body 1 is preferably formed.
- the fact that the first cover layer 6 and the second cover layer (sometimes simply referred to as a cover layer) and the effective layer 5 are directly joined is positively applied to the interface between the effective layer 5 and the cover layer. This means that no intermediate layer such as an adhesive is introduced.
- a reaction layer or a diffusion layer may be formed at the interface between the effective layer 5 and the cover layer. Cases are also considered to be directly joined.
- FIG. 15 schematically showing the entire evaluation component, in a pair of surfaces positioned in the stacking direction of the evaluation component, a region where the vibration amplitude is small near the center of each side, that is, a node of vibration ( It can be seen that there are 24).
- the ratio of T1 to T0 (T1 / T0) is It is preferable to set it to 0.1 or more.
- T1 / T0 should be 1/3 or less to reduce defects such as cracking due to firing shrinkage and differences in thermal expansion coefficient when the entire body 1 including the high Young's modulus layer 10 is manufactured by simultaneous firing. This is preferable from the viewpoint of concentrating vibration energy on the second surface 9 side.
- the high Young's modulus layer 10 may be a part of the first cover layer 6. Absent.
- the high Young's modulus layer 10 may be the outermost layer on the first surface 8 side of the main body 1, but other layers may exist further outside the high Young's modulus layer 10.
- an effective portion 5 ′ (broken line in FIG. 1C). Portion) on the projection plane perpendicular to the stacking direction, the effective portion 5 ′ only needs to be inside the outline of the high Young's modulus layer 10.
- the outline of the high Young's modulus layer may be present in an annular shape between the outline of the main body 1 and the outline of the effective portion 5 ′.
- the vibration of the multilayer electronic component is caused by the fact that a piezoelectric property is generated in the dielectric layer 3 by applying a DC voltage to the dielectric layer 3 having the electrostrictive effect, and the piezoelectric vibration is generated by the AC voltage. ing. That is, the stress in the spreading direction due to the piezoelectric effect is generated in the effective portion 5 ′ to which the voltage is applied in the effective layer 5. Therefore, the effective portion 5 ′ that is a source of piezoelectric vibration is constrained by the high Young's modulus layer 10, in other words, at least the region facing the effective portion 5 ′ in the first cover layer 8 is the high Young modulus layer 10. By doing so, an effect of suppressing sound generation can be obtained.
- the ratio of E1 to E0 is preferably 1.4 or more.
- E1 / E0 the Young's modulus of the high Young's modulus layer 10 is increased as compared with the effective layer 5 in which the dielectric layer 3 and the internal electrode layer 4 having a relatively high Young's modulus are combined.
- vibration on the first surface 8 side of the multilayer electronic component can be suppressed.
- E1 / E0 is 3.0 or less from the viewpoint of suppressing the occurrence of defects such as cracks when the entire body 1 including the high Young's modulus layer 10 is manufactured by simultaneous firing.
- a multilayer ceramic capacitor in which a ferroelectric material such as barium titanate is used for the dielectric layer 3 and a metal material such as Ni, Cu, Ag, Ag—Pd is used for the internal electrode layer 4 is used.
- a ferroelectric material such as barium titanate
- a metal material such as Ni, Cu, Ag, Ag—Pd
- the present invention can also be applied to other multilayer electronic components when it is necessary to suppress excitation of the substrate 21 on which the multilayer electronic component is mounted due to piezoelectric vibration of the multilayer electronic component itself.
- the present embodiment can exert a remarkable effect particularly in a multilayer electronic component of a 1005 type or more type.
- the high Young's modulus layer 10 may be made of a paraelectric material having the same degree of sinterability and thermal expansion coefficient as the material used for the dielectric layer 3. Since the Young's modulus of the paraelectric material is higher than the Young's modulus of the ferroelectric material, for example, when a barium titanate-based ferroelectric material is used as the dielectric layer 3, it is the same as barium titanate. In addition, a paraelectric material such as barium zirconate or calcium zirconate having a perovskite crystal structure may be used as the high Young's modulus layer 10.
- a mixed material in which a ferroelectric material that is the same as or equivalent to that of the dielectric layer 3 and a metal material such as Ni that is a conductive material constituting the internal electrode layer 4 may be used.
- a metal material such as Ni has a relatively higher Young's modulus than the ferroelectric material, and the high Young's modulus layer 10 is obtained by mixing so that the ratio of the metal material in the mixed material is higher than that of the effective layer 5. It can be used as a material.
- the high Young's modulus layer 10 may be a single material, or the constituent material may be a mixture of a plurality of materials.
- the high Young's modulus layer 10 may be a single layer or may be composed of a plurality of layers having the same or different materials.
- the first cover layer 6 located on the first surface 8 side of the effective layer 5 in the main body 1 has a Young's modulus higher than the average Young's modulus of the effective layer 5 as a whole. What is necessary is just to have the high Young's modulus layer 10 which is a site
- the multilayer electronic component of the present embodiment is equivalent to the conventional multilayer electronic component in its outer shape, and it is not necessary to greatly change the design. Therefore, the present embodiment can be applied to various existing multilayer electronic components. . In addition, there is an advantage that no special jig is required for mounting on the substrate.
- a multilayer ceramic capacitor having a general structure having the external electrodes 2 at both ends in the longitudinal direction has been described as an example of a multilayer electronic component.
- the present invention can be applied to multilayer electronic components having various structures such as a mold and a multi-terminal type.
- many multilayer ceramic capacitors use an external electrode 2 in which a base electrode made of Cu is plated with Ni and Sn.
- the external electrode is composed of only a plated electrode without using the base electrode.
- the present invention can also be suitably applied to those having the electrode 2. Since the base electrode made of Cu is relatively soft, the base electrode absorbs and attenuates the piezoelectric vibration of the main body 1 to some extent, and the sound is suppressed. On the other hand, when the external electrode 2 is composed only of the plating electrode, the piezoelectric vibration of the main body 1 is not attenuated by the external electrode 2 and the sounding becomes remarkable. Therefore, when this embodiment is applied to what has the external electrode 2 comprised only by the plating electrode, the bigger noise reduction effect is acquired.
- the first cover layer 6 includes the high Young's modulus layer 10 having a Young's modulus higher than that of the dielectric layer 3.
- the first surface 8 has a rectangular shape, and is constituted by the main body 1 and the external electrode 2 and has two pairs of sides and apexes V facing each other.
- the two pairs of sides and the vertex V facing each other are contours formed by the body 1 and the external electrode 2 of the multilayer electronic component in the plan view of the multilayer electronic component as viewed from the first surface 8 side. It is composed.
- the sides of the external electrode 2 protrude outward from the sides of the main body 1, but the protruding amount is sufficiently small with respect to the length of each side. Therefore, such a surface is regarded as having a rectangular shape.
- one pair of sides is the first side 12
- the other pair of sides is the second side 13
- the first surface 8 and the first side 12 are A pair of side surfaces adjacent to each other via a first side surface 14 and a pair of side surfaces adjacent to each other via the first surface 8 and the second side 13 are referred to as second side surfaces 15.
- the pair of joining members 11 extends from the pair of first sides 12 to the regions adjacent to the first sides 12 of the first surface 8 and the first side surface 14. Are provided. Further, the joining member 11 is not provided on the second side 13 and the second side surface 15.
- the joining member 11 is located at a portion including the center 12c of the first side 12 and not including the vertex V.
- the center 12c of the first side 12 is a bisection point that bisects the length of the first side 12.
- L1 and L2 are the lengths of the multilayer electronic component that includes the main body 1 and the external electrode 2 and does not include the bonding member 11 in the plan view viewed from the first surface 8 side. This is the length of the multilayer electronic component excluding the member 11.
- L1 and L2 may be regarded as the external dimensions of the main body 1 and the external electrode 2.
- a noise reduction effect can be obtained. That is, by fixing the multilayer electronic component to the substrate 21 at the node portion 24 of the multilayer electronic component as shown in FIG. 15 via the joining member 11, the piezoelectric of the multilayer electronic component itself to the substrate 21 is obtained. Propagation of vibration is suppressed, and sound generation can be reduced.
- M1 is the length of the joining member 11 in the length direction of the first side 12
- P1 is the first side of the first surface 8 of the multilayer electronic component.
- 12 is a length in a direction perpendicular to the first side 12 of the joining member 11 extended from 12 to the center side of the first surface 8.
- H0 is the height of the multilayer electronic component including the main body 1 and the external electrode 2 in the stacking direction of the main body 1, and H1 is from the first side 12 on the first side surface 14.
- the length in the stacking direction of the bonding member 11 extending to the center side of the first side surface 14, C is the distance between the mounting surface of the substrate 21 and the external electrode 2.
- the pair of joining members 11 in the present embodiment are formed on the surfaces of the different external electrodes 2 and have electrical conductivity.
- a brazing material such as eutectic solder or lead-free solder (Sn—Ag—Cu), a conductive adhesive, or the like can be used.
- a solder paste may be printed on a predetermined portion on the first surface 8 side of the external electrode 2, heat-treated at the melting temperature of the solder and then cooled. Further, the solder ball may be bonded to a predetermined portion on the first surface 8 side of the external electrode 2 using a flux, a low melting point solder or the like.
- the solid solder used as the bonding member 11 is not necessarily a spherical solder ball, and may have other shapes such as a plate shape, a rod shape, and a wire shape. Further, a plurality of spherical solder balls may be used as the bonding member 11.
- the joining member 11 when using an electrically conductive paste for formation of the joining member 11, it forms on the predetermined part by the side of the 1st surface 8 of the external electrode 2 by screen printing etc., and forms the joining member 11 by drying. Can do.
- the joining member 11 may be provided not only on the external electrode 2 on the first surface 8 side but also on the main body 1 or may be provided across both the external electrode 2 and the main body 1. .
- the mounting structure of the multilayer electronic component of this embodiment will be described.
- the external electrode 2 of the multilayer electronic component and the land pattern 22 on the substrate 21 are connected to each other via the bonding member 11.
- the surface 8 and the mounting surface of the substrate 21 are joined so as to face each other.
- the joining member 11 in the present embodiment serves to join the multilayer electronic component to the substrate 21 and to electrically connect the external electrode 2 of the multilayer electronic component and a circuit (not shown) of the substrate 21. Also bears.
- the multilayer electronic component When the multilayer electronic component is mounted on the substrate 21, it may be directly bonded to the land pattern 22 of the substrate 21 by the bonding member 11, but a conductive material such as solder is applied on the land pattern 22 of the substrate 21.
- the multilayer electronic component may be mounted on the substrate 21 via the same.
- a conductor 23 such as solder applied on the land pattern 22 is formed between the bonding member 11 and the land pattern 22.
- the conductor 23 is formed so as to contact or cover the bonding member 11. It is preferable that the conductor 23 and the external electrode 2 are joined via the joining member 11, and the conductor 23 and the external electrode 2 are not in direct contact.
- the multilayer electronic component can be bonded to the land pattern 22 of the substrate 21 at the portion where the bonding member 11 is disposed.
- the conductive material to be used is a material of the same kind as the joining member 11, but wettability with the joining member 11 There is no particular limitation as long as it is good.
- a sound simulation was performed using the following model of the present embodiment.
- the conditions relating to the main body 1 and the external electrode 2 are the same as in the simulation of the sound of the evaluation part described above (dielectric material: barium titanate material, internal electrode: Ni, external electrode: Cu, main body size: 1100 ⁇ 620 ⁇ 620 ⁇ m, external electrode thickness 20 ⁇ m).
- the material of the high Young's modulus layer 10 was BaZrO 3 (Young's modulus 220 GPa), and the thickness T1 of the high Young's modulus layer 10 was 155 ⁇ m.
- a pair of sides of the first surface 8 having a length of 660 ⁇ m is referred to as a first side 12
- a pair of sides having a length of 1140 ⁇ m is referred to as a second side 13.
- the joining member 11 had M1 of 620 ⁇ m, P1 of 160 ⁇ m, and H1 of 78 ⁇ m. Further, C in the mounting structure of the present embodiment was 140 ⁇ m. When the obtained results are averaged over the frequency range of 5 Hz to 20 kHz, the average value of the sound pressure level in the present embodiment is a result of 19 dBA reduction with respect to the above-described evaluation component, that is, the conventional mounting structure. It was.
- the ratio (M1 / L1) of M1 (620 ⁇ m) to L1 (660 ⁇ m) is set to 0.94, but this is set to 0.5, and the region including the nodal portion 24 on the first side 12 If the joining member 11 is provided, the sound pressure level can be reduced by 22 dBA compared to the conventional art.
- M1 / L1 is preferably set to 0.4 or more.
- the ratio H1 (78 ⁇ m) to the ratio H0 (660 ⁇ m) (H1 / H0) is set to 0.12, but even if this is set to 0.5, the sound pressure level can be reduced by 10 dBA compared to the conventional case. .
- the vibration amplitude is large near the center of each surface constituting the evaluation part, so the ratio of H1 to H0 (H1 / H0) is 0.4 or less.
- the length P1 of the joining member 11 in the direction perpendicular to the first side 12 on the first surface 8 is preferably 0.25 or less in terms of the ratio (P1 / L2) to L2.
- the joining member 11 even when the joining member 11 is separated from the first side 12, it is preferable that the joining member 11 exists in the region within the range of P1 and H1 described above from the first side 12. However, it goes without saying that there is no need to consider P1 when the joining member 11 does not exist on the first surface 8 and H1 when the joining member 11 does not exist on the first side surface 14.
- the main body 1 and the external electrode 2 of the multilayer electronic component are not in direct contact with the mounting surface of the substrate 21.
- the ratio (C / H0) of C to H0, which is the distance between the external electrode 2 and the mounting surface of the substrate 21, is preferably 0.1 or more.
- substrate 21 as a mounting structure of this embodiment, even if it is a case where the joining member 11 and another joining member are not provided. If the multilayer electronic component mounted on the substrate 21 is bonded to the substrate 21 at the portion where the bonding member 11 is to be provided, it is included in the mounting structure of this embodiment. In this case, a conductor 23 such as solder for joining the multilayer electronic component to the substrate 21 corresponds to the joining member 11.
- the bonding member 11 having an insulating property.
- the formation site of the joining member 11 may extend not only on the external electrode 2 but also on the main body 1 or both the external electrode 2 and the main body 1.
- the external electrode 2 may be electrically connected to the electric circuit of the substrate 21 by wire bonding or the like.
- the insulating material for example, thermoplastic resins such as ethylene vinyl acetate (EVA) and polypropylene (PP) are suitable.
- Sn plating of the external electrode 2 has a role of improving wettability between the external electrode 2 and the solder when the multilayer electronic component is mounted on the substrate 21, but in this embodiment, the multilayer electronic component is a pair. Since it is joined to the land pattern 22 of the substrate 21 via the joining member 11, the external electrode 2 having no Sn plating can be used. In addition, after forming the bonding member 11, for example, an oxide film may be formed on the exposed portion of the external electrode 2 to make the exposed portion of the external electrode 2 difficult to wet with solder.
- the third embodiment further includes a joining member 11 on the first surface 8 side of the external electrode 2 in the above-described first embodiment.
- the first surface 8 and the second surface 9 have a rectangular shape, and are constituted by the main body 1 and the external electrode 2 and have two pairs of sides and apexes V that face each other.
- the two pairs of sides and the vertex V facing each other are the main body 1 and the external electrode of the multilayer electronic component in the plan view of the multilayer electronic component as viewed from the first surface 8 side or the second surface 9 side. 2 constitutes a contour formed by two.
- first side 12 A pair of side surfaces adjacent to each other via 8 and the first side 12 is referred to as a first side surface 14, and a pair of side surfaces adjacent to each other via the first surface 8 and the second side 13 is referred to as a second side surface 15.
- the center of the first side 12 is 12c, and the center of the second side 13 is 13c.
- the center of the side is a bisection point that bisects the length of the side.
- the joining member 11 includes the apex V on the first surface 8 side of the main body 1 and the external electrode 2, and the first surface 8 A region that is provided over the first side surface 14 and the second side surface 15 and does not include a line connecting the centers of the sides of the first surface 8, the first side surface 14, and the second side surface 15 facing each other. Is provided.
- the line connecting the centers of the opposing sides is a line connecting 12 c and 13 c (broken line connecting the midpoints shown in FIG. 6C), and the first side surface 14.
- the first cover layer 6 includes the high Young's modulus layer 10 having a Young's modulus higher than that of the dielectric layer 3.
- the first surface 8 side of the main body 1 and the external electrode 2 that is, the four corners on the side having the high Young's modulus layer 10, bonded to the portions that are both ends of the pair of external electrodes 2.
- a member 11 is provided.
- at least one of the bonding members 11 provided at both ends of the external electrode 2 has electrical conductivity.
- the material of the joining member 11 for example, eutectic solder, brazing material such as lead-free solder (Sn—Ag—Cu), conductive adhesive, and the like can be used as in the second embodiment.
- FIG. 7A is a cross-sectional view of the multilayer electronic component of the present embodiment mounted on a substrate, taken along line A3-A3 in the multilayer electronic component of FIG. 6C, and FIG. FIG. 7 is a cross-sectional view taken along line B3-B3 in the multilayer electronic component of FIG.
- the external electrode 2 of the multilayer electronic component and the substrate 21 are provided.
- the land pattern 22 is bonded via the bonding member 11 so that the first surface 8 and the mounting surface of the substrate 21 face each other.
- the bonding member 11 in the present embodiment is such that at least one of the bonding members 11 provided at both ends of the external electrode 2 joins the multilayer electronic component to the substrate 21 and the outside of the multilayer electronic component. It also plays a role of electrically connecting the electrode 2 and a circuit (not shown) of the substrate 21.
- both of the joining members 11 provided at both ends of the external electrode 2 electrically connect the external electrode 2 of the multilayer electronic component and a circuit (not shown) of the substrate 21. ing.
- the pair of sides having the shorter length among the two pairs of sides facing each other on the first surface 8 constituted by the main body 1 and the external electrode 2 is defined as the first side.
- One side 12 and a pair of longer sides are defined as a second side 13. Therefore, in FIG. 8, L1 is the length of the first side 12, and L2 is the length of the second side 13.
- L1 and L2 are both the length of the multilayer electronic component including the main body 1 and the external electrode 2 and not including the bonding member 11, in other words, the length of the multilayer electronic component excluding the bonding member 11. .
- L1 and L2 may be regarded as the external dimensions of the main body 1 and the external electrode 2.
- P1 is a length in a direction perpendicular to the first side 12 of the joining member 11 extending from the first side 12 to the center side of the first surface 8
- P2 is from the second side 13. This is the length in the direction perpendicular to the second side 13 of the joining member 11 extending to the center side of the first surface 8.
- H ⁇ b> 1 is the stacking direction of the joining member 11 extending from the first side 12 to the center side of the first side surface 14 on the first side surface 14.
- the length in the stacking direction of the joining member 11 extending from the second side 13 to the center side of the second side surface 15 on the second side surface 15, C is the mounting surface of the substrate 12, The distance from the external electrode 2.
- the simulation of sound generation was performed using the following model of this embodiment.
- P1 was 160 micrometers
- P2 was 155 micrometers
- H1 was 78 micrometers.
- C in the mounting structure of the present embodiment was 140 ⁇ m.
- Other conditions related to the main body 1 and the external electrode 2 were the same as those of the sound simulation in the second embodiment.
- the average value of the sound pressure level in the present embodiment was reduced by 23 dBA with respect to the conventional mounting structure.
- P2 (155 ⁇ m) is set to 0.235 as a ratio (P2 / L1) to L1 (660 ⁇ m), but 0.2 to 0.4 is preferable from the viewpoint of mountability.
- P1, H1, and C it is preferable to set it as the range similar to 2nd Embodiment.
- the bonding member 11 may be made of an insulating material as described above.
- the external electrode 2 may be electrically connected to the electric circuit of the substrate 21 by wire bonding or the like.
- only one of the joining members 11 provided at both ends of the external electrode 2 may be conductive, and the other may be insulating.
- the shape of the joining member 11 is mainly rectangular, and preferred ranges of dimensions and ratios have been described based on the shape.
- the shape of 11 is not limited to a rectangular shape, and may be other various shapes and irregular shapes.
- various changes and modifications can be made without departing from the gist of the present invention described in the claims based on the description of the vibration mode of the multilayer electronic component and the nodal portion 24 confirmed by the above simulation. Is possible.
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Abstract
Description
第1の実施形態である積層型電子部品は、図1(a)~(c)に示すように本体1と、その両端部の外表面に設けられた外部電極2とを備えた積層コンデンサである。なお、本体1の積層方向は座標軸のz軸方向と一致するものとする。
なお、図1(c)に示した誘電体層3および内部電極層4の構造は模式的なものであり、実際には数層~数百層の誘電体層3と内部電極層4とが積層されたものが多く用いられる。これは、後述する他の形態についても同様である。
第2の実施形態においては、図3(a)~(c)に示すように、上述した第1の実施形態における外部電極2の第1の面8側に、さらに接合部材11を備えている。なお、本実施形態においても、第1の実施形態と同様に、第1のカバー層6が、誘電体層3よりも高いヤング率を有する高ヤング率層10を備えている。
第3の実施形態も、第2の実施形態と同様、上述した第1の実施形態における外部電極2の第1の面8側に、さらに接合部材11を備えている。また、第1の面8および第2の面9は矩形状であり、本体1および外部電極2により構成されるとともに互いに対向する二対の辺および頂点Vを備えている。換言すれば、互いに対向する二対の辺および頂点Vは、積層型電子部品を第1の面8側または第2の面9側からみた平面図において、積層型電子部品の本体1および外部電極2により形成される輪郭を構成している。ここで、第1の面8を構成する二対の辺のうち、いずれか一対の辺を第1の辺12とし、他方の一対の辺を第2の辺13とし、さらに、第1の面8と第1の辺12を介して隣接する一対の側面を第1の側面14、第1の面8と第2の辺13を介して隣接する一対の側面を第2の側面15とする。また、第1の辺12の中央を12c、第2の辺13の中央を13cとする。辺の中央とは、辺の長さを2等分する2等分点である。
2、102 外部電極
3、103 誘電体層
4、104 内部電極層
5 有効層
6 第1カバー層
7 第2カバー層
107 カバー層
8 第1の面
9 第2の面
10 高ヤング率層
11 接合部材
12 第1の辺
12c 第1の辺の中央
13 第2の辺
13c 第2の辺の中央
14 第1の側面
15 第2の側面
21 基板
22 ランドパターン
23、123 導電体
24 節状部
31 実装基板
32 無響箱
33 集音マイク
34 アンプ
35 FETアナライザ
V 頂点
Claims (12)
- 誘電体層と内部電極層とが交互に積層された有効層、および該有効層における積層方向の両側に設けられた一対のカバー層である第1のカバー層および第2のカバー層を有する本体と、
該本体の外表面に設けられた複数の外部電極と、を備え、
前記内部電極層は、1層毎に異なる前記外部電極に接続されており、
前記第1のカバー層が、前記誘電体層よりも高いヤング率を有する高ヤング率層を有することを特徴とする積層型電子部品。 - 前記誘電体層および前記カバー層がセラミックスからなり、前記本体は、前記誘電体層、前記内部電極層、および前記一対のカバー層が一体化されていることを特徴とする請求項1に記載の積層型電子部品。
- 積層セラミックコンデンサであることを特徴とする請求項2に記載の積層型電子部品。
- 前記第2のカバー層のヤング率が、前記誘電体層のヤング率以下であることを特徴とする請求項1乃至3のいずれかに記載の積層型電子部品。
- 前記本体の前記積層方向における厚さをT0とし、前記高ヤング率層の前記積層方向における厚さをT1としたとき、T1のT0に対する比率T1/T0が0.1以上であることを特徴とする請求項1乃至4のいずれかに記載の積層型電子部品。
- 前記誘電体層のヤング率をE0とし、前記高ヤング率層のヤング率をE1としたとき、E1のE0に対する比率E1/E0が1.4以上であることを特徴とする請求項1乃至5のいずれかに記載の積層型電子部品。
- 前記積層型電子部品は、前記積層方向に対向して位置する一対の面であり、前記第1のカバー層側に位置する第1の面および前記第2のカバー層側に位置する第2の面を有し、前記第1の面と前記第2の面との間にある4つの側面を有する直方体形状をなしており、
前記第1の面側において、前記本体および前記外部電極のうち少なくともいずれか一方に、さらに接合部材を備えることを特徴とする請求項1乃至6のいずれかに記載の積層型電子部品。 - 前記第1の面が矩形状であり、該第1の面の互いに対向する二対の辺のうち、いずれか一対の辺を第1の辺とし、他方の一対の辺を第2の辺とし、
前記第1の面と前記第1の辺を介して隣接する一対の前記側面を第1の側面としたとき、
前記第1の辺、前記第1の面の前記第1の辺に隣接する領域、および前記第1の側面の前記第1の辺に隣接する領域のうち少なくともいずれかに、接合部材をそれぞれ備えることを特徴とする請求項7に記載の積層型電子部品。 - 前記第1の辺の長さをL1とし、前記第2の辺の長さをL2としたとき、L1<L2であることを特徴とする請求項8に記載の積層型電子部品。
- 前記第1の面および前記第2の面が、それぞれ4つの頂点および二対の辺を備える矩形状であり、
前記第1の面の前記4つの頂点、前記第1の面の前記4つの頂点に隣接する領域、および4つの前記側面の前記4つの頂点に隣接する領域のうち少なくともいずれかに、接合部材をそれぞれ備え、
該接合部材は、前記第1の面および前記側面の、互いに対向する前記辺の中央を結ぶ線上には設けられていないことを特徴とする請求項7に記載の積層型電子部品。 - 基板の実装面に請求項1乃至10のいずれかに記載の積層型電子部品を接合してなり、該積層型電子部品の前記第1のカバー層が、前記実装面に対向していることを特徴とする積層型電子部品の実装構造体。
- 基板の実装面に請求項7乃至10のいずれかに記載の積層型電子部品を、前記接合部材により接合してなり、該積層型電子部品の前記第1の面が、前記実装面に対向していることを特徴とする積層型電子部品の実装構造体。
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US15/110,508 US10283271B2 (en) | 2014-01-17 | 2015-01-16 | Laminated electronic component and laminated electronic component mounting structure |
CN201580003769.1A CN105900195B (zh) | 2014-01-17 | 2015-01-16 | 层叠型电子部件及其安装构造体 |
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JP2019050278A (ja) * | 2017-09-08 | 2019-03-28 | Tdk株式会社 | 電子部品及び電子部品装置 |
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JP2020198419A (ja) * | 2019-06-03 | 2020-12-10 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 積層セラミック電子部品及びその実装基板 |
JPWO2021019867A1 (ja) * | 2019-07-30 | 2021-02-04 | ||
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CN105900195A (zh) | 2016-08-24 |
JP6220898B2 (ja) | 2017-10-25 |
US20160336114A1 (en) | 2016-11-17 |
US10283271B2 (en) | 2019-05-07 |
CN105900195B (zh) | 2018-10-26 |
JPWO2015108151A1 (ja) | 2017-03-23 |
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