WO2015027588A1 - 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 - Google Patents
薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 Download PDFInfo
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- WO2015027588A1 WO2015027588A1 PCT/CN2013/087941 CN2013087941W WO2015027588A1 WO 2015027588 A1 WO2015027588 A1 WO 2015027588A1 CN 2013087941 W CN2013087941 W CN 2013087941W WO 2015027588 A1 WO2015027588 A1 WO 2015027588A1
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- film transistor
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 7
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Classifications
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
Definitions
- the present invention relates to the field of display technologies, and in particular, to a thin film transistor and a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device. Background technique
- a material having a lower resistance such as copper (Cu)
- Cu copper
- a metal oxide is used to form an active layer so that a resolution can be prepared. Display products with higher quality, better quality and better performance.
- a plan view of a pixel structure in the prior art is shown in Fig. 1-1, in which a thin film transistor 15 is disposed in a region where the gate line 13 and the data line 14 are intersected.
- 1-2 is a cross-sectional view of a thin film transistor of a bottom gate structure taken along line AA' in FIG. 1-1.
- the thin film transistor includes a substrate 1 on which a buffer layer 8 and a gate are sequentially disposed.
- the gate electrode 2 formed of copper is disposed under the active layer 5, and the gate electrode 2 and the active layer 5 are insulated and separated by the gate insulating layer 41.
- the use of copper to form gate and gate lines and the use of metal oxides to form a source layer is still a relatively advanced technology in the fabrication process of array substrates, but there are still some problems in the preparation process.
- the upper and lower sides of the gate insulating layer 41 are the active layer 5 and the gate 2, respectively, and the ability of the gate insulating layer 41 to block the diffusion of copper ions is weak.
- the temperature is generally high, which causes copper ions to easily diffuse into the active layer 5, affecting the switching characteristics of the thin film transistor, making the performance of the thin film transistor unstable, and even causing the film in severe cases. The switching performance of the transistor fails. Summary of the invention
- the present invention provides a film for the above technical problems existing in the prior art. Transistor and preparation method thereof, array substrate, preparation method thereof and display device.
- the thin film transistor can effectively prevent the material forming the gate from diffusing into the active layer by providing an isolation layer between the gate electrode and the active layer, thereby ensuring the stability of the performance of the thin film transistor and further ensuring the performance of the array substrate. stability.
- the present invention provides a thin film transistor including a substrate and a gate, an insulating layer, an active layer, a source and a drain disposed on the substrate, the insulating layer being disposed on the gate and the active layer Between the gate and the active layer, an isolation layer is further disposed, the isolation layer has a greater barrier capability for material diffusion forming the gate than the insulating layer to form the gate The barrier property of the material diffusion.
- the spacer layer coincides with at least one of the gate and the active layer having a smaller area in at least the right projection direction.
- the isolation layer is closer to the gate than the insulating layer, and the insulating layer is disposed between the isolation layer and the active layer; the source and the drain respectively correspond Provided at both ends of the active layer and partially overlapping the gate in a right projection direction.
- the insulating layer is a gate insulating layer
- the thin film transistor further includes an etch barrier layer
- the gate is disposed above the substrate, and the isolation layer is sequentially disposed above the gate
- the gate insulating layer and the active layer, the etch barrier layer is disposed above the active layer, and the etch barrier layer is respectively disposed at two ends corresponding to the active layer a hole, the source and the drain are respectively connected to the active layer through the via.
- the insulating layer is a passivation layer
- the source and the drain are separately disposed above the substrate
- the active layer is disposed at the source and the drain.
- the passivation layer and the isolation layer being sequentially disposed Above the active layer, the gate is disposed above the isolation layer.
- the spacer layer is formed of a metal material or a metal oxide material having a property of being electrically conductive to insulating, the gate electrode being formed of copper or aluminum, and the active layer being formed of a metal oxide.
- the isolation layer is oxidized by nano silver, indium tin oxide, indium zinc oxide, or indium gallium zinc oxide Object formation.
- An array substrate comprising the above thin film transistor.
- the array substrate further includes a gate line formed by using the same material as the gate electrode, the gate line is connected to the gate and disposed in the same layer, and the isolation layer is further extended. To a region corresponding to the gate line and coincident with the gate line at least in a right projection direction.
- a display device comprising the above array substrate.
- a method of fabricating a thin film transistor comprising: forming a gate, an insulating layer, an active layer, a source and a drain on a substrate, wherein the insulating is formed between the gate and the active layer
- the layer further includes a step of forming an isolation layer between the gate electrode and the active layer, the isolation layer having a barrier property for material diffusion forming a gate electrode being larger than a diffusion of the insulating layer for a material forming a gate electrode Barrier ability.
- the spacer layer coincides with at least one of the gate and the smaller one of the active layers in a right projection direction.
- the insulating layer is formed between the isolation layer and the active layer.
- the active layer or the substrate is retained by an ion implantation process or a plasma treatment process. The conductivity of the isolation layer in the region corresponding to the gate is changed, and the conductivity of the isolation layer in the remaining region is converted into insulation.
- the isolation layer is formed of a metal material or a metal oxide material having conductivity-to-insulation conversion properties
- the step of forming the isolation layer includes: the material for forming the isolation layer is in an argon atmosphere Forming an isolation layer film, the isolation layer film having electrical conductivity; and the isolation layer film forming a pattern including the isolation layer by an ion implantation process or a plasma treatment process in an oxygen or nitrogen atmosphere, wherein The isolation layer has conductivity in a region corresponding to the active layer or the gate, and has an insulating property in a region corresponding to the active layer or the gate.
- the spacer layer is formed of nanosilver, indium tin oxide, indium-doped zinc oxide, or indium gallium zinc oxide.
- a method for preparing an array substrate comprising the above method for preparing a thin film transistor.
- the preparation method further comprises: forming a gate line on the substrate and Corresponding to the step of the isolation layer of the gate line, the gate line is formed in the same patterning process as the gate, the gate line is connected to the gate and disposed in the same layer, and the isolation layer is at least positive The grid line coincides with the projection line.
- the conductivity of the isolation layer corresponding to the gate line region is further retained by an ion implantation process or a plasma processing process And converting the conductivity of the region corresponding to the active layer or the gate and the isolation layer corresponding to the gate line region into insulation.
- the thin film transistor provided by the present invention can effectively prevent diffusion of a material forming a gate electrode by providing an isolation layer between the gate electrode and the active layer, for example, preventing diffusion of copper ions or aluminum ions to the active layer.
- the isolation layer can prevent the material forming the gate electrode in the thin film transistor from diffusing into the active layer, and further prevent the material forming the gate line from diffusing into the active layer, thereby ensuring the stability of the performance of the array substrate.
- 1-1 is a plan view showing a pixel structure in the prior art
- FIG. 1-1 is a cross-sectional view showing the thin film transistor of FIG. 1-1 taken along a line AA' in FIG. 1-1;
- FIG. 2 is a cross-sectional view showing a thin film transistor according to Embodiment 1 of the present invention
- FIGS. 3-1 to 3-7 are cross-sectional views showing respective steps in the process of fabricating the thin film transistor of FIG. 2;
- FIG. 3-1 is a cross-sectional view of forming a pattern including a gate
- FIG. 3-2 is a cross-sectional view showing formation of an isolation layer film, a gate insulating layer film, and an active layer film
- FIG. 3-3 is a cross-sectional view showing a pattern including an active layer and a gate insulating layer
- FIG. 3-4 is a formation including an isolation layer. a cross-sectional view of the graph
- Figure 3-5 is a cross-sectional view after forming a pattern including an isolation layer
- Figure 3-6 is a cross-sectional view after stripping the photoresist mask
- FIGS. 5-1 to 5-6 are cross-sectional views showing respective steps in the process of fabricating the thin film transistor of FIG. 4;
- FIG. 5-1 is a cross-sectional view of forming a pattern including a source and a drain;
- 5-2 is a cross-sectional view showing formation of a pattern including an active layer and a passivation layer, and forming an isolation layer film and a gate film;
- Figure 5-3 is a cross-sectional view showing the formation of a pattern including a gate
- Figure 5-4 is a cross-sectional view showing the formation of a pattern including an isolation layer
- Figure 5-5 is a cross-sectional view after forming a pattern including an isolation layer
- Figure 5-6 is a cross-sectional view after stripping the photoresist mask
- Figure 6 is a cross-sectional view showing an array substrate using the thin film transistor of Figure 2;
- Figure 7 is a cross-sectional view showing an array substrate using the thin film transistor of Figure 4. Description of the reference signs:
- Example 1 In order to enable those skilled in the art to better understand the technical solutions of the present invention, the thin film transistor of the present invention, a method for fabricating the same, an array substrate, a method for fabricating the same, and a display device will be further described in detail below with reference to the accompanying drawings and embodiments.
- Example 1
- the thin film transistor which is a bottom gate structure.
- the thin film transistor includes a substrate 1 and a gate electrode 2 disposed on the substrate 1, a gate insulating layer 41 as an insulating layer, an active layer 5, a source electrode 6, and a drain electrode 7, wherein The edge layer 41 is disposed between the gate electrode 2 and the active layer 5, and an isolation layer 3 is further disposed between the gate electrode 2 and the active layer 5, and the isolation layer 3 is provided with the gate electrode 2 at least in the forward projection direction.
- the thin film transistor further includes a buffer layer 8 disposed under the gate 2 and overlapping the gate 1 in the forward projection direction, and the gate 2 is disposed on the buffer layer 8 to enable the gate
- the pole 1 is more firmly attached and does not fall off easily.
- the gate electrode 2 is disposed opposite to the active layer 5, and the source electrode 6 and the drain electrode 7 are respectively disposed at both ends of the active layer 5 and partially overlap the gate electrode 2 in the forward projection direction.
- the gate insulating layer 41 is disposed between the gate electrode 2 and the active layer 5, the isolation layer 3 is closer to the gate electrode 2 than the gate insulating layer 41, and the gate insulating layer 41 is disposed between the isolation layer 3 and the active layer 5, so that Conducive to the diffusion of the material of the gate 2 is blocked.
- the thin film transistor further includes an etch barrier layer 9.
- the gate 2 is disposed above the buffer layer 8, and an isolation layer 3, a gate insulating layer 41, and an active layer 5 are sequentially disposed above the gate 1, and the active layer 5 is disposed at On the gate insulating layer 41 above the gate 1, an etch barrier layer 9 is disposed over the active layer 5 and contacts the active layer 5 and the gate insulating layer 41, and the source 6 and the drain 7 are disposed in an etch barrier
- the layer 9 is above the both ends of the active layer 5, and the source 6 and the drain 7 partially overlap the gate 2 in the front projection direction, respectively, and the etch stop layer 9 corresponds to both ends of the active layer 5.
- Via holes are respectively formed at the positions, and the source 6 and the drain 7 are respectively connected to the active layer 5 through the via holes.
- the etch barrier layer 9 when the source electrode 6 and the drain electrode 7 are formed by etching with an etching solution, the etching liquid is prevented from affecting the active layer 5 under the source electrode 6 and the drain electrode 7.
- the isolation layer 3 is formed by a metal material (such as nano silver) or a metal oxide material (such as indium tin oxide IT0, indium zinc oxide IZ0, indium gallium zinc oxide IGZ0) having conductivity to insulation transition
- the pole 2 is formed of copper or aluminum, or a copper alloy or an aluminum alloy
- the active layer 5 is formed of a metal oxide such as indium gallium zinc oxide, indium zinc oxide, indium tin oxide or indium gallium tin oxide.
- the embodiment further provides a method for preparing a thin film transistor, comprising: on a substrate a step of forming a gate, a gate insulating layer, an active layer, a source and a drain, further comprising the step of forming an isolation layer between the gate and the active layer, the isolation layer being at least in a positive projection direction and having a gate or One of the smaller regions of the source layer coincides, and the barrier property of the spacer layer for material diffusion of the gate layer is greater than the barrier property of the insulating layer for material diffusion of the gate electrode so that the material forming the gate electrode cannot diffuse to the active layer.
- the patterning process may include only a photolithography process, or may include a photolithography process and an etching process, and may also include printing, inkjet, etc. for forming a predetermined pattern.
- the lithography process refers to a process of forming a pattern by using a photoresist, a reticle, an exposure machine, or the like, including a process of film formation, exposure, and development.
- the corresponding patterning process can be selected according to the structure formed by the array substrate.
- the active layer or the gate is retained by an ion implantation process or a plasma processing process.
- the conductivity of the isolation layer in the region corresponding to the pole is converted to the electrical conductivity of the barrier layer in the remaining region.
- the method for fabricating the thin film transistor specifically includes the following steps: Step S1: forming a pattern including the gate electrode 2 on the substrate 1.
- a step of forming a pattern including the buffer layer 8 on the substrate 1 may be further included.
- the specific formation process of the pattern including the buffer layer 8 is: depositing a metal film (such as molybdenum, titanium, molybdenum alloy or titanium alloy) on the surface of the substrate 1, and then forming, corresponding to the gate 2 by exposure, development and etching. shape.
- a pattern including the gate electrode 2 is formed on the buffer layer 8, and the buffer layer 8 overlaps the gate electrode 1 in the forward projection direction, and the gate electrode 2 can be attached very strongly to the buffer layer. On 8, it is not easy to fall off.
- Step S2 As shown in Fig. 3-2, an isolation layer film 30, a gate insulating layer film 410, and an active layer film 50 are formed on the substrate 1 on which the step S1 is completed.
- the isolation layer film 30 is formed of a metal material or a metal oxide material capable of being electrically conductive to insulating property, and the material for forming the isolation layer 3 is deposited in an argon atmosphere to form the isolation layer film 30, which is isolated.
- the layer film 30 has electrical conductivity; the gate electrode 2 is formed of copper, and the active layer film 50 is made of a metal oxide such as indium gallium zinc oxide or indium zinc oxide. Formed as a compound, indium tin oxide or indium gallium tin oxide.
- Step S3 As shown in FIG. 3-3, on the substrate 1 on which the step S2 is completed, a pattern including the active layer 5 and the gate insulating layer 41 is formed by a patterning process, and the active layer 5 is disposed opposite to the gate electrode 2; As shown in FIGS. 3-4, a pattern including the isolation layer 3 is formed by an ion implantation process or a plasma treatment process.
- This step specifically includes:
- Step S31 Applying a photoresist on the substrate 1 on which the step S2 is completed.
- Step S32 A photoresist mask 10 is formed by an exposure process and a development process using a mask provided with an active layer 5 pattern.
- Step S33 The active layer film 50 is formed into a pattern including the active layer 5 by a first etching process, and the area of the active layer 5 is larger than the area of the gate 2.
- the etching process is a wet etching process.
- a nitric acid and a sulfuric acid solution to which glacial acetic acid is added may be used as an etching medium, and etching may be performed at a normal temperature to 45 degrees.
- Step S34 The gate insulating film 410 is formed into a pattern including the gate insulating layer 41 by a second etching process.
- the etching process is a dry etching process, and in the dry etching process, a fluorine-containing gas such as SF 6 , CF 4 , CHF 3 or a mixed gas of the foregoing gas and 0 2 may be used as an etching medium.
- Etching is performed in a reactive ion etching machine, a plasma etching machine, a reaction coupling plasma etching machine, or the like.
- Step S35 As shown in FIG. 3-4, the conductivity of the isolation layer film 30 in the region corresponding to the active layer 5 is retained by the ion implantation process or the plasma treatment process, and the conductivity of the isolation layer film 30 of the remaining region is maintained. The property is changed to insulative to form a pattern including the spacer layer 3, as shown in FIGS. 3-5.
- the separator film 30 is patterned in an oxygen or nitrogen atmosphere by an ion implantation process (such as implantation of oxygen ions) or a plasma treatment process, and the isolation layer 3 is in a region corresponding to the active layer 5. It has electrical conductivity and is insulative in a region other than the active layer 5.
- the spacer layer 3 thus treated can well block the diffusion of copper ions or aluminum ions forming the gate electrode 1.
- the isolation layer has a good prevention of copper ion or aluminum ion expansion of the gate electrode 2 Dispersed to the active layer 5;
- the gate insulating layer 41 has a good antistatic breakdown effect, and has the function of preventing copper ions or aluminum ions forming the gate electrode 2 from diffusing to the active layer 5 (but with respect to the isolation layer 3) Its ability to prevent proliferation is weak).
- Step S36 As shown in FIG. 3-6, the photoresist mask 10 is removed by a lift-off process.
- Step S4 As shown in Fig. 3-7, a pattern including the source 6 and the drain 7 is formed on the substrate 1 on which the step S3 is completed.
- a pattern including the etch barrier layer 9 may be formed on the substrate 1 on which the step S3 is completed, and then the source 6 and the drain 7 are formed on the etch barrier layer 9. That is, the etch stop layer 9 is formed over the active layer 5 and below the source 6 and the drain 7, and the etch stop layer 9 is respectively provided with via holes at positions corresponding to both ends of the active layer 5, the source The pole 6 and the drain 7 are connected to the active layer 5 through the via holes, respectively.
- the thin film transistor of the bottom gate structure is prepared.
- This embodiment is exemplified only in the case where the gate of the thin film transistor is at the bottom, the area of the gate is smaller than the area of the active layer, and the isolation layer recombines with the active layer in the forward projection direction.
- the material forming the gate When the material forming the gate is diffused, it will all diffuse forward to the region corresponding to the active layer, and the spacer and the insulating layer can more effectively prevent the diffusion of the material forming the gate, for example, preventing copper ions or aluminum.
- the ions diffuse into the active layer, thereby ensuring the stability of the performance of the thin film transistor.
- the isolation layer coincides with the active layer in the forward projection direction.
- the material forming the gate is diffused, a portion of the gate electrode corresponding to the active layer in the forward projection direction will be forwardly diffused to the active layer, and the gate is beyond the active layer.
- a portion of the copper ion or aluminum ion in the corresponding projection direction will be laterally diffused to the active layer, since the forward diffusion of copper ions or aluminum ions accounts for the majority of the diffused copper ions or aluminum ions,
- the isolation layer and the insulating layer can also effectively prevent the diffusion of the material forming the gate into the active layer, thereby ensuring the stability of the performance of the thin film transistor.
- the method of manufacturing the thin film transistor may include the steps of: forming a pattern including the gate 2 on the substrate 1; Forming the isolation film 30, and then forming a spacer layer 3 corresponding to the gate pattern by using a mask plate provided with a pattern of the gate 2 (the formation principle of the isolation layer is the same as that described above); and forming a gate insulating film 410 and the active layer film 50 are then patterned by a patterning process including the gate insulating layer 41 and the active layer 5.
- This embodiment provides a thin film transistor which is a top gate structure.
- the insulating layer in the thin film transistor is a passivation layer 42
- the source 6 and the drain 7 are separately disposed above the substrate 1
- the active layer 5 is disposed at Between the source 6 and the drain 7 and extending above the source 6 and the drain 7 respectively to contact the source
- the passivation layer 42 and the isolation layer 3 are sequentially disposed above the active layer 5
- the buffer layer 8 is disposed above the isolation layer 3
- the gate electrode 2 is disposed on the buffer layer 8 above.
- an etch stop layer may be disposed between the active layer and the source and the drain, or an etch stop layer may not be disposed, which is not set in this embodiment.
- the etch barrier layer is described as an example.
- the present embodiment further provides a method for fabricating the thin film transistor, which is different from the method for fabricating the thin film transistor of the first embodiment: the preparation method specifically includes the following steps:
- Step S l as shown in FIG. 5-1, forming a source 6 and a drain on the substrate 1
- Step S2 As shown in FIG. 5-2, a pattern including the active layer 5 and the passivation layer 42 is formed on the substrate 1 on which the step S1 is completed, and the isolation layer film 30 and the gate electrode are formed on the passivation layer 42. Membrane 20.
- a buffer layer film 80 may be formed over the isolation layer film 30, for example, by depositing a molybdenum, titanium, molybdenum alloy or titanium alloy material. A metal film is formed; then a gate film 20 is formed over the buffer layer film 80.
- Step S3 As shown in FIG. 5-3, on the substrate 1 that completes step S2, a pattern including the gate electrode 2 is formed by a patterning process, wherein the active layer 5 is disposed opposite to the gate electrode 2; As shown in FIG. 5-4, a pattern including the isolation layer 3 is formed by an ion implantation process or a plasma treatment process, as shown in FIG. 5-5.
- a pattern including the buffer layer 8 is formed by an etching process.
- the shape of the buffer layer 8 corresponds to the shape of the gate electrode 2, the gate electrode 2 is formed on the buffer layer 8, the buffer layer 8 overlaps the gate electrode 2 in the forward projection direction, and the gate electrode 2 can be attached to the buffer layer 8 very firmly. It is not easy to fall off.
- This step specifically includes:
- Step S31' A photoresist is applied on the substrate 1 on which the step S2' is completed.
- Step S32' A photoresist mask 10 is formed by an exposure process and a development process using a mask provided with a gate 1 pattern.
- Step S33' The gate film 20 is formed into a pattern including the gate electrode 2 by an etching process.
- the pattern in which the gate film 20 is formed to include the gate electrode 2 is usually a wet etching process; next, the buffer layer film 80 is formed into a pattern including the buffer layer 8 by an etching process.
- Step S34' as shown in FIG. 5-4, the conductivity of the isolation layer film 30 in the region corresponding to the gate electrode 2 is retained by the ion implantation process or the plasma treatment process, and the conductivity of the isolation layer film 30 of the remaining region is maintained.
- the properties are converted to insulative to form a pattern comprising the spacer layer 3, as shown in Figures 5-5.
- Step S35' As shown in Fig. 5-6, the photoresist mask 10 is removed by a lift-off process.
- the thin film transistor of the top gate structure is prepared.
- this embodiment shows only that the area of the gate electrode in the thin film transistor is smaller than the area of the active layer, and the isolation layer is shown to coincide with the gate in the forward projection direction.
- the isolation layer may also coincide with the active layer having a smaller area in the forward projection direction.
- the method of manufacturing the thin film transistor may include the steps of: forming a source 6 on the substrate 1 And a pattern of the drain electrode 7; forming a pattern including the active layer 5 and the passivation layer 42; forming the isolation layer film 30, and then forming a mask corresponding to the active layer pattern by using a mask provided with the pattern of the active layer 5
- the isolation layer 3 (the formation principle of the isolation layer is the same as that described above); and the formation of the pattern including the gate electrode 2.
- Embodiment 1-2 provides an isolation layer between the gate electrode and the active layer, compared to the prior art only between the gate electrode and the active layer
- the insulating layer is disposed to more effectively prevent the material forming the gate (such as copper ions or aluminum ions) from diffusing into the active layer, thereby ensuring stable performance of the thin film transistor.
- Example 3
- the present embodiment provides an array substrate of a thin film transistor having a bottom gate structure, which comprises the thin film transistor of the above embodiment 1.
- the array substrate in this embodiment further includes gate lines and data lines (not shown in FIG. 6) disposed at intersections, and the gate lines are connected to the gate 2 and disposed in the same layer, and the data lines and the source 6 are provided. Connected and set in the same layer.
- the gate lines are formed using the same material as the gate electrodes 2.
- the array substrate further includes a pixel electrode 12 connected to the drain electrode 7.
- a second insulating layer 11 is further disposed above the source 6 and the drain 7.
- the second insulating layer 11 is a passivation layer, and the second insulating layer 11 is opened in a region corresponding to the drain 7.
- the hole, the pixel electrode 12 is disposed above the second insulating layer 11, and is connected to the drain 7 through a via hole opened in the second insulating layer 11.
- the embodiment further provides a method for preparing the array substrate.
- the preparation method includes: forming a cross-arrangement on the substrate, in addition to the method for preparing the thin film transistor of the bottom gate structure in Embodiment 1. a step of a gate line and a data line, wherein the data line and the source are formed in the same patterning process, the data line is connected to the source and disposed in the same layer; the gate line and the gate are formed in the same patterning process, the gate line and the gate Connected and set in the same layer.
- the preparation method still further includes the step of forming a pixel electrode, the pixel electrode being connected to the drain.
- a second insulating layer is formed over the source and the drain, a via is formed in a region of the second insulating layer corresponding to the drain, and the pixel electrode is formed above the second insulating layer, and is opened in the second A via in the insulating layer is connected to the drain.
- the structure, the material, and the preparation method of the array substrate of the array substrate other than the thin film transistor in this embodiment are the same as those in the prior art, and are not described herein again.
- the isolation layer further extends to a region corresponding to the gate line, and coincides with the gate line at least in the forward projection direction.
- the buffer layer further extends to a region corresponding to the gate line, and coincides with the gate line at least in the forward projection direction. That is, the gate line is also disposed on the buffer layer, and the buffer layer can make the gate line adhesion more secure.
- the embodiment further provides a method for fabricating the array substrate.
- the method further includes: forming a gate line on the substrate and Corresponding to the step of the isolation layer of the gate line, the gate line and the gate are formed in the same patterning process, the gate line is connected to the gate and disposed in the same layer, and the isolation layer coincides with the gate line at least in the forward projection direction.
- the data lines and the source are formed in the same patterning process, and the data lines are connected to the source and disposed in the same layer; the gate lines and the gates Formed in the same patterning process, the gate lines are connected to the gate and disposed in the same layer, and the isolation layer also extends to a region corresponding to the gate lines and coincides with the gate lines at least in the forward projection direction.
- the conductivity in the region corresponding to the active layer or the gate, and the isolation layer corresponding to the gate line region are retained, and the conductivity of the isolation layer in the remaining region is retained. Change to insulation.
- Example 5 The structure, the material, and the method for preparing the array substrate of the array substrate other than the thin film transistor in this embodiment are the same as those in the third embodiment, and are not described herein again.
- Example 5 The structure, the material, and the method for preparing the array substrate of the array substrate other than the thin film transistor in this embodiment are the same as those in the third embodiment, and are not described herein again.
- the present embodiment provides an array substrate of a thin film transistor having a top gate structure, which comprises the thin film transistor of the above embodiment 2.
- the pixel electrode 12 is disposed on the surface of the substrate 1 and below the drain 7, and the pixel electrode 12 and the drain are omitted.
- the poles 7 overlap and are connected.
- the embodiment further provides a method for preparing the array substrate, which comprises the method for preparing a thin film transistor of the top gate structure in the second embodiment, which is different from the method for preparing the array substrate in the third embodiment, the pixel electrode It is formed on the surface of the substrate and below the drain.
- the isolation layer further extends to a region corresponding to the gate line, and coincides with the gate line at least in the forward projection direction.
- the buffer layer further extends to a region corresponding to the gate line, and coincides with the gate line at least in the forward projection direction.
- the conductivity of the region corresponding to the active layer or the gate and the isolation layer corresponding to the region of the gate line are retained, and The conductivity of the isolation layer in the remaining region is converted into insulation.
- the structure, the material, and the method for preparing the array substrate of the array substrate other than the thin film transistor in this embodiment are the same as those in the fourth embodiment, and are not described herein again.
- the isolation layer can prevent diffusion of a material (such as copper ions or aluminum ions) forming a gate electrode in the thin film transistor into the active layer, and further prevent further The material forming the gate line (such as copper ions or aluminum ions) diffuses into the active layer, thereby ensuring the stability of the performance of the array substrate.
- a material such as copper ions or aluminum ions
- the embodiment provides a display device comprising the array substrate of any of embodiments 3-6.
- the display device may be a liquid crystal display device or an electroluminescence display device such as a liquid crystal panel, a liquid crystal television, a mobile phone, a liquid crystal display or the like.
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Abstract
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US20150340455A1 (en) | 2015-11-26 |
CN103474471A (zh) | 2013-12-25 |
US9455324B2 (en) | 2016-09-27 |
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