WO2015027588A1 - 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 - Google Patents

薄膜晶体管及制备方法、阵列基板及制备方法、显示装置 Download PDF

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Publication number
WO2015027588A1
WO2015027588A1 PCT/CN2013/087941 CN2013087941W WO2015027588A1 WO 2015027588 A1 WO2015027588 A1 WO 2015027588A1 CN 2013087941 W CN2013087941 W CN 2013087941W WO 2015027588 A1 WO2015027588 A1 WO 2015027588A1
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Prior art keywords
layer
gate
active layer
isolation layer
film transistor
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PCT/CN2013/087941
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English (en)
French (fr)
Inventor
曹占锋
姚琪
丁录科
孙冰
孔祥春
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京东方科技集团股份有限公司
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Priority to US14/376,028 priority Critical patent/US9455324B2/en
Publication of WO2015027588A1 publication Critical patent/WO2015027588A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor and a method of fabricating the same, an array substrate, a method of fabricating the same, and a display device. Background technique
  • a material having a lower resistance such as copper (Cu)
  • Cu copper
  • a metal oxide is used to form an active layer so that a resolution can be prepared. Display products with higher quality, better quality and better performance.
  • a plan view of a pixel structure in the prior art is shown in Fig. 1-1, in which a thin film transistor 15 is disposed in a region where the gate line 13 and the data line 14 are intersected.
  • 1-2 is a cross-sectional view of a thin film transistor of a bottom gate structure taken along line AA' in FIG. 1-1.
  • the thin film transistor includes a substrate 1 on which a buffer layer 8 and a gate are sequentially disposed.
  • the gate electrode 2 formed of copper is disposed under the active layer 5, and the gate electrode 2 and the active layer 5 are insulated and separated by the gate insulating layer 41.
  • the use of copper to form gate and gate lines and the use of metal oxides to form a source layer is still a relatively advanced technology in the fabrication process of array substrates, but there are still some problems in the preparation process.
  • the upper and lower sides of the gate insulating layer 41 are the active layer 5 and the gate 2, respectively, and the ability of the gate insulating layer 41 to block the diffusion of copper ions is weak.
  • the temperature is generally high, which causes copper ions to easily diffuse into the active layer 5, affecting the switching characteristics of the thin film transistor, making the performance of the thin film transistor unstable, and even causing the film in severe cases. The switching performance of the transistor fails. Summary of the invention
  • the present invention provides a film for the above technical problems existing in the prior art. Transistor and preparation method thereof, array substrate, preparation method thereof and display device.
  • the thin film transistor can effectively prevent the material forming the gate from diffusing into the active layer by providing an isolation layer between the gate electrode and the active layer, thereby ensuring the stability of the performance of the thin film transistor and further ensuring the performance of the array substrate. stability.
  • the present invention provides a thin film transistor including a substrate and a gate, an insulating layer, an active layer, a source and a drain disposed on the substrate, the insulating layer being disposed on the gate and the active layer Between the gate and the active layer, an isolation layer is further disposed, the isolation layer has a greater barrier capability for material diffusion forming the gate than the insulating layer to form the gate The barrier property of the material diffusion.
  • the spacer layer coincides with at least one of the gate and the active layer having a smaller area in at least the right projection direction.
  • the isolation layer is closer to the gate than the insulating layer, and the insulating layer is disposed between the isolation layer and the active layer; the source and the drain respectively correspond Provided at both ends of the active layer and partially overlapping the gate in a right projection direction.
  • the insulating layer is a gate insulating layer
  • the thin film transistor further includes an etch barrier layer
  • the gate is disposed above the substrate, and the isolation layer is sequentially disposed above the gate
  • the gate insulating layer and the active layer, the etch barrier layer is disposed above the active layer, and the etch barrier layer is respectively disposed at two ends corresponding to the active layer a hole, the source and the drain are respectively connected to the active layer through the via.
  • the insulating layer is a passivation layer
  • the source and the drain are separately disposed above the substrate
  • the active layer is disposed at the source and the drain.
  • the passivation layer and the isolation layer being sequentially disposed Above the active layer, the gate is disposed above the isolation layer.
  • the spacer layer is formed of a metal material or a metal oxide material having a property of being electrically conductive to insulating, the gate electrode being formed of copper or aluminum, and the active layer being formed of a metal oxide.
  • the isolation layer is oxidized by nano silver, indium tin oxide, indium zinc oxide, or indium gallium zinc oxide Object formation.
  • An array substrate comprising the above thin film transistor.
  • the array substrate further includes a gate line formed by using the same material as the gate electrode, the gate line is connected to the gate and disposed in the same layer, and the isolation layer is further extended. To a region corresponding to the gate line and coincident with the gate line at least in a right projection direction.
  • a display device comprising the above array substrate.
  • a method of fabricating a thin film transistor comprising: forming a gate, an insulating layer, an active layer, a source and a drain on a substrate, wherein the insulating is formed between the gate and the active layer
  • the layer further includes a step of forming an isolation layer between the gate electrode and the active layer, the isolation layer having a barrier property for material diffusion forming a gate electrode being larger than a diffusion of the insulating layer for a material forming a gate electrode Barrier ability.
  • the spacer layer coincides with at least one of the gate and the smaller one of the active layers in a right projection direction.
  • the insulating layer is formed between the isolation layer and the active layer.
  • the active layer or the substrate is retained by an ion implantation process or a plasma treatment process. The conductivity of the isolation layer in the region corresponding to the gate is changed, and the conductivity of the isolation layer in the remaining region is converted into insulation.
  • the isolation layer is formed of a metal material or a metal oxide material having conductivity-to-insulation conversion properties
  • the step of forming the isolation layer includes: the material for forming the isolation layer is in an argon atmosphere Forming an isolation layer film, the isolation layer film having electrical conductivity; and the isolation layer film forming a pattern including the isolation layer by an ion implantation process or a plasma treatment process in an oxygen or nitrogen atmosphere, wherein The isolation layer has conductivity in a region corresponding to the active layer or the gate, and has an insulating property in a region corresponding to the active layer or the gate.
  • the spacer layer is formed of nanosilver, indium tin oxide, indium-doped zinc oxide, or indium gallium zinc oxide.
  • a method for preparing an array substrate comprising the above method for preparing a thin film transistor.
  • the preparation method further comprises: forming a gate line on the substrate and Corresponding to the step of the isolation layer of the gate line, the gate line is formed in the same patterning process as the gate, the gate line is connected to the gate and disposed in the same layer, and the isolation layer is at least positive The grid line coincides with the projection line.
  • the conductivity of the isolation layer corresponding to the gate line region is further retained by an ion implantation process or a plasma processing process And converting the conductivity of the region corresponding to the active layer or the gate and the isolation layer corresponding to the gate line region into insulation.
  • the thin film transistor provided by the present invention can effectively prevent diffusion of a material forming a gate electrode by providing an isolation layer between the gate electrode and the active layer, for example, preventing diffusion of copper ions or aluminum ions to the active layer.
  • the isolation layer can prevent the material forming the gate electrode in the thin film transistor from diffusing into the active layer, and further prevent the material forming the gate line from diffusing into the active layer, thereby ensuring the stability of the performance of the array substrate.
  • 1-1 is a plan view showing a pixel structure in the prior art
  • FIG. 1-1 is a cross-sectional view showing the thin film transistor of FIG. 1-1 taken along a line AA' in FIG. 1-1;
  • FIG. 2 is a cross-sectional view showing a thin film transistor according to Embodiment 1 of the present invention
  • FIGS. 3-1 to 3-7 are cross-sectional views showing respective steps in the process of fabricating the thin film transistor of FIG. 2;
  • FIG. 3-1 is a cross-sectional view of forming a pattern including a gate
  • FIG. 3-2 is a cross-sectional view showing formation of an isolation layer film, a gate insulating layer film, and an active layer film
  • FIG. 3-3 is a cross-sectional view showing a pattern including an active layer and a gate insulating layer
  • FIG. 3-4 is a formation including an isolation layer. a cross-sectional view of the graph
  • Figure 3-5 is a cross-sectional view after forming a pattern including an isolation layer
  • Figure 3-6 is a cross-sectional view after stripping the photoresist mask
  • FIGS. 5-1 to 5-6 are cross-sectional views showing respective steps in the process of fabricating the thin film transistor of FIG. 4;
  • FIG. 5-1 is a cross-sectional view of forming a pattern including a source and a drain;
  • 5-2 is a cross-sectional view showing formation of a pattern including an active layer and a passivation layer, and forming an isolation layer film and a gate film;
  • Figure 5-3 is a cross-sectional view showing the formation of a pattern including a gate
  • Figure 5-4 is a cross-sectional view showing the formation of a pattern including an isolation layer
  • Figure 5-5 is a cross-sectional view after forming a pattern including an isolation layer
  • Figure 5-6 is a cross-sectional view after stripping the photoresist mask
  • Figure 6 is a cross-sectional view showing an array substrate using the thin film transistor of Figure 2;
  • Figure 7 is a cross-sectional view showing an array substrate using the thin film transistor of Figure 4. Description of the reference signs:
  • Example 1 In order to enable those skilled in the art to better understand the technical solutions of the present invention, the thin film transistor of the present invention, a method for fabricating the same, an array substrate, a method for fabricating the same, and a display device will be further described in detail below with reference to the accompanying drawings and embodiments.
  • Example 1
  • the thin film transistor which is a bottom gate structure.
  • the thin film transistor includes a substrate 1 and a gate electrode 2 disposed on the substrate 1, a gate insulating layer 41 as an insulating layer, an active layer 5, a source electrode 6, and a drain electrode 7, wherein The edge layer 41 is disposed between the gate electrode 2 and the active layer 5, and an isolation layer 3 is further disposed between the gate electrode 2 and the active layer 5, and the isolation layer 3 is provided with the gate electrode 2 at least in the forward projection direction.
  • the thin film transistor further includes a buffer layer 8 disposed under the gate 2 and overlapping the gate 1 in the forward projection direction, and the gate 2 is disposed on the buffer layer 8 to enable the gate
  • the pole 1 is more firmly attached and does not fall off easily.
  • the gate electrode 2 is disposed opposite to the active layer 5, and the source electrode 6 and the drain electrode 7 are respectively disposed at both ends of the active layer 5 and partially overlap the gate electrode 2 in the forward projection direction.
  • the gate insulating layer 41 is disposed between the gate electrode 2 and the active layer 5, the isolation layer 3 is closer to the gate electrode 2 than the gate insulating layer 41, and the gate insulating layer 41 is disposed between the isolation layer 3 and the active layer 5, so that Conducive to the diffusion of the material of the gate 2 is blocked.
  • the thin film transistor further includes an etch barrier layer 9.
  • the gate 2 is disposed above the buffer layer 8, and an isolation layer 3, a gate insulating layer 41, and an active layer 5 are sequentially disposed above the gate 1, and the active layer 5 is disposed at On the gate insulating layer 41 above the gate 1, an etch barrier layer 9 is disposed over the active layer 5 and contacts the active layer 5 and the gate insulating layer 41, and the source 6 and the drain 7 are disposed in an etch barrier
  • the layer 9 is above the both ends of the active layer 5, and the source 6 and the drain 7 partially overlap the gate 2 in the front projection direction, respectively, and the etch stop layer 9 corresponds to both ends of the active layer 5.
  • Via holes are respectively formed at the positions, and the source 6 and the drain 7 are respectively connected to the active layer 5 through the via holes.
  • the etch barrier layer 9 when the source electrode 6 and the drain electrode 7 are formed by etching with an etching solution, the etching liquid is prevented from affecting the active layer 5 under the source electrode 6 and the drain electrode 7.
  • the isolation layer 3 is formed by a metal material (such as nano silver) or a metal oxide material (such as indium tin oxide IT0, indium zinc oxide IZ0, indium gallium zinc oxide IGZ0) having conductivity to insulation transition
  • the pole 2 is formed of copper or aluminum, or a copper alloy or an aluminum alloy
  • the active layer 5 is formed of a metal oxide such as indium gallium zinc oxide, indium zinc oxide, indium tin oxide or indium gallium tin oxide.
  • the embodiment further provides a method for preparing a thin film transistor, comprising: on a substrate a step of forming a gate, a gate insulating layer, an active layer, a source and a drain, further comprising the step of forming an isolation layer between the gate and the active layer, the isolation layer being at least in a positive projection direction and having a gate or One of the smaller regions of the source layer coincides, and the barrier property of the spacer layer for material diffusion of the gate layer is greater than the barrier property of the insulating layer for material diffusion of the gate electrode so that the material forming the gate electrode cannot diffuse to the active layer.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching process, and may also include printing, inkjet, etc. for forming a predetermined pattern.
  • the lithography process refers to a process of forming a pattern by using a photoresist, a reticle, an exposure machine, or the like, including a process of film formation, exposure, and development.
  • the corresponding patterning process can be selected according to the structure formed by the array substrate.
  • the active layer or the gate is retained by an ion implantation process or a plasma processing process.
  • the conductivity of the isolation layer in the region corresponding to the pole is converted to the electrical conductivity of the barrier layer in the remaining region.
  • the method for fabricating the thin film transistor specifically includes the following steps: Step S1: forming a pattern including the gate electrode 2 on the substrate 1.
  • a step of forming a pattern including the buffer layer 8 on the substrate 1 may be further included.
  • the specific formation process of the pattern including the buffer layer 8 is: depositing a metal film (such as molybdenum, titanium, molybdenum alloy or titanium alloy) on the surface of the substrate 1, and then forming, corresponding to the gate 2 by exposure, development and etching. shape.
  • a pattern including the gate electrode 2 is formed on the buffer layer 8, and the buffer layer 8 overlaps the gate electrode 1 in the forward projection direction, and the gate electrode 2 can be attached very strongly to the buffer layer. On 8, it is not easy to fall off.
  • Step S2 As shown in Fig. 3-2, an isolation layer film 30, a gate insulating layer film 410, and an active layer film 50 are formed on the substrate 1 on which the step S1 is completed.
  • the isolation layer film 30 is formed of a metal material or a metal oxide material capable of being electrically conductive to insulating property, and the material for forming the isolation layer 3 is deposited in an argon atmosphere to form the isolation layer film 30, which is isolated.
  • the layer film 30 has electrical conductivity; the gate electrode 2 is formed of copper, and the active layer film 50 is made of a metal oxide such as indium gallium zinc oxide or indium zinc oxide. Formed as a compound, indium tin oxide or indium gallium tin oxide.
  • Step S3 As shown in FIG. 3-3, on the substrate 1 on which the step S2 is completed, a pattern including the active layer 5 and the gate insulating layer 41 is formed by a patterning process, and the active layer 5 is disposed opposite to the gate electrode 2; As shown in FIGS. 3-4, a pattern including the isolation layer 3 is formed by an ion implantation process or a plasma treatment process.
  • This step specifically includes:
  • Step S31 Applying a photoresist on the substrate 1 on which the step S2 is completed.
  • Step S32 A photoresist mask 10 is formed by an exposure process and a development process using a mask provided with an active layer 5 pattern.
  • Step S33 The active layer film 50 is formed into a pattern including the active layer 5 by a first etching process, and the area of the active layer 5 is larger than the area of the gate 2.
  • the etching process is a wet etching process.
  • a nitric acid and a sulfuric acid solution to which glacial acetic acid is added may be used as an etching medium, and etching may be performed at a normal temperature to 45 degrees.
  • Step S34 The gate insulating film 410 is formed into a pattern including the gate insulating layer 41 by a second etching process.
  • the etching process is a dry etching process, and in the dry etching process, a fluorine-containing gas such as SF 6 , CF 4 , CHF 3 or a mixed gas of the foregoing gas and 0 2 may be used as an etching medium.
  • Etching is performed in a reactive ion etching machine, a plasma etching machine, a reaction coupling plasma etching machine, or the like.
  • Step S35 As shown in FIG. 3-4, the conductivity of the isolation layer film 30 in the region corresponding to the active layer 5 is retained by the ion implantation process or the plasma treatment process, and the conductivity of the isolation layer film 30 of the remaining region is maintained. The property is changed to insulative to form a pattern including the spacer layer 3, as shown in FIGS. 3-5.
  • the separator film 30 is patterned in an oxygen or nitrogen atmosphere by an ion implantation process (such as implantation of oxygen ions) or a plasma treatment process, and the isolation layer 3 is in a region corresponding to the active layer 5. It has electrical conductivity and is insulative in a region other than the active layer 5.
  • the spacer layer 3 thus treated can well block the diffusion of copper ions or aluminum ions forming the gate electrode 1.
  • the isolation layer has a good prevention of copper ion or aluminum ion expansion of the gate electrode 2 Dispersed to the active layer 5;
  • the gate insulating layer 41 has a good antistatic breakdown effect, and has the function of preventing copper ions or aluminum ions forming the gate electrode 2 from diffusing to the active layer 5 (but with respect to the isolation layer 3) Its ability to prevent proliferation is weak).
  • Step S36 As shown in FIG. 3-6, the photoresist mask 10 is removed by a lift-off process.
  • Step S4 As shown in Fig. 3-7, a pattern including the source 6 and the drain 7 is formed on the substrate 1 on which the step S3 is completed.
  • a pattern including the etch barrier layer 9 may be formed on the substrate 1 on which the step S3 is completed, and then the source 6 and the drain 7 are formed on the etch barrier layer 9. That is, the etch stop layer 9 is formed over the active layer 5 and below the source 6 and the drain 7, and the etch stop layer 9 is respectively provided with via holes at positions corresponding to both ends of the active layer 5, the source The pole 6 and the drain 7 are connected to the active layer 5 through the via holes, respectively.
  • the thin film transistor of the bottom gate structure is prepared.
  • This embodiment is exemplified only in the case where the gate of the thin film transistor is at the bottom, the area of the gate is smaller than the area of the active layer, and the isolation layer recombines with the active layer in the forward projection direction.
  • the material forming the gate When the material forming the gate is diffused, it will all diffuse forward to the region corresponding to the active layer, and the spacer and the insulating layer can more effectively prevent the diffusion of the material forming the gate, for example, preventing copper ions or aluminum.
  • the ions diffuse into the active layer, thereby ensuring the stability of the performance of the thin film transistor.
  • the isolation layer coincides with the active layer in the forward projection direction.
  • the material forming the gate is diffused, a portion of the gate electrode corresponding to the active layer in the forward projection direction will be forwardly diffused to the active layer, and the gate is beyond the active layer.
  • a portion of the copper ion or aluminum ion in the corresponding projection direction will be laterally diffused to the active layer, since the forward diffusion of copper ions or aluminum ions accounts for the majority of the diffused copper ions or aluminum ions,
  • the isolation layer and the insulating layer can also effectively prevent the diffusion of the material forming the gate into the active layer, thereby ensuring the stability of the performance of the thin film transistor.
  • the method of manufacturing the thin film transistor may include the steps of: forming a pattern including the gate 2 on the substrate 1; Forming the isolation film 30, and then forming a spacer layer 3 corresponding to the gate pattern by using a mask plate provided with a pattern of the gate 2 (the formation principle of the isolation layer is the same as that described above); and forming a gate insulating film 410 and the active layer film 50 are then patterned by a patterning process including the gate insulating layer 41 and the active layer 5.
  • This embodiment provides a thin film transistor which is a top gate structure.
  • the insulating layer in the thin film transistor is a passivation layer 42
  • the source 6 and the drain 7 are separately disposed above the substrate 1
  • the active layer 5 is disposed at Between the source 6 and the drain 7 and extending above the source 6 and the drain 7 respectively to contact the source
  • the passivation layer 42 and the isolation layer 3 are sequentially disposed above the active layer 5
  • the buffer layer 8 is disposed above the isolation layer 3
  • the gate electrode 2 is disposed on the buffer layer 8 above.
  • an etch stop layer may be disposed between the active layer and the source and the drain, or an etch stop layer may not be disposed, which is not set in this embodiment.
  • the etch barrier layer is described as an example.
  • the present embodiment further provides a method for fabricating the thin film transistor, which is different from the method for fabricating the thin film transistor of the first embodiment: the preparation method specifically includes the following steps:
  • Step S l as shown in FIG. 5-1, forming a source 6 and a drain on the substrate 1
  • Step S2 As shown in FIG. 5-2, a pattern including the active layer 5 and the passivation layer 42 is formed on the substrate 1 on which the step S1 is completed, and the isolation layer film 30 and the gate electrode are formed on the passivation layer 42. Membrane 20.
  • a buffer layer film 80 may be formed over the isolation layer film 30, for example, by depositing a molybdenum, titanium, molybdenum alloy or titanium alloy material. A metal film is formed; then a gate film 20 is formed over the buffer layer film 80.
  • Step S3 As shown in FIG. 5-3, on the substrate 1 that completes step S2, a pattern including the gate electrode 2 is formed by a patterning process, wherein the active layer 5 is disposed opposite to the gate electrode 2; As shown in FIG. 5-4, a pattern including the isolation layer 3 is formed by an ion implantation process or a plasma treatment process, as shown in FIG. 5-5.
  • a pattern including the buffer layer 8 is formed by an etching process.
  • the shape of the buffer layer 8 corresponds to the shape of the gate electrode 2, the gate electrode 2 is formed on the buffer layer 8, the buffer layer 8 overlaps the gate electrode 2 in the forward projection direction, and the gate electrode 2 can be attached to the buffer layer 8 very firmly. It is not easy to fall off.
  • This step specifically includes:
  • Step S31' A photoresist is applied on the substrate 1 on which the step S2' is completed.
  • Step S32' A photoresist mask 10 is formed by an exposure process and a development process using a mask provided with a gate 1 pattern.
  • Step S33' The gate film 20 is formed into a pattern including the gate electrode 2 by an etching process.
  • the pattern in which the gate film 20 is formed to include the gate electrode 2 is usually a wet etching process; next, the buffer layer film 80 is formed into a pattern including the buffer layer 8 by an etching process.
  • Step S34' as shown in FIG. 5-4, the conductivity of the isolation layer film 30 in the region corresponding to the gate electrode 2 is retained by the ion implantation process or the plasma treatment process, and the conductivity of the isolation layer film 30 of the remaining region is maintained.
  • the properties are converted to insulative to form a pattern comprising the spacer layer 3, as shown in Figures 5-5.
  • Step S35' As shown in Fig. 5-6, the photoresist mask 10 is removed by a lift-off process.
  • the thin film transistor of the top gate structure is prepared.
  • this embodiment shows only that the area of the gate electrode in the thin film transistor is smaller than the area of the active layer, and the isolation layer is shown to coincide with the gate in the forward projection direction.
  • the isolation layer may also coincide with the active layer having a smaller area in the forward projection direction.
  • the method of manufacturing the thin film transistor may include the steps of: forming a source 6 on the substrate 1 And a pattern of the drain electrode 7; forming a pattern including the active layer 5 and the passivation layer 42; forming the isolation layer film 30, and then forming a mask corresponding to the active layer pattern by using a mask provided with the pattern of the active layer 5
  • the isolation layer 3 (the formation principle of the isolation layer is the same as that described above); and the formation of the pattern including the gate electrode 2.
  • Embodiment 1-2 provides an isolation layer between the gate electrode and the active layer, compared to the prior art only between the gate electrode and the active layer
  • the insulating layer is disposed to more effectively prevent the material forming the gate (such as copper ions or aluminum ions) from diffusing into the active layer, thereby ensuring stable performance of the thin film transistor.
  • Example 3
  • the present embodiment provides an array substrate of a thin film transistor having a bottom gate structure, which comprises the thin film transistor of the above embodiment 1.
  • the array substrate in this embodiment further includes gate lines and data lines (not shown in FIG. 6) disposed at intersections, and the gate lines are connected to the gate 2 and disposed in the same layer, and the data lines and the source 6 are provided. Connected and set in the same layer.
  • the gate lines are formed using the same material as the gate electrodes 2.
  • the array substrate further includes a pixel electrode 12 connected to the drain electrode 7.
  • a second insulating layer 11 is further disposed above the source 6 and the drain 7.
  • the second insulating layer 11 is a passivation layer, and the second insulating layer 11 is opened in a region corresponding to the drain 7.
  • the hole, the pixel electrode 12 is disposed above the second insulating layer 11, and is connected to the drain 7 through a via hole opened in the second insulating layer 11.
  • the embodiment further provides a method for preparing the array substrate.
  • the preparation method includes: forming a cross-arrangement on the substrate, in addition to the method for preparing the thin film transistor of the bottom gate structure in Embodiment 1. a step of a gate line and a data line, wherein the data line and the source are formed in the same patterning process, the data line is connected to the source and disposed in the same layer; the gate line and the gate are formed in the same patterning process, the gate line and the gate Connected and set in the same layer.
  • the preparation method still further includes the step of forming a pixel electrode, the pixel electrode being connected to the drain.
  • a second insulating layer is formed over the source and the drain, a via is formed in a region of the second insulating layer corresponding to the drain, and the pixel electrode is formed above the second insulating layer, and is opened in the second A via in the insulating layer is connected to the drain.
  • the structure, the material, and the preparation method of the array substrate of the array substrate other than the thin film transistor in this embodiment are the same as those in the prior art, and are not described herein again.
  • the isolation layer further extends to a region corresponding to the gate line, and coincides with the gate line at least in the forward projection direction.
  • the buffer layer further extends to a region corresponding to the gate line, and coincides with the gate line at least in the forward projection direction. That is, the gate line is also disposed on the buffer layer, and the buffer layer can make the gate line adhesion more secure.
  • the embodiment further provides a method for fabricating the array substrate.
  • the method further includes: forming a gate line on the substrate and Corresponding to the step of the isolation layer of the gate line, the gate line and the gate are formed in the same patterning process, the gate line is connected to the gate and disposed in the same layer, and the isolation layer coincides with the gate line at least in the forward projection direction.
  • the data lines and the source are formed in the same patterning process, and the data lines are connected to the source and disposed in the same layer; the gate lines and the gates Formed in the same patterning process, the gate lines are connected to the gate and disposed in the same layer, and the isolation layer also extends to a region corresponding to the gate lines and coincides with the gate lines at least in the forward projection direction.
  • the conductivity in the region corresponding to the active layer or the gate, and the isolation layer corresponding to the gate line region are retained, and the conductivity of the isolation layer in the remaining region is retained. Change to insulation.
  • Example 5 The structure, the material, and the method for preparing the array substrate of the array substrate other than the thin film transistor in this embodiment are the same as those in the third embodiment, and are not described herein again.
  • Example 5 The structure, the material, and the method for preparing the array substrate of the array substrate other than the thin film transistor in this embodiment are the same as those in the third embodiment, and are not described herein again.
  • the present embodiment provides an array substrate of a thin film transistor having a top gate structure, which comprises the thin film transistor of the above embodiment 2.
  • the pixel electrode 12 is disposed on the surface of the substrate 1 and below the drain 7, and the pixel electrode 12 and the drain are omitted.
  • the poles 7 overlap and are connected.
  • the embodiment further provides a method for preparing the array substrate, which comprises the method for preparing a thin film transistor of the top gate structure in the second embodiment, which is different from the method for preparing the array substrate in the third embodiment, the pixel electrode It is formed on the surface of the substrate and below the drain.
  • the isolation layer further extends to a region corresponding to the gate line, and coincides with the gate line at least in the forward projection direction.
  • the buffer layer further extends to a region corresponding to the gate line, and coincides with the gate line at least in the forward projection direction.
  • the conductivity of the region corresponding to the active layer or the gate and the isolation layer corresponding to the region of the gate line are retained, and The conductivity of the isolation layer in the remaining region is converted into insulation.
  • the structure, the material, and the method for preparing the array substrate of the array substrate other than the thin film transistor in this embodiment are the same as those in the fourth embodiment, and are not described herein again.
  • the isolation layer can prevent diffusion of a material (such as copper ions or aluminum ions) forming a gate electrode in the thin film transistor into the active layer, and further prevent further The material forming the gate line (such as copper ions or aluminum ions) diffuses into the active layer, thereby ensuring the stability of the performance of the array substrate.
  • a material such as copper ions or aluminum ions
  • the embodiment provides a display device comprising the array substrate of any of embodiments 3-6.
  • the display device may be a liquid crystal display device or an electroluminescence display device such as a liquid crystal panel, a liquid crystal television, a mobile phone, a liquid crystal display or the like.

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Abstract

提供一种薄膜晶体管及制备方法、阵列基板及制备方法和显示装置。该薄膜晶体管包括基板（1）以及设置在基板（1）上的栅极（2）、绝缘层（41）、有源层（5）、源极（6）和漏极（7），在栅极（2）和有源层（5）之间还设置有隔离层（3），隔离层（3）至少在正投影方向上与面积较小的栅极（2）和有源层（5）中的一个重合，隔离层（3）能有效防止形成栅极（2）的材料扩散到有源层（5）中，进而保证薄膜晶体管的性能的稳定性。该阵列基板在采用该薄膜晶体管的基础上，使隔离层（3）进一步延伸到对应于栅线（13）的区域，从而能够有效防止形成栅极（3）和栅线（13）的材料扩散到有源层中，进而保证阵列基板的性能的稳定性。

Description

薄膜晶体管及制备方法、 阵列基板及制备方法、 显示装置 技术领域
本发明涉及显示技术领域， 具体地， 涉及一种薄膜晶体管及其 制备方法、 阵列基板及其制备方法、 以及显示装置。 背景技术
在大尺寸 0LED显示装置和液晶显示装置中，通常采用具有较低 电阻的材料， 例如铜（Cu)来形成栅极和栅线， 采用金属氧化物来形 成有源层，以便能够制备出分辨率更高、质量和性能更好的显示产品。 如图 1-1所示为一种现有技术中像素结构的平面图， 其中， 栅线 13 和数据线 14交叉围成的区域内设置有薄膜晶体管 15。如图 1-2所示 为一种底栅结构的薄膜晶体管的沿着图 1-1中 AA' 剖切线截取的剖 视图， 该薄膜晶体管包括基板 1， 基板 1上方依次设置有缓冲层 8、 栅极 2、栅绝缘层 41、有源层 5、刻蚀阻挡层 9和同层设置的源极 6、 漏极 7。 其中， 由铜形成的栅极 2设置在有源层 5的下方， 栅极 2和 有源层 5之间通过栅绝缘层 41绝缘隔开。
到目前为止， 采用铜形成栅极和栅线、 采用金属氧化物形成有 源层，在阵列基板的制备工艺中仍是一项比较先进的技术，但在该制 备工艺中还存在一些问题。例如，在图 1-2所示的薄膜晶体管的结构 中， 栅绝缘层 41的上下两侧分别为有源层 5和栅极 2， 由于栅绝缘 层 41阻挡铜离子扩散的能力较弱， 而在后续的膜层沉积和退火工艺 中一般温度均较高，从而导致铜离子易于扩散至有源层 5中，影响薄 膜晶体管的开关特性，使得薄膜晶体管的性能不稳定，严重时甚至会 使薄膜晶体管的开关性能失效。 发明内容
本发明针对现有技术中存在的上述技术问题， 提供了一种薄膜 晶体管及其制备方法、阵列基板及其制备方法和显示装置。该薄膜晶 体管通过在栅极和有源层之间设置隔离层，从而能够有效防止形成栅 极的材料扩散到有源层中，进而保证薄膜晶体管的性能的稳定性，进 一步保证阵列基板的性能的稳定性。
本发明提供一种薄膜晶体管， 包括基板以及设置在所述基板上 的栅极、 绝缘层、 有源层、源极和漏极， 所述绝缘层设置在所述栅极 和所述有源层之间，其中，在所述栅极和所述有源层之间还设置有隔 离层，所述隔离层对于形成所述栅极的材料扩散的阻隔能力大于所述 绝缘层对于形成所述栅极的材料扩散的阻隔能力。
优选的是， 所述隔离层至少在正投影方向上与面积较小的所述 栅极和所述有源层中的一个重合。
优选的是， 所述隔离层相对所述绝缘层更靠近所述栅极， 所述 绝缘层设置在所述隔离层与所述有源层之间；所述源极和所述漏极分 别对应设置在所述有源层的两端且与所述栅极在正投影方向上部分 重叠。
一种优选方案是， 所述绝缘层为栅绝缘层， 所述薄膜晶体管还 包括刻蚀阻挡层，所述栅极设置在所述基板的上方，所述栅极上方依 次设置有所述隔离层、所述栅绝缘层和所述有源层，所述刻蚀阻挡层 设置在所述有源层的上方，所述刻蚀阻挡层在对应于所述有源层的两 端分别开设有过孔，所述源极和所述漏极分别通过所述过孔与所述有 源层连接。
一种优选方案是， 所述绝缘层为钝化层， 所述源极和所述漏极 相分离地设置在所述基板的上方，所述有源层设置在所述源极和所述 漏极之间且分别延伸至所述源极和所述漏极的上方以接触所述源极 和所述漏极的部分侧壁和部分上表面，所述钝化层和所述隔离层依次 设置在所述有源层的上方， 所述栅极设置在所述隔离层上方。
优选的是， 所述隔离层采用具有由导电性向绝缘性转变性能的 金属材料或金属氧化物材料形成，所述栅极采用铜或铝形成，所述有 源层采用金属氧化物形成。
所述隔离层由纳米银、 氧化铟锡、 掺铟氧化锌、 或铟镓锌氧化 物形成。
一种阵列基板， 包括上述的薄膜晶体管。
优选的是， 所述阵列基板还包括栅线， 所述栅线采用与形成所 述栅极相同的材料形成，所述栅线与所述栅极连接且同层设置，所述 隔离层还延伸至对应于所述栅线的区域，且至少在正投影方向上与所 述栅线重合。
一种显示装置， 包括上述的阵列基板。
一种薄膜晶体管的制备方法， 包括： 在基板上形成栅极、 绝缘 层、有源层、源极和漏极的步骤， 其中在所述栅极与所述有源层之间 形成所述绝缘层，还包括在所述栅极和所述有源层之间形成隔离层的 步骤，所述隔离层对于形成栅极的材料扩散的阻隔能力大于所述绝缘 层对于形成栅极的材料扩散的阻隔能力。
优选的是， 所述隔离层至少在正投影方向上与所述栅极和所述 有源层中面积较小的一个重合。
优选的是， 在所述隔离层与所述有源层之间形成所述绝缘层。 优选的是， 在所述栅极和所述有源层之间形成隔离层的步骤中， 以光刻胶作为掩模，通过离子注入工艺或等离子处理工艺，保留与所 述有源层或所述栅极相对应的区域内的所述隔离层的导电性，而将剩 余区域的所述隔离层的导电性转变为绝缘性。
优选的是， 所述隔离层采用具有由导电性向绝缘性转变性能的 金属材料或金属氧化物材料形成， 并且形成所述隔离层的步骤包括： 用于形成所述隔离层的材料在氩气氛围中，沉积形成隔离层膜，所述 隔离层膜具有导电性； 以及所述隔离层膜在氧气或氮气氛围中，通过 离子注入工艺或等离子处理工艺形成包括所述隔离层的图形， 其中， 所述隔离层在对应于所述有源层或所述栅极的区域具有导电性，在对 应于所述有源层或所述栅极以外的区域具有绝缘性。
所述隔离层由纳米银、 氧化铟锡、 掺铟氧化锌、 或铟镓锌氧化 物形成。
一种阵列基板的制备方法， 包括上述的薄膜晶体管的制备方法。 优选的是， 所述制备方法还进一步包括： 在基板上形成栅线和 对应于所述栅线的隔离层的步骤，所述栅线与所述栅极在同一构图工 艺中形成，所述栅线与所述栅极连接且同层设置，所述隔离层至少在 正投影方向上与所述栅线重合。
优选的是， 在形成对应于栅线的隔离层的步骤中， 以光刻胶作 为掩模，通过离子注入工艺或等离子处理工艺，进一步保留对应于所 述栅线区域的所述隔离层的导电性，而将除了与所述有源层或所述栅 极相对应的区域、和对应于所述栅线区域以外的所述隔离层的导电性 转变为绝缘性。
本发明的有益效果： 本发明所提供的薄膜晶体管通过在栅极和 有源层之间设置隔离层，从而能够有效防止形成栅极的材料扩散，例 如防止铜离子或铝离子扩散到有源层中，进而保证薄膜晶体管的性能 的稳定性。本发明所提供的阵列基板，隔离层能防止薄膜晶体管中形 成栅极的材料扩散到有源层中，甚至进一步防止形成栅线的材料扩散 到有源层中， 进而保证阵列基板的性能的稳定性。 附图说明
图 1-1为现有技术中像素结构的平面图；
图 1-2为示出图 1-1中的薄膜晶体管的沿着图 1-1中 AA' 剖切 线截取的剖视图；
图 2为本发明实施例 1中提供的一种薄膜晶体管的剖视图； 图 3-1至图 3-7为图 2中薄膜晶体管制备过程中各步骤的剖视 图；
其中- 图 3-1为形成包括栅极的图形的剖视图；
图 3-2为形成隔离层膜、 栅绝缘层膜和有源层膜的剖视图； 图 3-3为形成包括有源层和栅绝缘层的图形的剖视图； 图 3-4为形成包括隔离层的图形的剖视图；
图 3-5为形成包括隔离层的图形之后的剖视图；
图 3-6为剥离光刻胶掩膜之后的剖视图；
图 3-7为形成包括源极和漏极的图形的剖视图； 图 4为本发明实施例 2中提供的一种薄膜晶体管的剖视图； 图 5-1至图 5-6为图 4中薄膜晶体管制备过程中各步骤的剖视 图；
其中- 图 5-1为形成包括源极和漏极的图形的剖视图；
图 5-2为形成包括有源层和钝化层的图形， 以及形成隔离层膜 和栅极膜的剖视图；
图 5-3为形成包括栅极的图形的剖视图；
图 5-4为形成包括隔离层的图形的剖视图；
图 5-5为形成包括隔离层的图形之后的剖视图；
图 5-6为剥离光刻胶掩膜之后的剖视图；
图 6为采用图 2中的薄膜晶体管的一种阵列基板的剖视图； 图 7为采用图 4中的薄膜晶体管的一种阵列基板的剖视图。 附图标记说明：
1.基板； 2.栅极； 20.栅极膜； 3.隔离层； 30.隔离层膜； 41.栅 绝缘层； 410.栅绝缘层膜； 42.钝化层； 5.有源层； 50.有源层膜； 6. 源极； 7.漏极； 8.缓冲层； 80.缓冲层膜； 9.刻蚀阻挡层； 10.光刻胶 掩膜； 1 1.第二绝缘层； 12.像素电极； 13.栅线； 14.数据线； 15.薄 膜晶体管。 具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案， 下面结 合附图和具体实施方式对本发明薄膜晶体管及其制备方法、阵列基板 及其制备方法、 以及显示装置作进一步详细描述。 实施例 1
本实施例提供一种薄膜晶体管， 该薄膜晶体管为底栅结构。 如 图 2所示， 该薄膜晶体管包括基板 1以及设置在基板 1上的栅极 2、 作为绝缘层的栅绝缘层 41、 有源层 5、 源极 6和漏极 7， 其中， 栅绝 缘层 41设置在栅极 2和有源层 5之间， 并且在栅极 2和有源层 5之 间还设置有隔离层 3， 隔离层 3至少在正投影方向上与栅极 2和有源 层 5中面积较小的一个重合，隔离层 3对于形成栅极 1的材料扩散的 阻隔能力大于栅绝缘层 41对于形成栅极 1的材料扩散的阻隔能力， 以使得形成栅极 2的材料不能扩散到有源层 5中。
其中， 优选的， 薄膜晶体管还包括缓冲层 8， 缓冲层 8设置在紧 邻栅极 2的下方且在正投影方向上与栅极 1重叠，将栅极 2设置在缓 冲层 8上， 能够使栅极 1附着更加牢固， 不易脱落。栅极 2与有源层 5相对设置，源极 6和漏极 7分别对应设置在有源层 5的两端且与栅 极 2在正投影方向上部分重叠。 栅绝缘层 41设置在栅极 2与有源层 5之间， 隔离层 3相对栅绝缘层 41更靠近栅极 2， 栅绝缘层 41设置 在隔离层 3与有源层 5之间，这样有利于对栅极 2材料的扩散进行阻 隔。
在本实施例中， 薄膜晶体管还包括刻蚀阻挡层 9。具体的， 在薄 膜晶体管的结构中，栅极 2设置在缓冲层 8的上方，在栅极 1的上方 依次设置隔离层 3、 栅绝缘层 41、 和有源层 5， 有源层 5设置在栅绝 缘层 41上相对于栅极 1的上方， 刻蚀阻挡层 9设置在有源层 5的上 方并接触有源层 5和栅绝缘层 41， 源极 6和漏极 7设置在刻蚀阻挡 层 9上相对于有源层 5两端的上方，并且源极 6和漏极 7分别与栅极 2在正投影方向上部分重叠，刻蚀阻挡层 9在与有源层 5的两端对应 的位置处分别开设有过孔，源极 6和漏极 7分别通过该过孔与有源层 5连接。 其中， 通过设置刻蚀阻挡层 9， 使得在采用刻蚀液刻蚀形成 源极 6和漏极 7时，避免刻蚀液对处于源极 6和漏极 7下方的有源层 5造成影响。
其中， 隔离层 3采用具有由导电性向绝缘性转变性能的金属材 料（如纳米银）或金属氧化物材料（如氧化铟锡 IT0、掺铟氧化锌 IZ0、 铟镓锌氧化物 IGZ0)形成， 栅极 2采用铜或铝、 或者铜合金或铝合金 形成， 有源层 5采用金属氧化物如铟镓锌氧化物、铟锌氧化物、铟锡 氧化物或铟镓锡氧化物形成。
本实施例还提供一种薄膜晶体管的制备方法， 包括： 在基板上 形成栅极、 栅绝缘层、 有源层、源极和漏极的步骤， 还包括在栅极和 有源层之间形成隔离层的步骤，隔离层至少在正投影方向上与栅极或 有源层中面积较小的一个重合，隔离层对于形成栅极的材料扩散的阻 隔能力大于绝缘层对于形成栅极的材料扩散的阻隔能力，以使得形成 栅极的材料不能扩散到有源层。
在详细说明制备方法之前， 首先对构图工艺进行解释： 构图工 艺， 可只包括光刻工艺， 或， 包括光刻工艺以及刻蚀步骤， 同时还可 以包括打印、 喷墨等其他用于形成预定图形的工艺； 光刻工艺， 是指 包括成膜、 曝光、 显影等工艺过程的利用光刻胶、掩模板、 曝光机等 形成图形的工艺。本发明中，可根据阵列基板所形成的结构选择相应 的构图工艺。
针对本实施例所提供的薄膜晶体管， 在栅极和有源层之间形成 隔离层的步骤中， 以光刻胶作为掩模，通过离子注入工艺或等离子处 理工艺，保留与有源层或栅极相对应的区域内的隔离层的导电性，而 将剩余区域的隔离层的导电性转变为绝缘性。
具体的， 该薄膜晶体管的制备方法具体包括如下步骤： 步骤 S 1 : 在基板 1上形成包括栅极 2的图形。
在该步骤之前， 即在形成栅极 2之前， 还可以进一步包括在基 板 1上形成包括缓冲层 8的图形的步骤。包括缓冲层 8的图形的具体 形成过程为： 在基板 1表面先沉积一层金属膜（如钼、 钛、 钼合金或 钛合金） ， 然后经过曝光、 显影、 刻蚀形成与栅极 2相对应的形状。
接着， 如图 3-1所示， 将包括栅极 2的图形形成在缓冲层 8上， 缓冲层 8在正投影方向上与栅极 1重叠，栅极 2能非常牢固地附着在 该缓冲层 8上， 不容易脱落。
步骤 S2 :如图 3-2所示，在完成步骤 S 1的基板 1上形成隔离层 膜 30、 栅绝缘层膜 410和有源层膜 50。
该步骤中， 隔离层膜 30采用具有能够由导电性向绝缘性转变性 能的金属材料或金属氧化物材料形成，用于形成隔离层 3的材料在氩 气氛围中沉积而形成隔离层膜 30， 隔离层膜 30具有导电性； 栅极 2 采用铜形成， 有源层膜 50采用金属氧化物如铟镓锌氧化物、 铟锌氧 化物、 铟锡氧化物或铟镓锡氧化物形成。
步骤 S3 : 如图 3-3所示， 在完成步骤 S2的基板 1上， 通过构图 工艺， 形成包括有源层 5和栅绝缘层 41的图形， 有源层 5与栅极 2 相对设置； 如图 3-4所示， 通过离子注入工艺或等离子处理工艺， 形 成包括隔离层 3的图形。
该步骤具体包括：
步骤 S31 : 在完成步骤 S2的基板 1上涂敷光刻胶。
步骤 S32 :采用设置有有源层 5图形的掩模板，通过曝光工艺和 显影工艺， 形成光刻胶掩膜 10。
步骤 S33 : 通过第一次刻蚀工艺， 将有源层膜 50形成为包括有 源层 5的图形， 有源层 5的面积大于栅极 2的面积。
在该步骤中， 刻蚀工艺为湿刻工艺。 湿刻工艺中， 可采用添加 冰醋酸的硝酸和硫酸溶液等作为刻蚀介质， 在常温到 45度的条件下 进行刻蚀。
步骤 S34:通过第二次刻蚀工艺，将栅绝缘层膜 410形成包括栅 绝缘层 41的图形。
在该步骤中， 刻蚀工艺为干刻工艺， 干刻工艺中， 可采用含氟 元素的气体， 如 SF6、 CF4、 CHF3等气体或者前述气体与 02的混合气体 作为刻蚀介质，在反应离子刻蚀机、等离子体刻蚀机或反应耦合等离 子体刻蚀机等中进行刻蚀。
步骤 S35 :如图 3-4所示，通过离子注入工艺或等离子处理工艺， 保留与有源层 5对应的区域内的隔离层膜 30的导电性， 而将剩余区 域的隔离层膜 30的导电性转变为绝缘性， 以形成包括隔离层 3的图 形， 如图 3-5所示。
在该步骤中， 隔离层膜 30在氧气或氮气氛围中， 通过离子注入 工艺 （如注入氧离子） 或等离子处理工艺形成包括隔离层 3的图形， 隔离层 3在对应于有源层 5 的区域具有导电性， 在对应于有源层 5 以外的区域具有绝缘性。经过这样处理的隔离层 3能够对形成栅极 1 的铜离子或铝离子的扩散进行很好的阻隔。
其中， 隔离层具有良好地防止形成栅极 2 的铜离子或铝离子扩 散到有源层 5的作用； 栅绝缘层 41具有良好的防静电击穿的作用， 同时具有防止形成栅极 2 的铜离子或铝离子扩散到有源层 5的作用 (但相对隔离层 3其防扩散的能力较弱） 。
步骤 S36 : 如图 3-6所示， 通过剥离工艺， 将光刻胶掩膜 10去 除。
步骤 S4:如图 3-7所示，在完成步骤 S3的基板 1上形成包括源 极 6和漏极 7的图形。
在该步骤之前， 可以先在完成步骤 S3的基板 1上形成包括刻蚀 阻挡层 9的图形，然后再在刻蚀阻挡层 9上形成源极 6和漏极 7。即， 刻蚀阻挡层 9形成在有源层 5的上方以及源极 6和漏极 7的下方，刻 蚀阻挡层 9在对应于有源层 5的两端的位置处分别开设有过孔，源极 6和漏极 7分别通过该过孔与有源层 5连接。
至此， 底栅结构的薄膜晶体管即制备完成。
本实施例仅以薄膜晶体管中栅极在底部、 栅极的面积小于有源 层的面积、并且隔离层在正投影方向上与有源层重合作为示例。当形 成栅极的材料发生扩散时，其将会全部正向扩散至对应于有源层的区 域， 通过隔离层和绝缘层， 能更有效防止形成栅极的材料扩散， 例如 防止铜离子或铝离子扩散到有源层中，进而保证薄膜晶体管的性能的 稳定性。
这里应该理解的是， 当薄膜晶体管中栅极的面积大于有源层的 面积时，根据本实施例的制备方法中，隔离层在正投影方向上与有源 层重合。当形成栅极的材料扩散时，栅极的与有源层在正投影方向上 相对应的部分的铜离子或铝离子将会正向扩散至有源层，而栅极的超 出与有源层在正投影方向上相对应的部分的铜离子或铝离子将侧向 扩散至有源层，由于正向扩散的铜离子或铝离子占全部扩散铜离子或 铝离子的绝大部分， 因此， 通过隔离层和绝缘层， 同样能有效防止形 成栅极的材料的扩散到有源层中， 保证薄膜晶体管的性能的稳定性。
另外， 在底栅薄膜晶体管中， 当栅极的面积小于有源层的面积 时， 隔离层可以在正投影方向上与栅极重合。此时， 该薄膜晶体管的 制备方法可以包括以下步骤：在基板 1上形成包括栅极 2的图形；形 成隔离层膜 30， 随后采用设置有栅极 2图形的掩膜板来形成与栅极 图形相对应的隔离层 3 (隔离层的形成原理与上述的形成原理相同）； 以及形成栅绝缘层膜 410和有源层膜 50， 随后通过构图工艺形成包 括栅绝缘层 41和有源层 5的图形。 实施例 2
本实施例提供一种薄膜晶体管， 该薄膜晶体管为顶栅结构。 与 实施例 1不同的是，如图 4所示，该薄膜晶体管中的绝缘层为钝化层 42 ,源极 6和漏极 7相分离地设置在基板 1的上方，有源层 5设置在 源极 6和漏极 7之间且分别延伸至源极 6和漏极 7的上方以接触源极
6和漏极 7的部分侧壁和部分上表面， 钝化层 42和隔离层 3依次设 置在有源层 5的上方，缓冲层 8设置在隔离层 3的上方，栅极 2设置 在缓冲层 8上方。
需要说明的是， 本实施例具有顶栅结构的薄膜晶体管中可以在 有源层与源极和漏极之间设置刻蚀阻挡层， 也可以不设置刻蚀阻挡 层， 本实施例以不设置刻蚀阻挡层为例进行说明。
针对本实施例所提供的上述薄膜晶体管， 本实施例还提供一种 该薄膜晶体管的制备方法，与实施例 1中薄膜晶体管的制备方法所不 同的是： 该制备方法具体包括如下步骤：
步骤 S l， ： 如图 5-1所示， 在基板 1上形成包括源极 6和漏极
7的图形。
步骤 S2， ： 如图 5-2所示， 在完成步骤 S l， 的基板 1上形成包 括有源层 5和钝化层 42的图形， 在钝化层 42上形成隔离层膜 30和 栅极膜 20。
在该步骤中， 在钝化层 42上形成隔离层膜 30之后， 还可以在 隔离层膜 30的上方形成缓冲层膜 80， 例如采用钼、 钛、 钼合金或钛 合金材料通过沉积方式形成一层金属膜； 然后在缓冲层膜 80的上方 形成栅极膜 20。
步骤 S3， ： 如图 5-3所示， 在完成步骤 S2， 的基板 1上， 通过 构图工艺，形成包括栅极 2的图形，其中有源层 5与栅极 2相对设置； 如图 5-4所示，通过离子注入工艺或等离子处理工艺，形成包括隔离 层 3的图形，如图 5-5所示。
在该步骤中， 在形成包括栅极 2 的图形之后， 通过刻蚀工艺形 成包括缓冲层 8的图形。缓冲层 8的形状与栅极 2的形状相对应，栅 极 2形成在缓冲层 8上，缓冲层 8在正投影方向上与栅极 2重叠，栅 极 2能非常牢固地附着在缓冲层 8上， 不容易脱落。
该步骤具体包括：
步骤 S31 ' ： 在完成步骤 S2 ' 的基板 1上涂敷光刻胶。
步骤 S32 ' ：采用设置有栅极 1图形的掩模板，通过曝光工艺和 显影工艺， 形成光刻胶掩膜 10。
步骤 S33 ' ： 通过刻蚀工艺， 将栅极膜 20形成为包括栅极 2的 图形。
在该步骤中，将栅极膜 20形成为包括栅极 2的图形通常采用湿 刻工艺； 紧接着， 再通过一次刻蚀工艺， 将缓冲层膜 80形成包括缓 冲层 8的图形。
步骤 S34' ：如图 5-4所示，通过离子注入工艺或等离子处理工 艺， 保留与栅极 2对应的区域内的隔离层膜 30的导电性， 而将剩余 区域的隔离层膜 30的导电性转变为绝缘性， 以形成包括隔离层 3的 图形， 如图 5-5所示。
步骤 S35 ' ： 如图 5-6所示， 通过剥离工艺， 将光刻胶掩膜 10 去除。
本实施例中薄膜晶体管的其它结构、 材质以及薄膜晶体管的制 备方法与实施例 1相同， 此处不再赘述。
至此， 顶栅结构的薄膜晶体管即制备完成。
与实施例 1相同， 这里应该理解的是， 本实施例仅以薄膜晶体 管中栅极的面积小于有源层的面积作为示例，示出了隔离层在正投影 方向上与栅极重合。
当然， 对于顶栅薄膜晶体管中栅极的面积大于有源层的面积的 情况，隔离层在正投影方向上也可以与面积较小的有源层重合。此时， 该薄膜晶体管的制备方法可以包括步骤：在基板 1上形成包括源极 6 和漏极 7的图形； 形成包括有源层 5和钝化层 42的图形； 形成隔离 层膜 30， 随后采用设置有有源层 5图形的掩膜板来形成与有源层图 形相对应的隔离层 3 (隔离层的形成原理与上述的形成原理相同） ； 以及形成包括栅极 2的图形。
实施例 1-2的有益效果： 实施例 1-2所提供的薄膜晶体管通过 在栅极和有源层之间设置隔离层，相比于现有技术中在栅极和有源层 之间仅设置绝缘层，能更有效地防止形成栅极的材料（如铜离子或铝 离子） 扩散到有源层中， 进而保证薄膜晶体管的性能稳定。 实施例 3
本实施例提供一种具有底栅结构的薄膜晶体管的阵列基板， 包 括上述实施例 1中的薄膜晶体管。
如图 6所示， 本实施例中的阵列基板还包括交叉设置的栅线和 数据线（图 6中未示出）， 栅线与栅极 2连接且同层设置， 数据线与 源极 6连接且同层设置。本实施例中，栅线采用与形成栅极 2相同的 材料形成。
该阵列基板还包括像素电极 12，像素电极 12与漏极 7连接。本 实施例中， 在源极 6和漏极 7上方还设置有第二绝缘层 11， 例如第 二绝缘层 11为钝化层，第二绝缘层 11在对应于漏极 7的区域开设有 过孔，像素电极 12设置在第二绝缘层 11的上方，且通过开设在第二 绝缘层 11中的过孔与漏极 7连接。
针对该阵列基板， 本实施例还提供一种该阵列基板的制备方法， 该制备方法除了包括实施例 1 中底栅结构的薄膜晶体管的制备方法 之外，还包括：在基板上形成交叉设置的栅线和数据线的步骤，其中， 数据线与源极在同一构图工艺中形成， 数据线与源极连接且同层设 置；栅线与栅极在同一构图工艺中形成，栅线与栅极连接且同层设置。
该制备方法还进一步包括形成像素电极的步骤， 像素电极与漏 极连接。本实施例中， 在源极和漏极上方形成第二绝缘层， 在第二绝 缘层对应于漏极的区域开设过孔， 像素电极形成在第二绝缘层的上 方， 且通过开设在第二绝缘层中的过孔与漏极连接。 本实施例中阵列基板除薄膜晶体管以外的其它结构、 材质以及 阵列基板的制备方法与现有技术相同， 此处不再赘述。 实施例 4
本实施例与实施例 3 的区别在于， 本实施例的阵列基板中， 隔 离层还延伸至对应于栅线的区域， 且至少在正投影方向上与栅线重 合。 本实施例的阵列基板中， 缓冲层还延伸至对应于栅线的区域， 且至少在正投影方向上与栅线重合。 即， 栅线也设置在缓冲层上， 缓 冲层能够使栅线附着更加牢固。
针对该阵列基板， 本实施例还提供一种该阵列基板的制备方法， 与实施例 1中底栅结构的薄膜晶体管的制备方法相比，该制备方法还 进一步包括：在基板上形成栅线和对应于栅线的隔离层的步骤，栅线 与栅极在同一构图工艺中形成，栅线与栅极连接且同层设置， 隔离层 至少在正投影方向上与栅线重合。
在本实施例中， 在基板上形成交叉设置的栅线和数据线的步骤 中，数据线与源极在同一构图工艺中形成，数据线与源极连接且同层 设置；栅线与栅极在同一构图工艺中形成，栅线与栅极连接且同层设 置， 隔离层还延伸至对应于栅线的区域，且至少在正投影方向上与栅 线重合。 同时， 在形成包括隔离层的图形的步骤中， 保留与有源层或 栅极相对应的区域内、和对应于栅线区域的隔离层的导电性，而将剩 余区域的隔离层的导电性转变为绝缘性。
本实施例中阵列基板除薄膜晶体管以外的其它结构、 材质以及 阵列基板的制备方法与实施例 3相同， 此处不再赘述。 实施例 5
本实施例提供一种具有顶栅结构的薄膜晶体管的阵列基板， 包 括上述实施例 2中的薄膜晶体管。
与实施例 3不同的是， 如图 7所示， 本实施例阵列基板中， 像 素电极 12设置在基板 1表面上以及漏极 7的下方，像素电极 12与漏 极 7重叠且连接。
针对该阵列基板， 本实施例还提供一种该阵列基板的制备方法， 包括实施例 2中顶栅结构的薄膜晶体管的制备方法，与实施例 3中阵 列基板的制备方法不同的是，像素电极形成在基板表面上以及漏极的 下方。
本实施例中阵列基板除薄膜晶体管以外的其它结构、 材质以及 阵列基板的制备方法与实施例 3相同， 此处不再赘述。 实施例 6
本实施例与实施例 5 的区别在于， 本实施例的阵列基板中， 隔 离层还延伸至对应于栅线的区域， 且至少在正投影方向上与栅线重 合。 本实施例的阵列基板中， 缓冲层还延伸至对应于栅线的区域， 且至少在正投影方向上与栅线重合。
在本实施例阵列基板的制备方法中， 在形成包括隔离层的图形 的步骤中，保留与有源层或栅极相对应的区域、和对应于栅线的区域 的隔离层的导电性， 而将剩余区域的隔离层的导电性转变为绝缘性。
本实施例中阵列基板除薄膜晶体管以外的其它结构、 材质以及 阵列基板的制备方法与实施例 4相同， 此处不再赘述。
实施例 3-6的有益效果： 实施例 3-6所提供的阵列基板， 隔离 层能防止薄膜晶体管中形成栅极的材料（如铜离子或铝离子）扩散到 有源层中， 甚至进一步防止形成栅线的材料（如铜离子或铝离子）扩 散到有源层中， 进而保证阵列基板的性能的稳定性。 实施例 7 :
本实施例提供一种显示装置， 包括实施例 3-6 中任一所述的阵 列基板。
所述显示装置可以为液晶显示装置或者电致发光显示装置， 例 如液晶面板、 液晶电视、 手机、 液晶显示器等。
该显示装置中， 通过采用设置有隔离层的阵列基板， 从而保证

Claims

显示装置的性能的稳定性。 可以理解的是， 以上实施方式仅仅是为了说明本发明的原理而 采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的 普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做 出各种变型和改进， 这些变型和改进也视为本发明的保护范围。 权 利 要 求 书
1 . 一种薄膜晶体管， 包括基板以及设置在所述基板上的栅极、 绝缘层、有源层、源极和漏极， 所述绝缘层设置在所述栅极和所述有 源层之间，其特征在于，在所述栅极和所述有源层之间还设置有隔离 层，所述隔离层对于形成所述栅极的材料扩散的阻隔能力大于所述绝 缘层对于形成所述栅极的材料扩散的阻隔能力。
2. 根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述隔离 层至少在正投影方向上与所述栅极和所述有源层中面积较小的一个 重合。
3. 根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述隔离 层与所述绝缘层相比更靠近所述栅极，所述绝缘层设置在所述隔离层 与所述有源层之间。
4. 根据权利要求 3所述的薄膜晶体管， 其特征在于， 所述源极 和所述漏极分别对应设置在所述有源层的两端且与所述栅极在正投 影方向上部分重叠。
5. 根据权利要求 4所述的薄膜晶体管， 其特征在于， 所述绝缘 层为栅绝缘层， 所述薄膜晶体管还包括刻蚀阻挡层， 其中，
所述栅极设置在所述基板的上方， 所述栅极上方依次设置有所 述隔离层、所述栅绝缘层、和所述有源层， 所述刻蚀阻挡层设置在所 述有源层的上方，所述刻蚀阻挡层在对应于所述有源层的两端分别开 设有过孔， 所述源极和所述漏极分别通过所述过孔与所述有源层连 接。
6. 根据权利要求 4所述的薄膜晶体管， 其特征在于， 所述绝缘 层为钝化层， 其中， 所述源极和所述漏极相分离地设置在所述基板的上方， 所述有 源层设置在所述源极和所述漏极之间且分别延伸至所述源极和所述 漏极的上方以接触所述源极和所述漏极的部分侧壁和部分上表面，所 述钝化层和所述隔离层依次设置在所述有源层的上方，所述栅极设置 在所述隔离层上方。
7. 根据权利要求 1-6中任意一项所述的薄膜晶体管， 其特征在 于，所述隔离层采用具有由导电性向绝缘性转变性能的金属材料或金 属氧化物材料形成，所述栅极采用铜或铝形成，所述有源层采用金属 氧化物形成。
8. 根据权利要求 7所述的薄膜晶体管， 其特征在于， 所述隔离 层由纳米银、 氧化铟锡、 掺铟氧化锌、 或铟镓锌氧化物形成。
9. —种阵列基板， 其特征在于， 所述阵列基板包括根据权利要 求 1-8中任意一项所述的薄膜晶体管。
10. 根据权利要求 9所述的阵列基板， 其特征在于， 所述阵列 基板还包括栅线，所述栅线采用与形成所述栅极相同的材料形成，所 述栅线与所述栅极连接且同层设置，所述隔离层还延伸至对应于所述 栅线的区域， 且至少在正投影方向上与所述栅线重合。
11. 一种显示装置， 其特征在于， 包括根据权利要求 9或 10所 述的阵列基板。
12. 一种薄膜晶体管的制备方法， 包括： 在基板上形成栅极、 绝缘层、有源层、源极和漏极的步骤， 其中在所述栅极与所述有源层 之间形成所述绝缘层，其特征在于，还包括在所述栅极和所述有源层 之间形成隔离层的步骤，所述隔离层对于形成栅极的材料扩散的阻隔 能力大于所述绝缘层对于形成栅极的材料扩散的阻隔能力。
13. 根据权利要求 12所述的薄膜晶体管的制备方法， 其特征在 于，所述隔离层至少在正投影方向上与所述栅极和所述有源层中面积 较小的一个重合。
14. 根据权利要求 12所述的薄膜晶体管的制备方法， 其特征在 于， 在所述隔离层与所述有源层之间形成所述绝缘层。
15. 根据权利要求 12所述的薄膜晶体管的制备方法， 其特征在 于，在所述栅极和所述有源层之间形成隔离层的步骤中， 以光刻胶作 为掩模，通过离子注入工艺或等离子处理工艺，保留与所述有源层或 所述栅极相对应的区域内的所述隔离层的导电性，而将剩余区域的所 述隔离层的导电性转变为绝缘性。
16. 根据权利要求 15所述的薄膜晶体管的制备方法， 其特征在 于，所述隔离层采用具有由导电性向绝缘性转变性能的金属材料或金 属氧化物材料形成，并且形成所述隔离层的步骤包括：用于形成所述 隔离层的材料在氩气氛围中，沉积形成隔离层膜，所述隔离层膜具有 导电性； 以及所述隔离层膜在氧气或氮气氛围中，通过离子注入工艺 或等离子处理工艺形成包括所述隔离层的图形，其中，所述隔离层在 对应于所述有源层或所述栅极的区域具有导电性，在对应于所述有源 层或所述栅极以外的区域具有绝缘性。
17. 根据权利要求 16所述的薄膜晶体管的制备方法， 其特征在 于， 所述隔离层由纳米银、 氧化铟锡、 掺铟氧化锌、 或铟镓锌氧化物 形成。
18. 一种阵列基板的制备方法， 其特征在于， 包括根据权利要 求 12-17中任意一项所述的薄膜晶体管的制备方法。
19.根据权利要求 18所述的阵列基板的制备方法，其特征在于， 所述制备方法还进一步包括：在基板上形成栅线和对应于所述栅线的 隔离层的步骤，所述栅线与所述栅极在同一构图工艺中形成，所述栅 线与所述栅极连接且同层设置，所述隔离层至少在正投影方向上与所 述栅线重合。
20.根据权利要求 19所述的阵列基板的制备方法，其特征在于， 在形成对应于栅线的隔离层的步骤中， 以光刻胶作为掩模，通过离子 注入工艺或等离子处理工艺，进一步保留对应于所述栅线区域的所述 隔离层的导电性， 而将除了与所述有源层或所述栅极相对应的区域、 和对应于所述栅线区域以外的所述隔离层的导电性转变为绝缘性。
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