WO2015096298A1 - 薄膜晶体管及其制备方法、阵列基板、显示装置 - Google Patents
薄膜晶体管及其制备方法、阵列基板、显示装置 Download PDFInfo
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- WO2015096298A1 WO2015096298A1 PCT/CN2014/075099 CN2014075099W WO2015096298A1 WO 2015096298 A1 WO2015096298 A1 WO 2015096298A1 CN 2014075099 W CN2014075099 W CN 2014075099W WO 2015096298 A1 WO2015096298 A1 WO 2015096298A1
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- metal oxide
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- oxide semiconductor
- oxidized
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- 239000010409 thin film Substances 0.000 title claims abstract description 80
- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 238000002360 preparation method Methods 0.000 title abstract description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 238
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 231
- 239000004065 semiconductor Substances 0.000 claims abstract description 136
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000002184 metal Substances 0.000 claims abstract description 55
- 238000005468 ion implantation Methods 0.000 claims abstract description 44
- 150000002500 ions Chemical class 0.000 claims abstract description 41
- 239000010410 layer Substances 0.000 claims description 236
- 238000000034 method Methods 0.000 claims description 62
- 230000004888 barrier function Effects 0.000 claims description 30
- -1 gallium ions Chemical class 0.000 claims description 16
- 239000011241 protective layer Substances 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 229910001449 indium ion Inorganic materials 0.000 claims description 3
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 3
- 229910001432 tin ion Inorganic materials 0.000 claims description 3
- 229910001887 tin oxide Inorganic materials 0.000 claims description 3
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims 2
- 229910001195 gallium oxide Inorganic materials 0.000 claims 2
- 229910052735 hafnium Inorganic materials 0.000 claims 2
- 238000000926 separation method Methods 0.000 claims 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 abstract description 8
- 239000002019 doping agent Substances 0.000 abstract description 4
- 239000007943 implant Substances 0.000 abstract description 4
- 239000011787 zinc oxide Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000000463 material Substances 0.000 description 22
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 description 16
- 239000004020 conductor Substances 0.000 description 15
- 238000000059 patterning Methods 0.000 description 13
- 239000010408 film Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 8
- BNEMLSQAJOPTGK-UHFFFAOYSA-N zinc;dioxido(oxo)tin Chemical compound [Zn+2].[O-][Sn]([O-])=O BNEMLSQAJOPTGK-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 208000001848 dysentery Diseases 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021645 metal ion Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- NPXOKRUENSOPAO-UHFFFAOYSA-N Raney nickel Chemical class [Al].[Ni] NPXOKRUENSOPAO-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052691 Erbium Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052762 osmium Inorganic materials 0.000 description 1
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium atom Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/42—Bombardment with radiation
- H01L21/423—Bombardment with radiation with high-energy radiation
- H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/42—Bombardment with radiation
- H01L21/423—Bombardment with radiation with high-energy radiation
- H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/426—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Definitions
- Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device. Background technique
- a high mobility thin film transistor has a polysilicon TFT and a metal oxide TFT.
- the uniformity of the polysilicon TFT is complicated, the fabrication process is complicated, and it is limited by the equipment such as laser crystallization, which is not conducive to large-mode production; and the metal oxide TFT has high mobility, uniformity, transparency, simple fabrication process, and can be better.
- the demand for a large liquid crystal display (LCD), an organic light emitting diode (OLED), and a polymer light emitting diode (PLED) has been met. Widespread concern.
- a certain energy barrier is generated on a contact surface between a source, a drain, and a semiconductor active layer, thereby forming a contact resistance; the energy barrier can hinder the movement of carriers. .
- the energy barrier at the interface is large, when a Schottky contact is formed, the loss of the signal is easily caused, thereby affecting the performance of the TFT.
- the subsequent preparation process may cause damage to the metal oxide semiconductor active layer, resulting in deterioration of TFT performance.
- Embodiments of the present invention provide a thin film transistor and a method of fabricating the same, an array substrate, and a display device, which can solve the problem of contact resistance between a source, a drain, and a semiconductor active layer, and avoid the semiconductor active layer during the preparation process. damage.
- a thin film transistor including a gate electrode disposed on a substrate, a gate insulating layer, a metal oxide semiconductor active layer, a source and a drain; and the metal oxide semiconductor active layer is disposed on the substrate Between the source and the drain, and corresponding to a gap between the source and the drain; the thin film transistor further includes a layer disposed in the same layer as the metal oxide semiconductor active layer a first pattern and a second pattern that are in contact; the first pattern corresponds to the source and is in direct contact, and the second pattern corresponds to the drain and is in direct contact.
- the first pattern and the second pattern each comprise an oxidized dibasic metal oxide
- the metal oxide semiconductor active layer comprises an oxidized multi-element metal oxide semiconductor
- the oxidized multi-element metal oxide The material is a metal oxide obtained by injecting metal doping ions into the oxidized dibasic metal oxide.
- a width of the metal oxide semiconductor active layer is the same as a gap width between the source and the drain.
- the thin film transistor is a bottom gate type; the thin film transistor further includes a protective layer disposed above the source and the drain.
- the thin film transistor is a top gate type.
- the oxidized dibasic metal oxide comprises indium oxide (Indium
- the metal doping ions include at least one of gallium ions (Ga 3+ ), tin ions (Sn 2+ ), germanium ions (Hi 4 —), aluminum ions (Al 3+ ), and indium ions (In 3+ ).
- gallium ions Ga 3+
- tin ions Sn 2+
- germanium ions Hi 4 —
- aluminum ions Al 3+
- indium ions In 3+
- both side edges of the metal oxide semiconductor active layer are respectively aligned with edges opposite to the source and the drain.
- An array substrate is also provided, including the thin film transistor described above.
- a method of fabricating the above thin film transistor comprising forming a gate, a gate insulating layer, a metal oxide semiconductor active layer, a source and a drain on a substrate.
- Forming the metal oxide semiconductor active layer on the substrate includes: forming an oxidized binary metal oxide pattern layer on the substrate, the pattern layer including a first pattern corresponding to the source, and the drain a second pattern corresponding to the pole, and a third pattern corresponding to a gap between the source and the drain, and the oxidized binary metal oxide pattern layer and the source and the drain Very direct contact; forming an insulating layer over the source and the drain as a barrier layer, using an ion implantation technique to the oxidized word system
- the metal oxide pattern layer is implanted with metal doping ions, and the oxidized dibasic metal oxide of the third pattern is converted into an oxidized polysystem metal oxide semiconductor to form the metal oxide semiconductor active layer .
- the thin film transistor is of a bottom gate type.
- the method further includes: forming a protective layer on the substrate on which the source and the drain are formed; wherein, the insulating layer is used as a barrier layer, and the oxidized word binary metal is oxidized by an ion implantation technique Injecting metal doping ions into the pattern layer, converting the oxidized dibasic metal oxide of the third pattern into an oxidized multi-element metal oxide semiconductor, and forming the metal oxide semiconductor active layer comprises:
- the protective layer is a barrier layer, and the metal-doped ions are implanted into the oxidized dysentery binary metal oxide pattern layer by an ion implantation technique, and the third layer is not blocked by the source and the drain
- the oxidized dibasic metal oxide of the pattern is converted into an oxidized multi-element metal oxide semiconductor to form the metal oxide semiconductor active layer.
- the thin film transistor is a top gate type.
- the insulating layer is used as a barrier layer, and metal ion doping ions are implanted into the oxidized dysentery binary metal oxide pattern layer by an ion implantation technique, and the oxidized lexic binary metal of the third pattern is
- the oxide is converted into an oxidized multi-element metal oxide semiconductor, and the forming of the metal oxide semiconductor active layer includes: using the gate insulating layer as a barrier layer, and oxidizing the oxidized divalent metal by using an ion implantation technique
- the pattern layer implants metal doping ions, and converts the oxidized dibasic metal oxide of the third pattern that is not blocked by the source and the drain into an oxidized multi-element metal oxide semiconductor,
- the metal oxide semiconductor active layer is formed.
- the method further comprises performing an annealing treatment.
- the oxidized dibasic metal oxide includes IZO, or AZO, or GZO, or tin oxide TZO; the Ga 3+ , Sn 2+ , 1 +, Al 3+ , and In 3+ At least one of them.
- Embodiments of the present invention provide a thin film transistor and a method of fabricating the same, an array substrate, and a display device.
- the preparation method includes forming a gate, a gate insulating layer, a metal oxide semiconductor active layer, a source and a drain on a substrate.
- the forming a metal oxide semiconductor active layer on the substrate may include: forming an oxidized binary metal oxide pattern layer on the substrate, the pattern layer including a first pattern corresponding to the source, and the a second pattern corresponding to the drain, and a third pattern corresponding to a gap between the source and the drain, and the oxidized binary metal oxide pattern layer and the source Directly contacting the drain and the drain; forming an insulating layer over the source and the drain as a barrier layer, and implanting a metal dopant into the oxidized binary metal oxide pattern layer by an ion implantation technique The ionic oxide-based binary metal oxide of the third pattern is converted into an oxidized polyene metal oxide semiconductor to form the metal oxide semiconductor active layer.
- the third pattern of the oxidized dibasic metal oxide is converted into an oxidized multi-element metal by ion implantation.
- a region from the conductor to the semiconductor is formed under the source and the drain, so that a transition is provided under the source and the drain to provide carrier transport.
- the insulating layer is a barrier layer, and the metal oxide semiconductor active layer is formed by an ion implantation technique, which not only avoids damage of the metal oxide semiconductor active layer which may be caused during ion implantation, but also prevents preparation of the thin film transistor. Other subsequent processes in the process may have an effect on the metal oxide semiconductor active layer, thereby improving the performance of the thin film transistor.
- FIG. 1 (a) is a schematic diagram of performing ion implantation according to an embodiment of the present invention
- FIG. 1(b) is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention
- FIG. 2(a) is a schematic diagram of another ion implantation according to an embodiment of the present invention
- FIG. 3 to FIG. 5 are schematic diagrams showing a process of forming a thin film transistor according to an embodiment of the present invention
- FIG. 6 to FIG. 8 are another method for forming a thin film according to an embodiment of the present invention.
- Schematic diagram of a process of a transistor FIG. 9 is a schematic structural view of an array substrate provided by the present invention. detailed description
- Embodiments of the present invention provide a method of fabricating a thin film transistor 10 including forming a gate electrode 101, a gate insulating layer 102, a metal oxide semiconductor active layer 103, a source 104, and a drain 105 on a substrate.
- the forming the metal oxide semiconductor active layer 103 on the substrate may include: forming an oxidized binary metal oxide pattern layer 1030 on the substrate, the pattern layer including the first pattern 1031 corresponding to the source 104 a second pattern 1032 corresponding to the drain 105 and a third pattern 1033 corresponding to a gap between the source 104 and the drain 105, and the oxidized binary metal oxide pattern
- the layer 1030 is in direct contact with the source 104 and the drain 105; the insulating layer formed over the source 104 and the drain 105 is a barrier layer, and the oxidization system is applied by ion implantation technique.
- the binary metal oxide pattern layer 1030 injects metal doping ions, and converts the oxidized dibasic metal oxide of the third pattern 1033 into an oxidized multi-element metal oxide semiconductor to form the metal oxide semiconductor. Active layer 103.
- the third pattern 1033 or the formed metal oxide semiconductor active layer 103 corresponds to the gap between the source 104 and the drain 105.
- a width of the MOS active layer 103 and a gap between the source 104 and the drain 105 The width is the same.
- both side edges of the MOS active layer 103 are opposite to the source 104 and the drain 105, respectively. The edges are aligned.
- the oxidized dibasic metal oxide refers to a binary metal oxide formed by doping other metal elements with an oxidized word as a matrix; here, the oxidized dibasic metal oxide It is a conductive material.
- the oxidized double metal oxide pattern layer 1030 includes three portions of a first pattern 1031, a second pattern 1032, and a third pattern 1033, the three portions being merely structurally distinguished regardless of the constituent materials.
- the material of the third pattern 1033 is converted from the oxidized dibasic metal oxide to the oxidized multi-element metal oxide semiconductor after ion implantation; but for the thin film transistor 10, Keep the original pattern shape and in the original position.
- the direct contact of the oxidized binary metal oxide pattern layer 1030 with the source 104 and the drain 105 refers to the first diagram of the oxidized binary metal oxide pattern layer 1030.
- the first pattern 1031 and the second pattern 1032 are in direct contact with the source 104 and the drain 105, respectively, and the third pattern 1033 is exposed by a gap between the source 104 and the drain 105.
- the insulating layer formed over the source 104 and the drain 105 is a barrier layer.
- the source 104 and the drain 105 are formed first, and the barrier layer is formed.
- the barrier layer may be any insulating layer having a barrier effect.
- the insulating layer having the blocking effect when the insulating layer having the blocking effect is already included, the insulating layer can be directly used as the barrier layer; when the insulating layer itself is not used as the barrier layer, the layer can be newly prepared.
- An insulating layer with a barrier effect when the insulating layer having the blocking effect is already included, the insulating layer can be directly used as the barrier layer; when the insulating layer itself is not used as the barrier layer, the layer can be newly prepared. An insulating layer with a barrier effect.
- the method for forming the metal oxide semiconductor active layer 103 by the ion implantation technique can be applied to any of the thin film transistors including the bottom gate type and the top gate type, which is not limited herein, and the specific process can be based on the thin film transistor.
- the actual construction is designed.
- Embodiments of the present invention provide a method of fabricating a thin film transistor 10 including forming a gate electrode 101, a gate insulating layer 102, a metal oxide semiconductor active layer 103, a source 104, and a drain 105 on a substrate.
- the forming the metal oxide semiconductor active layer 103 on the substrate may include: forming an oxidized binary metal oxide pattern layer 1030 on the substrate, the pattern layer including the first pattern 1031 corresponding to the source 104 a second pattern 1032 corresponding to the drain 105 and a third pattern 1033 corresponding to a gap between the source 104 and the drain 105, and the oxidized binary metal oxide pattern
- the layer 1030 is in direct contact with the source 104 and the drain 105; the insulating layer formed over the source 104 and the drain 105 is a barrier layer, and the oxidization system is applied by ion implantation technique.
- the binary metal oxide pattern layer 1030 injects metal doping ions, and converts the oxidized dibasic metal oxide of the third pattern 1033 into an oxidized multi-element metal oxide semiconductor to form the metal oxide semiconductor. Active layer 103.
- the oxidized dibasic metal oxide of the third pattern 1033 is converted into an oxidized plural by ion implantation.
- a region corresponding to a transition from a conductor to a semiconductor is formed under the source 104 and the drain 105, so that the source 104 and the A transition layer capable of providing carrier transport is formed under the drain electrode 105, effectively solving the problem of contact resistance between the metal oxide semiconductor active layer 103 and the source 104 and the drain 105.
- forming the metal oxide semiconductor active layer 103 by an ion implantation technique with the insulating layer as a barrier layer can not only avoid damage of the metal oxide semiconductor active layer 103 which may be caused during ion implantation, but also The influence that other subsequent processes may have on the metal oxide semiconductor active layer 103 during the preparation of the thin film transistor 10 can be prevented, thereby improving the performance of the thin film transistor 10.
- the method may specifically include: sequentially forming the gate electrode 101, the gate insulating layer 102, and the oxidized word system on a substrate. a patterned metal layer 1030, the source 104 and the drain 105, and a protective layer 106 over the source 104 and the drain 105.
- the oxidized double metal oxide pattern layer 1030 includes the first pattern 1031 corresponding to the source 104 and directly contacting the second pattern 1032 corresponding to and directly contacting the drain 105. And the third pattern 1033 corresponding to a gap between the source 104 and the drain 105.
- the protective layer 106 may be used as a barrier layer, and the oxidization system may be applied by ion implantation.
- the binary metal oxide pattern layer 1030 implants metal doping ions to convert the oxidized dibasic metal oxide of the third pattern 1033 not blocked by the source 104 and the drain 105 into
- the oxidized multi-element metal oxide semiconductor is formed to form the metal oxide semiconductor active layer 103, and a bottom-gate thin film transistor shown in FIG. 1(b) is obtained.
- the implantation dose of the metal doping ions and the bombardment energy need to be strictly controlled.
- the implantation dose may be proportional to the content of the two metals in the oxidized dibasic metal oxide; and the bombardment energy is required to ensure that most of the metal doping ions can enter the oxidized dibasic metal oxide.
- the third pattern 1033 of the pattern layer 1030 is combined with the oxidized dibasic metal oxide to form the oxidized multi-element metal oxide semiconductor. Therefore, in the process of ion implantation, high energy deep injection can be used according to the actual situation.
- the third pattern 1033 blocked by the drain 105 is described. Due to the binary system in the oxidation The source 104 and the drain 105 have been formed above the metal oxide pattern layer 1030, and metal doping ions penetrating the protective layer 106 are blocked by the source 104 and the drain 105, and The metal doping ions are not implanted into the first pattern 1031 corresponding to the source 104 and the second pattern 1032 corresponding to the drain 105, and only the source 104 and the drain are not implanted The third pattern 1033 blocked by the pole 105, thereby converting only the oxidized dibasic metal oxide of the third pattern 1033 into the oxidized multi-element metal oxide semiconductor, forming a metal oxide semiconductor Source layer 103.
- the material of the third pattern 1033 is an oxidized multi-element metal oxide semiconductor material, and the materials of the first pattern 1031 and the second pattern 1032 are oxidized binary Metal oxide conductive material. Since the first pattern 1031 is in direct contact with the source 104, the second pattern 1032 is in direct contact with the drain 105, so it can be considered that the source 104 further includes the first pattern 1031. The drain 105 further includes the second pattern 1032.
- the method may further include: sequentially forming the oxidized binary metal oxide pattern layer 1030 on the substrate, the source 104 and the drain 105, the gate insulating layer 102, and the gate electrode 101.
- the oxidized double metal oxide pattern layer 1030 includes the first pattern 1031 corresponding to the source 104 and directly contacting the second pattern 1032 corresponding to and directly contacting the drain 105. And the third pattern 1033 corresponding to a gap between the source 104 and the drain 105.
- the gate insulating layer 102 may be used as a barrier layer. Injecting metal doping ions into the oxidized dysentery binary metal oxide pattern layer 1030 by ion implantation techniques, as described in the third pattern 1033 not blocked by the source 104 and the drain 105 The oxidized dibasic metal oxide is converted into the oxidized multi-element metal oxide semiconductor to form the metal oxide semiconductor active layer 103; then, the gate 201 is formed over the gate insulating layer 102 Thereby, the top gate type thin film transistor shown in FIG. 2(b) is obtained.
- the source 104 and the drain 105 are located above the oxidized binary metal oxide pattern layer 1030, and the ionic oxide binary metal oxide pattern layer 1030 is formed by ion implantation.
- metal doping ions When metal doping ions are implanted, metal doping ions penetrating the gate insulating layer 102 are subject to Blocking to the source 104 and the drain 105, such that the metal doping ions cannot be implanted into the first pattern 1031 corresponding to the source 104 and the second corresponding to the drain 105
- the pattern 1032 implants only the third pattern 1033 that is not blocked by the source 104 and the drain 105, thereby converting only the oxidized dibasic metal oxide of the third pattern 1033 into a
- the oxidized polysystem is a multi-metal oxide semiconductor, and a metal oxide semiconductor active layer 103 is formed.
- the material of the third pattern 1033 is an oxidized multi-element metal oxide semiconductor material, and the materials of the first pattern 1031 and the second pattern 1032 are oxidized lines.
- the first pattern 1031 is in direct contact with the source 104, and the second pattern 1032 is in direct contact with the drain 105. Therefore, the source 104 may be further included as the first pattern 1031.
- the drain 105 further includes the second pattern 1032.
- the method may further include performing an annealing treatment.
- the structure of the oxidized multi-element metal oxide semiconductor formed directly after ion implantation is disordered, and the structure of the oxidized multi-element metal oxide semiconductor can be made by annealing. Being in an effective conductive position, the performance of the thin film transistor 10 can be optimized.
- the oxidized dibasic metal oxide may include IZO, or AZO, or GZO, or TZO; the metal doping ions may include Ga 3+ , Sn 2+ , Hi 4 — Al 3+ And at least one of In 3+ .
- IZO, AZO, GZO, and TZO are all widely studied metal oxide semiconductor active layer materials for the oxidized dibasic metal oxide.
- a metal doping element is usually added to the above-described oxidized binary metal oxide to form, for example, IGZO, ITZO, ruthenium, osmium, and iridium.
- a stable semiconductor material for example, IGZO, ITZO, ruthenium, osmium, and iridium.
- the control of the conductivity of the semiconductor material can be controlled by controlling the carrier concentration inside the semiconductor material; when the carrier concentration inside the semiconductor material is greater than a certain critical value, That is, the conductor characteristics are exhibited.
- the material of the oxidized binary metal oxide pattern layer 1030 may include IZO, AZO, GZO, and TZO, which are utilized as the conductor characteristics thereof; Forming the said The oxidized multi-element metal oxide semiconductor can exhibit its semiconductor characteristics at this time.
- the method specifically includes:
- a pattern including the gate electrode 101 is formed by a patterning process on the base substrate; and a gate insulating layer 102 is formed on the substrate on which the gate electrode 101 is formed.
- gate electrode 101 While the gate electrode 101 is formed, gate lines, gate line leads, and the like are also formed. Of course, a common electrode line may be formed.
- a thickness of 1000A can be deposited on the substrate by magnetron sputtering.
- a metal film of 7000A wherein the metal film can be generally made of a metal or alloy material such as chromium, titanium, molybdenum, tungsten, aluminum, copper, aluminum-nickel alloy, molybdenum-tungsten alloy, tungsten-copper alloy, etc.; a patterning process such as development, etching, stripping, etc., forming the gate electrode 101 and the gate line (an insulating film having a thickness of 1000 A to 6000 A is deposited on the substrate of the pattern without the gate electrode 101 in the figure, the insulating film is The material is usually silicon nitride, and silicon oxide, silicon oxynitride or the like can also be used.
- a metal or alloy material such as chromium, titanium, molybdenum, tungsten, aluminum, copper, aluminum-nickel alloy, molybdenum-tungsten alloy, tungsten-copper alloy, etc.
- a patterning process such as development, etching, stripping, etc., forming
- an IZO binary metal oxide thin film is formed, and an IZO binary metal oxide pattern layer 1030 is formed by one patterning process.
- the IZO binary metal oxide pattern layer 1030 includes a first pattern 1031 corresponding to the source 104 to be formed, a second pattern 1032 corresponding to the drain 105 to be formed, and a place to be formed A third pattern 1033 corresponding to the gap between the source 104 and the drain 105 is described.
- an IZO metal oxide film having a thickness of 1000 A to 6000 A may be deposited on the substrate on which the gate insulating layer 102 is formed by chemical vapor deposition; and then exposed, developed, etched, peeled, etc. by using a mask. The patterning process is performed to form the IZO binary metal oxide pattern layer 1030.
- IZO is a material that is insensitive to the metal etching liquid, so that it is not necessary to prepare an etch barrier layer, and the metal etching can be directly performed. eclipse. Compared with the prior art, this can reduce the number of patterning processes, thereby increasing mass production efficiency and saving costs.
- step S103 as shown in FIG. 5, forming a source/drain metal layer film on the substrate on which step S102 is completed,
- the source 104 and the drain 105 are formed by one patterning process.
- the first pattern 1031 and the second pattern 1032 of the IZO binary metal oxide pattern layer 1030 correspond to and directly contact the source 104 and the drain 105, respectively.
- a metal thin film having a thickness of 1000 A to 7000 A may be deposited on the substrate on which the IZO binary metal oxide pattern layer 1030 is formed by magnetron sputtering; and then exposed, developed, and etched using a mask. And a patterning process such as stripping, forming the source 104 corresponding to the first pattern 1031 and directly contacting the drain electrode 105 corresponding to the second pattern 1032 and directly contacting.
- a protective layer 106 is formed on the substrate on which step S103 is completed.
- a protective layer film having a thickness of 1000 A to 6000 A may be deposited on the substrate on which the source 104 and the drain 105 are formed by chemical vapor deposition, and the material of the protective layer film is usually silicon nitride.
- One or more of insulating materials such as silicon oxide, silicon oxynitride, and aluminum oxide may also be used.
- the protective layer 106 is used as a barrier layer, and the IZO binary metal oxide pattern layer 1030 is implanted with Ga 3+ by an ion implantation technique. And performing an annealing treatment to convert the IZO of the third pattern 1033 into an IGZO semiconductor, thereby forming the metal oxide semiconductor active layer 103, and obtaining the structure of the thin film transistor 10 shown in FIG. 1(b).
- the thin film transistor 10 having the bottom gate type structure can be formed.
- the metal oxide semiconductor active layer 103 includes an IGZO semiconductor, the source 104 further includes the first pattern 1031, and the drain 105 further includes the second pattern 1032.
- the method specifically includes:
- an AZO binary metal oxide thin film is formed on the base substrate, and the AZO binary metal oxide pattern layer 1030 is formed by one patterning process.
- the AZO binary metal oxide pattern layer 1030 includes a first pattern 1031 corresponding to the source 104 to be formed, a second pattern 1032 corresponding to the drain 105 to be formed, and a place to be formed A third pattern 1033 corresponding to the gap between the source 104 and the drain 105 is described.
- a layer of AZO metal oxide film having a thickness of 1000A to 6000A may be deposited on the substrate by chemical vapor deposition; and then exposed, developed, etched, and etched using a mask.
- the AZO binary metal oxide pattern layer 1030 is formed by a lift-off composition process.
- a source/drain metal layer film is formed, and the source 104 and the drain 105 are formed by one patterning process.
- the first pattern 1031 and the second pattern 1032 of the AZO binary metal oxide pattern layer 1030 correspond to and directly contact the source 104 and the drain 105, respectively.
- a metal thin film having a thickness of 1000 A to 7000 A may be deposited on the substrate on which the AZO binary metal oxide pattern layer 1030 is formed by magnetron sputtering; and then exposed, developed, and etched using a mask. And a patterning process such as stripping, the source 104 corresponding to the first pattern 1031 and in direct contact with the drain 105 corresponding to the second pattern 1032 and in direct contact.
- a gate insulating layer 102 is formed on the substrate on which step S202 is completed.
- an insulating film having a thickness of 1000 A to 6000 A may be deposited on the substrate on which the source 104 and the drain 105 are formed by chemical vapor deposition, and the material of the insulating film is usually silicon nitride.
- An insulating material such as silicon oxide or silicon oxynitride can be used.
- the gate insulating layer 102 is used as a barrier layer, and Sn 2+ is implanted into the AZO binary metal oxide pattern layer 1030 by an ion implantation technique, and is annealed.
- the AZO of the third pattern 1033 is converted into an ATZO semiconductor, thereby forming the metal oxide semiconductor active layer 103.
- step S205 Referring to FIG. 2(b), a metal thin film is formed on the substrate on which step S204 is completed, and the gate electrode 101 is formed by one patterning process.
- a gate line, a gate line, and the like are formed, and of course, a common electrode line may be formed.
- a metal thin film having a thickness of 1000 A to 7000 A may be deposited on the substrate on which the gate insulating layer 102 is formed by magnetron sputtering; the metal thin film may be generally made of chromium, titanium, molybdenum, tungsten, aluminum. a metal or alloy material such as copper, aluminum-nickel alloy, molybdenum-tungsten alloy, or tungsten-copper alloy; and a patterning process such as exposure, development, etching, and stripping using a mask to form the gate electrode 101 and the gate line (in the figure) Not marked), grid lines and other patterns.
- the thin film transistor 10 having the top gate type structure can be formed.
- the metal oxide semiconductor active layer 103 includes an ATZO semiconductor
- the source 104 further includes the first pattern 1031
- the drain 105 further includes the second pattern 1032.
- An embodiment of the present invention provides a thin film transistor 10 prepared by the above method, and as shown in FIG. 1(b) and FIG. 2(b), includes a gate electrode 101, a gate insulating layer 102, and a metal oxide semiconductor disposed on a substrate.
- the thin film transistor 10 further includes a first pattern 1031 and a second pattern 1032 disposed in the same layer as the metal oxide semiconductor active layer 103; the first pattern 1031 is in direct contact with the source 104 The second pattern 1032 corresponds to the drain 105 and is in direct contact.
- the first pattern 1031 and the second pattern 1032 each include an oxidized dibasic metal oxide
- the metal oxide semiconductor active layer 103 includes an oxidized multi-element metal oxide semiconductor
- the multi-metal oxide is a metal oxide obtained by injecting metal-doped ions into the oxidized dibasic metal oxide.
- the thin film transistor 10 may be a top gate type structure or a bottom gate type structure, which is not limited herein.
- the first pattern 1031 and the second pattern 1032 and the metal oxide semiconductor active layer 103 are located at the source 104 and the drain. Below the 105, thereby ensuring that only the oxidized dibasic metal oxide corresponding to the gap between the source 104 and the drain 105 can be converted into an oxidized plural in the process of performing ion implantation.
- Metal oxide semiconductor is a top gate type structure or a bottom gate type structure, which is not limited herein.
- the bottom gate type thin film transistor 10 refers to a type of thin film transistor in which the gate electrode 101 is below, the source electrode 104, and the drain electrode 105;
- the top gate type thin film transistor 10 refers to the gate electrode 101 is a type of thin film transistor in which the source 104 and the drain 105 are under.
- the first pattern 1031 is in direct contact with the source 104
- the second pattern 1032 is in direct contact with the drain 105
- the first pattern 1031 and the second pattern 1032 both include the oxidation.
- the problem of the contact resistance between the metal oxide semiconductor active layer 103 and the source 104 and the drain 105 is solved.
- the thin film transistor 10 when the thin film transistor 10 is of a bottom gate type, the thin film transistor 10 may include a gate electrode 101 disposed on a base substrate, and disposed on the gate electrode 101.
- the upper gate insulating layer 102 and the metal oxide semiconductor disposed above the gate insulating layer 102 have a source layer 103, a first pattern 1031 and a second pattern 1032 disposed in the same layer as the metal oxide semiconductor active layer 103, and a source disposed above the first pattern 1031 and the second pattern 1032, respectively a drain 104 and a drain 105, and a protective layer 106 disposed over the source 104 and the drain 105; the metal oxide semiconductor active layer 103 and the source 104 and the drain 105 The gap between them corresponds.
- the first pattern 1031 and the second pattern 1032 each include an oxidized dibasic metal oxide
- the metal oxide semiconductor active layer 103 includes an oxidized multi-element metal oxide semiconductor
- the multi-metal oxide is a metal oxide obtained by injecting metal-doped ions into the oxidized dibasic metal oxide.
- the oxidized dibasic metal oxide is a conductive material
- the second pattern 1032 corresponds to the drain 105 because the first pattern 1031 corresponds to and directly contacts the source 104. Direct contact, therefore, it can be seen that the source 104 further includes the first pattern 1031, and the drain 105 further includes the second pattern 1032.
- the metal oxide semiconductor active layer 103 is formed by an ion implantation technique after forming the source 104 and the drain 105, before the ion implantation, with the source 104 and the
- the material of the portion corresponding to the gap between the drain electrodes 105 is an oxidized binary metal oxide which is insensitive to the metal etching liquid, so that the etching of the etching stopper layer can be omitted and the metal etching can be directly performed. Compared with the prior art, this can reduce the number of patterning processes, thereby increasing mass productivity and saving costs.
- the thin film transistor 10 when the thin film transistor 10 is of a top gate type, the thin film transistor 10 may include a metal oxide semiconductor active layer 103 disposed on a base substrate, and a first pattern 1031 and a second pattern 1032 in which the metal oxide semiconductor active layer 103 is disposed in the same layer and in contact with the source 104 and the drain 105 respectively disposed above the first pattern 1031 and the second pattern 1032 a gate insulating layer 102 disposed above the source 104 and the drain 105, and a gate 101 disposed above the gate insulating layer 102; the metal oxide semiconductor active layer 103 and the source A gap between 104 and the drain 105 corresponds.
- the oxidized dibasic metal oxide is a conductive material
- the second pattern 1032 corresponds to the drain 105 because the first pattern 1031 corresponds to and directly contacts the source 104. Direct contact, therefore, it can be seen that the source 104 further includes the first pattern 1031, and the drain 105 further includes the second pattern 1032.
- the oxidized dibasic metal oxide may include IZO, or AZO, or GZO, or TZO; the metal doping ions may include Ga 3+ , Sn 2+ , Hi 4 — Al 3+ And at least one of In 3+ .
- the above-mentioned oxidized dibasic metal oxide and the metal-doped ion may be appropriately combined to make the characteristics of the obtained oxidized multi-element metal oxide semiconductor and the thin film transistor
- the purpose of 10 is to achieve the best match.
- An embodiment of the present invention provides a thin film transistor 10 including a gate electrode 101, a gate insulating layer 102, a metal oxide semiconductor active layer 103, a source electrode 104, and a drain electrode 105 disposed on a substrate;
- the source layer 103 is disposed between the substrate and the source 104 and the drain 105, and corresponds to a gap between the source 104 and the drain 105.
- the thin film transistor 10 further includes a first pattern 1031 and a second pattern 1032 disposed in the same layer as the metal oxide semiconductor active layer 103; the first pattern 1031 is in direct contact with the source 104 The second pattern 1032 corresponds to the drain 105 and is in direct contact.
- the first pattern 1031 and the second pattern 1032 each include an oxidized dibasic metal oxide
- the metal oxide semiconductor active layer 103 includes an oxidized multi-element metal oxide semiconductor
- the multi-metal oxide is a metal oxide obtained by injecting metal-doped ions into the oxidized dibasic metal oxide.
- the first pattern 1031 and the second pattern 1032 are disposed and in contact with the metal oxide semiconductor active layer 103 in the same layer, and the metal oxide semiconductor is active.
- the layer 103 corresponds to a gap between the source 104 and the drain 105. Since the first pattern 1031 corresponds to and contacts the source 104, the second pattern 1032 corresponds to and contacts the drain 105, and the first pattern 1031 and the second pattern 1032 both include
- the oxidation of the binary metal oxide conductive material is such that a region transitioning from the conductor to the semiconductor is formed under the source 104 and the drain 105, thereby forming a carrier capable of providing a carrier.
- the transported transition layer effectively solves the problem of contact resistance between the metal oxide semiconductor active layer 103 and the source 104 and the drain 105.
- Embodiments of the present invention provide an array substrate including the above-described thin film transistor 10.
- the array substrate when the array substrate is applied to a liquid crystal display device, as shown in FIG. 9, the array substrate further includes a pixel electrode 20 electrically connected to the drain 105 of the thin film transistor 10.
- the array substrate when the array substrate is applied to an organic electroluminescent device, the array substrate further includes a cathode and an anode.
- a planarization layer, a pixel defining layer, and the like can also be formed as needed.
- the pixel defining layer is used to ensure that droplets of the luminescent material can fill the pixel region evenly while forming the luminescent layer by printing techniques, while preventing droplets from flowing to adjacent pixel regions.
- the embodiment of the invention further provides a display device comprising the above array substrate.
- the display device may be: a product or a component having any display function such as a liquid crystal panel, an OLED, an electronic paper, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
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Abstract
提供了一种薄膜晶体管及其制备方法、阵列基板、显示装置。该制备方法包括在基板上形成栅极(101)、栅绝缘层(102)、金属氧化物半导体有源层(103)、源极(104)和漏极(105);所述形成金属氧化物半导体有源层包括:在基板上形成氧化锌系二元金属氧化物图案层,所述图案层包括第一图案(1031)、第二图案(1032)、以及第三图案(1033);釆用离子注入技术向氧化锌系二元金属氧化物图案层注入金属掺杂离子,将第三图案(1033)的二元金属氧化物转化为多元金属氧化物半导体,形成金属氧化物半导体有源层(103)。可解决源、漏极与半导体有源层之间的接触电阻问题,并避免制备过程中对半导体有源层的损伤。
Description
薄膜晶体管及其制备方法、 阵列基板、 显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制备方法、 阵列基板、 显示装 置。 背景技术
随着显示器尺寸的不断增大以及驱动电路频率的不断提高, 现有的非晶 硅薄膜晶体管的迁移率已经难以满足需求。
高迁移率的薄膜晶体管( Thin Film Transistor, TFT )有多晶硅 TFT和金 属氧化物 TFT。 但多晶硅 TFT的均一性差, 制作工艺复杂, 且受到激光晶化 等设备的限制, 不利于大 模生产; 而金属氧化物 TFT的迁移率高、 均一性 好、透明、制作工艺简单,可以更好地满足大尺寸的液晶显示器( Liquid Crystal Display, 简称 LCD )、有机发光二极管显示器( Organic Light Emitting Diode, 简称 OLED )、以及高分子发光二极管显示器( Polymer Light Emitting Diode, 简称 PLED ) 的需求, 受到了广泛的关注。
一般情况下, 对于薄膜晶体管而言, 在源、 漏极与半导体有源层之间的 接触表面上会产生一定的能量势垒, 从而形成接触电阻; 该能量势垒可以阻 碍载流子的运动。 当界面处的能量势垒较大, 形成肖特基接触时, 便容易引 起信号的损失, 从而影响 TFT的性能。
此外, 现有的金属氧化物 TFT的制备过程中, 后续的制备工艺可能会对 金属氧化物半导体有源层产生损害, 导致 TFT性能的恶化。
因此, 如何保证 TFT的性能十分重要。 发明内容
本发明的实施例提供一种薄膜晶体管及其制备方法、 阵列基板、 显示装 置, 可解决源、 漏极与半导体有源层之间的接触电阻问题, 同时避免制备过 程中对半导体有源层的损伤。
为达到上述目的, 本发明的实施例釆用如下技术方案:
一方面, 提供一种薄膜晶体管, 包括设置在基板上的栅极、 栅绝缘层、 金属氧化物半导体有源层、 源极和漏极; 所述金属氧化物半导体有源层设置 在所述基板与所述源极和所述漏极之间, 且与所述源极和所述漏极之间的间 隙对应; 所述薄膜晶体管还包括与所述金属氧化物半导体有源层同层设置且 接触的第一图案和第二图案; 所述第一图案与所述源极对应且直接接触, 所 述第二图案与所述漏极对应且直接接触。 所述第一图案和所述第二图案均包 括氧化辞系二元金属氧化物, 所述金属氧化物半导体有源层包括氧化辞系多 元金属氧化物半导体, 且所述氧化辞系多元金属氧化物为在所述氧化辞系二 元金属氧化物中注入金属掺杂离子得到的金属氧化物。
例如, 在沿所述源极和所述漏极的间隔方向的截面中, 所述金属氧化物 半导体有源层的宽度与所述源极和所述漏极之间的间隙宽度相同。
可选的, 所述薄膜晶体管为底栅型; 所述薄膜晶体管还包括设置在所述 源极和所述漏极上方的保护层。
可选的, 所述薄膜晶体管为顶栅型。
进一步可选的, 所述氧化辞系二元金属氧化物包括铟辞氧化物 (Indium
Zinc Oxide, 简称 IZO )、或铝辞氧化物( Aluminum Zinc Oxide, 简称 AZO )、 或镓辞氧化物 ( Gallium Zinc Oxide, 简称 GZO ) 、 或锡辞氧化物 ( Tin Zinc Oxide, 简称 TZO ) ; 所述金属掺杂离子包括镓离子(Ga3+ )、锡离子(Sn2+ )、 铪离子 (Hi4—) 、 铝离子(Al3+ ) 、 以及铟离子 (In3+ ) 中的至少一种。
例如, 在沿所述源极和所述漏极的间隔方向的截面中, 所述金属氧化物 半导体有源层的两侧边缘分别与所述源极和所述漏极相对的边缘对齐。
还提供一种阵列基板, 包括上述的薄膜晶体管。
还提供一种显示装置, 包括上述的阵列基板。
另一方面, 提供一种上述薄膜晶体管的制备方法, 包括在基板上形成栅 极、 栅绝缘层、 金属氧化物半导体有源层、 源极和漏极。 所述在基板上形成 金属氧化物半导体有源层包括: 在基板上形成氧化辞系二元金属氧化物图案 层, 所述图案层包括与所述源极对应的第一图案、 与所述漏极对应的第二图 案、 以及与所述源极和所述漏极之间的间隙对应的第三图案, 且所述氧化辞 系二元金属氧化物图案层与所述源极和所述漏极直接接触; 以形成在所述源 极和所述漏极上方的绝缘层为阻挡层, 釆用离子注入技术向所述氧化辞系二
元金属氧化物图案层注入金属掺杂离子, 将所述第三图案的所述氧化辞系二 元金属氧化物转化为氧化辞系多元金属氧化物半导体, 形成所述金属氧化物 半导体有源层。
可选的, 所述薄膜晶体管为底栅型。 所述方法还包括: 在形成所述源极 和所述漏极的基板上形成保护层; 其中, 所述以绝缘层为阻挡层, 釆用离子 注入技术向所述氧化辞系二元金属氧化物图案层注入金属掺杂离子, 将所述 第三图案的所述氧化辞系二元金属氧化物转化为氧化辞系多元金属氧化物半 导体, 形成所述金属氧化物半导体有源层包括: 以所述保护层为阻挡层, 釆 用离子注入技术向所述氧化辞系二元金属氧化物图案层注入金属掺杂离子, 将未被所述源极和所述漏极阻挡的所述第三图案的所述氧化辞系二元金属氧 化物转化为氧化辞系多元金属氧化物半导体, 形成所述金属氧化物半导体有 源层。
可选的, 所述薄膜晶体管为顶栅型。 其中, 所述以绝缘层为阻挡层, 釆 用离子注入技术向所述氧化辞系二元金属氧化物图案层注入金属掺杂离子, 将所述第三图案的所述氧化辞系二元金属氧化物转化为氧化辞系多元金属氧 化物半导体, 形成所述金属氧化物半导体有源层包括: 以所述栅绝缘层为阻 挡层, 釆用离子注入技术向所述氧化辞系二元金属氧化物图案层注入金属掺 杂离子, 将未被所述源极和所述漏极阻挡的所述第三图案的所述氧化辞系二 元金属氧化物转化为氧化辞系多元金属氧化物半导体, 形成所述金属氧化物 半导体有源层。
进一步可选的, 在所述釆用离子注入技术向所述氧化辞系二元金属氧化 物图案层注入金属掺杂离子之后, 所述方法还包括进行退火处理。
进一步的, 所述氧化辞系二元金属氧化物包括 IZO、 或 AZO、 或 GZO、 或锡辞氧化物 TZO; 所述 Ga3+、 Sn2+、 1 +、 Al3+、 以及 In3+中的至少一种。
本发明实施例提供了一种薄膜晶体管及其制备方法、 阵列基板、 显示装 置, 该制备方法包括在基板上形成栅极、 栅绝缘层、 金属氧化物半导体有源 层、 源极和漏极。 所述在基板上形成金属氧化物半导体有源层可以包括: 在 基板上形成氧化辞系二元金属氧化物图案层, 所述图案层包括与所述源极对 应的第一图案、 与所述漏极对应的第二图案、 以及与所述源极和所述漏极之 间的间隙对应的第三图案, 且所述氧化辞系二元金属氧化物图案层与所述源
极和所述漏极直接接触; 以形成在所述源极和所述漏极上方的绝缘层为阻挡 层, 釆用离子注入技术向所述氧化辞系二元金属氧化物图案层注入金属掺杂 离子, 将所述第三图案的所述氧化辞系二元金属氧化物转化为氧化辞系多元 金属氧化物半导体, 形成所述金属氧化物半导体有源层。
在本发明实施例中, 一方面, 由于所述氧化辞系二元金属氧化物为导电 材料, 经过离子注入将所述第三图案的氧化辞系二元金属氧化物转化为氧化 辞系多元金属氧化物半导体时, 在所述源极和所述漏极下方形成了一个由导 体向半导体过渡的区域, 这样便在所述源极和所述漏极下方形成了一个提供 载流子传输的过渡层, 有效的解决了所述金属氧化物半导体有源层与所述源 极和所述漏极之间的接触电阻的问题; 另一方面, 以形成在所述源极和所述 漏极上方的绝缘层为阻挡层, 通过离子注入技术形成所述金属氧化物半导体 有源层, 不仅可以避免离子注入过程中可能引起的金属氧化物半导体有源层 的损伤, 还可以防止在薄膜晶体管的制备过程中其它后续工艺可能对所述金 属氧化物半导体有源层产生的影响, 从而提高薄膜晶体管的性能。 附图说明
为了更清楚地说明本发明实施例的技术方案, 下面将对实施例的附图作 简单地介绍,显而易见地,下面描述中的附图仅仅涉及本发明的一些实施例, 而非对本发明的限制。
图 1 ( a )为本发明实施例提供的一种进行离子注入的示意图;
图 1 ( b )为本发明实施例提供的一种薄膜晶体管的结构示意图; 图 2 ( a )为本发明实施例提供的另一种进行离子注入的示意图; 图 2 ( b )为本发明实施例提供的另一种薄膜晶体管的结构示意图; 图 3〜图 5为本发明实施例提供的一种形成薄膜晶体管的过程示意图; 图 6〜图 8为本发明实施例提供的另一种形成薄膜晶体管的过程示意图; 图 9为本发明提供的一种阵列基板的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚, 下面将结合本发 明实施例的附图, 对本发明实施例的技术方案进行清楚、 完整地描述。显然,
所描述的实施例是本发明的一部分实施例, 而不是全部的实施例。 基于所描 述的本发明的实施例, 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例, 都属于本发明保护的范围。
本发明实施例提供了一种薄膜晶体管 10的制备方法,包括在基板上形成 栅极 101、栅绝缘层 102、金属氧化物半导体有源层 103、源极 104和漏极 105。
所述在基板上形成金属氧化物半导体有源层 103可以包括: 在基板上形 成氧化辞系二元金属氧化物图案层 1030,所述图案层包括与所述源极 104对 应的第一图案 1031、与所述漏极 105对应的第二图案 1032、 以及与所述源极 104和所述漏极 105之间的间隙对应的第三图案 1033, 且所述氧化辞系二元 金属氧化物图案层 1030与所述源极 104和所述漏极 105直接接触;以形成在 所述源极 104和所述漏极 105上方的绝缘层为阻挡层, 釆用离子注入技术向 所述氧化辞系二元金属氧化物图案层 1030注入金属掺杂离子,将所述第三图 案 1033 的所述氧化辞系二元金属氧化物转化为氧化辞系多元金属氧化物半 导体, 形成所述金属氧化物半导体有源层 103。
如图 1 ( a )至图 2 ( b )所示, 第三图案 1033或形成的金属氧化物半导 体有源层 103与源极 104和漏极 105之间的间隙对应。 例如, 在沿所述源极 104和所述漏极 105的间隔方向的截面中,所述金属氧化物半导体有源层 103 的宽度与所述源极 104和所述漏极 105之间的间隙宽度相同。 例如, 在沿所 述源极 104和所述漏极 105的间隔方向的截面中, 所述金属氧化物半导体有 源层 103的两侧边缘分别与所述源极 104和所述漏极 105相对的边缘对齐。
需要说明的是, 所述氧化辞系二元金属氧化物是指以氧化辞为基体, 掺 杂其它金属元素形成的一种二元金属氧化物; 这里, 所述氧化辞系二元金属 氧化物为一种导电材料。
所述氧化辞系二元金属氧化物图案层 1030包括第一图案 1031、 第二图 案 1032和第三图案 1033三个部分, 该三个部分仅仅是从结构上进行区分, 与组成材料无关。 当进行离子注入之后,所述第三图案 1033的材料由所述氧 化辞系二元金属氧化物转化为所述氧化辞系多元金属氧化物半导体; 但对于 所述薄膜晶体管 10而言, 其仍保持原有的图案形状并处于原先的位置。
所述氧化辞系二元金属氧化物图案层 1030与所述源极 104和所述漏极 105直接接触是指,所述氧化辞系二元金属氧化物图案层 1030的所述第一图
案 1031和所述第二图案 1032分别与所述源极 104和所述漏极 105直接接触, 而所述第三图案 1033被所述源极 104和所述漏极 105之间的间隙露出。
以形成在所述源极 104和所述漏极 105上方的绝缘层为阻挡层是指, 在 制备薄膜晶体管 10时, 先形成所述源极 104和漏极 105, 再形成该阻挡层。
在离子注入的过程中, 需要以绝缘层为阻挡层, 这是由于进行离子注入 的金属掺杂离子具有很高的能量, 如果不设置阻挡层而直接进行离子注入, 可能会因离子的轰击能量过高而导致半导体有源层的损伤, 进而影响薄膜晶 体管 10的性能;因此在离子注入的过程中需要一种起阻挡作用的介质。这里, 所述阻挡层可以是任何一种具有阻挡作用的绝缘层。
根据薄膜晶体管的类型,当其本身就已包含了具有阻挡作用的绝缘层时, 可以直接釆用该绝缘层作为阻挡层; 当其本身包含的绝缘层无法作为阻挡层 时, 可以重新制备一层具有阻挡作用的绝缘层。
对于釆用离子注入技术形成所述金属氧化物半导体有源层 103的方法, 可适用于包括底栅型和顶栅型的任一种薄膜晶体管, 在此不作限定, 具体的 工艺可根据薄膜晶体管的实际构造进行设计。
本发明实施例提供了一种薄膜晶体管 10的制备方法,包括在基板上形成 栅极 101、栅绝缘层 102、金属氧化物半导体有源层 103、源极 104和漏极 105。 所述在基板上形成金属氧化物半导体有源层 103可以包括: 在基板上形成氧 化辞系二元金属氧化物图案层 1030,所述图案层包括与所述源极 104对应的 第一图案 1031、 与所述漏极 105对应的第二图案 1032、 以及与所述源极 104 和所述漏极 105之间的间隙对应的第三图案 1033,且所述氧化辞系二元金属 氧化物图案层 1030与所述源极 104和所述漏极 105直接接触;以形成在所述 源极 104和所述漏极 105上方的绝缘层为阻挡层, 釆用离子注入技术向所述 氧化辞系二元金属氧化物图案层 1030 注入金属掺杂离子, 将所述第三图案 1033 的所述氧化辞系二元金属氧化物转化为氧化辞系多元金属氧化物半导 体, 形成所述金属氧化物半导体有源层 103。
在本发明实施例中, 一方面, 由于所述氧化辞系二元金属氧化物为导电 材料,经过离子注入将所述第三图案 1033的氧化辞系二元金属氧化物转化为 氧化辞系多元金属氧化物半导体时, 相当于在所述源极 104和所述漏极 105 下方形成了一个由导体向半导体过渡的区域, 这样便在所述源极 104和所述
漏极 105下方形成了一个可以提供载流子传输的过渡层, 有效的解决了所述 金属氧化物半导体有源层 103与所述源极 104和所述漏极 105之间的接触电 阻的问题; 另一方面, 以绝缘层为阻挡层, 通过离子注入技术形成所述金属 氧化物半导体有源层 103, 不仅可以避免离子注入过程中可能引起的金属氧 化物半导体有源层 103的损伤,还可以防止在薄膜晶体管 10的制备过程中其 它后续工艺可能对所述金属氧化物半导体有源层 103产生的影响, 从而提高 薄膜晶体管 10的性能。
可选的, 如图 1 ( a )和图 1 ( b )所示, 所述方法具体可以包括: 在基板 上依次形成所述栅极 101、所述栅绝缘层 102、所述氧化辞系二元金属氧化物 的图案层 1030、 所述源极 104和所述漏极 105, 以及位于所述源极 104和所 述漏极 105上方的保护层 106。
所述氧化辞系二元金属氧化物图案层 1030包括与所述源极 104对应且直 接接触的所述第一图案 1031、与所述漏极 105对应且直接接触的所述第二图 案 1032、以及与所述源极 104和所述漏极 105之间的间隙对应的所述第三图 案 1033。
在此情况下,在形成所述金属氧化物半导体有源层 103时,参考图 1 ( a ) 所示, 可以以所述保护层 106为阻挡层, 釆用离子注入技术向所述氧化辞系 二元金属氧化物图案层 1030注入金属掺杂离子,将未被所述源极 104和所述 漏极 105阻挡的所述第三图案 1033的所述氧化辞系二元金属氧化物转化为所 述氧化辞系多元金属氧化物半导体, 从而形成所述金属氧化物半导体有源层 103, 进而得到参考图 1 ( b )所示的底栅型薄膜晶体管。
这里,所述金属掺杂离子的注入剂量以及轰击能量需要进行严格的控制。 其注入剂量可以与所述氧化辞系二元金属氧化物中的两种金属的含量呈正 比; 而其轰击能量则需保证大部分的金属掺杂离子能够进入所述氧化辞系二 元金属氧化物图案层 1030的所述第三图案 1033中, 从而与所述氧化辞系二 元金属氧化物结合形成所述氧化辞系多元金属氧化物半导体。 因此, 在进行 离子注入的过程中, 根据实际情况可釆用高能量深注入的方式进行作业。
由于在离子注入的过程中, 所述金属掺杂离子具有很高的轰击能量, 因 此, 大部分的金属掺杂离子可以直接穿透所述保护层 106而进入未被所述源 极 104和所述漏极 105阻挡的所述第三图案 1033。 由于在所述氧化辞系二元
金属氧化物图案层 1030的上方已经形成所述源极 104和所述漏极 105,穿透 所述保护层 106的金属掺杂离子受到所述源极 104和所述漏极 105的阻挡, 而使所述金属掺杂离子无法注入对应于所述源极 104 的所述第一图案 1031 和对应于所述漏极 105的第二图案 1032,仅注入未被所述源极 104和所述漏 极 105阻挡的所述第三图案 1033, 从而仅将所述第三图案 1033的所述氧化 辞系二元金属氧化物转化为所述氧化辞系多元金属氧化物半导体, 形成金属 氧化物半导体有源层 103。
基于上述描述可知,经过离子注入后,所述第三图案 1033的材料为氧化 辞系多元金属氧化物半导体材料, 所述第一图案 1031和所述第二图案 1032 的材料为氧化辞系二元金属氧化物导电材料。由于所述第一图案 1031与所述 源极 104直接接触,所述第二图案 1032与所述漏极 105直接接触, 因此可以 视为所述源极 104还包括所述第一图案 1031,所述漏极 105还包括所述第二 图案 1032。
可选的, 如图 2 ( a )和图 2 ( b )所示, 所述方法具体还可以包括: 在基 板上依次形成所述氧化辞系二元金属氧化物图案层 1030、所述源极 104和所 述漏极 105、 所述栅绝缘层 102、 以及所述栅极 101。
所述氧化辞系二元金属氧化物图案层 1030包括与所述源极 104对应且直 接接触的所述第一图案 1031、与所述漏极 105对应且直接接触的所述第二图 案 1032、以及与所述源极 104和所述漏极 105之间的间隙对应的所述第三图 案 1033。
在此情况下,在形成所述金属氧化物半导体有源层 103时,参考图 2 ( a ) 所示, 可以在形成所述栅绝缘层 102之后, 以所述栅绝缘层 102为阻挡层, 釆用离子注入技术向所述氧化辞系二元金属氧化物图案层 1030 注入金属掺 杂离子,将未被所述源极 104和所述漏极 105阻挡的所述第三图案 1033的所 述氧化辞系二元金属氧化物转化为所述氧化辞系多元金属氧化物半导体, 从 而形成所述金属氧化物半导体有源层 103; 然后, 在所述栅绝缘层 102上方 形成所述栅极 201, 从而得到参考图 2 ( b )所示的顶栅型薄膜晶体管。
这里, 所述源极 104和所述漏极 105位于所述氧化辞系二元金属氧化物 图案层 1030的上方,当釆用离子注入技术向所述氧化辞系二元金属氧化物图 案层 1030注入金属掺杂离子时,穿透所述栅绝缘层 102的金属掺杂离子会受
到所述源极 104和所述漏极 105的阻挡, 而使所述金属掺杂离子无法注入对 应于所述源极 104的所述第一图案 1031和对应于所述漏极 105的第二图案 1032, 仅注入未被所述源极 104和所述漏极 105阻挡的所述第三图案 1033, 从而仅将所述第三图案 1033 的所述氧化辞系二元金属氧化物转化为所述氧 化辞系多元金属氧化物半导体, 形成金属氧化物半导体有源层 103。
基于上述描述可知, 当经过离子注入后,所述第三图案 1033的材料为氧 化辞系多元金属氧化物半导体材料,所述第一图案 1031和所述第二图案 1032 的材料为氧化辞系二元金属氧化物导电材料。 其中, 由于所述第一图案 1031 与所述源极 104直接接触,所述第二图案 1032与所述漏极 105直接接触, 因 此可以视为所述源极 104还包括所述第一图案 1031,所述漏极 105还包括所 述第二图案 1032。
进一步可选的, 在釆用离子注入技术向所述氧化辞系二元金属氧化物图 案层 1030注入金属掺杂离子之后, 所述方法还可以包括进行退火处理。
经过离子注入后直接形成的所述氧化辞系多元金属氧化物半导体的结构 杂乱无序, 通过退火处理可使其组织均勾化, 从而使所述氧化辞系多元金属 氧化物半导体的载流子处于有效的导电位置, 进而可使所述薄膜晶体管 10 性能的得到优化。
进一步可选的, 所述氧化辞系二元金属氧化物可以包括 IZO、 或 AZO、 或 GZO、 或 TZO; 所述金属掺杂离子可以包括 Ga3+、 Sn2+、 Hi4— Al3+、 以 及 In3+中的至少一种。
目前, 对于所述氧化辞系二元金属氧化物而言, IZO、 AZO、 GZO、 以 及 TZO都是研究较为广泛的金属氧化物半导体有源层材料。但由于其作为半 导体有源层的性能不稳定, 因此, 通常会在上述的氧化辞系二元金属氧化物 中添加金属掺杂元素,从而形成例如 IGZO、 ITZO、 ΗΙΖΟ、 ΑΤΖΟ、以及 ΑΤΖΙΟ 等具有稳定特性的半导体材料。
需要说明的是, 对于半导体材料而言, 可以通过控制其内部的载流子浓 度实现对所述半导体材料导电性能的控制; 当所述半导体材料内部的载流子 浓度大于某一临界值时, 即呈现出导体特性。 在本发明实施例中, 所述氧化 辞系二元金属氧化物图案层 1030的材料可以包括 IZO、 AZO、 GZO、 以及 TZO, 此时所利用的为其导体特性; 通过添加金属掺杂元素之后, 形成所述
氧化辞系多元金属氧化物半导体, 此时才可呈现出其半导体特性。
下面提供两个具体的实施例对本发明中所述薄膜晶体管 10 的制备方法 进行具体说明。
一方面, 当所述薄膜晶体管 10为底栅型,所述氧化辞系二元金属氧化物 为 IZO, 所述金属掺杂离子为 Ga3+时, 所述方法具体包括:
5101、 如图 3所示, 在衬底基板上通过一次构图工艺形成包括栅极 101 的图案; 并在形成有所述栅极 101的基板上形成栅绝缘层 102。
在形成所述栅极 101的同时, 还形成栅线、 栅线引线等, 当然, 也可以 形成公共电极线。
这里, 可以通过磁控溅射法在衬底基板上沉积一层厚度为 1000A 至
7000A的金属薄膜; 其中, 所述金属薄膜通常可以釆用铬、 钛、 钼、 钨、 铝、 铜、 铝镍合金、 钼钨合金、 钨铜合金等金属或合金材料; 釆用掩模板进行曝 光、 显影、 刻蚀、 剥离等构图工艺处理, 形成所述栅极 101、 栅线(图中未 栅极 101的图案的基板上沉积一层厚度为 1000A至 6000A的绝缘薄膜,所述 绝缘薄膜的材料通常是氮化硅, 也可以使用氧化硅和氮氧化硅等。
5102、 如图 4所示, 在完成步骤 S101的基板上, 形成 IZO二元金属氧 化物薄膜, 并通过一次构图工艺形成 IZO二元金属氧化物图案层 1030。
所述 IZO二元金属氧化物图案层 1030包括与待形成的所述源极 104对 应的第一图案 1031、与待形成的所述漏极 105对应的第二图案 1032,以及与 待形成的所述源极 104和所述漏极 105之间的间隙对应的第三图案 1033。
这里, 可以利用化学气相沉积法在形成有所述栅绝缘层 102的基板上沉 积一层厚度为 1000A至 6000A的 IZO金属氧化物薄膜; 然后釆用掩模板通 过曝光、 显影、 刻蚀、 剥离等构图工艺处理, 形成所述 IZO二元金属氧化物 图案层 1030。
需要说明的是, 在后续的制备工艺过程中会进行源漏金属层的刻蚀, 而 IZO是一种对金属刻蚀液不敏感的材料, 因此无需制备刻蚀阻挡层, 可以直 接进行金属刻蚀。 与现有技术相比, 这样可以减少一次构图工艺, 从而提高 量产效率, 节约成本。
S103、 如图 5所示, 在完成步骤 S102的基板上, 形成源漏金属层薄膜,
并通过一次构图工艺形成源极 104和漏极 105。
所述 IZO二元金属氧化物图案层 1030的所述第一图案 1031和所述第二 图案 1032分别与所述源极 104和所述漏极 105对应并直接接触。
这里, 可以通过磁控溅射法在形成有所述 IZO二元金属氧化物图案层 1030的基板上沉积一层厚度为 1000A至 7000A的金属薄膜; 然后釆用掩模 板进行曝光、 显影、 刻蚀、 剥离等构图工艺处理, 形成与所述第一图案 1031 对应并直接接触的所述源极 104、以及与所述第二图案 1032对应并直接接触 的所述漏极 105。
5104、参考图 1 ( a )所示,在完成步骤 S103的基板上,形成保护层 106。 这里, 可以利用化学气相沉积法在形成有所述源极 104和所述漏极 105 的基板上沉积一层厚度为 1000A至 6000A的保护层薄膜,所述保护层薄膜的 材料通常是氮化硅, 也可以使用氧化硅、 氮氧化硅以及氧化铝等绝缘材料中 的一种或多种。
5105、 参考图 1 ( a )所示, 在完成步骤 S104的基板上, 以所述保护层 106 为阻挡层, 釆用离子注入技术向所述 IZO二元金属氧化物图案层 1030 注入 Ga3+, 并进行退火处理, 将所述第三图案 1033的 IZO转化为 IGZO半 导体, 从而形成金属氧化物半导体有源层 103, 得到参考图 1 ( b )所示的薄 膜晶体管 10的结构。
根据上述步骤 S101~S105, 可以形成具有底栅型结构的薄膜晶体管 10。 所述金属氧化物半导体有源层 103包括 IGZO半导体, 所述源极 104还包括 所述第一图案 1031, 所述漏极 105还包括所述第二图案 1032。
另一方面, 当所述薄膜晶体管 10为顶栅型,所述氧化辞系二元金属氧化 物为 AZO, 所述金属掺杂离子为 Sn2+时, 所述方法具体包括:
S201、 如图 6所示, 在衬底基板上形成 AZO二元金属氧化物薄膜, 并 通过一次构图工艺形成 AZO二元金属氧化物图案层 1030。
所述 AZO二元金属氧化物图案层 1030包括与待形成的所述源极 104对 应的第一图案 1031、与待形成的所述漏极 105对应的第二图案 1032、以及与 待形成的所述源极 104和所述漏极 105之间的间隙对应的第三图案 1033。
这里,可以利用化学气相沉积法在衬底基板上沉积一层厚度为 1000A至 6000A的 AZO金属氧化物薄膜; 然后釆用掩模板通过曝光、 显影、 刻蚀、
剥离等构图工艺处理, 形成所述 AZO二元金属氧化物图案层 1030。
5202、 如图 7所示, 在完成步骤 S201的基板上, 形成源漏金属层薄膜, 并通过一次构图工艺形成源极 104和漏极 105。
所述 AZO二元金属氧化物图案层 1030的所述第一图案 1031和所述第 二图案 1032分别与所述源极 104和所述漏极 105对应并直接接触。
这里, 可以通过磁控溅射法在形成有所述 AZO二元金属氧化物图案层 1030的基板上沉积一层厚度为 1000A至 7000A的金属薄膜; 然后釆用掩模 板进行曝光、 显影、 刻蚀、 剥离等构图工艺处理, 与所述第一图案 1031对应 并直接接触的所述源极 104、和与所述第二图案 1032对应并直接接触的所述 漏极 105。
5203、 如图 8所示, 在完成步骤 S202的基板上, 形成栅绝缘层 102。 这里, 可以利用化学气相沉积法在形成有所述源极 104和所述漏极 105 的基板上沉积一层厚度为 1000A至 6000A的绝缘薄膜,所述绝缘薄膜的材料 通常是氮化硅, 也可以使用氧化硅和氮氧化硅等绝缘材料。
S204、 参考图 2 ( a )所示, 以所述栅绝缘层 102为阻挡层, 釆用离子注 入技术向所述 AZO二元金属氧化物图案层 1030注入 Sn2+,并进行退火处理, 将所述第三图案 1033的 AZO转化为 ATZO半导体,从而形成金属氧化物半 导体有源层 103。
S205、 参考图 2 ( b )所示, 在完成步骤 S204的基板上形成金属薄膜, 并通过一次构图工艺形成栅极 101。
其中, 在形成所述栅极 101的同时, 还形成栅线、 栅线弓 I线等, 当然, 也可以形成公共电极线。
这里, 可以通过磁控溅射法在形成有所述栅绝缘层 102的基板上沉积一 层厚度为 1000A至 7000A的金属薄膜; 所述金属薄膜通常可以釆用铬、 钛、 钼、 钨、 铝、 铜、 铝镍合金、 钼钨合金、 钨铜合金等金属或合金材料; 釆用 掩模板进行曝光、 显影、 刻蚀、 剥离等构图工艺处理, 形成所述栅极 101、 栅线(图中未标出) 、 栅线引线等图案。
根据上述步骤 S201~S205, 可以形成具有顶栅型结构的薄膜晶体管 10。 所述金属氧化物半导体有源层 103包括 ATZO半导体, 所述源极 104还包括 所述第一图案 1031, 所述漏极 105还包括所述第二图案 1032。
本发明实施例提供一种利用上述方法制备的薄膜晶体管 10,参考图 1( b ) 和图 2 ( b )所示, 包括设置在基板上的栅极 101、 栅绝缘层 102、 金属氧化 物半导体有源层 103、 源极 104和漏极 105; 所述金属氧化物半导体有源层 103设置在所述衬底基板与所述源极 104和所述漏极 105之间, 且与所述源 极 104和所述漏极 105之间的间隙对应。所述薄膜晶体管 10还包括与所述金 属氧化物半导体有源层 103 同层设置且接触的第一图案 1031 和第二图案 1032; 所述第一图案 1031与所述源极 104对应且直接接触, 所述第二图案 1032与所述漏极 105对应且直接接触。
所述第一图案 1031和所述第二图案 1032均包括氧化辞系二元金属氧化 物,所述金属氧化物半导体有源层 103包括氧化辞系多元金属氧化物半导体, 且所述氧化辞系多元金属氧化物为在所述氧化辞系二元金属氧化物中注入金 属掺杂离子得到的金属氧化物。
需要说明的是,所述薄膜晶体管 10可以是顶栅型结构,也可以是底栅型 结构, 在此不作限定。但无论所述薄膜晶体管 10的结构如何, 其必须保证所 述第一图案 1031和所述第二图案 1032、 以及所述金属氧化物半导体有源层 103位于所述源极 104和所述漏极 105的下方, 从而保证在进行离子注入的 过程中可以仅使与所述源极 104和所述漏极 105之间的间隙对应的所述氧化 辞系二元金属氧化物转化为氧化辞系多元金属氧化物半导体。
所述底栅型薄膜晶体管 10是指所述栅极 101在下、所述源极 104和所述 漏极 105在上的一类薄膜晶体管; 所述顶栅型薄膜晶体管 10是指所述栅极 101在上、 所述源极 104和所述漏极 105在下的一类薄膜晶体管。
由于所述第一图案 1031与所述源极 104直接接触, 所述第二图案 1032 与所述漏极 105直接接触, 且所述第一图案 1031和所述第二图案 1032均包 括所述氧化辞系二元金属氧化物导电材料; 这样, 在所述源极 104和所述漏 极 105下方形成了一个由导体向半导体过渡的区域, 从而提供了一个载流子 传输的过渡层, 有效的解决了所述金属氧化物半导体有源层 103与所述源极 104和所述漏极 105之间的接触电阻的问题。
可选的, 参考图 1 ( b )所示, 当所述薄膜晶体管 10为底栅型时, 所述 薄膜晶体管 10可以包括设置在衬底基板上的栅极 101、 设置在所述栅极 101 上方的栅绝缘层 102、 设置在所述栅绝缘层 102上方的金属氧化物半导体有
源层 103、 与所述金属氧化物半导体有源层 103同层设置且接触的第一图案 1031和第二图案 1032、分别设置在所述第一图案 1031和所述第二图案 1032 上方的源极 104和漏极 105、 以及设置在所述源极 104和所述漏极 105上方 的保护层 106; 所述金属氧化物半导体有源层 103与所述源极 104和所述漏 极 105之间的间隙对应。
所述第一图案 1031和所述第二图案 1032均包括氧化辞系二元金属氧化 物,所述金属氧化物半导体有源层 103包括氧化辞系多元金属氧化物半导体, 且所述氧化辞系多元金属氧化物为在所述氧化辞系二元金属氧化物中注入金 属掺杂离子得到的金属氧化物。
这里, 所述氧化辞系二元金属氧化物为一种导电材料, 由于所述第一图 案 1031与所述源极 104对应且直接接触,所述第二图案 1032与所述漏极 105 对应且直接接触, 因此可视为所述源极 104还包括所述第一图案 1031, 所述 漏极 105还包括所述第二图案 1032。
此外, 由于所述金属氧化物半导体有源层 103是在形成所述源极 104和 所述漏极 105之后通过离子注入技术形成的, 而在离子注入之前, 与所述源 极 104和所述漏极 105之间的间隙对应的部位的材料为一种对金属刻蚀液不 敏感的氧化辞系二元金属氧化物, 因此可以省去刻蚀阻挡层的制备直接进行 金属刻蚀。 与现有技术相比, 这样可以减少一次构图工艺, 从而提高量产效 率, 节约成本。
可选的, 参考图 2 ( b )所示, 当所述薄膜晶体管 10为顶栅型时, 所述 薄膜晶体管 10可以包括设置在衬底基板上的金属氧化物半导体有源层 103、 与所述金属氧化物半导体有源层 103同层设置且接触的第一图案 1031和第二 图案 1032、分别设置在所述第一图案 1031和所述第二图案 1032上方的源极 104和漏极 105、 设置在所述源极 104和所述漏极 105上方的栅绝缘层 102、 以及设置在所述栅绝缘层 102上方栅极 101 ; 所述金属氧化物半导体有源层 103与所述源极 104和所述漏极 105之间的间隙对应。
这里, 所述氧化辞系二元金属氧化物为一种导电材料, 由于所述第一图 案 1031与所述源极 104对应且直接接触,所述第二图案 1032与所述漏极 105 对应且直接接触, 因此可视为所述源极 104还包括所述第一图案 1031, 所述 漏极 105还包括所述第二图案 1032。
进一步可选的, 所述氧化辞系二元金属氧化物可以包括 IZO、 或 AZO、 或 GZO、 或 TZO; 所述金属掺杂离子可以包括 Ga3+、 Sn2+、 Hi4— Al3+、 以 及 In3+中的至少一种。
在此基础上, 可以对上述的所述氧化辞系二元金属氧化物与所述金属掺 杂离子进行适当的组合, 以使得到的氧化辞系多元金属氧化物半导体的特性 与所述薄膜晶体管 10的用途实现最佳匹配即可。
本发明实施例提供一种薄膜晶体管 10, 包括设置在基板上的栅极 101、 栅绝缘层 102、 金属氧化物半导体有源层 103、 源极 104和漏极 105; 所述金 属氧化物半导体有源层 103设置在所述基板与所述源极 104和所述漏极 105 之间, 且与所述源极 104和所述漏极 105之间的间隙对应。 所述薄膜晶体管 10还包括与所述金属氧化物半导体有源层 103 同层设置且接触的第一图案 1031和第二图案 1032;所述第一图案 1031与所述源极 104对应且直接接触, 所述第二图案 1032与所述漏极 105对应且直接接触。 所述第一图案 1031和 所述第二图案 1032均包括氧化辞系二元金属氧化物,所述金属氧化物半导体 有源层 103包括氧化辞系多元金属氧化物半导体, 且所述氧化辞系多元金属 氧化物为在所述氧化辞系二元金属氧化物中注入金属掺杂离子得到的金属氧 化物。
对于本发明实施例提供的薄膜晶体管 10, 所述第一图案 1031和所述第 二图案 1032与所述金属氧化物半导体有源层 103同层设置且接触,且所述金 属氧化物半导体有源层 103与所述源极 104和所述漏极 105之间的间隙对应。 由于所述第一图案 1031与所述源极 104对应且接触, 所述第二图案 1032与 所述漏极 105对应且接触, 且所述第一图案 1031和所述第二图案 1032均包 括所述氧化辞系二元金属氧化物导电材料, 这样便相当于在所述源极 104和 所述漏极 105的下方形成了一个由导体向半导体过渡的区域, 从而形成了一 个可以提供载流子传输的过渡层, 有效的解决了所述金属氧化物半导体有源 层 103与所述源极 104和所述漏极 105之间的接触电阻的问题。
本发明实施例提供了一种阵列基板, 包括上述的薄膜晶体管 10。
这里, 当所述阵列基板应用于液晶显示装置时, 如图 9所示, 所述阵列 基板还包括与所述薄膜晶体管 10的所述漏极 105电连接的像素电极 20。
当然, 还可以包括公共电极等。
此外, 当所述阵列基板应用于有机电致发光器件时, 所述阵列基板还包 括阴极, 阳极。 当然还可以根据需要制作平坦化层、 像素界定层等。
所述像素界定层用于保证在通过打印技术形成发光层时, 发光材料的液 滴可以平整地铺满像素区域内, 同时避免液滴流到相邻像素区。
本发明实施例还提供了一种显示装置, 包括上述的阵列基板。
所述显示装置可以为: 液晶面板、 OLED、 电子纸、 液晶电视、 液晶显 示器、 数码相框、 手机、 平板电脑等具有任何显示功能的产品或部件。
以上所述仅是本发明的示范性实施方式, 而非用于限制本发明的保护范 围, 本发明的保护范围由所附的权利要求确定。
Claims
1、 一种薄膜晶体管, 包括设置在基板上的栅极、 栅绝缘层、金属氧化物 半导体有源层、 源极和漏极; 其中,
所述金属氧化物半导体有源层设置在所述基板与所述源极和所述漏极之 间, 且与所述源极和所述漏极之间的间隙对应;
所述薄膜晶体管还包括与所述金属氧化物半导体有源层同层设置且接触 的第一图案和第二图案; 所述第一图案与所述源极对应且直接接触, 所述第 二图案与所述漏极对应且直接接触;
其中, 所述第一图案和所述第二图案均包括氧化辞系二元金属氧化物, 所述金属氧化物半导体有源层包括氧化辞系多元金属氧化物半导体, 且所述 氧化辞系多元金属氧化物为在所述氧化辞系二元金属氧化物中注入金属掺杂 离子得到的金属氧化物。
2、根据权利要求 1所述的薄膜晶体管, 其中,在沿所述源极和所述漏极 的间隔方向的截面中, 所述金属氧化物半导体有源层的宽度与所述源极和所 述漏极之间的间隙宽度相同。
3、根据权利要求 1或 2所述的薄膜晶体管, 其中, 所述薄膜晶体管为底 栅型;
所述薄膜晶体管还包括设置在所述源极和所述漏极上方的保护层。
4、根据权利要求 1或 2所述的薄膜晶体管, 其中, 所述薄膜晶体管为顶 栅型。
5、 根据权利要求 1至 4任一项所述的薄膜晶体管, 其中,
所述氧化辞系二元金属氧化物包括铟辞氧化物 IZO、或铝辞氧化物 AZO、 或镓辞氧化物 GZO、 或锡辞氧化物 TZO;
所述金属掺杂离子包括镓离子 Ga3+、 锡离子 Sn2+、 铪离子 1 +、 铝离子
Al3+、 以及铟离子 In3+中的至少一种。
6、 根据权利要求 1至 5任一项所述的薄膜晶体管, 其中,
在沿所述源极和所述漏极的间隔方向的截面中, 所述金属氧化物半导体 有源层的两侧边缘分别与所述源极和所述漏极相对的边缘对齐。
7、 一种阵列基板, 包括权利要求 1至 6任一项所述的薄膜晶体管。
8、 一种显示装置, 包括权利要求 7所述的阵列基板。
9、 一种薄膜晶体管的制备方法, 包括在基板上形成栅极、栅绝缘层、金 属氧化物半导体有源层、 源极和漏极; 其中,
所述在基板上形成金属氧化物半导体有源层包括:
在基板上形成氧化辞系二元金属氧化物图案层, 所述图案层包括与所述 源极对应的第一图案、 与所述漏极对应的第二图案、 以及与所述源极和所述 漏极之间的间隙对应的第三图案, 且所述氧化辞系二元金属氧化物图案层与 所述源极和所述漏极直接接触;
以形成在所述源极和所述漏极上方的绝缘层为阻挡层, 釆用离子注入技 术向所述氧化辞系二元金属氧化物图案层注入金属掺杂离子, 将所述第三图 案的所述氧化辞系二元金属氧化物转化为氧化辞系多元金属氧化物半导体, 形成所述金属氧化物半导体有源层。
10、 根据权利要求 9所述的方法, 其中, 所述薄膜晶体管为底栅型; 所述方法还包括: 在形成所述源极和所述漏极的基板上形成保护层; 其中, 所述以绝缘层为阻挡层, 釆用离子注入技术向所述氧化辞系二元 金属氧化物图案层注入金属掺杂离子, 将所述第三图案的所述氧化辞系二元 金属氧化物转化为氧化辞系多元金属氧化物半导体, 形成所述金属氧化物半 导体有源层包括:
以所述保护层为阻挡层, 釆用离子注入技术向所述氧化辞系二元金属氧 化物图案层注入金属掺杂离子, 将未被所述源极和所述漏极阻挡的所述第三 图案的所述氧化辞系二元金属氧化物转化为氧化辞系多元金属氧化物半导 体, 形成所述金属氧化物半导体有源层。
11、 根据权利要求 9所述的方法, 其中, 所述薄膜晶体管为顶栅型; 其中, 所述以绝缘层为阻挡层, 釆用离子注入技术向所述氧化辞系二元 金属氧化物图案层注入金属掺杂离子, 将所述第三图案的所述氧化辞系二元 金属氧化物转化为氧化辞系多元金属氧化物半导体, 形成所述金属氧化物半 导体有源层包括:
以所述栅绝缘层为阻挡层, 釆用离子注入技术向所述氧化辞系二元金属 氧化物图案层注入金属掺杂离子, 将未被所述源极和所述漏极阻挡的所述第 三图案的所述氧化辞系二元金属氧化物转化为氧化辞系多元金属氧化物半导
体, 形成所述金属氧化物半导体有源层。
12、根据权利要求 9至 11任一项所述的方法, 其中, 在所述釆用离子注 入技术向所述氧化辞系二元金属氧化物图案层注入金属掺杂离子之后, 所述 方法还包括进行退火处理。
13、 根据权利要求 9至 12任一项所述的方法, 其中,
所述氧化辞系二元金属氧化物包括铟辞氧化物 IZO、或铝辞氧化物 AZO、 或镓辞氧化物 GZO、 或锡辞氧化物 TZO;
所述金属掺杂离子包括镓离子 Ga3+、 锡离子 Sn2+、 铪离子 1 +、 铝离子 Al3+、 以及铟离子 In3+中的至少一种。
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