WO2015067054A1 - 互补式薄膜晶体管及其制备方法、阵列基板和显示装置 - Google Patents

互补式薄膜晶体管及其制备方法、阵列基板和显示装置 Download PDF

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WO2015067054A1
WO2015067054A1 PCT/CN2014/080270 CN2014080270W WO2015067054A1 WO 2015067054 A1 WO2015067054 A1 WO 2015067054A1 CN 2014080270 W CN2014080270 W CN 2014080270W WO 2015067054 A1 WO2015067054 A1 WO 2015067054A1
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thin film
film transistor
active layer
substrate
layer
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PCT/CN2014/080270
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English (en)
French (fr)
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刘晓娣
王刚
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京东方科技集团股份有限公司
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Priority to US14/429,165 priority Critical patent/US10083988B2/en
Publication of WO2015067054A1 publication Critical patent/WO2015067054A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1233—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different thicknesses of the active layer in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the invention belongs to the technical field of preparation of thin film transistors, and particularly relates to a complementary thin film transistor and a preparation method thereof, an array substrate and a display device.
  • CMOS TFTs Each of the complementary thin film transistors (CMOS TFTs) includes a first thin film transistor and a second thin film transistor, wherein one of the two thin film transistors is a P-type thin film transistor (PMOS TFT) and the other is an N-type thin film transistor (NMOS) TFT), so CMOS TFTs can be used to implement various circuits and systems that are difficult to implement with PMOS TFTs or NMOS TFTs.
  • PMOS TFT P-type thin film transistor
  • NMOS N-type thin film transistor
  • the method for preparing a CMOS TFT generally includes the following steps 1 to 6.
  • Step 1 Form a pattern of a gate metal layer including the first thin film transistor gate 21 and the second thin film transistor gate 22 on the substrate 1, and the gate 21 of the first thin film transistor and the gate 22 of the second thin film transistor It is electrically connected together.
  • Step 2 forming a gate insulating layer 3 on the substrate 1 which has completed the above steps.
  • Step 3 On the substrate 1 which has completed the above steps, a pattern of the active layer 4 including the first thin film transistor is formed.
  • Step 4 On the substrate 1 which has completed the above steps, a pattern of the active layer 5 including the second thin film transistor is formed.
  • Step 5 forming an etch barrier layer 6 on the substrate 1 that completes the above steps, and etching the etch barrier layer 6 to form a source 71, a drain 72, and a second thin film transistor of the first thin film transistor.
  • Step 6 On the substrate 1 that completes the above steps, the source 81, the drain 72, and the source 81 and the drain 82 of the second thin film transistor are formed. A pattern of source and drain metal layers, wherein the drain 72 of the first thin film transistor and the source 81 of the second thin film transistor are adjacent and electrically connected.
  • the above steps are described by taking the first thin film transistor and the second thin film transistor of the bottom gate type as an example.
  • the method for preparing the first thin film transistor and the second thin film transistor of the top gate type is mainly different from the above method.
  • the source layer is further prepared with a gate electrode, and the description thereof will not be repeated here.
  • the inventors of the present invention have found that at least the following problems exist in the prior art: after the preparation of the active layer 4 of the first thin film transistor is completed, when the active layer 5 of the second thin film transistor is prepared, since the first thin film transistor has The material of the source layer 4 is different from the material of the active layer 5 of the second thin film transistor, and thus affects the material of the active layer 4 of the first thin film transistor that has been formed, specifically, the first thin film transistor is formed.
  • the active layer film of the second thin film transistor also affects the performance of the active layer 4 of the first thin film transistor, and the processing of the active layer 5 of the second thin film transistor also affects the presence of the first thin film transistor
  • the performance of the source layer 4, for example, plasma treatment of the active layer 5 of the second thin film transistor may cause plasma bombardment damage to the active layer 4 of the first thin film transistor, ,
  • Doping and other high energy processes and different atmosphere at annealing process also affect the energy of the CMOS TFT, resulting in degradation of CMOS TFT characteristics, such as threshold voltage CMOS TFT lead, sub wide swing value, stability and the like degeneration. Summary of the invention
  • the technical problem to be solved by the present invention is to provide a performance-stable complementary thin film transistor and a method for fabricating the same, an array substrate and a display device, in view of the above problems existing in the conventional complementary thin film transistor.
  • the technical solution to solve the technical problem to be solved by the present invention is a method for preparing a complementary thin film transistor, comprising: forming a pattern including an active layer of a first thin film transistor and a protective layer on a substrate by a patterning process, And the protective layer is located at least on the active layer of the first thin film transistor; on the substrate that completes the above steps,
  • the over patterning process forms a pattern including an active layer of the second thin film transistor.
  • a protective layer is provided on the active layer of the first thin film transistor, which can effectively avoid the existence of two thin film transistors when preparing the active layer of the second thin film transistor.
  • the material of the source layer affects the performance of the active layer of the first thin film transistor, thereby improving the performance of the complementary thin film transistor.
  • the step of forming a pattern including the active layer of the first thin film transistor and the protective layer on the substrate comprises: sequentially depositing an active layer film and a protective layer film of the first thin film transistor on the substrate; On the substrate of the step, a pattern including the active layer and the protective layer of the first thin film transistor is simultaneously formed by one patterning process.
  • the step of forming a pattern including the active layer of the first thin film transistor and the protective layer on the substrate specifically comprises: forming an active layer film of the first thin film transistor; forming a pattern by a patterning process on the substrate on which the above steps are completed A pattern including an active layer of the first thin film transistor; a protective layer film is formed on the substrate on which the above steps are performed; and a pattern including the protective layer is formed on the substrate on which the above steps are completed by a patterning process.
  • the protective layer film further comprising: a step of processing the active layer of the formed first thin film transistor by plasma modification or sputtering doping; and/or, forming a second
  • the pattern of the active layer of the thin film transistor further includes the step of processing the active layer of the formed second thin film transistor by plasma modification or sputtering doping.
  • the active layer of the first thin film transistor is formed of a first semiconductor material
  • the active layer of the second thin film transistor is formed of a second semiconductor material, wherein the first semiconductor material is P
  • the type of semiconductor material and the second semiconductor material is an N-type semiconductor material, or the first semiconductor material is an N-type semiconductor material and the second semiconductor material is a P-type semiconductor material.
  • the step of forming a pattern including the active layer of the first thin film transistor and the protective layer on the substrate further comprises: forming a pattern including a gate of the first thin film transistor and a gate of the second thin film transistor on the substrate ; after completing the above steps On the substrate, a gate insulating layer is formed.
  • the method further includes: forming an etch barrier layer on the substrate, and forming the etch stop layer and the protective layer for forming Forming a source and a drain of the first thin film transistor, a source and a drain of the second thin film transistor, and a source and a drain contact region respectively contacting the respective active layers; forming a pattern by a patterning process on the substrate on which the above steps are completed a source and a drain of a thin film transistor and a source and a drain of the second thin film transistor, and the source and drain of the first thin film transistor and the source and drain of the second thin film transistor respectively pass through respective source and drain contact regions Contact with the respective active layers.
  • the protective layer is a single layer or a multilayer film formed of one or more of an oxide of silicon, a nitride of silicon, an oxide of cerium, an oxynitride of silicon, and an oxide of aluminum. .
  • the technical solution to solve the technical problem to be solved by the present invention is a complementary thin film transistor including a first thin film transistor and a second thin film transistor, and the upper layer of the first thin film transistor is disposed above the active layer There is a protective layer for protecting the active layer of the first thin film transistor from being affected by the formation of the active layer of the second thin film transistor.
  • a protective layer is disposed over the active layer of the first thin film transistor of the complementary thin film transistor of the present invention, so that the active layer of the first thin film transistor can be prevented from being disadvantageous when it is formed by the active layer of the second thin film transistor.
  • the effect can further improve the performance of the complementary thin film transistor.
  • one of the first thin film transistor and the second thin film transistor is a P-type thin film transistor, and the other is an N-type thin film transistor, wherein an active layer of the N-type thin film transistor is doped with arsenic, antimony, Any one or more of phosphorus, wherein the active layer of the P-type thin film transistor is doped with any one or more of boron, indium, and gallium.
  • the protective layer is a single layer or a multilayer film formed of one or more of an oxide of silicon, a nitride of silicon, an oxide of cerium, an oxynitride of silicon, and an oxide of aluminum. .
  • the technical solution adopted to solve the technical problem to be solved by the present invention is a matrix A column substrate comprising the above complementary thin film transistor.
  • the array substrate of the present invention includes the above-described complementary thin film transistor, so that its performance is more stable.
  • the display device of the present invention includes the above array substrate, so that its performance is more stable.
  • Figure 1 is a cross-sectional view showing the structure of each step of a conventional method for fabricating a complementary thin film transistor.
  • Fig. 2 is a cross-sectional view showing the structure of each step of the method for fabricating the complementary thin film transistor of the first embodiment of the present invention.
  • Fig. 3 is a cross-sectional view showing the structure of a complementary thin film transistor of Embodiment 2 of the present invention.
  • Reference numerals 1. a substrate; 21. a gate of a first thin film transistor; 22. a gate of a second thin film transistor; 3. a gate insulating layer; 4. an active layer of the first thin film transistor; An active layer of the thin film transistor; 6. an etch stop layer; 71 a source of the first thin film transistor; 72, a drain of the first thin film transistor; 81, a source of the second thin film transistor; 82, a second thin film transistor Drain; 9, protective layer; 10, passivation layer; 11, metal electrode. detailed description
  • the embodiment provides a method for fabricating a complementary thin film transistor, the complementary thin film transistor including a first thin film transistor and a second thin film transistor, and the first thin film transistor and the second thin film transistor
  • One is a P-type thin film transistor and the other is an N-type thin film transistor, that is, the first thin film transistor is a P-type
  • the thin film transistor and the second thin film transistor are N-type thin film transistors, or the first thin film transistor is an N-type thin film transistor and the second thin film transistor is a P-type thin film transistor.
  • the preparation method specifically includes the following steps 1 to 8.
  • Step 1 depositing a gate metal layer film on the substrate 1 by magnetron sputtering, forming a gate electrode 22 including the first thin film transistor and a gate electrode 22 of the second thin film transistor and a gate line by a patterning process The pattern of the gate metal layer.
  • the gate 21 of the first thin film transistor and the gate 22 of the second thin film transistor are electrically connected together.
  • the substrate 1 may refer to a substrate which does not form any film layer, such as white glass, and may also refer to a substrate on which other film layers or patterns are formed, such as a substrate on which a buffer layer is formed.
  • the patterning process typically includes processes such as photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • a gate metal layer film is first formed, and a photoresist is applied to cover the gate metal layer film, and then exposed by a mask to form an exposed region and a non-exposed region, and developed to remove
  • the photoresist in the exposed region for example, a positive photoresist
  • the photoresist in the non-exposed region is retained, and then the gate metal film is etched, and the gate metal film of the non-exposed region is formed by the photoresist.
  • the protective layer is not etched.
  • the photoresist is stripped to form a pattern including the gate electrode 21 of the first thin film transistor and the gate electrode 22 of the second thin film transistor and the gate metal layer of the gate line.
  • the gate metal layer film may be one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (A1), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu) or A plurality of formed single-layer or multi-layer composite films, preferably a single-layer or multi-layer composite film formed of Mo, Al or an alloy containing Mo, Al.
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • AlNd aluminum-niobium alloy
  • Ti titanium
  • Cu copper
  • Step 2 On the substrate 1 which has completed the above steps, the gate insulating layer 3 is formed by a method of thermal growth, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, plasma-assisted chemical vapor deposition, sputtering or the like.
  • the gate insulating layer 3 may be an oxide of silicon (SiOx), a nitride of silicon (SiNx), an oxide of hafnium (HfOx), an oxide of silicon (SiON), an oxide of aluminum ( A single-layer or multi-layer composite film formed by AlOx) or the like.
  • Step 3 on the substrate 1 after completing the above steps, forming a pattern by a patterning process
  • the active layer 4 of the first thin film transistor and the pattern of the protective layer 9, and the protective layer 9 is located at least on the active layer 4 of the first thin film transistor.
  • the third step specifically includes: sequentially depositing the active layer film and the protective layer film of the first thin film transistor by spraying, vacuum evaporation, sol-gel, magnetron sputtering, etc., and simultaneously forming the first layer by one patterning process A pattern of the active layer 4 and the protective layer 9 of the thin film transistor.
  • the active layer 4 of the first thin film transistor is formed of a first semiconductor material, and the first semiconductor material is a P-type or N-type semiconductor material. This method is simple and easy to implement.
  • the step may further include: forming an active layer film of the thin film transistor, and doping the active layer film by an ion implantation method to form an active layer 4 of the first thin film transistor.
  • a layer of a tin oxide (SnOx) material is first formed, an active layer of the first thin film transistor is formed by a patterning process, and then the active layer of the first thin film transistor is doped with any one of arsenic, antimony, and phosphorus.
  • a plurality of ions to form an active layer 4 of the N-type thin film transistor, or an active layer of the first thin film transistor is doped with any one or more of boron, indium, and gallium to form a P-type thin film transistor Active layer 4.
  • the pattern of the protective layer 9 and the active layer 4 of the first thin film transistor is formed by a single patterning process, process steps such as exposure and development are not increased.
  • the third step may further include: forming an active layer film of the first thin film transistor, and forming a pattern of the active layer 4 including the first metal thin film transistor on the substrate 1 by a patterning process, after completing the above steps On the substrate 1, a protective layer film is formed, and a pattern including the protective layer 9 is formed by a patterning process.
  • the protective layer 9 formed in this step may cover only the active layer 4 of the first thin film transistor, or may form the protective layer 9 directly on the entire substrate 1 without exposing or developing the protective layer film.
  • the method further comprises: treating the active layer 4 of the formed first thin film transistor by plasma modification or sputtering doping. At this time, the performance of the active layer 4 of the first thin film transistor can be further optimized.
  • the protective layer 9 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), or the like. Single or multi-layer film.
  • Step 4 On the substrate 1 on which the above steps are completed, an active layer film of the second thin film transistor is formed, and a pattern including the active layer 5 of the second thin film transistor is formed by a patterning process.
  • the specific formation method is the same as that of the active layer 4 of the first thin film transistor, except that the materials used are different, and the description thereof will not be repeated here.
  • the method further comprises the step of treating the active layer 5 of the formed second thin film transistor by plasma modification or sputtering doping. At this time, the performance of the active layer 5 of the second thin film transistor can be further optimized.
  • Step 5 forming an etch barrier layer 6 on the substrate 1 that completes the above steps, and etching to form a source 71 and a drain through the etch barrier layer 6 and the protective layer 9 for the first thin film transistor to be formed.
  • the source and drain contact regions of the pole 72 and the source 81 and the drain 82 of the second thin film transistor are respectively in contact with the respective active layers.
  • the etch stop layer 6 may be an oxide of silicon (SiOx), a nitride of silicon (SiNx), an oxide of hafnium (HfOx), an oxide of silicon (SiON), an oxide of aluminum ( A single layer or a multilayer film formed by AlOx) or the like.
  • Step 6 On the substrate 1 that completes the above steps, a source/drain metal layer film is formed, and a source electrode 71 including a first thin film transistor, a drain electrode 72, and a source electrode 81 and a drain electrode 82 of the second thin film transistor are formed by a patterning process.
  • the pattern, and the source 71 of the first thin film transistor, the drain 72, and the source 81 and the drain 82 of the second thin film transistor are respectively in contact with the respective active layers through respective source and drain contact regions.
  • the material of the source/drain metal layer film may be one of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (A1), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu). Or more, preferably Mo, A1 or an alloy material containing Mo, A1.
  • Step 7 On the substrate 1 which has completed the above steps, a passivation layer 10 is formed, and contact vias penetrating through the passivation layer 10 above the electrodes are formed, so that the electrodes are taken out by contacting the via holes with the metal electrodes 11.
  • Step 8 The product which has completed the above steps is annealed in a vacuum, nitrogen or oxygen atmosphere, and the annealing temperature may be 120. C-400. Between C, a complementary thin film transistor is finally formed.
  • the first thin film crystal is disposed on the active layer 4 of the body tube, which can effectively prevent the first thin film transistor from being affected by the material of the active layers of the two thin film transistors when preparing the active layer 5 of the second thin film transistor.
  • the performance of the active layer 4 in turn, can improve the performance of the complementary thin film transistor.
  • first thin film transistor and the second thin film transistor of the complementary thin film transistor prepared by the above preparation method are bottom gate type thin film transistors.
  • first thin film transistor and the second thin film transistor may be prepared as a top gate type thin film transistor, and the specific steps are substantially the same as the above steps, except that the order in which the structures are formed is different, for example, the first type of the top gate type is prepared.
  • the steps of the thin film transistor and the second thin film transistor may include: forming a pattern including the active layer 4 of the first thin film transistor and the protective layer 9 on the substrate 1 by a patterning process; on the substrate 1 completing the above steps, by a patterning process Forming a pattern of the active layer 5 including the second thin film transistor; on the substrate 1 performing the above steps, simultaneously forming a source 81 including the first thin film transistor source 71, the drain 72, and the second thin film transistor by a patterning process, a pattern of the drain 82; a gate insulating layer 3 is formed on the substrate 1 which has completed the above steps; on the substrate 1 which has completed the above steps, the gate electrode 21 including the first thin film transistor and the second thin film transistor are simultaneously formed by a patterning process a pattern of the gate electrode 22; on the substrate 1 which has completed the above steps, a planarization layer is formed; On the substrate 1 which has completed the above steps, a contact via penetrating through the planarization layer and the gate insulating layer 3 is
  • the gate patterns of the gate electrode 21 of the first thin film transistor and the gate electrode 22 of the second thin film transistor are the gates of other thin film transistors on the substrate 1, due to Shown in the figure is only a cross-sectional view taken, so that the cross-sectional view shows only the gate of the other thin film transistor.
  • the first thin film transistor and the second thin film transistor are not limited to the top gate type or bottom gate type structure, and may be thin film transistors of other structures, which are not described here.
  • the embodiment provides a complementary thin film transistor including a first thin film transistor and a second thin film transistor, and a protective layer is disposed over the active layer of the first thin film transistor, wherein the first thin film transistor One of the second thin film transistors is a P-type thin film transistor, and the other is an N-type thin film transistor.
  • the complementary thin film transistor can be prepared by the method of Embodiment 1, since the protective layer 9 is disposed above the active layer 4 of the first thin film transistor, so that the active layer 4 of the first thin film transistor can be prevented from being protected from the second thin film transistor.
  • the adverse effect of the active layer 5 on it is formed, which in turn can improve the performance of the complementary thin film transistor.
  • the first thin film transistor is a P-type thin film transistor and the second thin film transistor is an N-type thin film transistor, or the first thin film transistor is an N-type thin film transistor and the second thin film transistor is a P-type thin film transistor.
  • the active layer of the N-type thin film transistor is doped with any one or more of arsenic, antimony and phosphorus.
  • the active layer of the P-type thin film transistor is doped with any one or more of boron, indium, and gallium. At this time, the performance of the complementary thin film transistor can be further improved.
  • Example 3 Example 3:
  • This embodiment provides an array substrate including the above-described complementary thin film transistor, and of course, other structures including a pixel electrode, a common electrode, and the like.
  • the embodiment provides a display device, which includes the above array substrate, and the display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device of this embodiment has the array substrate of the embodiment 3, so that the performance is better.

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Abstract

一种互补式薄膜晶体管及其制备方法、阵列基板、显示装置，属于薄膜晶体管制备技术领域，其可解决现有的互补式薄膜晶体管的第一薄膜晶体管与第二薄膜晶体管的有源层材料互相影响的问题。互补式薄膜晶体管的制备方法，包括：通过构图工艺，在基底（1）上形成包括第一薄膜晶体管的有源层（4）以及保护层（9）的图形，且保护层（9）至少位于第一薄膜晶体管的有源层（4）上；通过构图工艺形成包括第二薄膜晶体管有源层（5）的图形。可用于各种电路和***中。

Description

互补式薄膜晶体管及其制备方法、 阵列基板和显示装置 技术领域
本发明属于薄膜晶体管的制备技术领域， 具体涉及互补式薄 膜晶体管及其制备方法、 阵列基板和显示装置。
背景技术
每个互补式薄膜晶体管 （CMOS TFT ) 包括第一薄膜晶体管 和第二薄膜晶体管， 其中， 这两个薄膜晶体管中的一个为 P型薄 膜晶体管（PMOS TFT )，另一个为 N型薄膜晶体管（NMOS TFT ) , 所以利用 CMOS TFT可以实现 PMOS TFT或 NMOS TFT难以实 现的各种电路和***。
如图 1所示， 通常制备 CMOS TFT的方法具体包括以下的步 骤一至步骤六。
步骤一、在基底 1上形成包括第一薄膜晶体管栅极 21和第二 薄膜晶体管栅极 22的栅极金属层的图形， 且第一薄膜晶体管的栅 极 21和第二薄膜晶体管的栅极 22是电连接在一起的。
步骤二、 在完成上述步骤的基底 1上形成栅极绝缘层 3。
步骤三、 在完成上述步骤的基底 1上， 形成包括第一薄膜晶 体管的有源层 4的图形。
步骤四、 在完成上述步骤的基底 1上， 形成包括第二薄膜晶 体管的有源层 5的图形。
步骤五、 在完成上述步骤的基底 1 上， 形成刻蚀阻挡层 6， 并刻蚀该刻蚀阻挡层 6， 以形成使第一薄膜晶体管的源极 71、 漏 极 72和第二薄膜晶体管的源极 81、 漏极 82分别与各自的有源区 接触的源漏接触区。
步骤六、 在完成上述步骤的基底 1上， 形成包括第一薄膜晶 体管的源极 71、 漏极 72和第二薄膜晶体管的源极 81、 漏极 82的 源漏金属层的图形， 其中第一薄膜晶体管的漏极 72和第二薄膜晶 体管的源极 81相邻并电连接。
上述步骤是以制备底栅型的第一薄膜晶体管和第二薄膜晶体 管为例进行说明的， 制备顶栅型的第一薄膜晶体管和第二薄膜晶 体管的方法与上述方法的区别主要是先制备有源层再制备栅极， 在此就不重复赘述了。
本发明的发明人发现， 现有技术中至少存在如下问题： 在第 一薄膜晶体管的有源层 4制备完成后， 在制备第二薄膜晶体管的 有源层 5时， 由于第一薄膜晶体管的有源层 4的材料与第二薄膜 晶体管的有源层 5 的材料不同， 因此会对已经形成的第一薄膜晶 体管的有源层 4 的材料产生影响， 具体地说， 在形成第一薄膜晶 体管的有源层 4后沉积的第二薄膜晶体管的有源层薄膜会与第一 薄膜晶体管的有源层 4接触， 即使在后续工艺中会刻蚀掉第一薄 膜晶体管的有源层 4上方的第二薄膜晶体管的有源层薄膜， 也还 是会对第一薄膜晶管的有源层 4 的性能造成影响， 对第二薄膜晶 体管的有源层 5的处理也会影响第一薄膜晶管的有源层 4的性能， 例如， 对第二薄膜晶体管的有源层 5 的等离子体处理会导致对第 一薄膜晶管的有源层 4 的等离子体轰击损伤， 此外， 掺杂改性等 高能过程以及不同气氛的退火等处理也会影响 CMOS TFT 的性 能，导致 CMOS TFT的特性劣化，如导致 CMOS TFT的阔值电压、 亚阔值摆幅、 稳定性等退化。 发明内容
本发明所要解决的技术问题是， 针对现有的互补式薄膜晶体 管所存在的上述问题， 提供一种性能稳定的互补式薄膜晶体管及 其制备方法、 阵列基板和显示装置。
解决本发明所要解决的技术问题所釆用的技术方案是一种互 补式薄膜晶体管的制备方法， 包括： 通过构图工艺， 在基底上形 成包括第一薄膜晶体管的有源层以及保护层的图形， 且保护层至 少位于第一薄膜晶体管有源层上； 在完成上述步骤的基底上， 通 过构图工艺形成包括第二薄膜晶体管的有源层的图形。
本发明的互补式薄膜晶体管的制备方法中， 在第一薄膜晶体 管的有源层上设有保护层， 可以有效地避免在制备第二薄膜晶体 管的有源层时， 由于两个薄膜晶体管的有源层的材料不同而影响 第一薄膜晶体管的有源层的性能， 进而可以提高互补式薄膜晶体 管的性能。
优选的是， 在基底上形成包括第一薄膜晶体管的有源层以及 保护层的图形的步骤具体包括： 在基底上依次沉积第一薄膜晶管 的有源层薄膜和保护层薄膜； 在完成上述步骤的基底上， 通过一 次构图工艺， 同时形成包括第一薄膜晶体管的有源层和保护层的 图形。
优选的是， 在基底上形成包括第一薄膜晶体管的有源层以及 保护层的图形的步骤具体包括： 形成第一薄膜晶体管的有源层薄 膜； 在完成上述步骤的基底上， 通过构图工艺形成包括第一薄膜 晶体管的有源层的图形； 在完成上述步骤的基底上， 形成保护层 薄膜； 在完成上述步骤的基底上， 通过构图工艺形成包括保护层 的图形。
进一步优选的是， 在形成保护层薄膜之前还包括： 通过等离 子体改性或溅射掺杂对所形成的第一薄膜晶体管的有源层进行处 理的步骤； 和 /或， 在形成包括第二薄膜晶体管的有源层的图形之 后还包括： 通过等离子体改性或溅射掺杂对所形成的第二薄膜晶 体管的有源层进行处理的步骤。
优选的是， 所述第一薄膜晶体管的有源层釆用第一半导体材 料形成， 所述第二薄膜晶体管的有源层釆用第二半导体材料形成， 其中， 所述第一半导体材料为 P型半导体材料且第二半导体材料 为 N型半导体材料， 或者所述第一半导体材料为 N型半导体材料 且第二半导体材料为 P型半导体材料。
优选的是， 在基底上形成包括第一薄膜晶体管的有源层以及 保护层的图形的步骤之前还包括： 在基底上形成包括第一薄膜晶 体管的栅极和第二薄膜晶体管的栅极的图形； 在完成上述步骤的 基底上， 形成栅极绝缘层。
进一步优选的是， 在形成包括第二薄膜晶体管的有源层的图 形之后还包括： 在基底上， 形成刻蚀阻挡层， 且形成贯穿刻所述 刻蚀阻挡层和保护层的用于使待形成的第一薄膜晶体管的源、 漏 极和第二薄膜晶体管的源、 漏极分别与各自的有源层接触的源、 漏接触区； 在完成上述步骤的基底上， 通过构图工艺形成包括第 一薄膜晶体管的源、 漏极和第二薄膜晶体管的源、 漏极的图形， 且第一薄膜晶体管的源、 漏极和第二薄膜晶体管的源、 漏极分别 通过各自的源、 漏接触区与各自的有源层接触。
优选的是， 所述保护层为由硅的氧化物、 硅的氮化物、 铪的 氧化物、 硅的氮氧化物、 铝的氧化物中的一种或多种形成的单层 或多层膜。
解决本发明所要解决的技术问题所釆用的技术方案是一种互 补式薄膜晶体管， 所述互补式薄膜晶体管包括第一薄膜晶体管和 第二薄膜晶体管， 且第一薄膜晶体管的有源层上方设置有保护层， 用于保护第一薄膜晶体管的有源层不受第二薄膜晶体管的有源层 形成时的影响。
本发明的互补式薄膜晶体管的第一薄膜晶体管的有源层上方 设置有保护层， 从而可以避免第一薄膜晶体管的有源层不受第二 薄膜晶体管的有源层形成时对其造成的不利影响， 进而可以提高 互补式薄膜晶体管的性能。
优选的是， 所述第一薄膜晶体管和第二薄膜晶体管中的一个 为 P型薄膜晶体管， 另一个为 N型薄膜晶体管， 所述 N型薄膜晶 体管的有源层中掺杂有砷、 锑、 磷中的任意一种或多种离子， 所 述 P型薄膜晶体管的有源层中掺杂有硼、 铟、 镓中的任意一种或 多种离子。
优选的是， 所述保护层为由硅的氧化物、 硅的氮化物、 铪的 氧化物、 硅的氮氧化物、 铝的氧化物中的一种或多种形成的单层 或多层膜。
解决本发明所要解决的技术问题所釆用的技术方案是一种阵 列基板， 其包括上述互补式薄膜晶体管。
本发明的阵列基板包括上述互补式薄膜晶体管， 故其性能更 稳定。
解决本发明所要解决的技术问题所釆用的技术方案是一种显 示装置， 其包括上述阵列基板
本发明的显示装置包括上述阵列基板， 故其性能更稳定。 附图说明
图 1 为现有的互补式薄膜晶体管的制备方法的各步骤所形成 的结构的截面图。
图 2为本发明的实施例 1的互补式薄膜晶体管的制备方法的 各步骤所形成的结构的截面图。
图 3为本发明的实施例 2的互补式薄膜晶体管的结构的截面 图。
附图标记： 1、 基底； 21、 第一薄膜晶体管的栅极； 22、 第二 薄膜晶体管的栅极； 3、 栅极绝缘层； 4、 第一薄膜晶体管的有源 层； 5、 第二薄膜晶体管的有源层； 6、 刻蚀阻挡层； 71第一薄膜 晶体管的源极； 72、 第一薄膜晶体管的漏极； 81、 第二薄膜晶体 管的源极； 82、 第二薄膜晶体管的漏极； 9、 保护层； 10、 钝化层； 11、 金属电极。 具体实施方式
为使本领域技术人员更好地理解本发明的技术方案， 下面结 合附图和具体实施方式对本发明作进一步详细描述。 实施例 1 :
如图 2所示， 本实施例提供一种互补式薄膜晶体管的制备方 法， 所述互补式薄膜晶体管包括第一薄膜晶体管和第二薄膜晶体 管， 且第一薄膜晶管和第二薄膜晶体管中的一个为 P型薄膜晶体 管， 另一个为 N型薄膜晶体管， 也就是说， 第一薄膜晶管为 P型 薄膜晶体管且第二薄膜晶体管为 N型薄膜晶体管， 或者第一薄膜 晶管为 N型薄膜晶体管且第二薄膜晶体管为 P型薄膜晶体管。 该 制备方法具体包括如下步骤一至步骤八。
步骤一、 在基底 1上釆用磁控溅射的方法沉积一层栅极金属 层薄膜， 通过构图工艺形成包括第一薄膜晶体管的栅极 21和第二 薄膜晶体管的栅极 22以及栅极线的栅极金属层的图形。 其中， 第 一薄膜晶体管的栅极 21和第二薄膜晶体管的栅极 22是电连接在 一起的。
需要说明的是， 基底 1既可以指没有形成任何膜层的衬底， 如白玻璃， 也可以指形成有其他膜层或者图案的衬底， 例如形成 有緩冲层的衬底。 构图工艺通常包括光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻胶剥离等工艺。 即， 上述步骤中， 先形成栅极金属层 薄膜， 并涂覆光刻胶覆盖栅极金属层薄膜， 接着， 利用掩模板进 行曝光， 以形成曝光区和非曝光区， 并进行显影， 以去除曝光区 的光刻胶（以正性光刻胶为例）， 非曝光区的光刻胶保留， 然后， 刻蚀栅极金属层薄膜， 非曝光区的栅极金属层薄膜由于光刻胶的 保护而未被刻蚀， 最后， 剥离光刻胶， 以形成包括第一薄膜晶体 管的栅极 21和第二薄膜晶体管的栅极 22以及栅极线的栅极金属 层的图形。
其中， 所述栅极金属层薄膜可以为由钼 （Mo ) 、 钼铌合金 ( MoNb ) 、 铝 （ A1 ) 、 铝钕合金 ( AlNd ) 、 钛（ Ti ) 和铜 ( Cu ) 中的一种或多种形成的单层或多层复合膜， 优选由 Mo、 A1 或含 Mo、 A1的合金形成的单层或多层复合膜。
步骤二、 在完成上述步骤的基底 1上， 釆用热生长、 常压化 学气相沉积、 低压化学气相沉积、 等离子体辅助化学气相淀积、 溅射等制备方法， 形成栅极绝缘层 3。
其中， 所述栅极绝缘层 3可以为由硅的氧化物 （SiOx ) 、 硅 的氮化物（ SiNx )、铪的氧化物（ HfOx )、硅的氮氧化物（ SiON ) 、 铝的氧化物 （AlOx ) 等形成的单层或多层复合膜。
步骤三、 在完成上述步骤基底 1上， 通过构图工艺形成包括 第一薄膜晶体管的有源层 4以及保护层 9的图形， 且保护层 9至 少位于第一薄膜晶体管的有源层 4上。
优选地， 步骤三具体包括： 通过喷涂、 真空蒸发、 溶胶-凝胶、 磁控溅射等依次沉积第一薄膜晶体管的有源层薄膜和保护层薄 膜，并通过一次构图工艺同时形成包括第一薄膜晶体管的有源层 4 和保护层 9的图形。 其中， 第一薄膜晶体管的有源层 4釆用第一 半导体材料形成， 第一半导体材料为 P型或 N型半导体材料。 该 方法简单， 容易实现。 当然， 该步骤还可以具体包括： 形成薄膜 晶体管的有源层薄膜， 再釆用离子注入方法对该有源层薄膜进行 掺杂， 进而形成第一薄膜晶体管的有源层 4。 例如， 先形成一层氧 化锡 （SnOx ) 材料层， 通过构图工艺形成第一薄膜晶体管的有源 层， 然后对第一薄膜晶体管的有源层掺杂砷、 锑、 磷中的任意一 种或多种离子， 以形成 N型薄膜晶体管的有源层 4， 或者， 对第 一薄膜晶体管的有源层掺杂硼、 铟、 镓中的任意一种或多种离子， 以形成 P型薄膜晶体管的有源层 4。
由于保护层 9与第一薄膜晶体管的有源层 4的图形通过一次 构图工艺同步形成， 不会增加曝光、 显影等工艺步骤。
可选地， 步骤三还可以具体包括： 形成第一薄膜晶体管的有 源层薄膜， 并通过构图工艺在基底 1 上形成包括第一金属薄膜晶 体管的有源层 4的图形， 在完成上述步骤的基底 1上， 形成保护 层薄膜， 并通过构图工艺形成包括保护层 9的图形。
需要说明的是， 该步骤中形成的保护层 9可以仅仅覆盖第一 薄膜晶体管的有源层 4， 也可以不对保护层薄膜进行曝光、显影等 步骤， 直接在整个基底 1上形成保护层 9。
优选地， 在形成保护层薄膜之前还包括： 通过等离子体改性 或溅射掺杂对所形成的第一薄膜晶体管的有源层 4进行处理的步 骤。 此时， 可以进一步优化第一薄膜晶体管的有源层 4的性能。
其中， 保护层 9可以为由硅的氧化物 （SiOx ) 、 硅的氮化物 ( SiNx ) 、 铪的氧化物 （HfOx ) 、 硅的氮氧化物 （SiON ) 、 铝的 氧化物 （AlOx ) 等形成的单层或多层膜。 步骤四、 在完成上述步骤的基底 1上， 形成第二薄膜晶体管 的有源层薄膜， 并通过构图工艺形成包括第二薄膜晶体管的有源 层 5的图形。 具体形成方法与第一薄膜晶体管的有源层 4的形成 方式相同， 只是釆用的材料是不同的， 在此就不重复赘述了。
优选地， 在形成包括第二薄膜晶体管的有源层 5的图形之后 还包括： 通过等离子体改性或溅射掺杂对所形成的第二薄膜晶体 管的有源层 5 进行处理的步骤。 此时， 可以进一步优化第二薄膜 晶体管的有源层 5的性能。
步骤五、 在完成上述步骤的基底 1 上， 形成刻蚀阻挡层 6， 并刻蚀形成贯穿刻蚀阻挡层 6和保护层 9的用于使待形成的第一 薄膜晶体管的源极 71、 漏极 72和第二薄膜晶体管的源极 81、 漏 极 82分别与各自的有源层接触的源、 漏接触区。
其中， 所述刻蚀阻挡层 6可以为由硅的氧化物 （SiOx ) 、 硅 的氮化物（ SiNx )、铪的氧化物（ HfOx )、硅的氮氧化物（ SiON )、 铝的氧化物 （AlOx ) 等形成的单层或多层膜。
步骤六、 在完成上述步骤的基底 1上， 形成源漏金属层薄膜， 并通过构图工艺形成包括第一薄膜晶体管的源极 71、漏极 72和第 二薄膜晶体管的源极 81、 漏极 82的图形， 且第一薄膜晶体管的源 极 71、 漏极 72和第二薄膜晶体管的源极 81、 漏极 82分别通过各 自的源、 漏接触区与各自的有源层接触。
其中， 所述源漏金属层薄膜的材料可以是钼 （Mo ) 、 钼铌合 金 ( MoNb ) 、 铝（ A1 ) 、 铝钕合金 ( AlNd ) 、 钛（ Ti )和铜 ( Cu ) 中的一种或多种， 优选为 Mo、 A1或含 Mo、 A1的合金材料。
步骤七、 在完成上述步骤的基底 1上， 形成钝化层 10， 并形 成贯穿各电极上方的钝化层 10 的接触过孔， 以釆用金属电极 11 通过接触过孔将各电极引出。
步骤八、 将完成上述步骤的产品在真空、 氮气或氧气的环境 中进行退火， 退火的温度可以在 120。C -400。C之间， 最终形成互 补式薄膜晶体管。
本实施例的互补式薄膜晶体管的制备方法中， 在第一薄膜晶 体管的有源层 4上设有保护层 9，可以有效地避免在制备第二薄膜 晶体管的有源层 5 时， 由于两个薄膜晶体管的有源层的材料不同 而影响第一薄膜晶体管的有源层 4 的性能， 进而可以提高互补式 薄膜晶体管的性能。
需要说明的是， 上述制备方法制备的互补式薄膜晶体管的第 一薄膜晶体管和第二薄膜晶体管是底栅型薄膜晶体管。 当然， 也 可以将第一薄膜晶体管和第二薄膜晶体管制备成顶栅型的薄膜晶 体管， 其具体步骤与上述步骤大致相同， 区别在于形成各结构的 顺序不同， 例如， 制备顶栅型的第一薄膜晶体管和第二薄膜晶体 管的步骤可包括： 在基底 1 上， 通过构图工艺形成包括第一薄膜 晶体管的有源层 4以及保护层 9的图形；在完成上述步骤的基底 1 上， 通过构图工艺形成包括第二薄膜晶体管的有源层 5 的图形； 在完成上述步骤的基底 1 上， 通过构图工艺同时形成包括第一薄 膜晶体管源极 71、 漏极 72和第二薄膜晶体管的源极 81、 漏极 82 的图形； 在完成上述步骤的基底 1上， 形成栅极绝缘层 3; 在完成 上述步骤的基底 1 上， 通过构图工艺同时形成包括第一薄膜晶体 管的栅极 21和第二薄膜晶体管的栅极 22的图形； 在完成上述步 骤的基底 1上， 形成平坦化层； 在完成上述步骤的基底 1上， 形 成贯穿平坦化层和栅极绝缘层 3 的接触过孔， 所述接触过孔用于 使第一薄膜晶体管的源极 71、 漏极 72和第二薄膜晶体管的源极 81、 漏极 82分别与其各自的有源层连接。 其中， 其他步骤与制备 底栅型的第一薄膜晶体管和第二薄膜晶体管的步骤相似， 在此就 不再重复赘述了。
需要说明的是， 如图 2、 图 3所示， 第一薄膜晶体管的栅极 21和第二薄膜晶体管的栅极 22之外的栅极图形是基底 1上的其他 薄膜晶体管的栅极， 由于图中所示的只是截取的一个剖面图， 因 此所示剖面图只示出了该其他薄膜晶体管的栅极。 而且， 第一薄 膜晶体管和第二薄膜晶体管也不局限于顶栅型或底栅型结构， 也 可以是其他结构的薄膜晶体管， 在此不——描述。 实施例 2:
如图 3所示， 本实施例提供一种互补式薄膜晶体管， 其包括 第一薄膜晶体管和第二薄膜晶体管， 且第一薄膜晶体管的有源层 上方设置有保护层， 其中， 第一薄膜晶体管和第二薄膜晶体管中 的一个为 P型薄膜晶体管， 另一个为 N型薄膜晶体管。
该互补式薄膜晶体管可以由实施例 1 的方法制备， 由于第一 薄膜晶体管的有源层 4上方设置有保护层 9，从而可以避免第一薄 膜晶体管的有源层 4不受第二薄膜晶体管的有源层 5形成时对其 造成的不利影响， 进而可以提高互补式薄膜晶体管的性能。
其中， 第一薄膜晶管为 P型薄膜晶体管且第二薄膜晶体管为 N型薄膜晶体管， 或者第一薄膜晶管为 N型薄膜晶体管且第二薄 膜晶体管为 P型薄膜晶体管。 优选地， 所述 N型薄膜晶体管的有 源层中掺杂有砷、 锑、 磷中的任意一种或多种离子。 所述 P型薄 膜晶体管的有源层中掺杂有硼、 铟、 镓中的任意一种或多种离子。 此时， 可以进一步提高互补式薄膜晶体管的性能。 实施例 3:
本实施例提供一种阵列基板， 其包括上述的互补式薄膜晶体 管， 当然还包括像素电极、 公共电极等其他结构。
由于本实施例的阵列基板包括上述互补式薄膜晶体管， 故其 性能更稳定。 实施例 4:
本实施例提供一种显示装置， 其包括上述阵列基板， 该显示 装置可以为手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数 码相框、 导航仪等任何具有显示功能的产品或部件。
本实施例的显示装置中具有实施例 3 中的阵列基板， 故其性 能更好。
当然， 本实施例的显示装置中还可以包括其他常规结构， 如 电源单元、 显示驱动单元等。 而釆用的示例性实施方式， 然而本发明并不局限于此。 对于本领 域内的普通技术人员而言， 在不脱离本发明的精神和实质的情况 下， 可以做出各种变型和改进， 这些变型和改进也视为本发明的 保护范围。

Claims

权 利 要 求 书
1. 一种互补式薄膜晶体管的制备方法， 其特征在于， 包括： 通过构图工艺， 在基底上形成包括第一薄膜晶体管的有源层 以及保护层的图形， 且保护层至少位于第一薄膜晶体管的有源层 上；
在完成上述步骤的基底上， 通过构图工艺形成包括第二薄膜 晶体管的有源层的图形。
2. 根据权利要求 1所述的互补式薄膜晶体管的制备方法， 其 特征在于， 在基底上形成包括第一薄膜晶体管的有源层以及保护 层的图形的步骤包括：
在基底上依次沉积第一薄膜晶管的有源层薄膜和保护层薄 膜；
在完成上述步骤的基底上， 通过一次构图工艺， 同时形成包 括第一薄膜晶体管的有源层和保护层的图形。
3. 根据权利要求 1所述的互补式薄膜晶体管的制备方法， 其 特征在于， 在基底上形成包括第一薄膜晶体管的有源层以及保护 层的图形的步骤包括：
形成第一薄膜晶体管的有源层薄膜；
在完成上述步骤的基底上， 通过构图工艺形成包括第一薄膜 晶体管的有源层的图形；
在完成上述步骤的基底上， 形成保护层薄膜；
在完成上述步骤的基底上， 通过构图工艺形成包括保护层的 图形。
4. 根据权利要求 3所述的互补式薄膜晶体管的制备方法， 其 特征在于， 在形成保护层薄膜之前还包括：
通过等离子体改性或溅射掺杂对所形成的第一薄膜晶体管的 有源层进行处理的步骤；
和 /或，
在形成包括第二薄膜晶体管的有源层的图形之后还包括： 通过等离子体改性或溅射掺杂对所形成的第二薄膜晶体管的 有源层进行处理的步骤。
5. 根据权利要求 1至 4中任意一项所述的互补式薄膜晶体管 的制备方法， 其特征在于， 所述第一薄膜晶体管的有源层釆用第 一半导体材料形成， 所述第二薄膜晶体管的有源层釆用第二半导 体材料形成， 其中， 所述第一半导体材料为 P型半导体材料且第 二半导体材料为 N型半导体材料， 或者所述第一半导体材料为 N 型半导体材料且第二半导体材料为 P型半导体材料。
6. 根据权利要求 1至 5中任意一项所述的互补式薄膜晶体管 的制备方法， 其特征在于， 在基底上形成包括第一薄膜晶体管的 有源层以及保护层的图形之前还包括：
在基底上形成包括第一薄膜晶体管的栅极和第二薄膜晶体管 的极极的图形；
在完成上述步骤的基底上， 形成栅极绝缘层。
7. 根据权利要求 6所述的互补式薄膜晶体管的制备方法， 其 特征在于， 在形成包括第二薄膜晶体管的有源层的图形之后还包 括：
形成刻蚀阻挡层， 且形成贯穿所述刻蚀阻挡层和所述保护层 的用于使待形成的第一薄膜晶体管的源、 漏极和第二薄膜晶体管 的源、 漏极分别与各自的有源层接触的源、 漏接触区；
在完成上述步骤的基底上， 通过构图工艺形成包括第一薄膜 晶体管的源、 漏极和第二薄膜晶体管的源、 漏极的图形， 且第一 薄膜晶体管的源、 漏极和第二薄膜晶体管的源、 漏极分别通过各 自的源、 漏接触区与各自的有源层接触。
8. 根据权利要求 1至 7中任意一项所述的互补式薄膜晶体管 的制备方法， 其特征在于， 所述保护层为由硅的氧化物、 硅的氮 化物、 铪的氧化物、 硅的氮氧化物、 铝的氧化物中的一种或多种 形成的单层或多层膜。
9. 一种互补式薄膜晶体管， 包括第一薄膜晶体管和第二薄膜 晶体管， 且第一薄膜晶体管的有源层上方设置有保护层， 用于保 护第一薄膜晶体管的有源层不受第二薄膜晶体管的有源层形成时 的影响。
10. 根据权利要求 9所述的互补式薄膜晶体管， 其特征在于， 所述第一薄膜晶体管和第二薄膜晶体管中的一个为 P型薄膜晶体 管， 另一个为 N型薄膜晶体管， 所述 N型薄膜晶体管的有源层中 掺杂有砷、 锑、 磷中的任意一种或多种离子， 所述 P型薄膜晶体 管的有源层中掺杂有硼、 铟、 镓中的任意一种或多种离子。
11. 根据权利要求 9或 10所述的互补式薄膜晶体管， 其特征 在于， 所述保护层为由硅的氧化物、 硅的氮化物、 铪的氧化物、 硅的氮氧化物、 铝的氧化物中的一种或多种形成的单层或多层膜。
12. 一种阵列基板， 包括如权利要求 9至 11中的任意一项所 述的互补式薄膜晶体管。
13. 一种显示装置， 包括如权利要求 12所述的阵列基板。
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CN103579115B (zh) * 2013-11-11 2015-11-25 京东方科技集团股份有限公司 互补式薄膜晶体管及其制备方法、阵列基板、显示装置
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US9935127B2 (en) 2015-07-29 2018-04-03 Wuhan China Star Optoelectronics Technology Co., Ltd. Control circuit of thin film transistor
CN105742308B (zh) * 2016-02-29 2019-09-13 深圳市华星光电技术有限公司 互补型薄膜晶体管及其制造方法
KR102676341B1 (ko) 2016-12-30 2024-06-17 엘지디스플레이 주식회사 박막 트랜지스터, 그의 제조방법, 및 그를 포함한 표시장치
CN106847837B (zh) * 2017-04-26 2020-01-10 京东方科技集团股份有限公司 一种互补型薄膜晶体管及其制作方法和阵列基板
US10290666B2 (en) * 2017-05-12 2019-05-14 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd Thin film transistor (TFT) array substrates and manufacturing methods thereof
CN112530978B (zh) * 2020-12-01 2024-02-13 京东方科技集团股份有限公司 开关器件结构及其制备方法、薄膜晶体管膜层、显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05145073A (ja) * 1991-11-22 1993-06-11 Seiko Epson Corp 相補型薄膜トランジスタ
CN1312958A (zh) * 1998-06-19 2001-09-12 薄膜电子有限公司 集成无机/有机互补薄膜晶体管电路及其制造方法
CN101150092A (zh) * 2007-11-08 2008-03-26 友达光电股份有限公司 互补式金属氧化物半导体薄膜晶体管的制造方法
CN103579115A (zh) * 2013-11-11 2014-02-12 京东方科技集团股份有限公司 互补式薄膜晶体管及其制备方法、阵列基板、显示装置
CN103715147A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 互补型薄膜晶体管驱动背板及其制作方法、显示面板
CN103715196A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4420032B2 (ja) * 2007-01-31 2010-02-24 ソニー株式会社 薄膜半導体装置の製造方法
US8598025B2 (en) * 2010-11-15 2013-12-03 Varian Semiconductor Equipment Associates, Inc. Doping of planar or three-dimensional structures at elevated temperatures

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05145073A (ja) * 1991-11-22 1993-06-11 Seiko Epson Corp 相補型薄膜トランジスタ
CN1312958A (zh) * 1998-06-19 2001-09-12 薄膜电子有限公司 集成无机/有机互补薄膜晶体管电路及其制造方法
CN101150092A (zh) * 2007-11-08 2008-03-26 友达光电股份有限公司 互补式金属氧化物半导体薄膜晶体管的制造方法
CN103579115A (zh) * 2013-11-11 2014-02-12 京东方科技集团股份有限公司 互补式薄膜晶体管及其制备方法、阵列基板、显示装置
CN103715147A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 互补型薄膜晶体管驱动背板及其制作方法、显示面板
CN103715196A (zh) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

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