CN106298954B - 薄膜晶体管及其制作方法 - Google Patents

薄膜晶体管及其制作方法 Download PDF

Info

Publication number
CN106298954B
CN106298954B CN201610778598.6A CN201610778598A CN106298954B CN 106298954 B CN106298954 B CN 106298954B CN 201610778598 A CN201610778598 A CN 201610778598A CN 106298954 B CN106298954 B CN 106298954B
Authority
CN
China
Prior art keywords
layer
etching barrier
active layer
electrode
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610778598.6A
Other languages
English (en)
Other versions
CN106298954A (zh
Inventor
翟玉浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201610778598.6A priority Critical patent/CN106298954B/zh
Priority to PCT/CN2016/105433 priority patent/WO2018040287A1/zh
Priority to US15/324,702 priority patent/US10411132B2/en
Publication of CN106298954A publication Critical patent/CN106298954A/zh
Application granted granted Critical
Publication of CN106298954B publication Critical patent/CN106298954B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开了一种薄膜晶体管，其中，第一防损伤层一部分所述薄膜晶体管的有源层和源极之间，所述第一防损伤层剩余部分设在所述有源层和漏极之间。本发明的薄膜晶体管结构简单，通过在薄膜晶体管的有源层和源极之间设有第一防损伤层及薄膜晶体管的有源层和漏极之间设有第一防损伤层，能够有效的减小沟道长度，并且降低源极和栅极之间的寄生电容和降低漏极和栅极之间的寄生电容。

Description

薄膜晶体管及其制作方法
技术领域
本发明涉及一种，特别涉及一种薄膜晶体管及其制作方法。
背景技术
金属氧化物薄膜对酸非常敏感，即便是弱酸也能快速腐蚀氧化物半导体。因此常采用刻蚀阻挡型IGZO-TFT的结构，在金属氧化物上沉积一层刻蚀阻挡层，可以在制备源漏电极时保护IGZO层不被破坏，从而提高TFT基板的性能。但是需要一次额外的光刻工艺，增加了金属氧化物IGZO TFT的制作工艺流程。另一方面，传统TFT生产工艺中的曝光未对准和刻蚀偏差等影响，刻蚀阻挡层并不能做到很短，不可避免的限制了沟道的长度，从而导致增加了器件的寄生电容。
为解决上述问题，有必要提出一种新的薄膜晶体管。
发明内容
本发明提出了一种新的薄膜晶体管及其制作方法，本发明的薄膜晶体管结构简单，能够有效的减小沟道长度，并且降低源极(S)和栅极(Gate，简称G)之间的寄生电容和降低漏极(D)和栅极(G)之间的寄生电容，本发明的薄膜晶体管的制作方法简单，制备过程简单及能够方便地生产出本发明的薄膜晶体管。
为解决达到上述目的，本发明提出了一种新的薄膜晶体管及其制备方法，其中，所述第一防损伤层一部分设在所述薄膜晶体管的有源层和源极之间，所述第一防损伤层剩余部分设在所述有源层和漏极之间；
所述有源层设置在薄膜晶体管的栅极绝缘层上，所述有源层的上方设有第一刻蚀阻挡层，所述有源层的长度小于所述栅极绝缘层的长度，所述有源层的长度大于所述第一刻蚀阻挡层的长度；
所述薄膜晶体管的栅极的两侧分别设有第二刻蚀阻挡层，所述第二刻蚀阻挡层与所述有源层之间设有第二防损伤层；
所述第一防损伤层和所述第一刻蚀阻挡层完全覆盖所述有源层的表面；所述源极、所述漏极与所述第一防损伤层均未延伸至所述第一刻蚀阻挡层和所述第二刻蚀阻挡层的表面。
如上所述的薄膜晶体管，其中，所述第一防损伤层和第二防损伤层均采用ITO制成。
如上所述的薄膜晶体管，其中，所述薄膜晶体管还包括玻璃层；所述栅极设置在所述玻璃层的上方；所述栅极绝缘层设置在所述栅极的上方；
所述有源层的一侧设有所述源极，所述有源层的另一侧设有所述漏极，所述第一防损伤层一部分设在所述有源层和源极之间，所述第一防损伤层剩余部分设在所述有源层和漏极之间；
两根像素电极，所述源极远离所述有源层的一侧设有一根所述像素电极，所述漏极远离所述有源层的一侧设有另一根所述像素电极；所述像素电极和所述玻璃层之间设有所述第二刻蚀阻挡层；
两个所述第二刻蚀阻挡层与所述有源层之间分别设有第二防损伤层；
所述第一刻蚀阻挡层的上方设有保护层。
如上所述的薄膜晶体管，其中，所述栅极采用金属铝和钼复合而成或采用金属铝和金属铜复合而成，所述源极和所述漏极均采用金属铝和钼复合而成或采用金属铜或金属钼复合而成。
如上所述的薄膜晶体管，其中，所述栅极绝缘层、所述第一刻蚀阻挡层和所述第二刻蚀阻挡层均采用二氧化硅或氧化铝制成。
如上所述的薄膜晶体管，其中，所述像素电极采用ITO制成。
本发明还提出了一种薄膜晶体管的制作方法，所述制作方法包括以下步骤：
S1)在玻璃层的上方形成栅极，在所述栅极的上方形成栅极绝缘层，在所述栅极绝缘层上方形成所述有源层，所述有源层的长度小于所述栅极绝缘层的长度；
S2)所述有源层上方形成第一刻蚀阻挡层，所述有源层的长度大于所述第一刻蚀阻挡层的长度；在所述玻璃层的上方及所述栅极的两侧分别形成第二刻蚀阻挡层；
形成第一防损伤层和第二防损伤层；所述第一防损伤层和所述第一刻蚀阻挡层完全覆盖所述有源层的表面，且所述第一防损伤层未延伸至所述第一刻蚀阻挡层和所述第二刻蚀阻挡层的表面；所述第二刻蚀阻挡层与所述有源层之间形成第二防损伤层；
S3)所述有源层的一侧形成所述源极，所述有源层的另一侧形成漏极，所述第一防损伤层一部分在所述有源层和所述源极之间，所述第一防损伤层剩余部分在所述有源层和所述漏极之间；所述源极、所述漏极均未延伸至所述第一刻蚀阻挡层和所述第二刻蚀阻挡层的表面；
形成两根像素电极，其中，所述源极远离所述有源层的一侧形成一根所述像素电极，所述漏极远离所述有源层的一侧形成另一根所述像素电极；所述像素电极和所述玻璃层之间有所述第二刻蚀阻挡层；
S4)所述第一刻蚀阻挡层之上形成有保护层。
如上所述的薄膜晶体管的制作方法，其中，所述第一防损伤层和所述第二防损伤层均采用ITO制成。
如上所述的薄膜晶体管的制作方法，其中，所述防损伤层和所述第二防损伤层的形成过程包括以下步骤：
A)在第一刻蚀阻挡层上形成有光刻胶，所述第二刻蚀阻挡层上形成有所述光刻胶，所述第一刻蚀阻挡层上的所述光刻胶上形成所述第一防损伤层，所述第二刻蚀阻挡层上的所述光刻胶上形成所述第二防损伤层；所述第一防损伤层一部分在所述有源层和所述源极之间，所述第一防损伤层剩余部分在所述有源层和所述漏极之间，所述第二刻蚀阻挡层与所述有源层之间形成所述第二防损伤层；
B)去除所述第一刻蚀阻挡层上的所述光刻胶及所述光刻胶上的所述第一防损伤层，去除所述第二刻蚀阻挡层上的所述光刻胶及所述光刻胶上的所述第二防损伤层；
C)在200℃～300℃的温度下对所述第一防损伤层和所述第二防损伤层进行退火。
本发明的薄膜晶体管结构简单，通过将第一防损伤层的一部分设在薄膜晶体管的有源层和源极之间，及第一防损伤层的剩余部分设薄膜晶体管的有源层和漏极之间，第二刻蚀阻挡层与有源层之间设有第二防损伤层，能够有效的减小沟道长度，并且降低源极(S)和栅极(Gate，简称G)之间的寄生电容和降低漏极(D)和栅极(G)之间的寄生电容。本发明的薄膜晶体管的制作方法操作步骤简单，通过本发明的薄膜晶体管的制作方法能够制造出沟道长度短的薄膜晶体管。
附图说明
在此描述的附图仅用于解释目的，而不意图以任何方式来限制本发明公开的范围。另外，图中的各部件的形状和比例尺寸等仅为示意性的，用于帮助对本发明的理解，并不是具体限定本发明各部件的形状和比例尺寸。本领域的技术人员在本发明的教导下，可以根据具体情况选择各种可能的形状和比例尺寸来实施本发明。
图1为本发明的薄膜晶体管的结构示意图；
图2为本发明的薄膜晶体管的制造过程(一)的结构示意图；
图3为本发明的薄膜晶体管的制造过程(二)的结构示意图；
图4为本发明的薄膜晶体管的制造过程(三)的结构示意图；
图5为本发明的薄膜晶体管的制造过程(四)的结构示意图；
图6为本发明的薄膜晶体管的制造过程(五)的结构示意图。
附图标记说明：
10-有源层；20-源极；30-第一防损伤层；31-第二防损伤层；40-漏极；60-玻璃层；70-栅极；80-栅极绝缘层；90-第一刻蚀阻挡层；91-像素电极；92-第二刻蚀阻挡层；93-保护层；94-光刻胶。
具体实施方式
结合附图和本发明具体实施方式的描述，能够更加清楚地了解本发明的细节。但是，在此描述的本发明的具体实施方式，仅用于解释本发明的目的，而不能以任何方式理解成是对本发明的限制。在本发明的教导下，技术人员可以构想基于本发明的任意可能的变形，这些都应被视为属于本发明的范围，下面将结合附图对本发明作进一步说明。
图1至图6分别为本发明的薄膜晶体管的结构示意图、薄膜晶体管的制造过程(一)的结构示意图、薄膜晶体管的制造过程(二)的结构示意图、薄膜晶体管的制造过程(三)的结构示意图、薄膜晶体管的制造过程(四)的结构示意图和薄膜晶体管的制造过程(五)的结构示意图。
实施方式一
如图1所示，本发明提供了一种薄膜晶体管，第一防损伤层30一部分设在薄膜晶体管的有源层10和源极20之间，第一防损伤层30剩余部分设在有源层10和漏极40之间。
具体地，本发明的第一防损伤层30和第二防损伤层31均采用掺锡氧化铟(后简称ITO)制成，当然也可采用其他起到相同作用的材料，在此不做具体限制。
本发明的薄膜晶体管通过将第一防损伤层30的一部分设在有源层10和源极20之间，第一防损伤层30的剩余部分设在有源层10和漏极40之间，能够有效的减小沟道长度，并且降低源极20(S)和薄膜晶体管的栅极70(G)之间的寄生电容和降低漏极40(D)和栅极70(G)之间的寄生电容。
薄膜晶体管为现有技术，其种类很多，本发明采用其中一种现有的薄膜晶体管，构成本发明的薄膜晶体管，即本发明薄膜晶体管的一种具体实施方式，其结构如下所示：本发明的薄膜晶体管包括玻璃层60、栅极70、栅极绝缘层80、有源层10、第一刻蚀阻挡层90、源极20、第一防损伤层30、漏极40、像素电极91、第二刻蚀阻挡层92和保护层93。其中，栅极70设置在玻璃层60的上方，栅极绝缘层80设置在栅极70的上方，有源层10设置在栅极绝缘层80的上方，且有源层10的上方设置有第一刻蚀阻挡层90，有源层10的长度小于栅极绝缘层80的长度，有源层10的长度大于所述第一刻蚀阻挡层90的长度，在有源层10的两侧分别设有源层20和漏极40，有源层10和源极20之间设有本发明的第一防损伤层30，有源层10和漏极40之间设有本发明的第一防损伤层30，源极20远离有源层10的一侧设有像素电极91，漏极40远离有源层10的一侧也设有像素电极91，栅极70的两侧分别设有第二刻蚀阻挡层92，第二刻蚀阻挡层92位于玻璃层60和像素电极91之间，第一刻蚀阻挡层90的上方设有保护层93。进一步地，在本发明中，两个第二刻蚀阻挡层92与有源层10之间分别设有第二防损伤层31。当然，薄膜晶体管也可采用其他结构，但是在有源层10和源极20之间设有第一防损伤层30，有源层10和漏极40之间设有第一防损伤层30都视为本发明的保护范围。
具体地，在本发明中第二防损伤层31与第一防损伤层30均采用ITO制成，在本发明中，第一防损伤层30和第二防损伤层31是在同样材料构成的防损伤层(后简称为该防损伤层)，该防损伤层经过刻蚀之后将该防损伤层的中间断开，从而形成本发明的第一防损伤层30和第二防损伤层31。
具体地，在本发明中，栅极70采用金属铝和钼复合而成(简称Al/Mo)或采用金属铝和金属铜复合而成(简称Al/Cu)，当然栅极70也可采用其他材料，在此不做具体限制；本发明的薄膜晶体管的源极和漏极(简称源漏极，后用S/D表示)均采用金属铝和钼复合而成(Al/Mo材料)或采用金属铜或金属钼复合而成(Cu/Mo材料)，当然也可以采用其他复合金属材料，在此不做具体限制。
具体地，在本发明中，栅极绝缘层80(简称GI层)采用二氧化硅(SiO2)或氧化铝(Al2O3)制成，当然也可采用其他材料，在此不做具体限制，进一步的，本发明中第一刻蚀阻挡层90和第二刻蚀阻挡层92采用相同的材料制成，后统称为刻蚀阻挡层(ESL层)，在本发明中，第一刻蚀阻挡层91和第二刻蚀阻挡层92是在同一刻蚀阻挡层(后简称为“该刻蚀阻挡层”)，该刻蚀阻挡层经过刻蚀之后在该刻蚀阻挡层的中间断开，从而形成本发明的第一刻蚀阻挡层91和第二刻蚀阻挡层92，ESL层采用SiO2或Al2O3制成，当然也可采用其他材料，在此不做具体限制。
进一步地，本发明的薄膜晶体管的像素电极91采用ITO制成，当然，也可采用其他材料制成，在此不做具体限制。
本发明的第一防损伤层30一部分设在薄膜晶体管的有源层10和源极20之间，第一防损伤层30剩余部分设在有源层10和漏极40之间，本发明自对准结构的ITO沉积在a-IGZO的之上，作为有源层与源极及有源层与漏极之间的第一防损伤层和接触层，制备出了短沟道的a-IGZOTFT器件。并且由于源漏极并没有延伸到刻蚀阻挡层的表面，减少了S/D电极和Gate电极之间的正对面积，从而降低了器件的寄生电容，自对准结构的ITO作为第一防损伤层和接触层，能够有效减少沟道长度1-5μm，并且降低S/D电极和Gate之间的寄生电容。
实施方式二
本发明还提供了一种薄膜晶体管的制作方法，该薄膜晶体管的制作方法包括以下步骤：
S1)在玻璃层60的上方形成栅极70，在栅极70的上方形成栅极绝缘层80，在栅极绝缘层80上方形成有源层10，所述有源层10的长度小于栅极绝缘层80的长度；
S2)有源层10上方形成第一刻蚀阻挡层90，有源层10的长度大于第一刻蚀阻挡层90的长度；在玻璃层60的上方及栅极70的两侧分别形成第二刻蚀阻挡层92；
形成第一防损伤层30和第二防损伤层31；所述第一防损伤层30和所述第一刻蚀阻挡90层完全覆盖所述有源层10的表面，且所述第一防损伤层30未延伸至所述第一刻蚀阻挡层90和所述第二刻蚀阻挡层92的表面，所述第二刻蚀阻挡层92与所述有源层10之间形成第二防损伤层31；
S3)有源层10的一侧形成源极20，有源层10的另一侧形成漏极40，第一防损伤层30一部分在有源层10和源极20之间，第一防损伤层30剩余部分在有源层10和漏极40之间；源极20、漏极40均未延伸至第一刻蚀阻挡层90和第二刻蚀阻挡层92的表面；
形成两根像素电极91，其中，源极20远离有源层10的一侧形成一根像素电极91，漏极40远离有源层10的一侧形成另一根像素电极91；像素电极91和玻璃层60之间有第二刻蚀阻挡层92；
S4)所述第一刻蚀阻挡层90之上形成有保护层93。
具体地，在本发明中第二防损伤层31与第一防损伤层30均采用ITO制成。
进一步地，本发明的第一防损伤层30和第二防损伤层31的形成过程包括以下步骤：
A)在第一刻蚀阻挡层90上形成有光刻胶94(PR)，第二刻蚀阻挡层93上形成有光刻胶94，光刻胶94上形成该防损伤层，第一防损伤层30一部分形成在有源层10和源极20之间，第一防损伤层30剩余部分形成在有源层10和漏极40之间，第二刻蚀阻挡层92与有源层10之间形成第二防损伤层31；
B)去除第一刻蚀阻挡层90上的光刻胶94及光刻胶94上的第一防损伤层30，去除第二刻蚀阻挡层92上的光刻胶94及光刻胶94上的第一防损伤层30；
C)在200℃～300℃的温度下对第一防损伤层30和第二防损伤层31进行退火。
具体地，在本发明中，栅极70采用金属铝和钼复合而成(简称Al/Mo)或采用金属铝和金属铜复合而成(简称Al/Cu)，当然栅极70也可采用其他材料，在此不做具体限制；本发明的薄膜晶体管的源极和漏极(简称源漏极)均采用金属铝和钼复合而成(Al/Mo材料)或采用金属铜或金属钼复合而成(Cu/Mo材料)，当然也可以采用其他复合金属材料，在此不做具体限制。
具体地，在本发明中，栅极绝缘层80(简称GI层)采用二氧化硅(SiO2)或氧化铝(Al2O3)制成，当然也可采用其他材料，在此不做具体限制，进一步的，本发明中第一刻蚀阻挡层90和第二刻蚀阻挡层92采用相同的材料制成，统称为刻蚀阻挡层(ESL层)，ESL层采用SiO2或Al2O3制成，当然也可采用其他材料，在此不做具体限制。
进一步地，本发明的薄膜晶体管的像素电极91采用ITO制成，当然，也可采用其他材料制成，在此不做具体限制。
在一具体地实施方式中，本发明的薄膜晶体管的具体制作方法如下：在玻璃层60的上表面上采用PVD的沉积方式形成栅极70(也可称为金属底栅层)，栅极70的材料多为Al/Mo层，但不限定，亦可为其他Al/Cu材料或其他复合金属，之后在栅极70上采用PECVD的方式沉积SiO2(或者Al2O3等材料)作为栅极绝缘层80(GI层)，在栅极绝缘层80上采用PVD方式沉积70nm的a-IGZO作为有源层10(简称a-IGZO层)，即得到薄膜晶体管的制造过程(一)的结构，如图2所示；涂布光刻胶，按照设计的光罩进行曝光和显影，把多余的光刻胶(简称PR)除去之后，然后采用Half-Tone的方式先刻蚀a-IGZO和GI层，栅极70采用湿刻法刻蚀形成图案，并将PR进行灰化，草酸刻蚀a-IGZO作为有源层10，即得到薄膜晶体管的制造过程(二)的结构，也即如图3所示；采用PECVD方式在有源层10上方沉积SiO2(或者Al2O3等材料)作为第一刻蚀阻挡层90，采用PECVD方式在玻璃层60上方沉积SiO2(或者Al2O3等材料)作为第二刻蚀阻挡层92，且在栅极70的两侧分别形成第二刻蚀阻挡层92，第二刻蚀阻挡层92位于玻璃层60和像素电极91之间，在本发明中第一刻蚀阻挡层90和第二刻蚀阻挡层92采用相同的材料及相同的方式制成，在后面统称为刻蚀阻挡层(简称ESL)，并且将ESL刻蚀成图形，ESL层刻蚀之前需要涂布光刻胶(PR)曝光显影，之后对ESL进行干刻挖孔形成图形，正常情况干刻之后需要把PR进行剥离掉，但是本发明中光刻胶并没有剥离，而是在光刻胶上面沉积70nmITO，且如图1所示，在有源层10的两侧上沉积ITO，有源层10上表面的第一刻蚀阻挡层90以外的区域上沉积ITO以及两个第二刻蚀阻挡层92与有源层10之间分别设有ITO，即得到薄膜晶体管的制造过程(三)的结构，如图4所示；然后去除PR及PR表面上的ITO(也即去除多余的ITO)，在200℃～300℃的温度下对ITO退火，使ITO晶化，形成保护a-IGZO导电接触孔，从而形成本发明的第一防损伤层30和第二防损伤层31，即得到薄膜晶体管的制造过程(四)的结构，如图5所示；采用ITO作为像素电极91，Mo/Cu(亦可为其他Al/Mo材料或其复合金属)作为源漏极，同样采用Half-Tone的方式形成图案，即得到薄膜晶体管的制造过程(五)的结构，如图6所示；在第一刻蚀阻挡层90上方沉积200nmSi3N4(或者SiO2，Al2O3等材料)作为保护层93，保护层93的长度与玻璃层60的长度相同，且与玻璃层60的上表面的两端相接触，即得到本发明的薄膜晶体管，其结构如图1所示。
本发明的薄膜晶体管的制备方法简单，能够有效地制备出本发明的薄膜晶体管。
虽然已经参考优选实施例对本发明进行了描述，但在不脱离本发明的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本发明并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (9)

1.一种薄膜晶体管，其特征在于，第一防损伤层一部分设在所述薄膜晶体管的有源层和源极之间，所述第一防损伤层剩余部分设在所述有源层和漏极之间；
所述有源层设置在薄膜晶体管的栅极绝缘层上，所述有源层的上方设有第一刻蚀阻挡层，所述有源层的长度小于所述栅极绝缘层的长度，所述有源层的长度大于所述第一刻蚀阻挡层的长度；
所述薄膜晶体管的栅极的两侧分别设有第二刻蚀阻挡层，所述第二刻蚀阻挡层与所述有源层之间设有第二防损伤层；
所述第一防损伤层和所述第一刻蚀阻挡层完全覆盖所述有源层的表面；所述源极、所述漏极与所述第一防损伤层均未延伸至所述第一刻蚀阻挡层和所述第二刻蚀阻挡层的表面。
2.如权利要求1所述的薄膜晶体管，其特征在于，所述第一防损伤层和第二防损伤层均采用ITO制成。
3.如权利要求1或2所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括玻璃层；所述栅极设置在所述玻璃层的上方；所述栅极绝缘层设置在所述栅极的上方；
所述有源层的一侧设有所述源极，所述有源层的另一侧设有所述漏极，所述第一防损伤层一部分设在所述有源层和源极之间，所述第一防损伤层剩余部分设在所述有源层和漏极之间；
两根像素电极，所述源极远离所述有源层的一侧设有一根所述像素电极，所述漏极远离所述有源层的一侧设有另一根所述像素电极；所述像素电极和所述玻璃层之间设有所述第二刻蚀阻挡层；
所述第一刻蚀阻挡层的上方设保护层。
4.如权利要求3所述的薄膜晶体管，其特征在于，所述栅极采用金属铝和钼复合而成或采用金属铝和金属铜复合而成，所述源极和所述漏极均采用金属铝和钼复合而成或采用金属铜或金属钼复合而成。
5.如权利要求3所述的薄膜晶体管，其特征在于，所述栅极绝缘层、所述第一刻蚀阻挡层和所述第二刻蚀阻挡层均采用二氧化硅或氧化铝制成。
6.如权利要求3所述的薄膜晶体管，其特征在于，所述像素电极采用ITO制成。
7.一种薄膜晶体管的制作方法，其特征在于，所述制作方法包括以下步骤：
S1)在玻璃层的上方形成栅极，在所述栅极的上方形成栅极绝缘层，在所述栅极绝缘层上方形成有源层，所述有源层的长度小于所述栅极绝缘层的长度；
S2)所述有源层上方形成第一刻蚀阻挡层，所述有源层的长度大于所述第一刻蚀阻挡层的长度；在所述玻璃层的上方及所述栅极的两侧分别形成第二刻蚀阻挡层；
形成第一防损伤层和第二防损伤层；所述第一防损伤层和所述第一刻蚀阻挡层完全覆盖所述有源层的表面，且所述第一防损伤层未延伸至所述第一刻蚀阻挡层和所述第二刻蚀阻挡层的表面，所述第二刻蚀阻挡层与所述有源层之间形成所述第二防损伤层；
S3)所述有源层的一侧形成源极，所述有源层的另一侧形成漏极，所述第一防损伤层一部分在所述有源层和所述源极之间，所述第一防损伤层剩余部分在所述有源层和所述漏极之间；所述源极、所述漏极均未延伸至所述第一刻蚀阻挡层和所述第二刻蚀阻挡层的表面；
形成两根像素电极，其中，所述源极远离所述有源层的一侧形成一根所述像素电极，所述漏极远离所述有源层的一侧形成另一根所述像素电极；所述像素电极和所述玻璃层之间有所述第二刻蚀阻挡层；
S4)所述第一刻蚀阻挡层之上形成保护层。
8.如权利要求7所述的薄膜晶体管的制作方法，其特征在于，所述第一防损伤层和所述第二防损伤层均采用ITO制成。
9.如权利要求8所述的薄膜晶体管的制作方法，其特征在于，所述第一防损伤层和所述第二防损伤层的形成过程包括以下步骤：
A)在所述第一刻蚀阻挡层上形成有光刻胶，所述第二刻蚀阻挡层形成有所述光刻胶；所述第一刻蚀阻挡层上的所述光刻胶上形成所述第一防损伤层，所述第二刻蚀阻挡层上的所述光刻胶上形成所述第二防损伤层；所述第一防损伤层一部分形成在所述有源层和待形成的所述源极之间，所述第一防损伤层剩余部分形成在所述有源层和待形成的所述漏极之间，所述第二刻蚀阻挡层与所述有源层之间形成所述第二防损伤层；
B)去除所述第一刻蚀阻挡层上的所述光刻胶及所述光刻胶上的所述第一防损伤层，去除所述第二刻蚀阻挡层上的所述光刻胶及所述光刻胶上的所述第二防损伤层；
C)在200℃～300℃的温度下对所述第一防损伤层和所述第二防损伤层进行退火。
CN201610778598.6A 2016-08-31 2016-08-31 薄膜晶体管及其制作方法 Active CN106298954B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201610778598.6A CN106298954B (zh) 2016-08-31 2016-08-31 薄膜晶体管及其制作方法
PCT/CN2016/105433 WO2018040287A1 (zh) 2016-08-31 2016-11-11 薄膜晶体管及其制作方法
US15/324,702 US10411132B2 (en) 2016-08-31 2016-11-11 Thin film transistor and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610778598.6A CN106298954B (zh) 2016-08-31 2016-08-31 薄膜晶体管及其制作方法

Publications (2)

Publication Number Publication Date
CN106298954A CN106298954A (zh) 2017-01-04
CN106298954B true CN106298954B (zh) 2020-02-04

Family

ID=57672245

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610778598.6A Active CN106298954B (zh) 2016-08-31 2016-08-31 薄膜晶体管及其制作方法

Country Status (3)

Country Link
US (1) US10411132B2 (zh)
CN (1) CN106298954B (zh)
WO (1) WO2018040287A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298954B (zh) * 2016-08-31 2020-02-04 深圳市华星光电技术有限公司 薄膜晶体管及其制作方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202940240U (zh) * 2012-12-13 2013-05-15 京东方科技集团股份有限公司 一种阵列基板和显示装置
CN103474471A (zh) * 2013-08-29 2013-12-25 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2530990B2 (ja) * 1992-10-15 1996-09-04 富士通株式会社 薄膜トランジスタ・マトリクスの製造方法
TW373114B (en) * 1996-08-05 1999-11-01 Sharp Kk Liquid crystal display device
KR100661725B1 (ko) * 2004-12-30 2006-12-26 엘지.필립스 엘시디 주식회사 박막 트랜지스터 어레이 기판 및 그 제조 방법
KR101279324B1 (ko) * 2006-06-26 2013-06-26 엘지디스플레이 주식회사 액티브 매트릭스 유기전계발광소자 및 그 제조방법
KR20080030799A (ko) * 2006-10-02 2008-04-07 삼성전자주식회사 박막 트랜지스터 기판
JP2010123758A (ja) * 2008-11-19 2010-06-03 Nec Corp 薄膜デバイス及びその製造方法
JP5743064B2 (ja) * 2011-02-17 2015-07-01 株式会社Ｊｏｌｅｄ 薄膜トランジスタおよびその製造方法、並びに表示装置
KR20120124126A (ko) * 2011-05-03 2012-11-13 삼성디스플레이 주식회사 산화물 반도체 소자, 산화물 반도체 소자의 제조 방법 및 산화물 반도체소자를 포함하는 표시 장치
CN102646699B (zh) * 2012-01-13 2014-12-10 京东方科技集团股份有限公司 一种氧化物薄膜晶体管及其制备方法
US9054204B2 (en) * 2012-01-20 2015-06-09 Sony Corporation Thin-film transistor, method of manufacturing the same, display unit, and electronic apparatus
TWI492389B (zh) * 2012-07-13 2015-07-11 Au Optronics Corp 畫素結構及畫素結構的製作方法
CN103489921B (zh) * 2013-09-29 2016-02-17 合肥京东方光电科技有限公司 一种薄膜晶体管及其制造方法、阵列基板及显示装置
JP6111458B2 (ja) * 2013-03-28 2017-04-12 株式会社Ｊｏｌｅｄ 半導体装置、表示装置および電子機器
CN105161519B (zh) * 2015-08-20 2018-03-27 京东方科技集团股份有限公司 薄膜晶体管及制作方法、阵列基板及制作方法和显示装置
CN105789327B (zh) * 2016-05-17 2019-05-03 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN106298954B (zh) * 2016-08-31 2020-02-04 深圳市华星光电技术有限公司 薄膜晶体管及其制作方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202940240U (zh) * 2012-12-13 2013-05-15 京东方科技集团股份有限公司 一种阵列基板和显示装置
CN103474471A (zh) * 2013-08-29 2013-12-25 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置

Also Published As

Publication number Publication date
US20180182896A1 (en) 2018-06-28
WO2018040287A1 (zh) 2018-03-08
CN106298954A (zh) 2017-01-04
US10411132B2 (en) 2019-09-10

Similar Documents

Publication Publication Date Title
JP6078063B2 (ja) 薄膜トランジスタデバイスの製造方法
US20150340455A1 (en) Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device
CN109065551B (zh) Tft阵列基板的制造方法及tft阵列基板
US20180114854A1 (en) Metal oxide thin film transistor and method of preparing the same
TW201611298A (zh) 雙薄膜電晶體及其製造方法
KR20150004536A (ko) 박막 트랜지스터를 포함하는 표시 기판 및 이의 제조 방법
US20160336359A1 (en) Thin film transistor device, manufacturing method thereof, and display apparatus
KR102232539B1 (ko) 박막 트랜지스터, 이를 포함하는 표시 기판 및 박막 트랜지스터의 제조 방법
WO2017028493A1 (zh) 薄膜晶体管及其制作方法、显示器件
US20160043229A1 (en) Display device and method for manufacturing the same
WO2021026990A1 (zh) 一种阵列基板及其制作方法
TWI459477B (zh) 畫素結構及其製作方法
WO2012169388A1 (ja) Ｔｆｔ基板およびその製造方法
US20180130830A1 (en) Ltps array substrate and method for producing the same
CN106298954B (zh) 薄膜晶体管及其制作方法
US9178024B2 (en) Thin film transistor display panel and manufacturing method thereof
CN111029346A (zh) 一种显示面板及其制作方法及电子设备
US10497724B2 (en) Manufacturing method of a thin film transistor and manufacturing method of an array substrate
KR102086626B1 (ko) 자기 정렬 박막 트랜지스터 및 그 제조 방법
US10007175B2 (en) Mask and method for manufacturing thin film transistor using the same
US10600692B2 (en) Semiconductor device
US10204942B1 (en) Method for manufacturing top-gated thin film transistors
KR101813719B1 (ko) 박막트랜지스터 어레이 기판의 제조 방법
US7651876B2 (en) Semiconductor structures and method for fabricating the same
KR20160084923A (ko) 박막 트랜지스터 기판 및 그 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant