WO2015007052A1 - Goa电路、阵列基板、显示装置及驱动方法 - Google Patents

Goa电路、阵列基板、显示装置及驱动方法 Download PDF

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Publication number
WO2015007052A1
WO2015007052A1 PCT/CN2013/089480 CN2013089480W WO2015007052A1 WO 2015007052 A1 WO2015007052 A1 WO 2015007052A1 CN 2013089480 W CN2013089480 W CN 2013089480W WO 2015007052 A1 WO2015007052 A1 WO 2015007052A1
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WIPO (PCT)
Prior art keywords
transistor
unit
signal
signal output
selection
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PCT/CN2013/089480
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English (en)
French (fr)
Inventor
黄家成
何剑
冯霞
Original Assignee
合肥京东方光电科技有限公司
京东方科技集团股份有限公司
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Application filed by 合肥京东方光电科技有限公司, 京东方科技集团股份有限公司 filed Critical 合肥京东方光电科技有限公司
Priority to US14/366,119 priority Critical patent/US9269313B2/en
Publication of WO2015007052A1 publication Critical patent/WO2015007052A1/zh
Priority to US14/993,571 priority patent/US9626922B2/en

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve

Definitions

  • the present invention relates to the field of display, and in particular to a G0A circuit, an array substrate, a display device, and a driving method. Background technique
  • GOA Gate Dr iver On Array - gate line drive on the array substrate.
  • the existing G0A circuit usually includes a plurality of G0A units, and each G0A unit corresponds to one gate line.
  • the output end of each G0A unit is connected to one gate line, and the output end of each G0A unit is also connected to the next GO.
  • the input of the A unit is used to turn on the next G0A unit, and the output of the next GO A unit is also connected to the reset signal input end of the previous G0A unit.
  • a G0A unit usually includes 12 transistors and a capacitor.
  • the G0A circuit uses more transistors and occupies a larger area of the array substrate. Summary of the invention
  • Embodiments of the present invention are directed to providing a structure, a G0A circuit occupying an array substrate area, an array substrate, a display device, and a driving method.
  • An embodiment of the present invention provides a G0A circuit including a clock signal input line and two or more GO A units cascaded, the GO A unit including a selection signal output subunit and a selection subunit;
  • the selection signal output subunit is configured to receive a source signal and output a selection signal according to the source signal
  • the selecting subunit receives the selection signal and the N clock signals, and outputs the received clock signal according to the selection signal;
  • the clock signal input line is at least N for inputting a clock signal to the selection subunit; wherein N is an integer greater than or equal to 2.
  • the G0A circuit further includes an open signal line
  • the selection signal output subunit includes a source signal input terminal 1, a source signal input terminal 2, an enable signal input terminal, a signal output terminal 1, a signal output terminal 2, and a reset signal input terminal;
  • the source signal input end is used to input a first source signal;
  • the source signal input terminal 2 is configured to input a second source signal
  • the signal output end is connected to the selection subunit for outputting a selection signal generated according to the first source signal and the second source signal;
  • the turn-on signal input end of the selection signal output sub-unit of the first G0A unit is connected to the turn-on signal line for receiving an enable signal, and the reset signal input end of the select signal output sub-unit of the first G0A unit Connected to the signal output end of the selection signal output subunit of the second G0A unit, and receive a selection signal outputted by the signal output end of the selection signal output subunit of the second G0A unit;
  • the opening signal input end of the selection signal output subunit of the mth G0A unit is connected to the signal output end 2 of the selection signal output subunit of the m-1th GOA unit, and receives the m-1th G0A a selection signal of the signal output terminal of the selection signal output subunit of the unit; a reset signal input end of the mth selection signal output subunit of the G0A unit and a selection signal output subunit of the m+1th G0A unit
  • the signal output ends are connected, and receive a selection signal outputted by the signal output end of the selection signal output subunit of the m+1th GOA unit;
  • the open signal input end of the selection signal output subunit of the Mth G0A unit is connected to the signal output end 2 of the selection signal output subunit of the M-1th G0A unit, and receives the M-1th G0A a selection signal of the signal output terminal of the selection signal output subunit of the unit, and a reset signal input end of the selection signal output subunit of the Mth G0A unit is connected to the open signal line; wherein m is a natural number, M > m > l , the M is the number of GOA units.
  • the selection subunit includes N clock signal input ends, a selection signal input end, and N clock signal output ends;
  • the N clock signal input ends are respectively connected to the N clock signal input lines for inputting a clock signal
  • the selection signal input end is configured to receive a selection signal output by the selection signal output subunit
  • the clock signal output terminal outputs the received clock signal according to the selection signal.
  • the N 4;
  • the G0A unit further includes a gate line turn-on voltage line and a gate line turn-off voltage line;
  • the selection subunit includes a pull-up module, a hold module, a gate line turn-on voltage input terminal connected to the gate line turn-on voltage line, and a gate line turn-off voltage input terminal connected to the gate line turn-off voltage line ;
  • the pull-up module includes a first transistor, a second transistor, a third transistor, and a fourth transistor;
  • the gates of the first transistor, the second transistor, the third transistor, and the fourth transistor are all connected to the selection signal input end;
  • the drain of the first transistor is connected to the input end of the first clock signal, and the source is connected to the output end of the first clock signal for outputting the first clock signal to the outside;
  • the drain of the second transistor is connected to the input end of the second clock signal, and the source is connected to the output end of the second clock signal for outputting the second clock signal to the outside;
  • the drain of the third transistor is connected to the input end of the third clock signal, and the source is connected to the output end of the third clock signal for outputting the third clock signal to the outside;
  • the drain of the fourth transistor is connected to the fourth clock signal input end, and the source is connected to the fourth clock signal output end for outputting the fourth clock signal to the outside;
  • the holding module includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;
  • the gate and the drain of the fifth transistor are both connected to the gate line-on voltage input terminal, and the source is connected to the drain of the sixth transistor;
  • a gate of the sixth transistor is connected to the input signal of the selection signal, and a source is connected to the turn-off voltage line of the gate line signal;
  • the gates of the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all connected to a source of the fifth transistor;
  • the drain of the seventh transistor is connected to the source of the first transistor, and the source is connected to the input line of the gate line turn-off voltage;
  • the drain of the eighth transistor is connected to the source of the second transistor, and the source is connected to the gate line turn-off voltage input terminal;
  • the drain of the ninth transistor is connected to the source of the third transistor, and the source is connected to the gate line turn-off voltage input terminal;
  • An embodiment of the present invention provides an array substrate, the array substrate comprising the above-mentioned G0A circuit and a plurality of gate lines;
  • Each of the selected subunits is respectively connected to N consecutively distributed gate lines;
  • the product of the N and the total number M of the G0A cells in the G0A circuit is equal to the total number of the gate lines.
  • Embodiments of the present invention provide a display device including the above array substrate.
  • the array substrate further includes a pixel matrix, a gate line, and a data line;
  • Each row of pixels corresponds to two gate lines, and the two gate lines are divided into a first gate line and a second gate line; the odd column pixels are connected to the first gate line, and the even column pixels are connected to the second gate line;
  • the array substrate further includes a pixel matrix, a gate line, and a data line;
  • Each row of pixels is connected to one of the gate lines;
  • Each column of pixels is connected to one of the data lines;
  • the display device is a liquid crystal display device.
  • An embodiment of the present invention further provides a driving method of a display device, the method being used for the display device as described above, comprising:
  • Each G0A unit turns on a gate line by a clock signal during each field period
  • Each G0A unit sequentially turns on a gate line connected thereto;
  • the voltages of all data lines output during each field are of the same polarity
  • the output voltages of the 4S+1 field and the 4S+2 field data lines are opposite in polarity
  • the output voltages of the 4S+2 field and the 4S+3 field data lines have the same polarity
  • the output voltages of the 4S+3 field and the 4S+4 field data lines are opposite in polarity
  • the N is the number of clock signals output by each G0A unit, and is a multiple of 4.
  • An embodiment of the present invention further provides a driving method of a display device, the method being used for the display device as described above, comprising:
  • Each G0A unit turns on a gate line by a clock signal during each field period;
  • Each GOA unit sequentially turns on a gate line connected thereto;
  • the polarity inversion period of each data line output voltage is equal to the field period, and the polarity of the output voltage of the adjacent two data lines is always opposite;
  • the N is the number of clock signals output by each G0A unit.
  • Embodiments of the invention adopt the structure of the selection signal output subunit and the selection subunit, and can be connected to the N gate lines at the same time, thereby saving N-1.
  • the G0A unit, and the structure of the selection signal output sub-unit and the selection sub-unit reduce the electronic components such as transistors used with respect to the N G0A units, thereby also reducing the area of the occupied array substrate.
  • FIG. 1 is a schematic structural diagram of a selection subunit according to Embodiment 3 of the present invention.
  • FIG. 3 is a partial structural schematic view of an array substrate according to Embodiment 7 of the present invention.
  • FIG. 4 is a timing chart of signals of a first field of a polarity inversion driving method according to an embodiment of the present invention
  • FIG. 5 is a timing chart of signals of a second field of the polarity inversion driving method according to the embodiment of the present invention.
  • FIG. 6 is a timing chart of signals of a third field of the polarity inversion driving method according to the embodiment of the present invention.
  • FIG. 7 is a timing diagram of each signal of the fourth field of the polarity inversion driving method according to the embodiment of the present invention
  • FIG. 7 is a partial pixel polarity diagram of the display device according to Embodiment 7
  • a schematic diagram of a partial pixel polarity when the device is displayed a partial pixel polarity diagram of the display device according to the seventh embodiment; and a partial pixel polarity diagram of the display device according to the seventh embodiment
  • Embodiment 1 is a diagrammatic representation of the present invention.
  • the G0A circuit of the embodiment includes a clock signal input line and two or more G0A units cascaded (not shown),
  • the G0A unit includes a selection signal output subunit and a selection subunit
  • the selection signal output subunit is configured to receive a source signal and output a selection signal according to the source signal
  • the selecting subunit receives the selection signal and the N clock signals, and outputs the received clock signal according to the selection signal;
  • the clock signal input line is at least N for inputting a clock signal to the selection subunit.
  • the internal structure of the selection signal output sub-unit may be composed of a G0A unit which is now commonly connected by 12 transistors and a capacitor, or an SRC cascade register composed of thin film transistors;
  • the selection subunit receives N clock signals, and under the control of the selection signal, determines whether to output clock signals, and the clock signals are input to a gate line of an array substrate on which the G0A circuit is located, and the gate lines are according to the The high and low levels of the clock signal, turning on or off the switch (usually a thin film transistor) of the pixel electrode of the pixel to which it is connected.
  • the value of N may be determined according to parameters such as the size of the array substrate, and the specific value is an integer equal to or greater than 2, such as 3, 4, 6, and the like. The larger the value of N is, the more gates are connected to one G0A unit.
  • the G0A unit described in this embodiment firstly changes the connection structure of a conventional G0A unit drive and a gate line, and realizes the cascade structure of the selection signal output subunit and the selection subunit.
  • a GOA unit drives N gate lines, compared with the combination of N G0A units, the structure is cylindrical, and the components used are correspondingly reduced, so that the area of the array substrate occupied is also reduced, thereby Conducive to the cylinderization and miniaturization of the array substrate.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the present embodiment provides a G0A circuit, which further includes an ON signal line, wherein the structure of the selection signal output subunit (not shown) is as follows:
  • the signal output subunit includes a source signal input end, a source signal input end 2, an open signal input end, a signal output end 1, a signal output end 2, and a reset signal input end;
  • the source signal input end is used to input a first source signal
  • the source signal input terminal 2 is configured to input a second source signal
  • the signal output end is connected to the selection subunit for outputting a selection signal generated according to the first source signal and the second source signal;
  • the turn-on signal input end of the selection signal output sub-unit of the first G0A unit is connected to the turn-on signal line for receiving an enable signal, and the reset signal input end of the select signal output sub-unit of the first G0A unit Connected to the signal output end of the selection signal output subunit of the second G0A unit, and receive a selection signal outputted by the signal output end of the selection signal output subunit of the second G0A unit;
  • the opening signal input end of the selection signal output subunit of the mth G0A unit is connected to the signal output end 2 of the selection signal output subunit of the m-1th GOA unit, and receives the m-1th G0A a selection signal of the signal output terminal of the selection signal output subunit of the unit; a reset signal input end of the mth selection signal output subunit of the G0A unit and a selection signal output subunit of the m+1th G0A unit
  • the signal output ends are connected, and receive a selection signal outputted by the signal output end of the selection signal output subunit of the m+1th GOA unit;
  • the open signal input end of the selection signal output subunit of the Mth G0A unit is connected to the signal output end 2 of the selection signal output subunit of the M-1th G0A unit, and receives the M-1th G0A a selection signal of the signal output terminal of the selection signal output subunit of the unit, and a reset signal input end of the selection signal output subunit of the Mth G0A unit is connected to the open signal line; wherein m is a natural number, M > m > 1, the M is the number of GO A units.
  • the signal output terminal 2 of the selection signal output subunit of the previous G0A unit is connected to the ON signal input end of the next G0A unit, and the generated selection signal is simultaneously used as the ON signal of the next G0A unit, thereby triggering the operation of the next G0A unit.
  • the selection signal generated by the next GOA unit is used as the reset signal of the previous G0A unit, so that the selected subunit of the previous G0A unit is restored to the original state, so as to facilitate the next scan, and the signal multiplexing is also achieved, thereby reducing the number of signals.
  • the output circuit of different signals is generated, so that the circuit structure is once again refined, and the structure of the single tube is realized, and the occupied area is small.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • the present embodiment proposes a preferred selection sub-unit structure, which is specifically as follows:
  • the selection subunit includes N clock signal input ends, a selection signal input end, and N clock signal output ends;
  • the N clock signal input ends are respectively connected to the N clock signal input lines for inputting a clock signal
  • the selection signal input end is configured to receive a selection signal output by the selection signal output subunit
  • the clock signal output terminal outputs the received clock signal according to the selection signal.
  • the G0A cell further includes a gate line turn-on voltage line and a gate line turn-off voltage line; the gate line turn-on voltage Von is always at a high level, and the gate line turn-off voltage is Voff always at a low level;
  • the selection subunit includes a pull-up module, a hold module, a gate line turn-on voltage input terminal connected to the gate line turn-on voltage line, and a gate line turn-off voltage input terminal connected to the gate line turn-off voltage line ;
  • the pull-up module includes a first transistor T1, a second transistor ⁇ 2, a third transistor ⁇ 3, and a fourth transistor ⁇ 4;
  • the gates of the first transistor T1, the second transistor ⁇ 2, the third transistor ⁇ 3, and the fourth transistor ⁇ 4 are all connected to the selection signal input terminal Gin;
  • the drain of the first transistor T1 is connected to the first clock signal input terminal CLK1, and the source is used to output the first clock signal; the output terminal for outputting the first clock signal is 0UT1;
  • the drain of the second transistor T2 is connected to the second clock signal input terminal CLK2, and the source is used to output the second clock signal; the output terminal for outputting the second clock signal is 0UT2;
  • the drain of the third transistor T3 is connected to the third clock signal input terminal CLK3, the source is used to output a third clock signal; the output terminal for outputting the third clock signal is 0UT3;
  • the drain of the fourth transistor T4 is connected to the fourth clock signal input terminal CLK4, the source is used to output the fourth clock signal; the output terminal of the output fourth clock signal is 0UT4;
  • the holding module includes a fifth transistor T5, a sixth transistor ⁇ 6, a seventh transistor ⁇ 7, an eighth transistor ⁇ 8, a ninth transistor ⁇ 9, and a tenth transistor T10;
  • the gate and the drain of the fifth transistor ⁇ 5 are both connected to the gate line signal-on voltage line, and the source is connected to the drain of the sixth transistor ⁇ 6;
  • the sixth transistor ⁇ 6 has a gate connected to the selection signal input terminal, and a source connected to the gate line shutdown voltage input terminal;
  • the gates of the seventh transistor ⁇ 7, the eighth transistor ⁇ 8, the ninth transistor ⁇ 9, and the tenth transistor T10 are all connected to the source of the fifth transistor ⁇ 5; the Von voltage is a high level, the Vof f Low level, the gate-source voltage of the transistor T5 is greater than a threshold voltage, and the transistor T5 is turned on to output a high level;
  • the drain of the seventh transistor T7 is connected to the source of the first transistor T1, and the source is connected to the gate line turn-off voltage input terminal;
  • the drain of the eighth transistor T8 is connected to the source of the second transistor T2, and the source is connected to the gate line turn-off voltage input terminal;
  • the drain of the ninth transistor T9 is connected to the source of the third transistor T3, and the source is connected to the gate line turn-off voltage input terminal;
  • the drain of the tenth transistor T10 is connected to the source of the fourth transistor T4, and the source is connected to the gate line turn-off voltage input terminal.
  • the gate line corresponding to the array substrate of the G0A circuit according to the embodiment is turned on, and when the level is low, the corresponding The gate line is turned off, in order to realize the scanning of the gate lines one by one, it can be realized by setting the high level of different clock signals to be shifted.
  • the size ratio of the fifth transistor and the sixth transistor when the selection signal input to the selection signal input terminal G in is at a high level, the node of the source of the fifth transistor connected to the drain of the sixth transistor is Pulled low to turn off transistor T7-T1 0.
  • the selection signal of the Gin input when the selection signal of the Gin input is at a high level, the transistors T1-T4 are all turned on, and the clock signals CLK1-CLK4 are outputted outward.
  • the transistors T1 - T4 are all cut off, and the clock signals CLK1 - CLK4 cannot output the clock signals CLK1 - CLK4 through the signal output terminals 0UT1 - 0UT4 , and the transistor at this time T7-T1 0 turns on, pulling the output voltage of 0UT1-0UT4 low. To keep the voltage low.
  • a selection sub-unit capable of simultaneously connecting four gate lines is provided, so that the array substrate of the G0A circuit is used, the number of G0A units is only 1/4 of the original, and the number of transistors used is also Less than 1 /2 of the original transistor.
  • a selection sub-unit of 10 transistors is added to the original G0A unit, thereby realizing driving of four gate lines, and driving four gate lines with respect to the conventional single-ended four G0A units, the transistor.
  • the number of the array is reduced by 26, so that the structure is more compact, and the area of the array substrate occupied is also reduced.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • a preferred G0A circuit is proposed in combination with the preferred selection signal output subunit and selection subunit provided by the above embodiments:
  • the G0A circuit includes a clock signal input line and two or more G0A units that are cascaded, and the G0A unit includes a selection signal output subunit SR and a selection subunit CH;
  • the selection signal output subunit SR is configured to receive a source signal, and output a selection signal g in according to the source signal;
  • the selecting subunit CH receives the selection signal g in and N clock signals, and outputs the received clock signal according to the selection signal;
  • the clock signal input lines are at least four, and are used to input a clock signal to the selection subunit CH.
  • the G0A circuit further includes an open signal line STVP, wherein the signal selection subunit
  • the structure of the SR is as follows:
  • the selection signal output subunit SR includes a source signal input terminal Cl, a source signal input terminal C2, an enable signal input terminal 3, a signal output terminal 0ut1, a signal output terminal 2ut2, and a reset signal input terminal R;
  • the source signal input terminal C1 is used to input the first source signal CLKB;
  • the source signal input terminal C2 is used to input the second source signal CLKV;
  • the signal output terminal Out is connected to the selection sub-unit CH for outputting a selection signal g in generated according to the first source signal CLKV and the second source signal CLKB;
  • the turn-on signal input terminal s of the selection signal output sub-unit SR of the first GOA unit is connected to the turn-on signal line for receiving the turn-on signal STVP, and the selection signal output sub-unit SR of the first G0A unit Reset signal input terminal R and selection signal output of the second G0A unit
  • the signal output end of the subunit SR is connected to the Out1, and receives the selection signal gin outputted by the signal output end of the selection signal output subunit SR of the second G0A unit.
  • the turn-on signal input terminal s of the selection signal output sub-unit SR of the mth G0A unit is connected to the signal output terminal 2 Out 2 of the m-1th G0A unit, and receives the m-1th G0A unit
  • the selection signal gin of the signal output terminal 2 Out1 of the signal output subunit SR is selected; the reset signal input terminal R of the mth selection signal output subunit SR of the G0A unit and the selection signal of the m+1th G0A unit
  • the signal output end of the output subunit SR is connected to Out1, and receives the selection signal gin outputted by the signal output end of the selection signal output subunit SR of the m+1th GOA unit.
  • the signal output terminals of the selection signal output subunits SR of the M-1 G0A units are connected to each other, and the signal output terminal of the selection signal output subunit SR of the M-1th G0A unit is received.
  • a reset signal input terminal R of the selection signal output subunit SR of the Mth GOA unit is connected to the open signal line to receive an open signal STVP from the open signal line; wherein m is a natural number, M>m> l, the M is the number of GO A units.
  • the first source signal and the second source signal are also clock signals.
  • the processing of the logic circuit outputs the method described in this embodiment. Select the signal and enter it into the selection subunit to which it is connected.
  • the structure of the selection subunit CH is as follows:
  • the selection subunit includes four clock signal input terminals, a selection signal input terminal Gin, and four clock signal output terminals, which are 0UT1, 0UT2, 0UT3, and 0UT4, respectively;
  • the selection signal input terminal Gin is configured to receive the selection signal gin output by the selection signal output subunit SR;
  • the clock signal output terminal outputs the received clock signal according to the selection signal.
  • the selection signal sub-unit of the first G0A unit CH clock output terminals 0UT1, 0UT2, 0UT3 and 0UT4 are sequentially used to connect the gate lines G1, G2, G3 and G4 on the array substrate;
  • the clock signal output terminals 0UT1, 0UT2, 0UT3 and OUT4 of the second sub-unit CH of the G0A unit are sequentially used to connect the gate lines G5, G6, G7 and G8 on the array substrate;
  • the output terminals OUT1, 0UT2, 0UT3, and OUT4 of the selection sub-unit CH of the n/4-1th GOA unit are sequentially used to connect the gate lines Gn_7, Gn_6, Gn_5, and Gn_4 on the array substrate;
  • the output terminals of the n/4th GOA unit, CHUT1, 0UT2, 0UT3, and 0UT4 are sequentially used to connect the gate lines Gn_3, Gn_2, Gn_l, and Gn on the array substrate;
  • n is not more than an integer of the total number of gate lines on the array substrate.
  • the gate line turn-on voltage Von is connected to an input terminal on a selected sub-cell of each G0A cell, and the gate-line turn-off voltage line Voff is connected to an input terminal of f on a selected sub-unit of each G0A cell. .
  • the gate line turn-on voltage Von is normally always high, and the gate line turn-off voltage Vof f is normally low at all times.
  • each of the G0A units has four clock signal output ends, which can be used for opening four gate lines on the array substrate, and driving one grid with respect to a conventional G0A unit.
  • the structure of the wire has the advantages of compact structure, small number of transistors used, and small occupied area.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • the array substrate of this embodiment includes the G0A circuit and the plurality of gate lines as described in any one of Embodiments 1 to 4;
  • Each of the selected sub-units is respectively connected to N consecutively distributed gate lines; a clock signal of the selected sub-units in one G0A unit is correspondingly input to one gate line; the total number of gate lines.
  • the array substrate is scanned from top to bottom or from bottom to top by G0A unit to realize one-by-segment gate line scanning; and in the array substrate described in this embodiment, because a G0A unit is driven At least two (N) gate lines, the number of G0A cells is reduced ( ⁇ - ⁇ / ⁇ , the drive circuit is reduced, the area occupied by the drive circuit is reduced, and the area of the drive circuit integrated on the array substrate is reduced. It is advantageous for miniaturization of a display device using the array substrate.
  • the display device of this embodiment includes the array substrate of the fifth embodiment.
  • the display device according to the embodiment adopts an array substrate including the G0A circuit according to the embodiment of the present invention, so that the gate drive circuit structure is also simple, and the G0A circuit occupies a small area of the array substrate. It is advantageous for miniaturization of the display device.
  • the display device may include a display device of an array substrate, and may be an OLED display device or a liquid crystal display device.
  • Example 7 Example 7:
  • the display device provided in this embodiment includes the array substrate according to the embodiment of the present invention, and the array substrate further includes a pixel matrix, a gate line, and a data line;
  • Each row of pixels corresponds to two gate lines, and the two gate lines are divided into a first gate line and a second gate line; the odd column pixels are connected to the first gate line, and the even column pixels are connected to the second gate line;
  • the display device is a liquid crystal display device.
  • the liquid crystal display device generally includes an array substrate and a color filter substrate disposed opposite to each other, and the liquid crystal molecular layer is located between the array substrate and the color filter substrate.
  • the pixel 11 and the pixel 12 are the same row of pixels, the pixel 11 is connected to the gate line 13, and the pixel 12 is connected to the gate line 14, that is, adjacent pixels in one row are used with different gate lines.
  • the pixels 11 and 12 in different columns are connected to the same data line 15; in the specific implementation process, the signal input by the data line is driven by the data line connected to the data line to drive K input, in actual production
  • the cost of the data line driver IC is much higher than that of the gate line driver IC. Therefore, in this embodiment, the number of gate lines is doubled and the number of data lines is halved. When the pixel is independently driven, the price is reduced.
  • the costly data line drives the application of the IC, thereby reducing the overall cost of the display device.
  • the G0A unit In the conventional display device using double-gate (Dua l Ga te ) driving, since one row of pixels is driven by two gate lines, the G0A unit is also doubled, which directly leads to an increase in the area of the non-display area of the array substrate. Large, resulting in an increase in the frame of the display device, which is disadvantageous for the narrow frame and miniaturization of the display device.
  • the G0A unit can simultaneously drive N gate lines, and N is an integer greater than or equal to 2
  • N is an integer greater than or equal to 2
  • the display device provided in this embodiment includes the array substrate according to the embodiment of the present invention; the OLED substrate is provided with the G0A circuit according to the embodiment of the present invention, and the array substrate further includes a pixel matrix and a gate line. And data lines;
  • Each row of pixels is connected to one of the gate lines;
  • Each column of pixels is connected to one of the data lines;
  • the display device is a liquid crystal display device.
  • the number of gate lines is equal to the number of rows of pixels in the pixel matrix
  • the number of data lines is equal to the number of columns of pixels in the pixel matrix.
  • the pixel device described in this embodiment is a liquid crystal display device.
  • the liquid crystal display device generally includes an array substrate, an opposite substrate disposed opposite to the array substrate, and a liquid crystal layer between the array substrate and the opposite substrate; the opposite substrate is usually a color film substrate, but in a specific application process
  • the color filter on the color filter substrate may be disposed on the array substrate, and the substrate facing the array substrate only needs to be a transparent substrate.
  • a pixel electrode and a thin film transistor TFT are disposed on the array substrate; a drain of the thin film transistor is connected to the pixel electrode, a gate of the thin film transistor is connected to a gate line, and a source and a data of the thin film transistor are The lines are connected to each other; the gate line is connected to a clock signal output end of the G0A circuit; the gate line and the data line are vertically distributed to each other, and the entire substrate is divided into independent pixel spaces, and the pixel electrodes are located in the pixel space.
  • the liquid crystal layer exhibits different optical rotation characteristics according to the driving voltage of the pixel electrode, thereby realizing different gray scales; filtering is performed by the color film substrate to form different colors (for example, the R/G/B color resist layer forms three primary colors) Then, the image is displayed by the light mixing phenomenon of different color lights.
  • the color of the color resist layer may also be other colors, such as yellow.
  • the display device according to the embodiment of the present invention adopts the G0A circuit according to the embodiment of the present invention, and the display device of the conventional G0A circuit has a gate drive circuit structure.
  • Multiple advantages such as compact size and small footprint.
  • the polarity inversion driving method has various methods, including frame polarity inversion driving, row or column polarity inversion driving, and single-point polarity inversion driving; the inversion driving is performed so that liquid crystal molecules are not at both ends of the liquid crystal layer.
  • the electric field remains unchanged for a long time, the characteristics of the liquid crystal molecules are destroyed, resulting in a decrease in display effect and display performance.
  • the effect of single-point polarity inversion is optimal, but the energy consumption is large.
  • the frame polarity inversion driving and the row or column polarity inversion driving the period in which the polarity of the output voltage in the data line is inverted is equal to the frame period, but the improvement effect on the display effect of the display device is small;
  • the polarity of the voltage reversed to the pixel around each pixel in the same frame is opposite to the polarity of the voltage of the surrounded pixel at the same time, so the time of opening a gate line during pixel refreshing, the data line is
  • the period of the inversion is 1 / P frame period; P is the total number of gate lines, and the polarity inversion of the data line output voltage is high, resulting in a single point polarity inversion drive.
  • P is the total number of gate lines
  • the polarity inversion of the data line output voltage is high, resulting in a single point polarity inversion drive.
  • the frame polarity inversion driving and the row polarity inversion driving the data line voltage polarity inversion period is small, the energy consumption is small, but the improvement effect on the display effect is poor, and the image flicker is highly prone to occur;
  • the polarity inversion drive is good for improving the display effect, but the voltage polarity inversion period of the data line is small, resulting in high energy consumption;
  • the G0A circuit provided by the embodiment according to the embodiment of the present invention provides a display device driving method different from the conventional polarity inversion driving, which can realize single point polarity inversion;
  • the driving method of the display device according to the embodiment can be used to solve the above contradiction, and can effectively reconcile the contradiction between the display improvement effect and the energy consumption.
  • the specific display device of the embodiment The driving method used in the display device of the seventh embodiment specifically includes:
  • Each G0A unit turns on a gate line by a clock signal during each field period
  • Each G0A unit sequentially turns on the gate line connected thereto, specifically, the first field G0A unit turns on the first gate line connected thereto by the clock signal, and the second field G0A unit turns on the second line connected thereto by the clock signal.
  • Grid line The voltages of all the data lines output are the same in each field cycle; the output voltages of the 4S+1 field and the 4S+2 field data lines are opposite in polarity;
  • the output voltages of the 4S+2 field and the 4S+3 field data lines have the same polarity
  • the output voltages of the 4S+3 field and the 4S+4 field data lines are opposite in polarity
  • S is a natural number, 4 S+4 is less than or equal to N;
  • the N is the number of clock signals output by each G0A unit, and is a multiple of 4.
  • each data line needs to input a signal once for each gate line.
  • the number of times of scanning each data line is M times.
  • the output voltage polarity of the data line is known.
  • the period of the inversion is not less than the field period, that is, 1 / N frame period. Therefore, compared with the conventional display device having the same number of gate lines as the display device of the present embodiment, the voltage polarity inversion period of the data line of the embodiment is at least the output voltage of the conventional single-point polarity inversion data line. Since the polarity inversion period is M times, the inversion period is greatly elongated, thereby contributing to a reduction in power consumption, and thus the contradiction of the driving loss of the display device described in this embodiment.
  • the array substrate includes a G0A circuit according to an embodiment of the present invention, and each G0A unit in the G0A circuit Connected to 4 grid lines;
  • the first 1/4 frame period is the first field, and the STVP signal is as shown by 1 in FIG. 4, and the corresponding first source signal CLKV, second source signal CLKB, first clock signal CLK1, and second clock signal CLK2.
  • the third clock signal CLK 3, the fourth clock signal CLK4, and the sequentially turned-on gate lines are G1, G5 ⁇ .
  • Gn- 3 where n is the number of gate lines; and the turned-on gate lines are turned on
  • the timing is as shown in the figure; at this time, only the first clock signal CLK1 is high level in each G0A unit, that is, only the gate lines G1, G5, ... Gn-3 corresponding to the first clock signal are turned on;
  • the second 1/4 frame period is the second field.
  • the STVP signal is as shown in 2 of FIG. 5, and the corresponding first source signal CLKV, second source signal CLKB, first clock signal CLK1, and second clock signal CLK2.
  • the third clock signal CLK 3, the fourth clock signal CLK4, and the turned-on gate lines are G2, G6, ..., Gn-2, where n is the number of gate lines; and the timing of the turn-on between the turned-on gate lines is as shown in the figure As shown in the figure; at this time, only the second clock signal CLK2 is high level in each G0A unit, that is, only the gate lines G2, G6 corresponding to the second clock signal are turned on;
  • the polarity of the output voltage of the first field and the second field data line is changed once, and the inversion period of the polarity of the output voltage of the data line is the field period, that is, 1 / N frame period;
  • the third 1/4 frame period is the third field, the third 1/4 frame period, the STVP signal is as shown in 3 of FIG. 6, the corresponding first source signal CLKV, the second source signal CLKB, the first clock The signal CLK 1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, and the turned-on gate line are G3, G7 ⁇ . Gn-1 , where n is the gate The number of lines; and the timing of the opening between the turned-on gate lines is as shown in the figure; at this time, only the third clock signal CLK 3 in each G0A unit is at a high level, that is, only corresponds to the gate of the third clock signal. Lines G 3, G7 ... Gn-1 are turned on;
  • the polarity of the output voltage of the data line of the third field is the same as that of the second field, which is equivalent to the time when the polarity of the voltage of the data output remains unchanged at 2/N frame periods;
  • the fourth 1/4 frame period is the fourth field, and the STVP signal is as shown in 4 of FIG. 7, corresponding to the first source signal CLKV, the second source signal CLKB, the first clock signal CLK1, and the second clock signal CLK2.
  • the third clock signal CLK 3, the fourth clock signal CLK4, and the turned-on gate lines are G4, G8, ..., Gn, where n is the number of gate lines; and the timing of the turn-on between the turned-on gate lines is as shown At this time, only the fourth clock signal CLK4 in each G0A unit is at a high level, that is, only the gate lines G4, G8 ... Gn corresponding to the fourth clock signal are turned on;
  • the gate line of the fourth clock signal of each corresponding G0A unit is turned on, and the driving is even-numbered even-numbered rows of pixels, and the polarity of the even-numbered even-numbered rows of the driven pixels is positive (in The figure is indicated by "+");
  • the polarity of the output voltage of all the data lines is changed in the fourth field relative to the third field, and the polarity inversion period of the output voltage of the data line is 1 / N frame period;
  • the period of the polarity inversion of the output voltage of the data line is greatly increased compared with the conventional single-point driving method, so that the inversion frequency of the output voltage of the data line is greatly increased. Reduced, thus reducing energy consumption, and because it is a single point drive to ensure a good display.
  • Embodiment 10 The moving method, each G0A unit in the G0A circuit is connected to four gate lines, as follows:
  • the first 1/4 frame period of each frame is the first field, and the STVP signal is as shown in FIG.
  • the gate lines are Gl, G5, ..., Gn-3, where n is the number of gate lines; and the timing of the turn-on between the turned-on gate lines is as shown; at this time, only the first clock signal CLK1 in each G0A unit is High level, that is, only the gate lines G1, G5, ... Gn3 corresponding to the first clock signal are turned on;
  • the polarity of the pixel voltage of all the even columns in the pixel row corresponding to the turn-on gate line is negative (indicated by "-" in the figure), and the voltage polarity of the corresponding data line driving the even-numbered column pixel is negative;
  • the second 1/4 frame period is the second field, and the STVP signal is as shown in 2 of FIG. 5, and the corresponding first source signal CLKV, second source signal CLKB, first clock signal CLK1, and second clock signal.
  • CLK2 The third clock signal CLK 3, the fourth clock signal CLK4, and the turned-on gate lines are G2, G6, ..., Gn-2, where n is the number of gate lines; and the timing of the turn-on between the turned-on gate lines is as shown in the figure At this time, only the second clock signal CLK2 is high level in each G0A unit, that is, only the gate lines G2, G6 corresponding to the second clock signal are turned on;
  • the pixel voltage polarity of the odd-numbered column in the pixel row corresponding to the turn-on gate line is negative (indicated by "-" in the figure;), and the voltage polarity of the corresponding data line driving the odd-numbered column pixel is also negative;
  • the third 1/4 frame period is the third field, and the STVP signal is as shown by 3 in FIG. 6, the corresponding first source signal CLKV, second source signal CLKB, first clock signal CLK1, and second clock signal.
  • CLK2, the third clock signal CLK3, the fourth clock signal CLK4, and the turned-on gate lines are G3, G7, ..., Gn-1, where n is the number of gate lines; and the timing of the turn-on between the turned-on gate lines As shown in the figure; at this time, only the third clock signal CLK 3 in each G0A unit is at a high level, that is, only the gate lines G 3, G7 ... Gn_l corresponding to the third clock signal are turned on. ;
  • the polarity of the pixel voltage of the even-numbered column in the pixel row corresponding to the turn-on gate line is negative (indicated by "-" in the figure), and the voltage polarity of the corresponding data line driving the even-numbered column pixel is also negative;
  • the fourth 1/4 frame period is the fourth field, and the STVP signal is as shown in 4 of FIG. 7, corresponding to the first source signal CLKV, the second source signal CLKB, the first clock signal CLK1, and the second clock signal.
  • CLK2, the third clock signal CLK3, the fourth clock signal CLK4, and the turned-on gate lines are G4, G8 ⁇ .
  • Gn where n is the number of gate lines; and the turned-on gate lines are turned on
  • the timing is as shown in the figure; at this time, only the fourth clock signal CLK4 is high level in each G0A unit, that is, only the gate lines G4, G8, ... Gn corresponding to the fourth clock signal are turned on;
  • the pixel voltage polarity of the odd-numbered column in the pixel row corresponding to the turn-on gate line is negative (indicated by "-" in the figure;), and the voltage polarity of the corresponding data line driving the odd-numbered column pixel is also negative;
  • the gate line is different, and the polarity of the data line voltage can be positive or negative. Satisfy the need for point polarity reversal.
  • the polarity inversion driving method described in this embodiment inherits not only the good driving effect of the conventional single-point polarity inversion driving method, but also the voltage of the data line relative to the conventional point polarity inversion driving method.
  • the polarity inversion period is extended to 1 / 4 frame period, and the data line output voltage is reversed at a low frequency, thereby greatly reducing power consumption.

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Abstract

一种GOA电路、阵列基板、显示装置及驱动方法。所述GOA电路包括时钟信号输入线以及级联的两个以上的GOA单元，所述GOA单元包括选择信号输出子单元以及选择子单元；所述选择信号输出子单元，用以接收源信号，并根据源信号输出选择信号；所述选择子单元，接收所述选择信号和N个时钟信号，并根据所述选择信号输出所接收的时钟信号；所述时钟信号输入线至少为N根，用以向所述选择子单元输入时钟信号；其中N为大于2的整数。所述的GOA电路、阵列基板和显示装置的栅极驱动结占用面积小，所述的驱动方法可实现单点极性反转。

Description

GOA电路、 阵列基板、 显示装置及驱动方法 技术领域
本发明涉及显示领域， 尤其涉及一种 G0A电路、 阵列基板、 显示装置及驱 动方法。 背景技术
GOA: Gate Dr iver On Array——位于阵列基板上的栅线驱动。
现有的 G0A电路， 通常包括若干个 G0A单元， 每一 G0A单元对应一条栅 线， 具体的每一个 G0A单元的输出端连接一条栅线， 且每一 G0A单元的输出 端还连接到下一 GO A单元的输入端， 用以开启下一 G0A单元， 同时下一 GO A 单元的输出端还连接到上一 G0A单元的复位信号输入端。
在现有的技术当中， 一个 G0A单元通常包括 12个晶体管以及一个电容， 当一个 G0A单元对应驱动一条栅线时， G0A电路的采用的晶体管多， 占用的 阵列基板面积大。 发明内容
本发明的实施例旨在提供一种结构筒单、 占用阵列基板面积小的 G0A电 路、 阵列基板、 显示装置及驱动方法。
本发明的实施例提供了一种 G0A电路， 所述 G0A电路包括时钟信号输入线 以及级联的两个以上的 GO A单元， 所述 GO A单元包括选择信号输出子单元以及 选择子单元；
所述选择信号输出子单元， 用以接收源信号， 并根据源信号输出选择信 号；
所述选择子单元， 接收所述选择信号和 N个时钟信号， 并根据所述选择信 号输出所接收的时钟信号；
所述时钟信号输入线至少为 N根， 用以向所述选择子单元输入时钟信号； 其中 N为大于或等于 2的整数。
进一步地， 所述 G0A电路还包括开启信号线；
所述选择信号输出子单元包括源信号输入端一、 源信号输入端二、 开启 信号输入端、 信号输出端一、 信号输出端二以及复位信号输入端； 所述源信号输入端一用以输入第一源信号；
所述源信号输入端二用以输入第二源信号；
所述信号输出端一与所述选择子单元相连， 用以输出根据第一源信号和 第二源信号产生的选择信号；
第一个所述 G0A单元的选择信号输出子单元的开启信号输入端与所述开 启信号线相连， 用以接收开启信号， 第一个所述 G0A单元的选择信号输出子 单元的复位信号输入端与第二个所述 G0A单元的选择信号输出子单元的信号 输出端一相连， 接收第二个所述 G0A单元的选择信号输出子单元的信号输出 端一输出的选择信号；
第 m个所述 G0A单元的选择信号输出子单元的开启信号输入端与第 m-1 个所述 GOA单元的选择信号输出子单元的信号输出端二相连， 接收第 m-1个 所述 G0A单元的选择信号输出子单元的信号输出端二的选择信号； 第 m个所 述 G0A单元的选择信号输出子单元的复位信号输入端与第 m+1个所述 G0A单 元的选择信号输出子单元的信号输出端一相连， 接收第 m+1个所述 GOA单元 的选择信号输出子单元的信号输出端一输出的选择信号；
第 M个所述 G0A单元的选择信号输出子单元的开启信号输入端与第 M-1 个所述 G0A单元的选择信号输出子单元的信号输出端二相连， 接收第 M-1个 所述 G0A单元的选择信号输出子单元的信号输出端二的选择信号， 第 M个所 述 G0A单元的选择信号输出子单元的复位信号输入端与所述开启信号线相 连； 其中， m为自然数， 所述 M > m > l , 所述 M为 GOA单元的数量。
优选地 ,
所述选择子单元包括 N个时钟信号输入端、 选择信号输入端以及 N个时 钟信号输出端；
所述 N个时钟信号输入端分别与所述 N根时钟信号输入线相连， 用以输 入时钟信号；
所述选择信号输入端， 用以接收所述选择信号输出子单元输出的选择信 号；
所述时钟信号输出端， 根据所述选择信号输出所接收的时钟信号。
优选地 ,
所述 N=4;
所述 G0A单元还包括栅线导通电压线以及栅线关断电压线； 所述选择子单元包括上拉模块、 保持模块、 与所述栅线导通电压线相连 的栅线导通电压输入端和与所述栅线关断电压线相连的栅线关断电压输入 端；
所述上拉模块包括第一晶体管、 第二晶体管、 第三晶体管以及第四晶体 管；
所述第一晶体管、 第二晶体管、 第三晶体管以及第四晶体管的栅极均与 所述选择信号输入端相连；
所述第一晶体管的漏极与第一个时钟信号输入端相连， 源极与第一个时 钟信号输出端相连用以向外输出第一时钟信号；
所述第二晶体管的漏极与第二个时钟信号输入端相连， 源极与第二个时 钟信号输出端相连用以向外输出第二时钟信号；
所述第三晶体管的漏极与第三个时钟信号输入端相连， 源极与第三个时 钟信号输出端相连用以向外输出第三时钟信号；
所述第四晶体管的漏极与第四个时钟信号输入端相连， 源极与第四个时 钟信号输出端相连用以向外输出第四时钟信号；
所述保持模块包括第五晶体管、 第六晶体管、 第七晶体管、 第八晶体管、 第九晶体管以及第十晶体管；
所述第五晶体管的栅极和漏极均与栅线导通电压输入端相连， 源极与所 述第六晶体管的漏极相连；
所述第六晶体管的栅极与选择信号输入端相连， 源极与栅线信号关断电 压线相连；
所述第七晶体管、 第八晶体管、 第九晶体管以及第十晶体管的栅极均连 接在所述第五晶体管的源极；
所述第七晶体管的漏极与第一晶体管的源极相连， 源极与栅线关断电压 输入端相连；
所述第八晶体管的漏极与第二晶体管的源极相连， 源极与栅线关断电压 输入端相连；
所述第九晶体管的漏极与第三晶体管的源极相连， 源极与栅线关断电压 输入端相连；
所述第十晶体管的漏极与第四晶体管的源极相连， 源极与栅线关断电压 输入端相连。 本发明的实施例提供了一种阵列基板， 所述阵列基板包括上述的 G0A电 路以及若干栅线；
每一所述选择子单元分别与 N条连续分布的栅线相连；
其中， 所述 N与所述 G0A电路中的所述 G0A单元总数 M的乘积等于所述 栅线总的条数。
本发明的实施例提供了一种显示装置， 所述显示装置包括上述的阵列基 板。
优选地， 所述阵列基板还包括像素矩阵、 栅线以及数据线；
每一行像素对应两条栅线， 且所述两条栅线分为第一栅线和第二栅线； 奇数列像素与第一栅线相连， 偶数列像素与第二栅线相连；
2 i+l列像素和 2 ( i+1 ) 列像素共用一条数据线， i为自然数； 所述显示装置为液晶显示装置。
优选地， 所述阵列基板还包括像素矩阵、 栅线以及数据线；
每一行像素与一条所述栅线相连；
每一列像素与一条所述数据线相连；
所述显示装置为液晶显示装置。
本发明的实施例还提供了一种显示装置的驱动方法， 所述方法用于如上 所述的显示装置， 包括：
将每一帧图像均分为 N场显示；
每一场周期内每一 G0A单元通过时钟信号开启一条栅线；
每一 G0A单元均顺序开启与其相连的栅线；
每一场周期内所有数据线输出的电压极性相同；
第 4S+1场与第 4S+2场数据线的输出电压极性相反；
第 4S+2场与第 4S+3场数据线的输出电压极性相同；
第 4S+3场与第 4S+4场数据线的输出电压极性相反；
其中， S为自然数， 4S+4小于或等于 N;
所述 N为每一 G0A单元输出的时钟信号的个数， 且为 4的倍数。
本发明的实施例还提供了一种显示装置的驱动方法， 所述方法用于如上 所述的显示装置， 包括：
将每一帧图像均分为 N场显示；
每一场周期内每一 G0A单元通过时钟信号开启一条栅线； 每一 GOA单元均顺序开启与其相连的栅线；
每一数据线输出电压的极性反转周期等于场周期， 且相邻两条数据线输 出电压极性总是相反；
其中， 所述 N为每一 G0A单元输出的时钟信号的个数。
本发明的实施例本发明的实施例 G0A电路、 阵列基板、 显示装置及驱动方 法， 采用选择信号输出子单元以及选择子单元的结构， 可以同时与 N条栅线相 连， 从而节省了 N-1个 G0A单元， 而选择信号输出子单元以及选择子单元的结 构相对于 N个 G0A单元减少了所采用的晶体管等电子元件， 从而也减小了占用 的阵列基板的面积。 附图说明
图 1为本发明的实施例三所述的选择子单元的结构示意图；
图 2为本发明的实施例四所述的 G0A电路结构示意图；
图 3为本发明的实施例七所述的阵列基板的局部结构示意图；
图 4为本发明的实施例所述的极性反转驱动方法的第一场的各信号时序 图；
图 5为本发明的实施例所述的极性反转驱动方法的第二场的各信号时序 图；
图 6为本发明的实施例所述的极性反转驱动方法的第三场的各信号时序 图；
图 7为本发明的实施例所述的极性反转驱动方法的第四场的各信号时序 图； 的实施例七所述的显示装置时部分像素极性示意图； 的实施例七所述的显示装置时部分像素极性示意图； 的实施例七所述的显示装置时部分像素极性示意图； 的实施例七所述的显示装置时部分像素极性示意图； 的实施例八所述的显示装置时部分像素极性示意图； 的实施例八所述的显示装置时部分像素极性示意图； 的实施例八所述的显示装置时部分像素极性示意图； 的实施例八所述的显示装置时部分像素极性示意图。 具体实施方式
下面结合说明书附图以及实施例对本发明的实施例做进一步的说明。 实施例一：
本实施例 G0A电路， 包括时钟信号输入线以及级联的两个以上的 G0A单元 (未被图示出 ),
所述 G0A单元包括选择信号输出子单元以及选择子单元；
所述选择信号输出子单元， 用以接收源信号， 并根据源信号输出选择信 号；
所述选择子单元， 接收所述选择信号和 N个时钟信号， 并根据所述选择信 号输出所接收的时钟信号；
所述时钟信号输入线至少为 N根， 用以向所述选择子单元输入时钟信号。 所述选择信号输出子单元的内部结构可以采用现在通用由 12个晶体管以 及一个电容连接而成的 G0A单元组成， 或采用由薄膜晶体管组成的 SRC级联寄 存器；
所述选择子单元是接收 N个时钟信号， 在所述选择信号的控制下， 决定是 否输出时钟信号， 而这些时钟信号是输入到 G0A电路所在阵列基板的栅线上 的， 栅线根据所述时钟信号的高低电平， 导通或关断与其相连像素的像素电 极的开关（通常为薄膜晶体管）。
所述 N的数值可以根据阵列基板的尺寸等参数决定，具体的取值为等于或 大于 2的整数， 如 3、 4、 6等。 所述 N的取值越大， 则一个 G0A单元所连接的栅 线越多。
本实施例所述的 G0A单元， 首先改变了传统的一个 G0A单元驱动与一条栅 线的连接结构， 采用选择信号输出子单元以及选择子单元的级联结构实现了 一个 GOA单元对 N条栅线的驱动， 与 N个 G0A单元的组合相比较， 结构筒化了， 采用的元器件也相应的减少了， 故所占用的阵列基板的面积也减少了， 从而 有利于阵列基板的筒化和小型化。
实施例二：
本实施例在上一实施例的基础上， 提供一种 G0A电路， 该 G0A电路还包括 开启信号线， 其中所述选择信号输出子单元的结构（未被图示出）具体如下: 所述选择信号输出子单元包括源信号输入端一、 源信号输入端二、 开启 信号输入端、 信号输出端一、 信号输出端二以及复位信号输入端；
所述源信号输入端一用以输入第一源信号；
所述源信号输入端二用以输入第二源信号；
所述信号输出端一与所述选择子单元相连， 用以输出根据第一源信号和 第二源信号产生的选择信号；
第一个所述 G0A单元的选择信号输出子单元的开启信号输入端与所述开 启信号线相连， 用以接收开启信号， 第一个所述 G0A单元的选择信号输出子 单元的复位信号输入端与第二个所述 G0A单元的选择信号输出子单元的信号 输出端一相连， 接收第二个所述 G0A单元的选择信号输出子单元的信号输出 端一输出的选择信号；
第 m个所述 G0A单元的选择信号输出子单元的开启信号输入端与第 m-1 个所述 GOA单元的选择信号输出子单元的信号输出端二相连， 接收第 m-1个 所述 G0A单元的选择信号输出子单元的信号输出端二的选择信号； 第 m个所 述 G0A单元的选择信号输出子单元的复位信号输入端与第 m+1个所述 G0A单 元的选择信号输出子单元的信号输出端一相连， 接收第 m+1个所述 GOA单元 的选择信号输出子单元的信号输出端一输出的选择信号；
第 M个所述 G0A单元的选择信号输出子单元的开启信号输入端与第 M-1个 所述 G0A单元的选择信号输出子单元的信号输出端二相连， 接收第 M-1个所述 G0A单元的选择信号输出子单元的信号输出端二的选择信号， 第 M个所述 G0A 单元的选择信号输出子单元的复位信号输入端与所述开启信号线相连；其中, m为自然数， 所述 M > m > 1 , 所述 M为 GO A单元的数量。
上一 G0A单元的选择信号输出子单元的信号输出端二与下一 G0A单元的 开启信号输入端相连，将产生的选择信号同时作为下一 G0A单元的开启信号, 从而触发下一 G0A单元的工作， 实现栅线的扫描， 结构筒单巧妙； 同时通过 下一 GOA单元的产生的选择信号作为上一 G0A单元的复位信号， 使上一 G0A 单元的选择子单元恢复到原始状态， 以方便下一次扫描， 同样的实现了信号 的复用， 从而减少了不同信号的产生输出电路， 从而再一次精筒了电路结构， 实现了结构筒单， 占用的面积小的目的。
实施例三：
本实施例在实施例一或实施例二的基础上， 提出了一种优选的选择子单 元的结构， 具体如下：
所述选择子单元包括 N个时钟信号输入端、 选择信号输入端以及 N个时 钟信号输出端；
所述 N个时钟信号输入端分别与所述 N根时钟信号输入线相连， 用以输 入时钟信号；
所述选择信号输入端， 用以接收所述选择信号输出子单元输出的选择信 号；
所述时钟信号输出端， 根据所述选择信号输出所接收的时钟信号。
如图 1所示， 作为本实施例进一步的具体化：
所述 =4;
所述 G0A单元还包括栅线导通电压线以及栅线关断电压线； 栅线导通电 压 Von始终为高电平， 栅线关断电压为 Vof f 始终为低电平；
所述选择子单元包括上拉模块、 保持模块、 与所述栅线导通电压线相连 的栅线导通电压输入端和与所述栅线关断电压线相连的栅线关断电压输入 端；
所述上拉模块包括第一晶体管 Tl、 第二晶体管 Τ2、 第三晶体管 Τ3以及 第四晶体管 Τ4 ;
所述第一晶体管 Tl、 第二晶体管 Τ2、 第三晶体管 Τ3以及第四晶体管 Τ4 的栅极均与所述选择信号输入端 G in相连；
所述第一晶体管 T1的漏极与第一个时钟信号输入端 CLK1相连， 源极用 以向外输出第一时钟信号； 输出第一时钟信号的输出端子为 0UT1 ;
所述第二晶体管 T2的漏极与第二个时钟信号输入端 CLK2相连， 源极用 以向外输出第二时钟信号； 输出第二时钟信号的输出端子为 0UT2;
所述第三晶体管 T3的漏极与第三个时钟信号输入端 CLK3相连， 源极用 以向外输出第三时钟信号； 输出第三时钟信号的输出端子为 0UT3; 所述第四晶体管 T4的漏极与第四个时钟信号输入端 CLK4相连， 源极用 以向外输出第四时钟信号； 输出第四时钟信号的输出端子为 0UT4;
所述保持模块包括第五晶体管 T5、 第六晶体管 Τ6、 第七晶体管 Τ7、 第 八晶体管 Τ8、 第九晶体管 Τ9以及第十晶体管 T10;
所述第五晶体管 Τ5的栅极和漏极均与栅线信号导通电压线相连，源极与 所述第六晶体管 Τ6的漏极相连；
所述第六晶体管 Τ6的栅极与选择信号输入端相连，源极与栅线关断电压 输入端相连；
所述第七晶体管 Τ7、第八晶体管 Τ8、第九晶体管 Τ9以及第十晶体管 T10 的栅极均连接在所述第五晶体管 Τ5的源极； 所述 Von电压为高电平、 所述 Vof f 为低电平， 所述晶体管 T5的栅源电压大于阈值电压， 所述晶体管 T5开 启， 输出高电平；
所述第七晶体管 T7的漏极与第一晶体管 T1的源极相连， 源极与栅线关 断电压输入端相连；
所述第八晶体管 T8的漏极与第二晶体管 T2的源极相连， 源极与栅线关 断电压输入端相连；
所述第九晶体管 T9的漏极与第三晶体管 T3的源极相连， 源极与栅线关 断电压输入端相连；
所述第十晶体管 T10的漏极与第四晶体管 T4的源极相连，源极与栅线关 断电压输入端相连。
第一时钟信号、 第二时钟信号、 第三时钟信号以及第四时钟信号为高电 平时， 设有本实施例所述的 G0A电路的阵列基板对应的栅线开启， 为低电平 时则相应的栅线关断， 为了实现栅线的逐一扫描， 可以通过设定将不同时钟 信号的高电平错开来实现。
通过合理设计第五晶体管和第六晶体管的尺寸比， 使得在所述选择信号 输入端 G i n输入的选择信号为高电平时， 第五晶体管的源极与第六晶体管的 漏极相连的节点被拉低从而使晶体管 T7-T1 0关闭。 这样， 当所述 G in输入的 选择信号为高电平， 则所述晶体管 T1-T4全部开启， 向外输出时钟信号 CLK1-CLK4。 当所述 G in输出的选择信号为低电平时， 则所述晶体管 T1-T4全 部截断， 时钟信号 CLK1-CLK4不能通过所述信号输出端 0UT1-0UT4输出时钟 信号 CLK1-CLK4 ,且此时晶体管 T7-T1 0导通，将 0UT1-0UT4的输出电压拉低， 以保持低电压。
在本实施例中提供了一种可以同时连接 4条栅线的选择子单元， 从而采 用此种 G0A电路的阵列基板， G0A单元的个数仅为原先的 1 /4 , 所用的晶体管 的数目也不到原来晶体管的 1 /2。
在本实施例中，可以认为在原有的 G0A单元上增设了一个 10个晶体管的 选择子单元， 从而实现了 4条栅线的驱动， 相对传统单端的 4个 G0A单元驱 动 4条栅线， 晶体管的数量减少了 26个， 从而结构更加筒单， 占用的阵列基 板的面积也减小了。
实施例四：
如图 2所示，在本实施例中结合上述实施例提供的优选的选择信号输出子 单元以及选择子单元提出了一种优选的 G0A电路：
本实施例 G0A电路， 包括时钟信号输入线以及级联的两个以上的 G0A单元， 所述 G0A单元包括选择信号输出子单元 SR以及选择子单元 CH;
所述选择信号输出子单元 SR, 用以接收源信号， 并根据源信号输出选择 信号 g in;
所述选择子单元 CH , 接收所述选择信号 g in和 N个时钟信号， 并根据所述 选择信号输出所接收的时钟信号；
所述时钟信号输入线至少为 4根， 用以向所述选择子单元 CH输入时钟信 号。
具体地， 所述 G0A电路还包括开启信号线 STVP , 其中所述信号选择子单元
SR的结构具体如下：
所述选择信号输出子单元 SR包括源信号输入端一 Cl、 源信号输入端二 C2 、 开启信号输入端3、 信号输出端一 0ut l、 信号输出端二 0ut 2以及复位信 号输入端 R;
所述源信号输入端一 C1用以输入第一源信号 CLKB;
所述源信号输入端二 C2用以输入第二源信号 CLKV;
所述信号输出端一 Out l与所述选择子单元 CH相连， 用以输出根据第一源 信号 CLKV、 第二源信号 CLKB产生的选择信号 g in;
第一个所述 GOA单元的选择信号输出子单元 SR的开启信号输入端 s与所 述开启信号线相连， 用以接收开启信号 STVP , 第一个所述 G0A单元的选择信 号输出子单元 SR的复位信号输入端 R与第二个所述 G0A单元的选择信号输出 子单元 SR的信号输出端一 Outl相连， 接收第二个所述 G0A单元的选择信号 输出子单元 SR的信号输出端一 Outl输出的选择信号 gin;
第 m个所述 G0A单元的选择信号输出子单元 SR的开启信号输入端 s与第 m-1个所述 G0A单元的信号输出端二 Out 2相连， 接收第 m-1个所述 G0A单元 的选择信号输出子单元 SR的信号输出端二 Outl的选择信号 gin; 第 m个所 述 G0A单元的选择信号输出子单元 SR的复位信号输入端 R与第 m+1个所述 G0A单元的选择信号输出子单元 SR的信号输出端一 Outl相连， 接收第 m+1 个所述 GOA单元的选择信号输出子单元 SR的信号输出端一 Outl输出的选择 信号 gin;
第 M个所述 GOA单元的选择信号输出子单元 SR的开启信号输入端 s与与第
M-1个所述 G0A单元的选择信号输出子单元 SR的信号输出端二 0ut2相连， 接收 第 M-1个所述 G0A单元的选择信号输出子单元 SR的信号输出端二 0ut2的选择信 号 gin, 第 M个所述 GOA单元的选择信号输出子单元 SR的复位信号输入端 R与所 述开启信号线相连， 以从所述开启信号线中接收开启信号 STVP; 其中， m为自 然数， 所述 M>m> l, 所述 M为 GO A单元的数量。
在具体的实现过程中， 所述第一源信号、 第二源信号同样也为时钟信号， 在 G0A单元的使能信号 VSS为高电平时， 通过逻辑电路的处理输出本实施例 中所述的选择信号， 并输入至与其相连的选择子单元中。
所述选择子单元 CH的结构， 具体如下：
所述选择子单元包括 4个时钟信号输入端、 选择信号输入端 Gin以及 4 个时钟信号输出端， 分别是 0UT1、 0UT2、 0UT3以及 0UT4;
4个时钟信号输入端分别与所述 4根时钟信号输入线相连， 用以输入时 钟信号 CLK1 ^4;
所述选择信号输入端 Gin, 用以接收所述选择信号输出子单元 SR输出的 选择信号 gin;
所述时钟信号输出端， 根据所述选择信号输出所接收的时钟信号。
具体的如图 2所示，
第一个 G0A单元的选择子单元 CH的时钟信号输出端 0UT1、 0UT2、 0UT3 以及 0UT4依次用于连接阵列基板上的栅线 Gl、 G2、 G3以及 G4;
第二个 G0A单元的选择子单元 CH的时钟信号输出端 0UT1、 0UT2、 0UT3 以及 0UT4依次用于连接阵列基板上的栅线 G5、 G6、 G7以及 G8; 第 n/4-1个 GOA单元的选择子单元 CH的输出端 0UT1、 0UT2、 0UT3以及 0UT4依次用于连接阵列基板上的栅线 Gn_7、 Gn_6、 Gn_5以及 Gn_4;
第 n/4个 GOA单元的选择子单元 CH的输出端 0UT1、0UT2、0UT3以及 0UT4 依次用于连接阵列基板上的栅线 Gn_ 3、 Gn_2、 Gn_l以及 Gn;
其中， n的取值为不大于阵列基板上栅线总数的整数。 所述栅线导通电 压 Von与每一个 G0A单元的选择子单元上的输入端 on相连，所述栅线关断电 压线 Vof f 与每一 G0A单元的选择子单元上的输入端 of f相连。所述栅线导通 电压 Von通常情况下始终都是高电平，所述栅线关断电压 Vof f 通常情况下始 终都是低电平。
由图 2可知， 本实施例所述的 G0A电路， 每一个所述 G0A单元有 4个时 钟信号输出端， 可用于阵列基板上 4条栅线的开启， 相对于传统的一个 G0A 单元驱动一条栅线的结构， 具有结构精巧， 使用的晶体管数目少， 占用的面 积小的优点。
实施例五：
本实施例阵列基板，包括如实施例一至实施例四中任一实施例所述的 G0A 电路以及若干栅线；
每一所述选择子单元分别与 N条连续分布的栅线相连； 一个 G0A单元中 选择子单元的时钟信号对应输入到一条栅线中； 栅线总的条数。
在传统的阵列基板中， 所述阵列基板是从上至下或从下至上逐个 G0A单 元扫描， 实现逐条栅线扫描； 而在本实施例中所述的阵列基板中， 因为一个 G0A单元驱动了至少两条（N条）栅线， G0A单元的数目减少了（Ν-υ /Ν , 筒 化了驱动电路， 缩小了驱动电路所占的面积， 使得集成在阵列基板上的驱动 电路面积减小， 有利于小型化采用此阵列基板的显示装置。
实施例六：
本实施例显示装置， 包括实施例五所述的阵列基板。 由于本实施例所述 的显示装置， 采用了包含本发明的实施例所述的 G0A电路的阵列基板， 从而 同样具有栅极驱动电路结构筒单， 精巧的特点、 G0A电路占用阵列基板的面 积小， 有利于显示装置的小型化。 所述的显示装置可以包含有阵列基板的显 示器件， 可以是 0LED显示装置也可以是液晶显示装置。 实施例七：
本实施例提供的显示装置包括本发明的实施例所述的阵列基板， 所述阵 列基板还包括像素矩阵、 栅线以及数据线；
每一行像素对应两条栅线， 且所述两条栅线分为第一栅线和第二栅线； 奇数列像素与第一栅线相连， 偶数列像素与第二栅线相连；
2 i+l列像素和 2 ( i+1 ) 列像素共用一条数据线， i为自然数；
所述显示装置为液晶显示装置。
液晶显示装置通常包括相对设置的阵列基板以及彩膜基板， 液晶分子层 位于阵列基板与彩膜基板之间。
具体的如图 3所示， 像素 11与像素 12为同一行像素， 像素 11连接在栅 线 13上， 像素 12连接在栅线 14上， 即实现了一行中相邻的像素采用不同的 栅线来驱动； 且位于不同列的像素 11和像素 12连接在同一条数据线 15上； 在具体的实施过程中数据线输入的信号是通过与数据线相连的数据线驱动 K 输入的， 在实际生产中， 数据线驱动 IC成本远远高于栅线驱动 IC , 故在本 实施例中选择栅线条数加倍而数据线的条数减半， 在达到对每一像素独立驱 动的同时， 减少了价格成本高的数据线驱动 IC的应用， 从而降低了显示装置 整体的成本。
在传统的采用双栅 ( Dua l Ga te )驱动的显示装置， 由于一行像素由两条 栅线驱动， 从而 G0A单元也增加了一倍， 从而直接导致了阵列基板的非显示 区域的面积的增大， 导致显示装置的边框的加大， 从而不利于显示装置的窄 边框化以及小型化， 而在本实施例中由于 G0A单元可以同时驱动 N条栅线， 且 N为大于等于 2的整数， 为保持双栅驱动的阵列基板以及显示装置相对于 传统的单栅驱动的显示装置的非显示区域面积不变以及缩小提供了可能， 从 而有利于显示装置的小型化以及边框窄型化。
实施例八：
本实施例提供的显示装置， 包括本发明的实施例所述的阵列基板； 所述 阵列基板上设有本发明的实施例所述的 G0A电路， 此外所述阵列基板还包括 像素矩阵、 栅线以及数据线；
每一行像素与一条所述栅线相连；
每一列像素与一条所述数据线相连；
所述显示装置为液晶显示装置。 在本实施例中栅线的条数与像素矩阵中像素的行数相等， 数据线的条数 与像素矩阵中像素的列数相等。 且进一步的本实施例所述的像素装置为液晶 显示装置。
液晶显示装置通常包括阵列基板、 与阵列基板相对设置的对置基板以及 位于阵列基板与对置基板之间的液晶层； 所述对置基板通常为彩膜基板， 然 而在具体的应用过程中也可以将彩膜基板上的彩色滤光片设置在阵列基板 上， 此时与阵列基板对置的基板仅需是一个透明基板即可。
具体地， 阵列基板上设有像素电极、 薄膜晶体管 TFT; 所述薄膜晶体管 的漏极与所述像素电极相连， 所述薄膜晶体管的栅极与栅线相连， 所述薄膜 晶体管的源极与数据线相连； 栅线与 G0A电路一个时钟信号输出端相连； 栅 线与数据线相互垂直分布， 将整个基板分割成了一个个独立的像素空间， 像 素电极位于像素空间内。液晶层依据像素电极的驱动电压呈现不同旋光特性， 从而实现不同灰阶的呈现； 通过彩膜基板上色阻层实现滤光以呈现不同的颜 色（如 R/G/B色阻层形成三原色）， 再通过不同颜色光线的光混现象实现图像 的显示。 在具体的应用过程中， 所述色阻层的颜色也可以是其他颜色， 如黄 色等。
综合实施例六至实施例七， 本发明的实施例所述的显示装置， 由于采用 了本发明的实施例所述的 G0A电路， 相对采用传统的 G0A电路的显示装置， 具有栅极驱动电路结构精巧、 占用的面积小等多重优点。
实施例九：
极性反转驱动方法有多种方式， 包括帧极性反转驱动、 行或列极性反转 驱动以及单点极性反转驱动； 进行反转驱动是为了使液晶分子不在液晶层两 端电场长时间保持不变时， 液晶分子的特性遭到破坏， 而导致显示效果以及 显示性能的降低； 在具体的应用过程中单点极性反转的效果最佳， 但是能耗 较大。
其中， 帧极性反转驱动以及行或列极性反转驱动， 数据线中输出电压极 性反转的周期等于帧周期， 但是对显示装置的显示效果的改良效果较小； 单点极性反转为在同一帧内每一像素四周的像素的电压极性在同一时刻 与被环绕的像素的电压极性都是相反的， 故在进行像素刷新时开启一条栅线 的时间， 数据线就要实现一次电压极性反转， 反转的周期为 1 /P帧周期； P 为栅线的总数， 数据线输出电压的极性反转频率高是导致单点极性反转驱动 方法中驱动能耗大的最主要原因。
总结上述， 帧极性反转驱动以及行极性反转驱动， 数据线电压极性反转 周期小， 能耗较小， 但是对显示效果的改良效果较差， 极易出现图像闪烁； 单点极性反转驱动， 对显示效果的改良效果好， 但是数据线的电压极性反转 周期小， 导致能耗大；
首先， 本实施例基于本发明的实施例所提供的 G0A电路提供了一种与以 往极性反转驱动的不同的显示装置驱动方法， 可实现单点极性反转；
其次， 本实施例所述的显示装置的驱动方法， 可以用来 ^艮好的解决上述 矛盾， 能有效的调和显示改良效果和能耗之间的矛盾； 具体的本实施例所述 的显示装置的驱动方法用于实施例七所述的显示装置中， 具体包括：
将每一帧图像均分为 N场显示；
每一场周期内每一 G0A单元通过时钟信号开启一条栅线；
每一 G0A单元均顺序开启与其相连的栅线， 具体的如第一场 G0A单元通 过时钟信号开启与其相连的第一条栅线， 第二场则 G0A单元通过时钟信号开 启与其相连的第二条栅线。 每一场周期内所有数据线输出的电压极性相同； 第 4S+1场与第 4S+2场数据线的输出电压极性相反；
第 4S+2场与第 4S+3场数据线的输出电压极性相同；
第 4S+3场与第 4S+4场数据线的输出电压极性相反；
其中， S为自然数， 4 S+4小于或等于 N;
所述 N为每一 G0A单元输出的时钟信号的个数， 且为 4的倍数。 为了实 现像素刷新， 每开启一条栅线， 所有的数据线需输入信号一次； 在本实施例 中每一场数据线扫描的次数为 M次， 在本实施例中可知数据线的输出电压极 性反转的周期不小于场周期即 1 /N帧周期。 故相对于传统技术中与本实施例 所述的显示装置栅线条数相等的显示装置， 本实施例数据线的电压极性反转 周期至少为传统的单点极性反转数据线的输出电压极性反转周期的 M倍， 反 转周期大大拉长了， 从而有利于降低能耗， 故本实施例所述的显示装置的驱 耗的矛盾。
以下是一个基于本实施例所述的显示装置的单点反转驱动方法的实例： 所述阵列基板上包括本发明的实施例所述的 G0A电路， 且所述 G0A电路 中的每一个 G0A单元与 4条栅线相连； 第一 1 / 4帧周期即第一场， STVP信号如图 4中 1所示， 相应的第一源信 号 CLKV、 第二源信号 CLKB、 第一个时钟信号 CLK1、 第二个时钟信号 CLK2、 第三个时钟信号 CLK 3、 第四个时钟信号 CLK4、 以及依次开启的栅线为 Gl、 G5 ··. ··. Gn- 3 , 其中 n为栅线条数； 且开启的栅线之间开启的时序如图所示； 此时每一个 G0A单元中仅有第一个时钟信号 CLK1为高电平，即仅对应了第一 个时钟信号的栅线 Gl、 G5…… Gn-3开启;
同时如图 8所示，对应的每一个 G0A单元第一个时钟信号的栅线开启后， 奇数列奇数行像素的电压极性为正 （在图示中用 "+" 表示）， 在这一场中所 有的数据线输出的电压极性均为正；
第二个 1 /4帧周期即第二场， STVP信号如图 5中 2所示， 相应的第一源 信号 CLKV、 第二源信号 CLKB、 第一个时钟信号 CLK1、 第二个时钟信号 CLK2、 第三个时钟信号 CLK 3、第四个时钟信号 CLK4、 以及开启的栅线为 G2、 G6…… Gn-2 , 其中 n为栅线条数； 且开启的栅线之间开启的时序如图所示； 此时每 一个 G0A单元中仅有第二个时钟信号 CLK2为高电平，即仅对应了第二个时钟 信号的栅线 G2、 G6 ··· ··· Gn-2开启;
同时如图 9所示，对应的每一个 G0A单元第二个时钟信号的栅线开启后， 偶数列奇数行像素的电压极性为负 （在图示中用 "-" 表示）， 在这一场所有 的数据线输出的电压极性均为负；
由上述可知第一场与第二场数据线的输出电压极性改变了一次， 此时数 据线输出电压极性的反转周期为场周期， 即为 1 /N帧周期；
第三个 1 /4帧周期即第三场， 第三个 1 /4帧周期， STVP信号如图 6中 3 所示， 相应的第一源信号 CLKV、 第二源信号 CLKB、 第一个时钟信号 CLK 1、 第二个时钟信号 CLK2、 第三个时钟信号 CLK 3、 第四个时钟信号 CLK4、 以及 开启的栅线为 G 3、 G7 ··. ··. Gn-1 , 其中 n为栅线条数； 且开启的栅线之间开启 的时序如图所示；此时每一个 G0A单元中仅有第三个时钟信号 CLK 3为高电平， 即仅对应了第三个时钟信号的栅线 G 3、 G7 ... ... Gn-1开启；
同时如图 1 0所示，对应的每一个 G0A单元第三个时钟信号的栅线开启后， 驱动的是奇数列偶数行像素， 且奇数列偶数行的电压极性为负 （在图示中用 "-" 表示）；
由此可知第三场的数据线输出电压极性与第二场相同， 相当于此时数据 输出的电压极性保持不变的时间为 2/N个帧周期； 第四个 1 /4帧周期即第四场， STVP信号如图 7中 4所示， 相应的第一 源信号 CLKV、第二源信号 CLKB、第一个时钟信号 CLK1、第二个时钟信号 CLK2、 第三个时钟信号 CLK 3、第四个时钟信号 CLK4、 以及开启的栅线为 G4、 G8…… Gn , 其中 n为栅线条数； 且开启的栅线之间开启的时序如图所示； 此时每一 个 G0A单元中仅有第四个时钟信号 CLK4为高电平，即仅对应了第四个时钟信 号的栅线 G4、 G8 ... ... Gn开启；
同时如图 1 1所示，对应的每一个 G0A单元第四个时钟信号的栅线开启后， 驱动为偶数列偶数行像素，且被驱动的偶数列偶数行像素的电压极性为正（在 图示中用 "+" 表示）；
故第四场相对于第三场， 所有数据线的输出电压的极性都改变了， 此时 数据线输出电压的极性反转周期为 1 /N帧周期；
综合上述， 本实施例所述的显示装置的驱动方法， 相对于传统的单点驱 动方法， 数据线输出电压极性反转的周期大大的增加了， 从而数据线输出电 压的反转频率大大的降低了， 从而降低了能耗， 且因为是单点驱动从而保证 良好的显示效果。
实施例十： 动方法， 所述 G0A电路中的每一个 G0A单元与 4条栅线相连， 具体如下： 每一帧的第一 1 / 4帧周期即为第一场， STVP信号如图 4中 1所示， 相应 的第一源信号 CLKV、 第二源信号 CLKB、 第一个时钟信号 CLK1、 第二个时钟 信号 CLK2、 第三个时钟信号 CLK 3、 第四个时钟信号 CLK4、 以及开启的栅线 为 Gl、 G5…… Gn-3 , 其中 n为栅线条数； 且开启的栅线之间开启的时序如图 所示； 此时每一个 G0A单元中仅有第一个时钟信号 CLK1为高电平， 即仅对应 了第一个时钟信号的栅线 Gl、 G5…… Gn3开启；
同时如图 1 2所示，对应的每一个 G0A单元第一个时钟信号的栅线开启后： 开启栅线对应的像素行中所有的奇数列像素的电压极性为正（在图示中 用 "+" 表示）， 对应的驱动奇数列像素的数据线的电压极性为正；
开启栅线对应的像素行中所有的偶数列像素电压极性为负 （在图示中用 "-" 表示）， 对应的驱动偶数列像素的数据线的电压极性为负；
第二个 1 /4帧周期即为第二场， STVP信号如图 5中 2所示， 相应的第一 源信号 CLKV、第二源信号 CLKB、第一个时钟信号 CLK1、第二个时钟信号 CLK2、 第三个时钟信号 CLK 3、第四个时钟信号 CLK4、 以及开启的栅线为 G2、 G6…… Gn-2 , 其中 n为栅线条数； 且开启的栅线之间开启的时序如图所示； 此时每 一个 G0A单元中仅有第二个时钟信号 CLK2为高电平，即仅对应了第二个时钟 信号的栅线 G2、 G6 ··· ··· Gn_2开启；
同时如图 1 3所示，对应的每一个 G0A单元第二个时钟信号的栅线开启后： 开启栅线对应的像素行中偶数列像素的电压极性为正（在图示中用 "+" 表示 ), 对应的驱动偶数列像素的数据线的电压极性为正；
开启栅线对应的像素行中奇数列像素电压极性为负 （在图示中用 "-"表 示；)， 对应的驱动奇数列像素的数据线的电压极性同样为负；
第三个 1 /4帧周期即为第三场， STVP信号如图 6中 3所示， 相应的第一 源信号 CLKV、第二源信号 CLKB、第一个时钟信号 CLK1、第二个时钟信号 CLK2、 第三个时钟信号 CLK 3、第四个时钟信号 CLK4、 以及开启的栅线为 G 3、 G7…… Gn-1 , 其中 n为栅线条数； 且开启的栅线之间开启的时序如图所示； 此时每 一个 G0A单元中仅有第三个时钟信号 CLK 3为高电平，即仅对应了第三个时钟 信号的栅线 G 3、 G7 ... ... Gn_l开启；
同时如图 14所示，对应的每一个 G0A单元第三个时钟信号的栅线开启后， 开启栅线对应的像素行中奇数列像素的电压极性为正（在图示中用 "+" 表示 ), 对应的驱动奇数列像素的数据线的电压极性为正；
开启栅线对应的像素行中偶数列像素电压极性为负 （在图示中用 "-"表 示）， 对应的驱动偶数列像素的数据线的电压极性同样为负；
第四个 1 /4帧周期即为第四场， STVP信号如图 7中 4所示， 相应的第 一源信号 CLKV、 第二源信号 CLKB、 第一个时钟信号 CLK1、 第二个时钟信号 CLK2、 第三个时钟信号 CLK 3、 第四个时钟信号 CLK4、 以及开启的栅线为 G4、 G8 ··. ··. Gn , 其中 n为栅线条数； 且开启的栅线之间开启的时序如图所示； 此 时每一个 G0A单元中仅有第四个时钟信号 CLK4为高电平，即仅对应了第四个 时钟信号的栅线 G4、 G8…… Gn开启；
同时如图 14所示，对应的每一个 G0A单元第四个时钟信号的栅线开启后： 开启栅线对应的像素行中偶数列像素的电压极性为正（在图示中用 "+" 表示 ), 对应的驱动偶数列像素的数据线的电压极性为正；
开启栅线对应的像素行中奇数列像素电压极性为负 （在图示中用 "-"表 示；)， 对应的驱动奇数列像素的数据线的电压极性同样为负； 其中， 在具体的实施过程中， 可以通过改变 CLK1-CLK4时钟的周期的起 始点进行平移， 则开启的栅线就不同了， 数据线电压极性的起始可以是正也 可以是负， 仅需满足点极性反转的需求即可。
当本实施例所述的极性反转驱动方法， 不仅继承了传统的单点极性反转 驱动方法的良好的驱动效果， 同时相对于传统的点极性反转驱动方法， 数据 线的电压极性反转周期延长至 1 /4帧周期， 数据线输出电压反转频率低， 从 而大大的降低了能耗。
以上实施方式仅用于说明本发明的实施例， 而并非对本发明的限制， 有 关技术领域的普通技术人员， 在不脱离本发明的实施例的精神和范围的情况 下， 还可以做出各种变化和变型， 因此所有等同的技术方案也属于本发明的 范畴， 本发明的专利保护范围应由权利要求限定。

Claims

权 利 要 求 书
1、 一种 GOA电路， 包括时钟信号输入线以及级联的两个以上的 GOA单元， 其中，
所述 G0A单元包括选择信号输出子单元以及选择子单元；
所述选择信号输出子单元， 用以接收源信号， 并根据源信号输出选择信 号；
所述选择子单元， 接收所述选择信号和 N个时钟信号， 并根据所述选择信 号输出所接收的时钟信号；
所述时钟信号输入线至少为 N根， 用以向所述选择子单元输入时钟信号； 其中 N为大于或等于 2的整数。
2、 根据权利要求 1所述的 G0A电路， 其中， 所述 G0A电路还包括开启信号 线；
所述选择信号输出子单元包括源信号输入端一、 源信号输入端二、 开启 信号输入端、 信号输出端一、 信号输出端二以及复位信号输入端；
所述源信号输入端一用以输入第一源信号；
所述源信号输入端二用以输入第二源信号；
所述信号输出端一与所述选择子单元相连， 用以输出根据第一源信号和 第二源信号产生的选择信号；
第一个所述 G0A单元的选择信号输出子单元的开启信号输入端与所述开 启信号线相连， 用以接收开启信号， 第一个 G0A单元的选择信号输出子单元 的复位信号输入端与第二个所述 G0A单元的选择信号输出子单元的信号输出 端一相连， 接收第二个所述 G0A单元的选择信号输出子单元的信号输出端一 输出的选择信号；
第 m个所述 G0A单元的选择信号输出子单元的开启信号输入端与第 m-1 个所述 GOA单元的选择信号输出子单元的信号输出端二相连， 接收第 m-1个 所述 G0A单元的选择信号输出子单元的信号输出端二的选择信号； 第 m个所 述 G0A单元的选择信号输出子单元的复位信号输入端与第 m+1个所述 G0A单 元的选择信号输出子单元的信号输出端一相连， 接收第 m+1个所述 GOA单元 的选择信号输出子单元的信号输出端一输出的选择信号；
第 M个所述 G0A单元的选择信号输出子单元的开启信号输入端与第 M-1 个所述 GOA单元的选择信号输出子单元的信号输出端二相连， 接收第 M-1个 所述 G0A单元的选择信号输出子单元的信号输出端二的选择信号， 第 M个所 述 G0A单元的选择信号输出子单元的复位信号输入端与所述开启信号线相 连； 其中， m为自然数， 所述 M > m > l , 所述 M为 GOA单元的数量。
3、 根据权利要求 1或 2所述的 G0A电路， 其中，
所述选择子单元包括 N个时钟信号输入端、 选择信号输入端以及 N个时 钟信号输出端；
所述 N个时钟信号输入端分别与所述 N根时钟信号输入线相连， 用以输 入时钟信号；
所述选择信号输入端， 用以接收所述选择信号输出子单元输出的选择信 号；
所述时钟信号输出端， 根据所述选择信号输出所接收的时钟信号。
4、 根据权利要求 3所述所述的 G0A电路， 其中，
所述 =4 ;
所述 G0A单元还包括栅线导通电压线以及栅线关断电压线；
所述选择子单元包括上拉模块、 保持模块、 与所述栅线导通电压线相连 的栅线导通电压输入端和与所述栅线关断电压线相连的栅线关断电压输入 端；
所述上拉模块包括第一晶体管、 第二晶体管、 第三晶体管以及第四晶体 管；
所述第一晶体管、 第二晶体管、 第三晶体管以及第四晶体管的栅极均与 所述选择信号输入端相连；
所述第一晶体管的漏极与第一个时钟信号输入端相连， 源极与第一个时 钟信号输出端相连用以向外输出第一时钟信号；
所述第二晶体管的漏极与第二个时钟信号输入端相连， 源极与第二个时 钟信号输出端相连用以向外输出第二时钟信号；
所述第三晶体管的漏极与第三个时钟信号输入端相连， 源极与第三个时 钟信号输出端相连用以向外输出第三时钟信号；
所述第四晶体管的漏极与第四个时钟信号输入端相连， 源极与第四个时 钟信号输出端相连用以向外输出第四时钟信号；
所述保持模块包括第五晶体管、 第六晶体管、 第七晶体管、 第八晶体管、 第九晶体管以及第十晶体管；
所述第五晶体管的栅极和漏极均与栅线导通电压输入端相连， 源极与所 述第六晶体管的漏极相连；
所述第六晶体管的栅极与选择信号输入端相连， 源极与栅线信号关断电 压线相连；
所述第七晶体管、 第八晶体管、 第九晶体管以及第十晶体管的栅极均连 接在所述第五晶体管的源极；
所述第七晶体管的漏极与第一晶体管的源极相连， 源极与栅线关断电压 输入端相连；
所述第八晶体管的漏极与第二晶体管的源极相连， 源极与栅线关断电压 输入端相连；
所述第九晶体管的漏极与第三晶体管的源极相连， 源极与栅线关断电压 输入端相连；
所述第十晶体管的漏极与第四晶体管的源极相连， 源极与栅线关断电压 输入端相连。
5、 一种阵列基板， 包括如权利要求 1-4任一项所述的 G0A电路以及若干 栅线；
每一所述选择子单元分别与 N条连续分布的栅线相连；
其中， 所述 N与所述 G0A电路中的所述 G0A单元总数 M的乘积等于所述 栅线总的条数。
6、 一种显示装置， 包括如权利要求 5所述的阵列基板。
7、 根据权利要求 6所述的显示装置， 其中， 所述阵列基板还包括像素矩 阵、 栅线以及数据线；
每一行像素对应两条栅线， 且所述两条栅线分为第一栅线和第二栅线； 奇数列像素与第一栅线相连， 偶数列像素与第二栅线相连；
2 i+l列像素和 2 ( i+1 ) 列像素共用一条数据线， i为自然数； 所述显示装置为液晶显示装置。
8、 根据权利要求 6所述的显示装置， 其中， 所述阵列基板还包括像素矩 阵、 栅线以及数据线；
每一行像素与一条所述栅线相连；
每一列像素与一条所述数据线相连； 所述显示装置为液晶显示装置。
9、 一种显示装置驱动方法， 用于如权利要求 7所述的显示装置， 将每一帧图像均分为 N场显示；
每一场周期内每一 G0A单元通过时钟信号开启一条栅线；
每一 G0A单元均顺序开启与其相连的栅线；
每一场周期内所有数据线输出的电压极性相同；
第 4S+1场与第 4S+2场数据线的输出电压极性相反；
第 4S+2场与第 4S+3场数据线的输出电压极性相同；
第 4S+3场与第 4S+4场数据线的输出电压极性相反；
其中， S为自然数， 4 S+4小于或等于 N;
所述 N为每一 G0A单元输出的时钟信号的个数， 且为 4的倍数。
1 0、 一种显示装置驱动方法， 用于如权利要求 8所述的显示装置， 将每一帧图像均分为 N场显示；
每一场周期内每一 G0A单元通过时钟信号开启一条栅线；
每一 G0A单元均顺序开启与其相连的栅线；
每一数据线输出电压的极性反转周期等于场周期， 且相邻两条数据线输 出电压极性总是相反；
其中， 所述 N为每一 G0A单元输出的时钟信号的个数。
PCT/CN2013/089480 2013-07-18 2013-12-16 Goa电路、阵列基板、显示装置及驱动方法 WO2015007052A1 (zh)

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