WO2015096207A1 - 一种阵列基板驱动电路、阵列基板及相应的液晶显示器 - Google Patents

一种阵列基板驱动电路、阵列基板及相应的液晶显示器 Download PDF

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Publication number
WO2015096207A1
WO2015096207A1 PCT/CN2014/070316 CN2014070316W WO2015096207A1 WO 2015096207 A1 WO2015096207 A1 WO 2015096207A1 CN 2014070316 W CN2014070316 W CN 2014070316W WO 2015096207 A1 WO2015096207 A1 WO 2015096207A1
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Prior art keywords
thin film
film transistor
goa
output terminal
driving unit
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PCT/CN2014/070316
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English (en)
French (fr)
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徐向阳
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深圳市华星光电技术有限公司
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Priority to US14/235,129 priority Critical patent/US20150221272A1/en
Publication of WO2015096207A1 publication Critical patent/WO2015096207A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0272—Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the invention relates to an array substrate driving circuit, an array substrate and a corresponding liquid crystal display.
  • the application is submitted to the Chinese Patent Office on December 26, 2013, and the application number is 201310730254.4, and the invention name is "an array substrate driving circuit, an array substrate and corresponding The priority of the Chinese Patent Application for Liquid Crystal Display, the entire contents of which are incorporated herein by reference.
  • the present invention relates to the field of Thin Film Transistor liquid crystal display (TFT-LCD), and more particularly to an array substrate driving circuit, an array substrate, and a corresponding liquid crystal display.
  • TFT-LCD Thin Film Transistor liquid crystal display
  • the liquid crystal display technology has developed rapidly, and has made great progress from the size of the screen to the quality of the display.
  • the liquid crystal display has the characteristics of small size, low power consumption, no radiation, etc., and now occupies a dominant position in the field of flat display. .
  • high resolution, high contrast, high refresh rate, narrow bezel, and thinness have become the development trend of liquid crystal displays;
  • TFT Thin Film Transistor
  • GoA Gate On Array
  • FIG. 1 a schematic diagram of a structure of a unilaterally driven array substrate driving circuit in the prior art is shown.
  • each row corresponds to a GoA driving unit, usually a GoA driving unit.
  • GoA driving unit usually a GoA driving unit.
  • the frame design will be wider for the panel side of the GoA circuit, which is not conducive to the narrow bezel design.
  • FIG. 2 a schematic structural diagram of a matrix driving circuit using a bilateral driving in the prior art is shown.
  • the bilaterally driven array substrate it is a symmetrical structure, and each row uses two GoA driving units for bilateral Drive, the advantage of this design is to improve the gate drive capability.
  • the disadvantage is that the circuit is complicated, and the GoA drive unit occupies a large area, which is more disadvantageous for the narrow bezel design.
  • the technical problem to be solved by the present invention is to provide an array substrate driving circuit, an array substrate and a corresponding liquid crystal display, which can reduce the area occupied by the array substrate driving circuit and facilitate the narrow bezel design of the liquid crystal display.
  • an aspect of an embodiment of the present invention provides an array substrate driving circuit including a plurality of GoA driving units for driving gate lines of an array substrate, wherein each GoA driving unit is connected to one gate line ;
  • the GoA driving unit connected to the gate line of the odd row is disposed on one side of the array substrate, and the GoA driving unit connected to the even line of the gate line is disposed on the other side of the array substrate;
  • Each GoA driving unit has a first driving signal input end, a second driving signal input end and an output end.
  • the first driving signal input end is connected to the output end of the upper GoA driving unit, and the second driving signal input end and the lower level GoA
  • the output of the drive unit is connected to the output terminal of the GoA drive unit.
  • Each GoA driving unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a storage capacitor, wherein:
  • the source and the gate of the first thin film transistor are both connected to the signal output end of the upper GoA driving unit, and the drain thereof is respectively connected to the gate of the second thin film transistor, one end of the storage capacitor, and the drain of the third thin film transistor. ;
  • the source of the second thin film transistor is connected to the clock signal output end, the gate thereof is connected to the first end of the storage capacitor, and the drain and the signal output end of the current stage, the source of the fourth thin film transistor, and the storage capacitor Two ends are connected;
  • the source of the third thin film transistor is connected to the first end of the storage capacitor, and the gate thereof is connected to the signal output end of the lower GoA driving unit, and the source thereof is connected to the low potential input line or ground;
  • the source of the fourth thin film transistor is connected to the signal output end of the current stage and the second end of the storage capacitor, and the gate thereof is connected to the signal output end of the lower GoA driving unit, and the drain thereof is connected to the low potential input line or to the ground.
  • the clock signal output end connected to each GoA driving unit connected to each gate line of the odd row is the output end of the first clock signal
  • the signal output end connected to each GoA driving unit connected to each gate line of the even row As the output end of the second clock signal, the first clock signal and the second clock signal have the same period length, and the phases are different by half a cycle.
  • the first driving signal input end of the front-end GoA driving unit is connected with a sweep
  • the trigger signal line is used to trigger the GoA drive unit at the front end to start working.
  • another aspect of the embodiments of the present invention provides an array substrate of a liquid crystal display, including a plurality of pixel units defined by gate lines and data lines, each of which forms a thin film transistor and a pixel electrode; further comprising An array substrate driving circuit for driving a gate line, wherein the driving circuit comprises a plurality of GoA driving units, wherein an output end of each GoA driving unit is connected to a gate line;
  • the GoA driving unit connected to the gate line of the odd row is disposed on one side of the array substrate, and the GoA driving unit connected to the even line of the gate line is disposed on the other side of the array substrate;
  • Each GoA driving unit has a first driving signal input end, a second driving signal input end and an output end.
  • the first driving signal input end is connected to the output end of the upper GoA driving unit, and the second driving signal input end and the lower level GoA
  • the output of the drive unit is connected to the output terminal of the GoA drive unit.
  • Each GoA driving unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a storage capacitor, wherein:
  • the source and the gate of the first thin film transistor are both connected to the signal output end of the upper GoA driving unit, and the drain thereof is respectively connected to the gate of the second thin film transistor, one end of the storage capacitor, and the drain of the third thin film transistor. ;
  • the source of the second thin film transistor is connected to the clock signal output end, the gate thereof is connected to the first end of the storage capacitor, and the drain and the signal output end of the current stage, the source of the fourth thin film transistor, and the storage capacitor Two ends are connected;
  • the source of the third thin film transistor is connected to the first end of the storage capacitor, and the gate thereof is connected to the signal output end of the lower GoA driving unit, and the source thereof is connected to the low potential input line or ground;
  • the source of the fourth thin film transistor is connected to the signal output end of the current stage and the second end of the storage capacitor, and the gate thereof is connected to the signal output end of the lower GoA driving unit, and the drain thereof is connected to the low potential input line or to the ground.
  • the clock signal output end connected to each GoA driving unit connected to the odd line and the gate line is the output end of the first clock signal
  • the signal output end connected to each GoA driving unit connected to the even line and the gate line As the output end of the second clock signal, the first clock signal and the second clock signal have the same period length, and the phases are different by half a cycle.
  • a liquid crystal display includes: an array substrate;
  • liquid crystal layer disposed between the array substrate and the color filter substrate
  • the array substrate includes a plurality of pixel units defined by the gate lines and the data lines, and a thin film transistor and a pixel electrode are formed in each of the pixel units. Further, the array substrate further includes an array substrate driving circuit for driving the gate lines, and the driving circuit includes a plurality of GoA driving unit, the output end of each GoA driving unit is connected to a gate line;
  • the GoA driving unit connected to the gate line of the odd row is disposed on one side of the array substrate, and the GoA driving unit connected to the even line of the gate line is disposed on the other side of the array substrate;
  • Each GoA driving unit has a first driving signal input end, a second driving signal input end and an output end.
  • the first driving signal input end is connected to the output end of the upper GoA driving unit, and the second driving signal input end and the lower level GoA
  • the output of the drive unit is connected to the output terminal of the GoA drive unit.
  • Each GoA driving unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a storage capacitor, wherein:
  • the source and the gate of the first thin film transistor are both connected to the signal output end of the upper GoA driving unit, and the drain thereof is respectively connected to the gate of the second thin film transistor, one end of the storage capacitor, and the drain of the third thin film transistor. ;
  • the source of the second thin film transistor is connected to the clock signal output end, the gate thereof is connected to the first end of the storage capacitor, and the drain and the signal output end of the current stage, the source of the fourth thin film transistor, and the storage capacitor Two ends are connected;
  • the source of the third thin film transistor is connected to the first end of the storage capacitor, and the gate thereof is connected to the signal output end of the lower GoA driving unit, and the source thereof is connected to the low potential input line or ground;
  • the source of the fourth thin film transistor is connected to the signal output end of the current stage and the second end of the storage capacitor, and the gate thereof is connected to the signal output end of the lower GoA driving unit, and the drain thereof is connected to the low potential input line or to the ground.
  • the clock signal output end connected to each GoA driving unit connected to the odd line and the gate line is the output end of the first clock signal
  • the GoA driving units connected to the even line and the gate line The connected signal output end is the output end of the second clock signal
  • the first clock signal and the second clock signal have the same period length, and the phases are different by half a cycle.
  • the first driving signal input end of the frontmost GoA driving unit is connected with a scanning trigger signal line for triggering the frontmost GoA driving unit to start working.
  • a plurality of GoA driving units are respectively disposed on two sides of the array substrate, and the odd-line rows of the gate lines are alternately driven by the GoA driving units on both sides; thereby greatly reducing the area occupied by the driving circuit, and The complicated program of the driving circuit on each side is reduced, thereby facilitating the narrow frame design of the liquid crystal display.
  • FIG. 1 is a schematic structural view of an array substrate driving circuit using a single-side driving in the prior art
  • FIG. 2 is a schematic structural view of an array substrate driving circuit using a bilateral driving in the prior art
  • FIG. 3 is a schematic diagram of an array substrate driving circuit of the present invention. Schematic diagram of the structure of the embodiment;
  • FIG. 4 is a circuit schematic diagram of an embodiment of the GoA driving unit of FIG. 3;
  • Fig. 5 is a view showing the relationship of driving timings of the array substrate driving circuit of the present invention.
  • the array substrate driving circuit includes a plurality of GoA driving units for driving gate lines of the array substrate, wherein , each GoA driving unit is connected to a gate line;
  • a GoA driving unit connected to the gate line of the odd row is disposed on one side of the array substrate, and a GoA driving unit connected to the even line of the gate line is disposed on the other side of the array substrate;
  • Each GoA driving unit has a first driving signal input end, a second driving signal input end and an output end. The first driving signal input end is connected to the output end of the upper GoA driving unit, and the second driving signal input end and the lower level GoA The output of the drive unit is connected to the output terminal of the GoA drive unit.
  • the first driving signal input end of the frontmost GoA driving unit is connected with a scanning trigger signal line (STV) for triggering the frontmost GoA driving unit to start working.
  • STV scanning trigger signal line
  • the clock signal output terminals connected to the GoA driving units connected to the odd-numbered row gate lines are the output terminal Clk_A of the first clock signal, and the GoA drivers connected to the even-numbered row gate lines.
  • the signal output end connected to the unit is the output terminal Clk_B of the second clock signal.
  • the first clock signal and the second clock signal are set to a period. The length is the same, the phase is different by half a cycle, that is, when the first clock signal is at a high level, the second clock signal is at a low level, and when the first clock signal is at a low level, the second clock signal is at a high level. level.
  • a low-potential input line (Vss) is respectively disposed on both sides, and is respectively connected to each GoA driving unit. It can be understood that in other embodiments, the low-potential input line can be directly grounded.
  • each of the GoA driving units includes a first thin film transistor TFT1, a second thin film transistor TFT2, a third thin film transistor TFT3, a fourth thin film transistor TFT4, and a storage capacitor Cb, wherein:
  • the source and the gate of the first thin film transistor TFT1 are used as the first driving signal input end, and are connected to the signal output terminal N-1 of the upper GoA driving unit, and the drain thereof and the gate of the second thin film transistor TFT2 are respectively stored.
  • the first end of the capacitor Cb and the drain of the third thin film transistor TFT3 are connected;
  • the source of the second thin film transistor TFT2 is connected to the clock signal output end, and the gate thereof is connected to the first end of the storage capacitor Cb, and the drain thereof
  • the pole is connected to the signal output end of the current stage, the source of the fourth thin film transistor TFT4, and the second end of the storage capacitor Cb;
  • the source of the third thin film transistor TFT3 is connected to the first end of the storage capacitor Cb, and the gate thereof is used as the second driving signal input end, and is connected to the signal output terminal N+1 of the lower GoA driving unit, and the source thereof is connected to the low potential input line. (Vss) or grounded;
  • the source of the fourth thin film transistor TFT4 is connected to the signal output terminal N of the current stage and the second end of the storage capacitor Cb, and the gate line thereof is connected to the signal output terminal N+1 of the lower GoA driving unit, and the drain thereof is connected to the low potential input line ( Vss) or ground.
  • the input signal of the signal output terminal N-1 of the upper GoA drive unit is at a high level
  • the Clk signal is at a low level
  • the signal of the lower GoA drive unit is The input signal of the N+1 terminal is low, and the first thin film transistor TFT1 and the second thin film transistor TFT2 are turned on, the third thin film transistor TFT3 and the fourth thin film transistor TFT4 are turned off, and the output signal of the first thin film transistor TFT1 is turned off.
  • the storage capacitor Cd is driven by the output signal (high level signal) of the first thin film transistor TFT1;
  • the input signal of the signal output terminal N-1 of the upper GoA drive unit is low level
  • the Clk signal is high level
  • the signal output of the lower GoA drive unit The terminal N+1 signal is at a low level
  • the first thin film transistor TFT1, the third thin film transistor TFT3, and the fourth thin film transistor TFT4 are turned off, the second thin film transistor TFT2 is turned on, and the high output is outputted at the signal output terminal N of the current stage.
  • the signal output terminal N-1 of the upper GoA driving unit is at a low level
  • the Clk signal is at a low level
  • the signal output terminal N+ of the lower GoA driving unit is 1 signal is at a high level
  • the third thin film transistor TFT3 and the fourth thin film transistor TFT4 are turned on, the first thin film transistor TFT1 and the second thin film transistor TFT2 are turned off; the third thin film transistor TFT3 is turned on to make the capacitor Cd low. / Ground and discharge, after the fourth thin film transistor TFT4 is turned on, the signal output terminal N of the current stage is connected to the low potential / ground and discharged.
  • the GoA driving units on both sides of the array substrate alternately drive the gate lines of the odd-even rows, so that the gate lines are started line by line.
  • the first GoA driving unit on the left side drives the first line first.
  • a gate line (G1) then the first GoA drive unit on the right side drives the second gate line (G2), and then the second GoA drive unit on the left side drives the third gate line (G3), then the right side
  • the first GoA driving unit drives the fourth gate line (G4).
  • each gate line of the parity row is alternately driven by the GoA driving units on both sides, so that the gate lines are activated line by line.
  • FIG. 4 above shows a driving circuit driven by four TFT transistors.
  • other numbers of TFT transistors may be used for replacement.
  • a driving circuit driven by five TFT transistors may be used.
  • a plurality of GoA driving units are respectively disposed on both sides of the array substrate, and the odd-line rows of the gate lines are alternately driven by the GoA driving units on both sides; thereby greatly reducing the area occupied by the driving circuit, and each The complicated program of the driving circuit on one side is also reduced, thereby facilitating the narrow frame design of the liquid crystal display.
  • an embodiment of the present invention further provides an array substrate of a liquid crystal display, including a plurality of pixel units defined by gate lines and data lines, each of which forms a thin film transistor and a pixel electrode; further comprising a gate line for driving
  • the array substrate driving circuit and the driving circuit adopt the driving circuit as disclosed in FIG. 3 and FIG. 4 .
  • FIG. 3 and FIG. 5 For further details, reference may be made to the foregoing description of FIG. 3 to FIG. 5 , and details are not described herein.
  • an embodiment of the present invention further provides a liquid crystal display, comprising: an array substrate; a color filter substrate opposite to the array substrate; and a liquid crystal layer disposed between the array substrate and the color filter substrate;
  • the array substrate is the aforementioned driving circuit as disclosed in FIG. 3 and FIG. 4.
  • FIG. 3 and FIG. 4 For further details, reference may be made to the foregoing description of FIG. 3 to FIG. 5, which is not described herein.
  • a plurality of GoA driving units are respectively disposed on two sides of the array substrate, and the odd-line rows of the gate lines are alternately driven by the GoA driving units on both sides; thereby greatly reducing the area occupied by the driving circuit, and The complicated program of the driving circuit on each side is reduced, thereby facilitating the narrow frame design of the liquid crystal display.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种阵列基板驱动电路，包括多个GOA驱动单元，其中，每一GOA驱动单元连接一条栅线；奇数行的栅线所连接的GOA驱动单元设置在阵列基板的一侧，偶数行的栅线所连接的GOA驱动单元设置在阵列基板的另一侧；每一GOA驱动单元均具有两个驱动信号输入端以及一个输出端，两个驱动信号输入端分别连接上级GOA驱动单元的输出端和下级GOA驱动单元的输出端，接收上级GOA驱动单元和下线GOA驱动单元输出的驱动信号，并通过输出端输出本级驱动信号至与其连接的栅线，位于阵列基板的两侧的各GOA驱动单元交替驱动阵列基板的各栅线。还提供了一种阵列基板和液晶显示器。该阵列基板驱动电路、阵列基板和液晶显示器可以减少阵列基板驱动电路所占的面积，利于液晶显示器的窄边框设计。

Description

一种阵列基板驱动电路、 阵列基板及相应的液晶显示器 本申请要求于 2013 年 12 月 26 日提交中国专利局、 申请号为 201310730254.4、 发明名称为 "一种阵列基板驱动电路、 阵列基板及相应的 液晶显示器" 的中国专利申请的优先权， 上述专利的全部内容通过引用结合 在本申请中。 技术领域
本发明涉及薄膜晶体管液晶显示器（Thin Film Transistor liquid crystal display, TFT-LCD )领域， 特别涉及一种阵列基板驱动电路、 阵列基板及相 应的液晶显示器。
背景技术
液晶显示器技术有了飞速的发展，从屏幕的尺寸到显示的质量都取得了 极大的进步， 液晶显示器具有体积小、 功耗低、 无辐射等特点， 现已占据了 平面显示领域的主导地位。 随着液晶显示技术的发展， 高分辨率、 高对比度、 高刷新速率、 窄边框、 薄型化已成为液晶显示器的发展趋势；
目前常采用 TFT ( Thin Film Transistor, 薄膜晶体管 )来设置 GoA ( Gate On Array, 阵列栅驱动） 电路， 为了实现液晶显示面板的窄边框、 薄型化和 低成本简化 GoA电路和缩小 GoA电路面积已非常重要。
如图 1所示， 示出了现有技术中采用单边驱动的阵列基板驱动电路的结 构示意图； 在该种单边驱动的阵列基板中， 每一行对应一个 GoA驱动单元， 通常 GoA驱动单元都采用 7个以上的 TFT晶体管，对于 GoA电路的面板一 侧， 边框设计就会较宽， 这样不利于窄边框设计。
如图 2所示， 示出了现有技术中采用双边驱动的阵列基板驱动电路的结构示 意图； 在该种双边驱动的阵列基板中， 其为对称结构， 每一行采用两个 GoA 驱动单元进行双边驱动， 这种设计的优点是提高栅极驱动能力， 缺点是电路 复杂， GoA驱动单元占用面积较大， 更加不利于窄边框设计。
发明内容 本发明所要解决的技术问题在于， 提供一种阵列基板驱动电路、 阵列基 板及相应的液晶显示器， 可以减少阵列基板驱动电路所占的面积， 有利于液 晶显示器的窄边框设计。
为了解决上述技术问题，本发明的实施例的一方面提供了一种阵列基板 驱动电路， 包括多个用于驱动阵列基板的栅线的 GoA驱动单元， 其中， 每 一 GoA驱动单元连接一条栅线；
奇数行的栅线所连接的 GoA驱动单元设置在阵列基板的一侧， 偶数行 的栅线所连接的 GoA驱动单元设置在阵列基板的另一侧；
每一 GoA驱动单元均具有第一驱动信号输入端、 第二驱动信号输入端 以及一个输出端， 第一驱动信号输入端与上级 GoA驱动单元的输出端相连， 第二驱动信号输入端与下级 GoA驱动单元的输出端相连， 与 GoA驱动单元 连接栅线连接在输出端上。
其中， 每一 GoA驱动单元包括第一薄膜晶体管、 第二薄膜晶体管、 第 三薄膜晶体管、 第四薄膜晶体管和储存电容， 其中：
第一薄膜晶体管的源极和栅极均与上级 GoA驱动单元的信号输出端相 连接， 其漏极分别与第二薄膜晶体管的栅极、 储存电容的一端、 第三薄膜晶 体管的漏极相连接；
第二薄膜晶体管的源极与时钟信号输出端相连接，其栅极与储存电容的 第一端相连接， 其漏极与本级信号输出端、 第四薄膜晶体管的源极、 储存电 容的第二端相连接；
第三薄膜晶体管的源极与储存电容的第一端连接，其栅极连接下级 GoA 驱动单元的信号输出端， 其源极接低电位输入线或接地；
第四薄膜晶体管的源极与本级信号输出端和储存电容的第二端相连， 其 栅极连接下级 GoA驱动单元的信号输出端， 其漏极接低电位输入线或接地。
其中， 奇数行的各栅线所连接的各 GoA驱动单元所连接的时钟信号输 出端为第一时钟信号的输出端， 偶数行的各栅线所连接的各 GoA驱动单元 所连接的信号输出端为第二时钟信号的输出端， 第一时钟信号与第二时钟信 号周期长度相同， 相位相差半个周期。
其中， 位于最前端的 GoA驱动单元的第一驱动信号输入端连接有一扫 描触发信号线， 用于触发位于最前端的 GoA驱动单元开始工作。 相应地， 本发明实施例的另一方面提供一种液晶显示器的阵列基板， 包 括由栅线和数据线限定的多个像素单元，每个像素单元内形成薄膜晶体管和 像素电极； 进一步包括有用于驱动栅线的阵列基板驱动电路， 其中， 驱动电 路包括多个 GoA驱动单元， 其中， 每一 GoA驱动单元的输出端连接一条栅 线；
奇数行的栅线所连接的 GoA驱动单元设置在阵列基板的一侧， 偶数行 的栅线所连接的 GoA驱动单元设置在阵列基板的另一侧；
每一 GoA驱动单元均具有第一驱动信号输入端、 第二驱动信号输入端 以及一个输出端， 第一驱动信号输入端与上级 GoA驱动单元的输出端相连， 第二驱动信号输入端与下级 GoA驱动单元的输出端相连， 与 GoA驱动单元 连接栅线连接在输出端上。
其中， 每一 GoA驱动单元包括第一薄膜晶体管、 第二薄膜晶体管、 第 三薄膜晶体管、 第四薄膜晶体管和储存电容， 其中：
第一薄膜晶体管的源极和栅极均与上级 GoA驱动单元的信号输出端相 连接， 其漏极分别与第二薄膜晶体管的栅极、 储存电容的一端、 第三薄膜晶 体管的漏极相连接；
第二薄膜晶体管的源极与时钟信号输出端相连接，其栅极与储存电容的 第一端相连接， 其漏极与本级信号输出端、 第四薄膜晶体管的源极、 储存电 容的第二端相连接；
第三薄膜晶体管的源极与储存电容的第一端连接，其栅极连接下级 GoA 驱动单元的信号输出端， 其源极接低电位输入线或接地；
第四薄膜晶体管的源极与本级信号输出端和储存电容的第二端相连， 其 栅极连接下级 GoA驱动单元的信号输出端， 其漏极接低电位输入线或接地。
其中， 奇数行的和栅线所连接的各 GoA驱动单元所连接的时钟信号输 出端为第一时钟信号的输出端， 偶数行的和栅线所连接的各 GoA驱动单元 所连接的信号输出端为第二时钟信号的输出端， 第一时钟信号与第二时钟信 号周期长度相同， 相位相差半个周期。
其中， 位于最前端的 GoA驱动单元的第一驱动信号输入端连接有一扫 描触发信号线， 用于触发位于最前端的 GoA驱动单元开始工作。 相应地， 本发明实施例的再一方面， 还提供一种液晶显示器， 包括： 阵列基板；
彩色滤光片基板， 与阵列基板相对； 以及
液晶层， 配置于阵列基板与彩色滤光片基板之间；
其中， 阵列基板包括由栅线和数据线限定的多个像素单元， 每个像素单 元内形成薄膜晶体管和像素电极； 其中， 进一步包括有用于驱动栅线的阵列 基板驱动电路， 驱动电路包括多个 GoA驱动单元， 每一 GoA驱动单元的输 出端连接一条栅线；
奇数行的栅线所连接的 GoA驱动单元设置在阵列基板的一侧， 偶数行 的栅线所连接的 GoA驱动单元设置在阵列基板的另一侧；
每一 GoA驱动单元均具有第一驱动信号输入端、 第二驱动信号输入端 以及一个输出端， 第一驱动信号输入端与上级 GoA驱动单元的输出端相连， 第二驱动信号输入端与下级 GoA驱动单元的输出端相连， 与 GoA驱动单元 连接栅线连接在输出端上。
其中， 每一 GoA驱动单元包括第一薄膜晶体管、 第二薄膜晶体管、 第 三薄膜晶体管、 第四薄膜晶体管和储存电容， 其中：
第一薄膜晶体管的源极和栅极均与上级 GoA驱动单元的信号输出端相 连接， 其漏极分别与第二薄膜晶体管的栅极、 储存电容的一端、 第三薄膜晶 体管的漏极相连接；
第二薄膜晶体管的源极与时钟信号输出端相连接，其栅极与储存电容的 第一端相连接， 其漏极与本级信号输出端、 第四薄膜晶体管的源极、 储存电 容的第二端相连接；
第三薄膜晶体管的源极与储存电容的第一端连接，其栅极连接下级 GoA 驱动单元的信号输出端， 其源极接低电位输入线或接地；
第四薄膜晶体管的源极与本级信号输出端和储存电容的第二端相连， 其 栅极连接下级 GoA驱动单元的信号输出端， 其漏极接低电位输入线或接地。
其中， 奇数行的和栅线所连接的各 GoA驱动单元所连接的时钟信号输 出端为第一时钟信号的输出端， 偶数行的和栅线所连接的各 GoA驱动单元 所连接的信号输出端为第二时钟信号的输出端， 第一时钟信号与第二时钟信 号周期长度相同， 相位相差半个周期。
其中， 位于最前端的 GoA驱动单元的第一驱动信号输入端连接有一扫 描触发信号线， 用于触发位于最前端的 GoA驱动单元开始工作。
实施本发明的实施例， 具有如下的有益效果：
本发明的实施例中， 将多个 GoA驱动单元分设在阵列基板的两侧， 并 且使栅线奇偶行分别采用两侧的 GoA驱动单元交替驱动； 从而大大减少了 驱动电路所占的面积， 以及降低了每一侧的驱动电路的复杂程序， 进而有利 于液晶显示器的窄边框化设计。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其它的附图。
图 1为现有技术中采用单边驱动的阵列基板驱动电路的结构示意图； 图 2为现有技术中采用双边驱动的阵列基板驱动电路的结构示意图； 图 3为本发明阵列基板驱动电路的一个实施例的结构示意图；
图 4为图 3中 GoA驱动单元的一个实施例的电路原理图；
图 5是本发明阵列基板驱动电路的驱动时序关系的示意图。
具体实施方式
以下各实施例的说明是参考附图， 用以式例本发明可以用以实施的特定 实施例。 本发明所提到的方向用语， 例如「上」、 「下」、 「前」、 「后」、 「左」、 r右」、 「内」、 「外」、 「侧面」等， 仅是参考附加图式的方向。 因此， 使用的 方向用语是用以说明及理解本发明， 而非用以限制本发明。
如图 3所示， 为本发明阵列基板驱动电路的一个实施例的结构示意图； 在该实施例中， 该阵列基板驱动电路， 包括多个用于驱动阵列基板的栅线的 GoA驱动单元， 其中， 每一 GoA驱动单元连接一条栅线；
奇数行的栅线所连接的 GoA驱动单元设置在阵列基板的一侧， 偶数行 的栅线所连接的 GoA驱动单元设置在阵列基板的另一侧； 每一 GoA驱动单元均具有第一驱动信号输入端、 第二驱动信号输入端 以及一个输出端， 第一驱动信号输入端与上级 GoA驱动单元的输出端相连， 第二驱动信号输入端与下级 GoA驱动单元的输出端相连， 与 GoA驱动单元 连接栅线连接在输出端上。
其中， 位于最前端的 GoA驱动单元的第一驱动信号输入端连接有一扫 描触发信号线 ( STV ), 用于触发位于最前端的 GoA驱动单元开始工作。
为了便于电路走线， 其中， 奇数行的栅线所连接的各 GoA驱动单元所 连接的时钟信号输出端为第一时钟信号的输出端 Clk— A, 偶数行的栅线所连 接的各 GoA驱动单元所连接的信号输出端为第二时钟信号的输出端 Clk— B, 为了使两侧的 GoA驱动单元可以交替并逐行驱动栅线， 故将第一时钟信号 与第二时钟信号设置为周期长度相同， 相位相差半个周期， 即当第一时钟信 号处于高电平时， 则第二时钟信号处于低电平， 反之， 当第一时钟信号处于 低电平时， 则第二时钟信号处于高电平。
另外， 在两侧还分别设置有一低电位输入线（Vss ), 分别和各 GoA驱 动单元相连接， 可以理解的是， 在其他的实施例中， 该低电位输入线可以采 用直接接地的方式进行替换；
如图 4所示， 示出了本发明图 3中 GoA驱动单元的一个实施例的电路 原理图； 一并结合图 5中示出的时序关系图。 在本实施例中， 每一 GoA驱 动单元包括第一薄膜晶体管 TFT1、 第二薄膜晶体管 TFT2、 第三薄膜晶体管 TFT3、 第四薄膜晶体管 TFT4和储存电容 Cb, 其中：
第一薄膜晶体管 TFT1的源极和栅极作为第一驱动信号输入端， 均与上 级 GoA驱动单元的信号输出端 N-1相连接， 其漏极分别与第二薄膜晶体管 TFT2的栅极、储存电容 Cb的第一端、第三薄膜晶体管 TFT3的漏极相连接； 第二薄膜晶体管 TFT2的源极与时钟信号输出端相连接， 其栅极与储存 电容 Cb的第一端相连接， 其漏极与本级信号输出端、第四薄膜晶体管 TFT4 的源极、 储存电容 Cb的第二端相连接；
第三薄膜晶体管 TFT3的源极与储存电容 Cb的第一端连接， 其栅极作 为第二驱动信号输入端， 连接下级 GoA驱动单元的信号输出端 N+1 , 其源 极接低电位输入线（Vss )或接地； 第四薄膜晶体管 TFT4的源极与本级信号输出端 N与储存电容 Cb的第 二端相连， 其栅线连接下级 GoA驱动单元的信号输出端 N+1 , 其漏极接低 电位输入线（Vss )或接地。
下述将描述图 4中的 GoA驱动单元的电路的工作原理， 为便于理解， 可一并结合图 5中的时序图， 其工作原理如下：
在第 N-1周期（为上级 GoA驱动单元的工作周期）时， 上级 GoA驱动 单元的信号输出端 N-1端输入信号为高电平， Clk信号为低电平， 下级 GoA 驱动单元的信号输出端 N+1 端输入信号为低电平， 此时第一薄膜晶体管 TFT1和第二薄膜晶体管 TFT2导通，第三薄膜晶体管 TFT3和第四薄膜晶体 管 TFT4截止， 第一薄膜晶体管 TFT1 的输出信号为高电平， 储存电容 Cd 在第一薄膜晶体管 TFT1的输出信号 (高电平信号 ) 的驱动下充电；
在第 N周期（为本级 GoA驱动单元的工作周期）时， 上级 GoA驱动单 元的信号输出端 N-1端输入信号为低电平， Clk信号为高电平， 下级 GoA驱 动单元的信号输出端 N+1信号为低电平， 此时第一薄膜晶体管 TFT1、 第三 薄膜晶体管 TFT3和第四薄膜晶体管 TFT4截止， 第二薄膜晶体管 TFT2导 通， 并在本级信号输出端 N输出高电平信号；
在第 N+1周期（为下级 GoA电路的工作周期）时， 上级 GoA驱动单元 的信号输出端 N-1为低电平， Clk信号为低电平， 下级 GoA驱动单元的信号 输出端 N+1信号为高电平， 此时第三薄膜晶体管 TFT3和第四薄膜晶体管 TFT4导通， 第一薄膜晶体管 TFT1和第二薄膜晶体管 TFT2截止； 第三薄膜 晶体管 TFT3导通后使得电容 Cd接低电位 /地并放电，第四薄膜晶体管 TFT4 导通后使得本级信号输出端 N接低电位 /接地并放电。
这样就实现了位于阵列基板的两侧的 GoA驱动单元交替驱动奇偶行的 各栅线， 使各栅线逐行进行启动， 具体来说， 即左侧的第一个 GoA驱动单 元先驱动第一条栅线（ G1 ), 然后右侧的第一个 GoA驱动单元驱动第二条栅 线（G2 ), 接着左侧的第二个 GoA驱动单元驱动第三条栅线（G3 ), 然后右 侧的第一个 GoA驱动单元驱动第四条栅线（G4 ), 按照这样的驱动方式， 通 过两侧的 GoA驱动单元交替驱动奇偶行的各栅线， 使各栅线逐行进行启动。
可以理解的是，上述图 4示出了一种由四个 TFT晶体管驱动的驱动电路 的原理图，在其他的实施例中，可以采用其他的数量的 TFT晶体管进行替换， 例如可以采用 5个 TFT晶体管驱动的驱动电路。
在该实施例中， 将多个 GoA驱动单元分设在阵列基板的两侧， 并且使 栅线奇偶行分别采用两侧的 GoA驱动单元交替驱动； 从而大大减少了驱动 电路所占的面积， 以及每一侧的驱动电路的复杂程序也降低了， 进而有利于 液晶显示器的窄边框化设计。
相应地， 本发明实施还提供了一种液晶显示器的阵列基板， 包括由栅线 和数据线限定的多个像素单元， 每个像素单元内形成薄膜晶体管和像素电 极； 进一步包括有用于驱动栅线的阵列基板驱动电路，驱动电路采用如图 3、 图 4所揭露的驱动电路， 更多的细节可以参考前述对图 3-图 5的描述， 在此 不进行贅述。
相应地， 本发明的实施例还提供了一种液晶显示器， 包括： 阵列基板； 彩色滤光片基板， 与阵列基板相对； 以及液晶层， 配置于阵列基板与彩色 滤光片基板之间； 其中， 阵列基板为前述采用如图 3和图 4所揭露的驱动电 路， 更多的细节可以参考前述对图 3-图 5的描述， 在此不进行赞述。
综上， 实施本发明的实施例， 具有如下的有益效果：
本发明的实施例中， 将多个 GoA驱动单元分设在阵列基板的两侧， 并 且使栅线奇偶行分别采用两侧的 GoA驱动单元交替驱动； 从而大大减少了 驱动电路所占的面积， 以及降低了每一侧的驱动电路的复杂程序， 进而有利 于液晶显示器的窄边框化设计。
以上所揭露的仅为本发明较佳实施例而已， 当然不能以此来限定本发明 之权利范围， 因此等同变化， 仍属本发明所涵盖的范围。

Claims

权 利 要 求
1、 一种阵列基板驱动电路， 其中， 包括多个用于驱动阵列基板的栅线 的 GoA驱动单元， 其中， 每一 GoA驱动单元连接一条栅线；
奇数行的栅线所连接的 GoA驱动单元设置在所述阵列基板的一侧， 偶 数行的栅线所连接的 GoA驱动单元设置在所述阵列基板的另一侧；
所述每一 GoA驱动单元均具有第一驱动信号输入端、 第二驱动信号输 入端以及一个输出端， 所述第一驱动信号输入端与上级 GoA驱动单元的输 出端相连， 所述第二驱动信号输入端与下级 GoA驱动单元的输出端相连， 与所述 GoA驱动单元连接栅线连接在所述输出端上。
2、 根据权利要求 1所述的阵列基板驱动电路， 其中， 每一 GoA驱动单 元包括第一薄膜晶体管、 第二薄膜晶体管、 第三薄膜晶体管、 第四薄膜晶体 管和储存电容， 其中：
第一薄膜晶体管的源极和栅极均与上级 GoA驱动单元的信号输出端相 连接， 其漏极分别与第二薄膜晶体管的栅极、 储存电容的第一端、 第三薄膜 晶体管的漏极相连接；
第二薄膜晶体管的源极与时钟信号输出端相连接，其栅极与储存电容的 第一端相连接， 其漏极与本级信号输出端、 第四薄膜晶体管的源极、 储存电 容的第二端相连接；
第三薄膜晶体管的源极与储存电容的第一端连接，其栅极连接下级 GoA 驱动单元的信号输出端， 其源极接低电位输入线或接地；
第四薄膜晶体管的源极与本级信号输出端和储存电容的第二端相连， 其 栅极连接下级 GoA驱动单元的信号输出端， 其漏极接低电位输入线或接地。
3、 如权利要求 2所述阵列基板驱动电路， 其中， 所述奇数行的各栅线 所连接的各 GoA驱动单元所连接的时钟信号输出端为第一时钟信号的输出 端， 所述偶数行的各栅线所连接的各 GoA驱动单元所连接的信号输出端为 第二时钟信号的输出端， 所述第一时钟信号与所述第二时钟信号周期长度相 同， 相位相差半个周期。
4、根据权利要求 3所述的阵列基板驱动电路，其中，位于最前端的 GoA 驱动单元的所述第一驱动信号输入端连接有一扫描触发信号线， 用于触发所 述位于最前端的 GoA驱动单元开始工作。
5、 一种液晶显示器的阵列基板， 包括由栅线和数据线限定的多个像素 单元， 每个像素单元内形成薄膜晶体管和像素电极； 进一步包括有用于驱动 所述栅线的阵列基板驱动电路， 其中， 所述驱动电路包括多个 GoA驱动单 元， 其中， 每一 GoA驱动单元的输出端连接一条栅线；
奇数行的栅线所连接的 GoA驱动单元设置在所述阵列基板的一侧， 偶 数行的栅线所连接的 GoA驱动单元设置在所述阵列基板的另一侧；
所述每一 GoA驱动单元均具有第一驱动信号输入端、 第二驱动信号输 入端以及一个输出端， 所述第一驱动信号输入端与上级 GoA驱动单元的输 出端相连， 所述第二驱动信号输入端与下级 GoA驱动单元的输出端相连， 与所述 GoA驱动单元连接栅线连接在所述输出端上。
6、 根据权利要求 5所述的液晶显示器的阵列基板， 其中， 每一 GoA驱 动单元包括第一薄膜晶体管、 第二薄膜晶体管、 第三薄膜晶体管、 第四薄膜 晶体管和储存电容， 其中：
第一薄膜晶体管的源极和栅极均与上级 GoA驱动单元的信号输出端相 连接， 其漏极分别与第二薄膜晶体管的栅极、 储存电容的一端、 第三薄膜晶 体管的漏极相连接；
第二薄膜晶体管的源极与时钟信号输出端相连接，其栅极与储存电容的 第一端相连接， 其漏极与本级信号输出端、 第四薄膜晶体管的源极、 储存电 容的第二端相连接；
第三薄膜晶体管的源极与储存电容的第一端连接，其栅极连接下级 GoA 驱动单元的信号输出端， 其源极接低电位输入线或接地；
第四薄膜晶体管的源极与本级信号输出端和储存电容的第二端相连， 其 栅极连接下级 GoA驱动单元的信号输出端， 其漏极接低电位输入线或接地。
7、 根据权利要求 6所述的液晶显示器的阵列基板， 其中， 所述奇数行 的和栅线所连接的各 GoA驱动单元所连接的时钟信号输出端为第一时钟信 号的输出端， 所述偶数行的和栅线所连接的各 GoA驱动单元所连接的信号 输出端为第二时钟信号的输出端， 所述第一时钟信号与所述第二时钟信号周 期长度相同， 相位相差半个周期。
8、 根据权利要求 7所述的液晶显示器的阵列基板， 其中， 位于最前端 的 GoA驱动单元的所述第一驱动信号输入端连接有一扫描触发信号线， 用 于触发所述位于最前端的 GoA驱动单元开始工作。
9、 一种液晶显示器， 包括：
阵列基板；
彩色滤光片基板， 与所述阵列基板相对； 以及
液晶层， 配置于所述阵列基板与所述彩色滤光片基板之间；
其中， 所述阵列基板包括由栅线和数据线限定的多个像素单元， 每个像 素单元内形成薄膜晶体管和像素电极； 其中， 进一步包括有用于驱动所述栅 线的阵列基板驱动电路， 所述驱动电路包括多个 GoA驱动单元， 每一 GoA 驱动单元的输出端连接一条栅线；
奇数行的栅线所连接的 GoA驱动单元设置在所述阵列基板的一侧， 偶 数行的栅线所连接的 GoA驱动单元设置在所述阵列基板的另一侧；
所述每一 GoA驱动单元均具有第一驱动信号输入端、 第二驱动信号输 入端以及一个输出端， 所述第一驱动信号输入端与上级 GoA驱动单元的输 出端相连， 所述第二驱动信号输入端与下级 GoA驱动单元的输出端相连， 与所述 GoA驱动单元连接栅线连接在所述输出端上。
10、 根据权利要求 9所述的液晶显示器， 其中， 每一 GoA驱动单元包 括第一薄膜晶体管、 第二薄膜晶体管、 第三薄膜晶体管、 第四薄膜晶体管和 储存电容， 其中：
第一薄膜晶体管的源极和栅极均与上级 GoA驱动单元的信号输出端相 连接， 其漏极分别与第二薄膜晶体管的栅极、 储存电容的一端、 第三薄膜晶 体管的漏极相连接；
第二薄膜晶体管的源极与时钟信号输出端相连接，其栅极与储存电容的 第一端相连接， 其漏极与本级信号输出端、 第四薄膜晶体管的源极、 储存电 容的第二端相连接；
第三薄膜晶体管的源极与储存电容的第一端连接，其栅极连接下级 GoA 驱动单元的信号输出端， 其源极接低电位输入线或接地； 第四薄膜晶体管的源极与本级信号输出端和储存电容的第二端相连， 其 栅极连接下级 GoA驱动单元的信号输出端， 其漏极接低电位输入线或接地。
11、 根据权利要求 10所述的液晶显示器， 其中， 所述奇数行的和栅线 所连接的各 GoA驱动单元所连接的时钟信号输出端为第一时钟信号的输出 端， 所述偶数行的和栅线所连接的各 GoA驱动单元所连接的信号输出端为 第二时钟信号的输出端， 所述第一时钟信号与所述第二时钟信号周期长度相 同， 相位相差半个周期。
12、 根据权利要求 11所述的液晶显示器， 其中， 位于最前端的 GoA驱 动单元的所述第一驱动信号输入端连接有一扫描触发信号线， 用于触发所述 位于最前端的 GoA驱动单元开始工作。
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